SN75LBC172DWG4 [TI]

Quadruple Low-Power Differential Line Driver 20-SOIC 0 to 70;


型号：	SN75LBC172DWG4
厂家：	TEXAS INSTRUMENTS
描述：	Quadruple Low-Power Differential Line Driver 20-SOIC 0 to 70 驱动信息通信管理光电二极管接口集成电路驱动器
文件：	总17页 (文件大小：870K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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ꢋ ꢌꢍꢎꢏ ꢌꢐꢄ ꢑ ꢄ ꢒꢓꢔꢐꢒ ꢓ ꢑꢏ ꢎꢕ ꢖꢖ ꢑꢏ ꢑꢁꢗ ꢕꢍ ꢄ ꢄ ꢕꢁ ꢑ ꢎ ꢏꢕ ꢘ ꢑꢏ

SLLS163E − JULY 1993 − REVISED APRIL 2006

N PACKAGE

(TOP VIEW)

Meets or Exceeds EIA Standard RS-485

Designed for High-Speed Multipoint

Transmission on Long Bus Lines in Noisy

Environments

Support Data Rates up to and Exceeding

Ten Million Transfers Per Second

13 4Z

Common-Mode Output Voltage Range of

−7 V to 12 V

Positive- and Negative-Current Limiting

GND

Low Power Consumption . . . 1.5 mA Max

(Output Disabled)

DW PACKAGE

(TOP VIEW)

Functionally Interchangeable With SN75172

description

The SN65LBC172 and SN75LBC172 are

monolithic quadruple differential line drivers with

3-state outputs. Both devices are designed to

meet the requirements of EIA Standard RS-485.

These devices are optimized for balanced

multipoint bus transmission at data rates up to and

exceeding 10 million bits per second. Each driver

features wide positive and negative common-

mode output voltage ranges, current limiting, and

thermal-shutdown circuitry making it suitable for

party-line applications in noisy environments.

Both devices are designed using LinBiCMOS,

facilitating ultra-low power consumption and

inherent robustness.

GND

NC − No internal connection

FUNCTION TABLE

(each driver)

INPUT

ENABLES

OUTPUTS

Both the SN65LBC172 and SN75LBC172 provide

positive- and negative-current limiting and

thermal shutdown for protection from line fault

conditions on the transmission bus line. These

devices offer optimum performance when

used with the SN75LBC173 or SN75LBC175

quadruple line receivers. The SN65LBC172 and

SN75LBC172 are available in the 16-pin DIP

package (N) and the 20-pin wide-body small-

outline inline-circuit (SOIC) package (DW).

H = high level, L = low level,

X = irrelevant, Z = high impedance (off)

The SN75LBC172 is characterized for operation

over the commercial temperature range of 0°C to

70°C. The SN65LBC172 is characterized over the

industrial temperature range of −40°C to 85°C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

LinBiCMOS is a trademark of Texas Instruments Incorporated.

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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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ꢋꢌ ꢍ ꢎꢏ ꢌ ꢐꢄ ꢑ ꢄ ꢒꢓꢔꢐ ꢒꢓ ꢑ ꢏ ꢎꢕ ꢖ ꢖꢑ ꢏꢑ ꢁꢗ ꢕꢍ ꢄ ꢄ ꢕꢁꢑ ꢎꢏꢕ ꢘꢑ ꢏ

SLLS163E − JULY 1993 − REVISED APRIL 2006

†

logic symbol

logic diagram (positive logic)

≥1

†

This symbol is in accordance with ANSI/IEEE Std 91-1984

and IEC Publication 617-12.

Pin numbers shown are for the N package.

schematic diagrams of inputs and outputs

ALL INPUTS

Y OR Z OUTPUT

50 µA

200 Ω

Output

Input

Driver

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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SLLS163E − JULY 1993 − REVISED APRIL 2006

†

absolute maximum ratings

Supply voltage range, V

Output voltage range, V

(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 7 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −10 V to 15 V

Voltage range at A, G, G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to V

Continuous power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internally limited

+ 0.5 V

‡

Storage temperature range, T

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C

stg

†

‡

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

The maximum operating junction temperature is internally limited. Use the dissipation rating table to operate below this temperature.

NOTE 1: All voltage values are with respect to GND.

recommended operating conditions

MIN NOM

MAX

UNIT

Supply voltage, V

4.75

5.25

High-level input voltage, V

Low-level input voltage, V

0.8

Voltage at any bus terminal (separately or common mode), V

Y or Z

−7

High-level output current, I

Y or Z

−60

Low-level output current, I

Continuous total power dissipation

Junction temperature, T

See Dissipation Rating Table

140

°C

SN65LBC172

SN75LBC172

−40

Operating free-air temperature, T

°C

DISSIPATION RATING TABLE

THERMAL

MODEL

< 25°C

DERATING FACTOR

= 70°C

T = 85°C

PACKAGE

ABOVE T = 25°C

POWER RATING POWER RATING

POWER RATING

†

Low K

1094 mW

10.4 mW/°C

15.9 mW/°C

9.2 mW/°C

625 mW

954 mW

736 mW

469 mW

715 mW

598 mW

‡

High K

1669 mW

1150 mW

†

‡

In accordance with the low effective thermal conductivity metric definitions of EIA/JESD 51−3.

In accordance with the high effective thermal conductivity metric definitions of EIA/JESD 51−7.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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SLLS163E − JULY 1993 − REVISED APRIL 2006

electrical characteristics over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted)

†

PARAMETER

Input clamp voltage

TEST CONDITIONS

MIN TYP

MAX

−1.5

UNIT

I = −18 mA

SN65LBC172

SN75LBC172

SN65LBC172

SN75LBC172

1.1

1.5

1.1

1.5

1.8

1.7

= 54 Ω,

See Figure 1

‡

Differential output voltage

= 60 Ω,

See Figure 2

∆|V

0.2

Change in magnitude of common-mode output voltage

− 1

Common-mode output voltage

= 54 Ω,

See Figure 1

∆|V

0.2

100

−100

250

Change in magnitude of common-mode output voltage

Output current with power off

= 0,

V = − 7 V to 12 V

µA

High-impedance-state output current

High-level input current

= − 7 V to 12 V

V = 2.4 V

Low-level input current

V = 0.4 V

Short-circuit output current

= −7 V to 12 V

Outputs enabled

Outputs disabled

Supply current (all drivers)

No load

1.5

†

‡

All typical values are at V

= 5 V and T = 25°C.

The minimum V

specification does not fully comply with EIA-485 at operating temperatures below 0°C. The lower output signal should be used

to determine the maximum signal-transmission distance.

∆|V | and ∆|V | are the changes in magnitude of V and V , respectively, that occur when the input changes from a high level to a low

OD OC

level.

switching characteristics, V

= 5 V, T = 25°C

PARAMETER

Differential output delay time

TEST CONDITIONS

MIN

TYP

MAX

UNIT

d(OD)

t(OD)

PZH

PZL

= 54 Ω,

See Figure 3

Differential output transition time

Output enable time to high level

Output enable time to low level

Output disable time from high level

Output disable time from low level

= 110 Ω,

See Figure 4

See Figure 5

See Figure 4

See Figure 5

PHZ

PLZ

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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SLLS163E − JULY 1993 − REVISED APRIL 2006

PARAMETER MEASUREMENT INFORMATION

OD2

Figure 1. Differential and Common-Mode Output Voltages

test

R1 = 375 Ω

= 60 Ω

0 V or 3 V

G at 5 V

R2 = 375 Ω

G at 0 V

−7 V < V

< 12 V

test

NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, duty cycle = 50%, t ≤ 5 ns,

t ≤ 5 ns, Z = 50 Ω.

includes probe and stray capacitance.

Figure 2. Driver V

Test Circuit

3 V

Input

1.5 V

Input

50 Ω

0 V

= 54 Ω

Output

= 50 pF

Generator

(see Note A)

d(OD)

(see Note B)

≈ 2.5 V

90%

10%

50%

t(OD)

50%

Output

≈ − 2.5 V

3 V

t(OD)

VOLTAGE WAVEFORMS

NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, duty cycle = 50%, t ≤ 5 ns,

TEST CIRCUIT

t ≤ 5 ns, Z = 50 Ω.

includes probe and stray capacitance.

Figure 3. Driver Differential-Output Test Circuit and Delay and Transition-Time Waveforms

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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SLLS163E − JULY 1993 − REVISED APRIL 2006

PARAMETER MEASUREMENT INFORMATION

3 V

0 V

Input

1.5 V

Output

0 V or 3 V

Input

0.5 V

PZH

= 110 Ω

Generator

(see Note A)

= 50 pF

50 Ω

(see Note B)

Output

2.3 V

off

≈ 0 V

PHZ

VOLTAGE WAVEFORMS

NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, duty cycle = 50%, t ≤ 5 ns,

TEST CIRCUIT

t ≤ 5 ns, Z = 50 Ω.

includes probe and stray capacitance.

Figure 4. t

and t

Test Circuit and Voltage Waveforms

PZH

PHZ

5 V

= 110 Ω

3 V

0 V

Input

Output

1.5 V

0 V or 3 V

PZL

= 50 pF

Input

Generator

(see Note A)

PLZ

5 V

0.5 V

(see Note B)

50 Ω

2.3 V

Output

3 V

(see Note C)

TEST CIRCUIT

VOLTAGE WAVEFORMS

NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, duty cycle = 50%, t ≤ 5 ns,

t ≤ 5 ns, Z = 50 Ω.

includes probe and stray capacitance

C. To test the active-low enable G, ground G and apply an inverted waveform to G..

Figure 5. t

and t

Test Circuit and Waveforms

PZL

PLZ

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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SLLS163E − JULY 1993 − REVISED APRIL 2006

TYPICAL CHARACTERISTICS

OUTPUT CURRENT

LOW-LEVEL OUTPUT VOLTAGE

OUTPUT VOLTAGE

LOW-LEVEL OUTPUT CURRENT

Output Disabled

= 25°C

= 5 V

= 25°C

4.5

3.5

2.5

−10

−20

−30

−40

−50

= 0 V

1.5

= 5 V

0.5

−25 −20 −15 −10 −5

10 15 20 25

−20

100 120

− Output Voltage − V

− Low-Level Output Current − mA

Figure 6

Figure 7

DIFFERENTIAL OUTPUT VOLTAGE

HIGH-LEVEL OUTPUT VOLTAGE

HIGH-LEVEL OUTPUT CURRENT

FREE-AIR TEMPERATURE

2.5

= 54 Ω

= 5 V

= 25°C

4.5

3.5

1.5

2.5

0.5

1.5

−60 −40 −20

80 100

−20

−40 −60

−80

−100 −120

− Free-Air Temperature − °C

− High-Level Output Current − mA

Figure 8

Figure 9

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SLLS163E − JULY 1993 − REVISED APRIL 2006

TYPICAL CHARACTERISTICS

PROPAGATION DELAY TIME,

DIFFERENTIAL OUTPUT

DIFFERENTIAL OUTPUT VOLTAGE

OUTPUT CURRENT

FREE-AIR TEMPERATURE

2.5

= 5 V

= 25°C

= 54 Ω

= 50 pF

= 5 V

1.5

0.5

10 20 30 40 50 60 70 80 90 100

−60 −40 −20

80 100

− Output Current − mA

− Free-Air Temperature − °C

Figure 10

Figure 11

THERMAL CHARACTERISTICS − DW PACKAGE

TEST CONDITIONS

PARAMETER

Junction−to−ambient thermal reisistance, θ

MIN

TYP

MAX

UNIT

Low-K board, no air flow

†

High-K board, no air flow

62.9

39.6

29.1

°C/W

Junction−to−board thermal reisistance, θ

High-K board, no air flow

Junction−to−case thermal reisistance, θ

All four channels maximum loading,

maximum signaling rate, R = 54 Ω, input to

D is 10 Mbps 50% duty cycle square wave,

Average power dissipation, P

(AVG)

1100

= 5.25 V, T = 130 °C.

JEDEC high-K board model

−40

Ambient free−air temperature, T

°C

Thermal shutdown junction temperature, T

165

†

See TI application note literature number SZZA003, Package Thermal Characterization Methodologies, for an explanation of this parameter.

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SLLS163E − JULY 1993 − REVISED APRIL 2006

THERMAL CHARACTERISTICS OF IC PACKAGES

_JA(Junction-to-Ambient Thermal Resistance) is defined as the difference in junction temperature to ambient temperature

divided by the operating power

_JAis NOT a constant and is a strong function of

the PCB design (50% variation)

altitude (20% variation)

device power (5% variation)

_JAcan be used to compare the thermal performance of packages if the specific test conditions are defined and used.

Standardized testing includes specification of PCB construction, test chamber volume, sensor locations, and the thermal

characteristics of holding fixtures.

installations.

is often misused when it is used to calculate junction temperatures for other

TI uses two test PCBs as defined by JEDEC specifications. The low-k board gives average in-use condition thermal

performance and consists of a single trace layer 25 mm long and 2-oz thick copper. The high-k board givesbest case in−use

condition and consists of two 1-oz buried power planes with a single trace layer 25 mm long with 2-oz thick copper. A 4%

to 50% difference in Θ_JAcan be measured between these two test cards

Θ_JC(Junction-to-Case Thermal Resistance) is defined as difference in junction temperature to case divided by the

operating power. It is measured by putting the mounted package up against a copper block cold plate to force heat to flow

from die, through the mold compound into the copper block.

_JCis a useful thermal characteristic when a heatsink is applied to package. It is NOT a useful characteristic to predict

junction temperature as it provides pessimistic numbers if the case temperature is measured in a non-standard system and

junction temperatures are backed out. It can be used with Θ_JBin 1-dimensional thermal simulation of a package system.

Θ_JB(Junction-to-Board Thermal Resistance) is defined to be the difference in the junction temperature and the PCB

temperature at the center of the package (closest to the die) when the PCB is clamped in a cold−plate structure. Θ_JBis only

defined for the high-k test card.

_JBprovides an overall thermal resistance between the die and the PCB. It includes a bit of the PCB thermal resistance

(especially for BGA’s with thermal balls) and can be used for simple 1-dimensional network analysis of package system

(see Figure 12).

Ambient Node

Calculated

Surface Node

Calculated/Measured

Junction

Calculated/Measured

PC Board

Figure 12. Thermal Resistance

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PACKAGE OPTION ADDENDUM

www.ti.com

10-Jun-2014

PACKAGING INFORMATION

Orderable Device

SN65LBC172DW

SN65LBC172DWG4

SN65LBC172N

Status Package Type Package Pins Package

Eco Plan

Lead/Ball Finish

MSL Peak Temp

Op Temp (°C)

-40 to 85

0 to 70

Device Marking

Samples

Drawing

Qty

(1)

(2)

(6)

(3)

(4/5)

ACTIVE

SOIC

PDIP

SOIC

PDIP

Green (RoHS

& no Sb/Br)

CU NIPDAU

Level-1-260C-UNLIM

N / A for Pkg Type

Level-1-260C-UNLIM

N / A for Pkg Type

SN65LBC172

ACTIVE

Green (RoHS

& no Sb/Br)

SN65LBC172

SN65LBC172N

SN75LBC172

SN75LBC172N

Pb-Free

(RoHS)

SN65LBC172NE4

SN75LBC172DW

SN75LBC172DWG4

SN75LBC172DWR

SN75LBC172N

Pb-Free

(RoHS)

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

0 to 70

2000

Green (RoHS

& no Sb/Br)

0 to 70

Pb-Free

(RoHS)

0 to 70

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

10-Jun-2014

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

⁽⁶⁾Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish

value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF SN75LBC172 :

Military: SN55LBC172

•

NOTE: Qualified Version Definitions:

Military - QML certified for Military and Defense Applications

•

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

4-Jan-2013

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

SN75LBC172DWR

SOIC

2000

330.0

24.4

10.8

13.0

13.3

2.7

12.0

24.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

4-Jan-2013

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

SN75LBC172DWR

SOIC

2000

367.0

45.0

Pack Materials-Page 2

IMPORTANT NOTICE

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SN75LBC172DWG4 [TI]

相关型号：

SN75LBC172DWR

SN75LBC172DWRG4

SN75LBC172N

SN75LBC172NE4

SN75LBC173

SN75LBC173A

SN75LBC173AD

SN75LBC173ADG4

SN75LBC173ADR

SN75LBC173ADRG4

SN75LBC173AN

SN75LBC173ANE4