SN75LBC172AN [TI]
QUADRUPLE RS-485 DIFFERENTIAL LINE DRIVERS; 四路RS - 485差动线路驱动器
| 型号： | SN75LBC172AN |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | QUADRUPLE RS-485 DIFFERENTIAL LINE DRIVERS |
| 文件： | 总19页 (文件大小：477K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN65LBC172A, SN75LBC172A
QUADRUPLE RS-485 DIFFERENTIAL LINE DRIVERS
SLLS447B – OCTOBER 2000 – REVISED MAY 2003
D
D
D
D
Designed for TIA/EIA-485, TIA/EIA-422,
and ISO 8482 Applications
D
D
Driver Positive- and Negative-Current
Limiting
†
Signaling Rates up to 30 Mbps
Power-Up and Power-Down Glitch-Free for
Live Insertion Applications
Propagation Delay Times <11 ns
D
Thermal Shutdown Protection
Low Standby Power Consumption
1.5 mA Max
D
Industry Standard Pin-Out, Compatible
With SN75172, AM26LS31, DS96172,
LTC486, and MAX3045
D
Output ESD Protection Exceeds 13 kV
description
The SN65LBC172A and SN75LBC172A are quadruple differential line drivers with 3-state outputs, designed
for TIA/EIA-485 (RS-485), TIA/EIA-422 (RS-422), and ISO 8482 applications.
logic diagram (positive logic)
16-DW PACKAGE
N PACKAGE
(TOP VIEW)
(TOP VIEW)
4
G
G
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
12
1A
1Y
V
CC
1A
1Y
V
CC
1
2
3
4
5
6
7
8
16
15
14
13
12
4A
4Y
4Z
G
3Z
3Y
3A
4A
4Y
4Z
G
1Z
G
2Z
2
3
1Z
1Y
1Z
1
1A
2A
3A
4A
G
2Z
2Y
2A
GND
6
5
2Y
2Z
2Y
11 3Z
10 3Y
7
2A
9
GND
3A
10
11
3Y
3Z
9
14
13
4Y
4Z
15
20-DW PACKAGE
(TOP VIEW)
logic diagram (positive logic)
5
1
2
3
4
5
6
7
8
9
10
20
1A
1Y
NC
1Z
G
2Z
NC
2Y
2A
V
CC
G
19
18
17
16
15
14
13
12
11
4A
4Y
NC
4Z
G
3Z
NC
3Y
3A
15
G
2
4
1Y
1Z
1
1A
8
6
2Y
2Z
9
2A
GND
12
14
3Y
3Z
11
3A
18
16
4Y
4Z
19
4A
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
LinBiCMOS is a trademark of Texas Instruments.
†
The signaling rate of a line is the number of voltage transitions that are made per second expressed in the units bps (bits per second).
Copyright 2001 – 2003, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LBC172A, SN75LBC172A
QUADRUPLE RS-485 DIFFERENTIAL LINE DRIVERS
SLLS447B – OCTOBER 2000 – REVISED MAY 2003
description (continued)
These devices are optimized for balanced multipoint bus transmission at signalling rates up to 30 million bits
per second. The transmission media may be printed-circuit board traces, backplanes, or cables. The ultimate
rate and distance of data transfer is dependent upon the attenuation characteristics of the media and the noise
coupling to the environment.
Each driver features current limiting and thermal-shutdown circuitry making it suitable for high-speed mulitpoint
data transmission applications in noisy environments. These devices are designed using LinBiCMOSt,
facilitating low power consumption and robustness.
The G and G inputs provide driver enable control using either positive or negative logic. When disabled or
powered off, the driver outputs present a high-impedance to the bus for reduced system loading.
The SN75LBC172A is characterized for operation over the temperature range of 0°C to 70°C. The
SN65LBC172A is characterized over the temperature range from –40°C to 85°C.
AVAILABLE OPTIONS
PACKAGE
16-PIN PLASTIC
SMALL OUTLINE
(JEDEC MS-013)
20-PIN PLASTIC
SMALL OUTLINE
(JEDEC MS-013)
16-PIN PLASTIC
THROUGH-HOLE
(JEDEC MS-001)
T
A
†
†
SN75LBC172A16DW
SN65LBC172A16DW
SN75LBC172ADW
Marked as 75LBC172A
SN65LBC172ADW
SN75LBC172AN
0°C to 70°C
SN65LBC172AN
–40°C to 85°C
Marked as 65LBC172A
†
Add R suffix for taped and reeled version.
FUNCTION TABLE
(EACH DRIVER)
INPUT
ENABLES
OUTPUTS
A
G
G
Y
Z
H
H
L
L
H
X
L
L
L
X
L
H
H
X
H
H
H
H
H
L
H
X
L
L
OPEN
H
X
L
OPEN
X
OPEN
OPEN
L
L
X
L
H
L
L
X
H
Z
Z
X
X
H
Z
Z
L
OPEN
H = high level, L = low level, X = irrelevant,
Z = high impedance (off)
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LBC172A, SN75LBC172A
QUADRUPLE RS-485 DIFFERENTIAL LINE DRIVERS
SLLS447B – OCTOBER 2000 – REVISED MAY 2003
equivalent input and output schematic diagrams
Y or Z Output
A, G, or G Input
V
CC
V
CC
16 V
16 V
20 V
100 kΩ
1 kΩ
Input
Output
16 V
16 V
9 V
17 V
†
absolute maximum ratings
Supply voltage range, V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 6 V
CC
Output voltage range, V , at any bus (steady state) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –10 V to 15 V
O
Output voltage range, V , at any bus (transient pulse through 100 Ω, see Figure 8) . . . . . . . . . . . –30 V to 30 V
O
Input voltage range, V , at any A, G, or G terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
+ 0.5 V
I
CC
Electrostatic discharge: Human body model (see Note 2)
Y, Z, and GND . . . . . . . . . . . . . . . . . . . . . 13 kV
All pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 kV
Charged-device model (see Note 3) All pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 kV
Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
Continuous power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values, except differential I/O bus voltages, are with respect to GND.
2. Tested in accordance with JEDEC standard 22, Test Method A114–A.
3. Tested in accordance with JEDEC standard 22, Test Method C101.
DISSIPATION RATING TABLE
‡
JEDEC
BOARD
MODEL
T
≤ 25°C
DERATING FACTOR
T
= 70°C
T = 85°C
A
A
A
PACKAGE
POWER RATING
ABOVE T = 25°C
POWER RATING POWER RATING
A
Low K
High K
Low K
High K
Low K
1200 mW
2240 mW
1483 mW
2753 mW
1150 mW
9.6 mW/°C
17.9 mW/°C
11.86 mW/°C
22 mW/°C
769 mW
1434 mW
949 mW
1762 mW
736 mW
625 mW
1165 mW
771 mW
1432 mW
598 mW
16-PIN DW
20-PIN DW
16-PIN N
9.2 mW/°C
‡
This is the inverse of the junction-to-ambient thermal resistance when board-mounted with no air flow.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LBC172A, SN75LBC172A
QUADRUPLE RS-485 DIFFERENTIAL LINE DRIVERS
SLLS447B – OCTOBER 2000 – REVISED MAY 2003
recommended operating conditions
MIN NOM
MAX
5.25
12
UNIT
V
Supply voltage, V
CC
4.75
–7
2
5
Voltage at any bus terminal
High-level input voltage, V
Y, Z
V
V
CC
0.8
IH
A, G, G
V
Low-level input voltage, V
Output current
0
IL
–60
0
60
70
85
mA
SN75LBC172A
SN65LBC172A
Operating free-air temperature, T
°C
A
–40
electrical characteristics over recommended operating conditions
†
PARAMETER
Input clamp voltage
TEST CONDITIONS
MIN TYP
MAX
UNIT
V
V
V
I = –18 mA
I
–1.5 –0.77
IK
Open-circuit output voltage
Y or Z, No load
0
3
V
CC
V
CC
2.5
2.5
V
O
No load (open circuit)
Steady-state differential output voltage
V
R
= 54 Ω, see Figure 1
L
1
1
1.6
1.6
V
OD(SS)
‡
magnitude
With common-mode loading, see Figure 2
Change in steady-state differential output
voltage between logic states
∆V
See Figure 1
–0.1
0.1
2.8
V
V
OD(SS)
Steady-state common-mode output
voltage
V
See Figure 3
2
2.4
OC(SS)
Change in steady-state common-mode
output voltage between logic states
∆V
OC(SS)
See Figure 3
A, G, G
–0.02
–50
0.02
50
V
I
I
Input current
µA
I
V = 0 V
I
Short-circuit output current
–200
200
mA
µA
OS
V = V
I
CC
V
= –7 V to 12 V,
TEST
See Figure 7
I
I
High-impedance-state output current
Output current with power off
G at 0 V, G at V
–50
–10
50
10
OZ
CC
V
CC
= 0 V
O(OFF)
All drivers enabled
All drivers disabled
23
V = 0 V or V
I
No load
CC,
I
Supply current
mA
CC
1.5
†
‡
All typical values are at V
= 5 V and 25°C.
CC
may not fully comply with TIA/EIA-485-A at operating temperatures below 0°C. System designers should take the possibly
The minimum V
OD
of lower output signal into account in determining the maximum signal transmission distance.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LBC172A, SN75LBC172A
QUADRUPLE RS-485 DIFFERENTIAL LINE DRIVERS
SLLS447B – OCTOBER 2000 – REVISED MAY 2003
switching characteristics over recommended operating conditions
PARAMETER
TEST CONDITIONS
MIN
5.5
5.5
3
TYP
8
MAX
11
11
11
11
2
UNIT
ns
t
t
t
t
t
t
Propagation delay time, low-to-high level output
Propagation delay time, high-to-low level output
Differential output voltage rise time
PLH
PHL
r
8
ns
7.5
7.5
0.6
ns
R
= 54 Ω, C = 50 pF,
L
see Figure 4
L
Differential output voltage fall time
3
ns
f
Pulse skew |t
– t
|
ns
sk(p)
sk(o)
PLH PHL
†
2
ns
Output skew
Part-to-part skew
‡
t
t
t
t
t
3
ns
sk(pp)
PZH
PHZ
PZL
Propagation delay time, high-impedance-to-high-level output
Propagation delay time, high-level-output-to-high impedance
Propagation delay time, high-impedance-to-low-level output
Propagation delay time, low-level-output-to-high impedance
See Figure 5
See Figure 6
25
25
30
20
ns
ns
ns
ns
PLZ
†
‡
Output skew (t
Part-to-part skew (t
) is the magnitude of the time delay difference between the outputs of a single device with all of the inputs connected together.
sk(o)
) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when
sk(pp)
both devices operate with the same input signals, the same supply voltages, at the same temperature, and have identical packages and test
circuits.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LBC172A, SN75LBC172A
QUADRUPLE RS-485 DIFFERENTIAL LINE DRIVERS
SLLS447B – OCTOBER 2000 – REVISED MAY 2003
PARAMETER MEASUREMENT INFORMATION
I
OY
Y
Z
I
I
A
V
V
OD
54 Ω
I
V
OY
OZ
GND
V
I
OZ
Figure 1. Test Circuit, V
Without Common-Mode Loading
OD
375 Ω
Y
A
V
OD
V
TEST
= –7 V to 12 V
Input
60 Ω
375 Ω
Z
V
TEST
V
I
Figure 2. Test Circuit, V
With Common-Mode Loading
OD
27 Ω
Y
A
27 Ω
Z
V
OC
Signal
Generator
‡
= 50 pF
C
50 Ω
L
†
†
‡
PRR = 1 MHz, 50% duty cycle, t < 6 ns, t < 6 ns, Z = 50 Ω
r
f
O
Includes probe and jig capacitance
Figure 3. V
Test Circuit
OC
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LBC172A, SN75LBC172A
QUADRUPLE RS-485 DIFFERENTIAL LINE DRIVERS
SLLS447B – OCTOBER 2000 – REVISED MAY 2003
Y
A
‡
C = 50 pF
L
V
OD
R
= 54 Ω
L
Z
Signal
Generator
50 Ω
†
†
‡
PRR = 1 MHz, 50% duty cycle, t < 6 ns, t < 6 ns, Z = 50 Ω
r
f
O
Includes probe and jig capacitance
3 V
1.5 V
0 V
Input
t
t
PHL
PLH
≈ 1.5 V
90%
0 V
10%
Output
≈ –1.5 V
t
t
f
r
Figure 4. Output Switching Test Circuit and Waveforms
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LBC172A, SN75LBC172A
QUADRUPLE RS-485 DIFFERENTIAL LINE DRIVERS
SLLS447B – OCTOBER 2000 – REVISED MAY 2003
PARAMETER MEASUREMENT INFORMATION
Y
S1
A
Output
0 V or 3 V w
Z
‡
C
= 50 pF
R
= 110 Ω
L
L
Input
G
G
Signal
Generator
50 Ω
†
3 V
†
‡
§
PRR = 1 MHz, 50% duty cycle, t < 6 ns, t < 6 ns, Z = 50 Ω
Includes probe and jig capacitance
3-V if testing Y output, 0 V if testing Z output
r
f
O
3 V
1.5 V
0 V
Input
t
0.5 V
PZH
V
OH
2.3 V
0 V
Output
t
PHZ
Figure 5. Enable Timing Test Circuit and Waveforms, t
and t
PHZ
PZH
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LBC172A, SN75LBC172A
QUADRUPLE RS-485 DIFFERENTIAL LINE DRIVERS
SLLS447B – OCTOBER 2000 – REVISED MAY 2003
PARAMETER MEASUREMENT INFORMATION
5 V
R
= 110 Ω
L
Y
Z
S1
A
Output
0 V or 3 V w
‡
= 50 pF
C
L
Input
G
G
Signal
Generator
50 Ω
†
3 V
†
‡
§
PRR = 1 MHz, 50% duty cycle, t < 6 ns, t < 6 ns, Z = 50 Ω
Includes probe and jig capacitance
3-V if testing Y output, 0 V if testing Z output
r
f
O
3 V
1.5 V
0 V
Input
t
PZL
t
PLZ
5 V
Output
2.3 V
V
OL
0.5 V
Figure 6. Enable Timing Test Circuit and Waveforms, t
and t
PLZ
PZL
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LBC172A, SN75LBC172A
QUADRUPLE RS-485 DIFFERENTIAL LINE DRIVERS
SLLS447B – OCTOBER 2000 – REVISED MAY 2003
Y
I
O
V
I
Z
V
TEST
Voltage Source
= –7 V to 12 V
V
TEST
Slew Rate ≤ 1.2 V/µs
Figure 7. Test Circuit, Short-Circuit Output Current
Y
Z
V
TEST
100 Ω
0 V
15 µs
–V
TEST
Pulse Generator
15 µs Duration,
1% Duty Cycle
1.5 ms
Figure 8. Test Circuit and Waveform, Transient Over-Voltage
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LBC172A, SN75LBC172A
QUADRUPLE RS-485 DIFFERENTIAL LINE DRIVERS
SLLS447B – OCTOBER 2000 – REVISED MAY 2003
TYPICAL CHARACTERISTICS
DIFFERENTIAL OUTPUT VOLTAGE
DIFFERENTIAL OUTPUT VOLTAGE
vs
vs
OUTPUT CURRENT
FREE-AIR TEMPERATURE
4
2.5
3.5
3
V
CC
= 5.25 V
2
V
CC
= 5 V
V
CC
= 5.25 V
2.5
2
1.5
V
CC
= 5 V
V
CC
= 4.75 V
1
0.5
0
1.5
1
V
= 4.75 V
CC
0.5
0
0
20
40
60
80
100
–60 –40 –20
0
20
40
60
80
100
I
O
– Output Current – mA
T
A
– Free-Air Temperature – °C
Figure 9
Figure 10
PROPAGATION DELAY TIME
SUPPLY CURRENT (FOUR CHANNELS)
vs
vs
TEMPERATURE
SIGNALING RATE
8.5
144
142
140
138
136
134
132
130
128
R
C
= 54 Ω
= 50 pF
L
L
8
(Each Channel)
V
= 5.25 V
CC
7.5
V
= 4.75 V
CC
7
6.5
6
5.5
5
–40
–20
0
20
40
60
80
1
10
100
T – Temperature – °C
Signaling Rate – Mbps
Figure 11
Figure 12
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LBC172A, SN75LBC172A
QUADRUPLE RS-485 DIFFERENTIAL LINE DRIVERS
SLLS447B – OCTOBER 2000 – REVISED MAY 2003
TYPICAL CHARACTERISTICS
R
C
= 54 Ω
= 50 pF
L
L
Figure 13. Eye Pattern, Pseudorandom Data at 30 Mbps
APPLICATION INFORMATION
TMS320F243
DSP
SN65LBC172A
SN65LBC175A
TMS320F241
DSP
(Controller)
(Embedded
Application)
SPISIMO
SPISIMO
IOPA1
(Enable)
SPISTE
SPISTE
IOPA1
IOPA2
SPICLK
SPICLK
IOPA0
IOPA0
(Handshake
/Status)
SPISOMI
SPISOMI
Figure 14. Typical Application Circuit, DSP-to-DSP Link via Serial Peripheral Interface
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LBC172A, SN75LBC172A
QUADRUPLE RS-485 DIFFERENTIAL LINE DRIVERS
SLLS447B – OCTOBER 2000 – REVISED MAY 2003
MECHANICAL DATA
DW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
16 PINS SHOWN
0.050 (1,27)
16
0.020 (0,51)
0.010 (0,25)
M
0.014 (0,35)
9
0.419 (10,65)
0.400 (10,15)
0.010 (0,25) NOM
0.299 (7,59)
0.291 (7,39)
Gage Plane
0.010 (0,25)
1
8
0°–ā8°
0.050 (1,27)
0.016 (0,40)
A
Seating Plane
0.004 (0,10)
0.012 (0,30)
0.004 (0,10)
0.104 (2,65) MAX
PINS **
16
20
24
28
0.710
DIM
0.410
0.510
0.610
A MAX
A MIN
(10,41) (12,95) (15,49) (18,03)
0.400
0.500
0.600
0.700
(10,16) (12,70) (15,24) (17,78)
4040000/D 01/00
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
D. Falls within JEDEC MS-013
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN65LBC172A, SN75LBC172A
QUADRUPLE RS-485 DIFFERENTIAL LINE DRIVERS
SLLS447B – OCTOBER 2000 – REVISED MAY 2003
MECHANICAL DATA
N (R-PDIP-T**)
PLASTIC DUAL-IN-LINE PACKAGE
16 PINS SHOWN
PINS **
14
16
18
20
DIM
0.775
(19,69)
0.775
(19,69)
0.920
(23,37)
0.975
(24,77)
A MAX
A
16
9
0.745
(18,92)
0.745
(18,92)
0.850
(21,59)
0.940
(23,88)
A MIN
0.260 (6,60)
0.240 (6,10)
1
8
0.070 (1,78) MAX
0.325 (8,26)
0.300 (7,62)
0.035 (0,89) MAX
0.020 (0,51) MIN
0.015 (0,38)
Gauge Plane
0.200 (5,08) MAX
Seating Plane
0.010 (0,25) NOM
0.125 (3,18) MIN
0.100 (2,54)
0.010 (0,25)
0.430 (10,92) MAX
0.021 (0,53)
0.015 (0,38)
M
14/18 PIN ONLY
4040049/D 02/00
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-001 (20-pin package is shorter than MS-001).
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
12-Jan-2006
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
SOIC
SOIC
SOIC
SOIC
PDIP
SOIC
SOIC
SOIC
SOIC
PDIP
Drawing
DW
DW
DW
DW
N
SN65LBC172A16DW
SN65LBC172A16DWR
SN65LBC172ADW
SN65LBC172ADWR
SN65LBC172AN
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
16
16
20
20
16
16
16
20
20
16
40
2000
25
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
CU NIPDAU Level-1-220C-UNLIM
CU NIPDAU Level-1-220C-UNLIM
CU NIPDAU Level-1-220C-UNLIM
CU NIPDAU Level-1-220C-UNLIM
2000
25
CU NIPD
N / A for Pkg Type
SN75LBC172A16DW
SN75LBC172A16DWR
SN75LBC172ADW
SN75LBC172ADWR
SN75LBC172AN
DW
DW
DW
DW
N
40
CU NIPDAU Level-1-220C-UNLIM
CU NIPDAU Level-1-220C-UNLIM
CU NIPDAU Level-1-220C-UNLIM
CU NIPDAU Level-1-220C-UNLIM
2000
25
2000
25
CU NIPD
N / A for Pkg Type
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
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incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
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