SN74SSTV32852_09 [TI]
24-BIT TO 48-BIT REGISTERED BUFFER WITH SSTL_2 INPUTS AND OUTPUTS;
| 型号： | SN74SSTV32852_09 |
| 厂家： | 
TEXAS INSTRUMENTS |
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SN74SSTV32852-EP
24-BIT TO 48-BIT REGISTERED BUFFER
WITH SSTL_2 INPUTS AND OUTPUTS
www.ti.com
SCES700–OCTOBER 2007
1
FEATURES
2
•
Controlled Baseline
•
•
•
•
Supports SSTL_2 Data Inputs
–
One Assembly/Test Site, One Fabrication
Site
Outputs Meet SSTL_2 Class II Specifications
Differential Clock (CLK and CLK) Inputs
•
•
Extended Temperature Performance of –40°C
to 85°C
Supports LVCMOS Switching Levels on the
RESET Input
Enhanced Diminishing Manufacturing Sources
(DMS) Support
•
RESET Input Disables Differential Input
Receivers, Resets All Registers, and Forces
All Outputs Low
•
•
•
Enhanced Product-Change Notification
(1)
Qualification Pedigree
•
•
•
Pinout Optimizes DIMM PCB Layout
One Device Per DIMM Required
Member of the Texas Instruments Widebus™
Family
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
•
1-to-2 Outputs Support Stacked DDR DIMMs
(1) Component qualification in accordance with JEDEC and
industry standards to ensure reliable operation over an
extended temperature range. This includes, but is not limited
to, Highly Accelerated Stress Test (HAST) or biased 85/85,
temperature cycle, autoclave or unbiased HAST,
•
ESD Protection Exceeds JESD 22
–
–
2000-V Human-Body Model (A114-A)
1000-V Charged-Device Model (C101)
electromigration, bond intermetallic life, and mold compound
life. Such qualification testing should not be viewed as
justifying use of this component beyond specified
performance and environmental limits.
DESCRIPTION/ORDERING INFORMATION
This 24-bit to 48-bit registered buffer is designed for 2.3-V to 2.7-V VCC operation.
All inputs are SSTL_2, except the LVCMOS reset (RESET) input. All outputs are SSTL_2, Class II compatible.
The SN74SSTV32852 operates from a differential clock (CLK and CLK). Data are registered at the crossing of
CLK going high and CLK going low.
The device supports low-power standby operation. When RESET is low, the differential input receivers are
disabled, and undriven (floating) data, clock, and reference voltage (VREF) inputs are allowed. In addition, when
RESET is low, all registers are reset and all outputs are forced low. The LVCMOS RESET input always must be
held at a valid logic high or low level.
To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held in the
low state during power up.
ORDERING INFORMATION(1)
TA
PACKAGE(2)
ORDERABLE PART NUMBER
TOP-SIDE MARKING
SV852IEP
–40°C to 85°C
LFBGA – GKF Tape and reel
CSSTV32852GKFREP
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
(2) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/packaging.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
Widebus is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007, Texas Instruments Incorporated
SN74SSTV32852-EP
24-BIT TO 48-BIT REGISTERED BUFFER
WITH SSTL_2 INPUTS AND OUTPUTS
www.ti.com
SCES700–OCTOBER 2007
GKF PACKAGE
(TOP VIEW)
Terminal Assignments
1
2
3
4
5
6
1
2
3
4
5
6
A
B
C
D
E
F
Q2A
Q3A
Q5A
Q7A
Q8A
Q10A
Q12A
Q13A
Q14A
Q17A
Q18A
Q20A
Q22A
Q23A
Q24A
D2
Q1A
VDDQ
Q4A
Q6A
GND
Q9A
Q11A
VCC
CLK
CLK
GND
VDDQ
GND
VDDQ
VDDQ
GND
VDDQ
GND
VDDQ
GND
GND
VDDQ
GND
VREF
D18
Q1B
VDDQ
Q4B
Q6B
GND
Q9B
Q11B
VCC
Q2B
GND
VDDQ
GND
VDDQ
VDDQ
GND
VDDQ
GND
VDDQ
GND
GND
VDDQ
GND
RESET
D6
Q3B
A
B
C
D
Q5B
Q7B
Q8B
Q10B
Q12B
Q13B
Q14B
Q17B
Q18B
Q20B
Q22B
Q23B
Q24B
D14
E
F
G
H
J
G
H
J
Q15A
Q16A
Q19A
VDDQ
Q21A
VDDQ
VCC
Q15B
Q16B
Q19B
VDDQ
Q21B
VDDQ
VCC
K
L
M
N
P
R
T
K
L
M
N
P
R
T
D1
D13
U
V
W
D4
D3
D10
D22
D15
D16
D5
D7
D11
D23
D19
D17
D8
D9
D12
D24
D21
D20
U
V
W
FUNCTION TABLE
INPUTS
OUTPUT
Q
RESET
CLK
CLK
D
H
L
H
H
H
L
↑
↑
↓
↓
H
L
L or H
L or H
X
Q0
L
X or floating X or floating X or floating
2
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Copyright © 2007, Texas Instruments Incorporated
Product Folder Link(s): SN74SSTV32852-EP
SN74SSTV32852-EP
24-BIT TO 48-BIT REGISTERED BUFFER
WITH SSTL_2 INPUTS AND OUTPUTS
www.ti.com
SCES700–OCTOBER 2007
LOGIC DIAGRAM (POSITIVE LOGIC)
R3
RESET
A3
A4
CLK
CLK
R4
VREF
One of 24 Channels
T2
D1
A2
A5
Q1A
Q1B
1D
C1
R
To 23 Other Channels
ABSOLUTE MAXIMUM RATINGS(1)
over operating free-air temperature range (unless otherwise noted)
VALUE
UNIT
VCC or
Supply voltage range
VDDQ
–0.5 to 3.6
V
VI
Input voltage range(2)(3)
Output voltage range(2)(3)
–0.5 to VCC + 0.5
V
V
VO
IIK
IOK
IO
–0.5 to VDDQ + 0.5
Input clamp current
VI < 0
–50
±50
mA
mA
mA
mA
°C/W
°C
Output clamp current
VO < 0 or VO > VDDQ
VO = 0 to VDDQ
Continuous output current
Continuous current through each VCC, VDDQ, or GND
Package thermal impedance(4)
Storage temperature range
±50
±100
θJA
36
Tstg
–65 to 150
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
(3) This value is limited to 3.6 V maximum.
(4) The package thermal impedance is calculated in accordance with JESD 51-7.
Copyright © 2007, Texas Instruments Incorporated
Submit Documentation Feedback
3
Product Folder Link(s): SN74SSTV32852-EP
SN74SSTV32852-EP
24-BIT TO 48-BIT REGISTERED BUFFER
WITH SSTL_2 INPUTS AND OUTPUTS
www.ti.com
SCES700–OCTOBER 2007
RECOMMENDED OPERATING CONDITIONS(1)
MIN
NOM
MAX
UNIT
V
VCC
VDDQ
VREF
VTT
VI
Supply voltage
VDDQ
2.7
2.7
Output supply voltage
2.3
1.15
V
Reference voltage (VREF = VDDQ/2)
Termination voltage
1.25
1.35
V
VREF – 40 mV
0
VREF
VREF + 40 mV
VCC
V
Input voltage
V
VIH
AC high-level input voltage
AC low-level input voltage
DC high-level input voltage
DC low-level input voltage
High-level input voltage
Low-level input voltage
Common-mode input voltage range
Peak-to-peak input voltage
High-level output current
Low-level output current
Operating free-air temperature
Data inputs
Data inputs
Data inputs
Data inputs
RESET
VREF + 310 mV
V
VIL
VREF – 310 mV
VREF – 150 mV
V
VIH
VREF + 150 mV
1.7
V
VIL
V
VIH
V
VIL
RESET
0.7
V
VICR
VI(PP)
IOH
CLK, CLK
CLK, CLK
0.97
360
1.53
V
mV
–20
20
mA
IOL
TA
-40
85
°C
(1) The RESET input of the device must be held at valid logic voltage levels (not floating) to ensure proper device operation. The differential
inputs must not be floating unless RESET is low. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs,
literature number SCBA004.
ELECTRICAL CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
2.3 V
MIN TYP(1)
MAX
UNIT
V
VIK
II = –18 mA
–1.2
IOH = –100 μA
2.3 V to 2.7 V
2.3 V
VDDQ – 0.2
V
VOH
IOH = –16 mA
1.95
IOL = 100 μA
2.3 V to 2.7 V
2.3 V
0.2
0.35
±5
V
VOL
II
IOL = 16 mA
All inputs
VI = VCC or GND
RESET = GND
2.7 V
μA
μA
Static standby
Static operating
IO = 0
IO = 0
10
ICC
2.7 V
RESET = VCC, VI= VIH(AC) or VIL(AC)
35
mA
RESET = VCC, VI = VIH(AC) or VIL(AC)
CLK and CLK switching 50% duty
cycle
,
Dynamic operating –
clock only
μA/
MHz
46
12
RESET = VCC, VI = VIH(AC) or VIL(AC)
CLK and CLK switching 50% duty
cycle, one data input switching at
one-half clock frequency, 50% duty
cycle
,
ICCD
2.7 V
μA/
clock
MHz/
D input
Dynamic operating –
per each data input
rOH
rOL
Output high
Output low
Data inputs
CLK, CLK
RESET
IOH = –20 mA
2.3 V to 2.7 V
2.3 V to 2.7 V
7
7
20
20
Ω
Ω
IOL = 20 mA
VI = VREF ± 310 mV
VICR = 1.25 V, VI(PP) = 360 mV
VI = VCC or GND
3
3.75
3.5
4.25
4
CI
2.5 V
3
pF
3.5
4.35
5
(1) All typical values are at VCC = 2.5 V, TA = 25°C.
4
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Copyright © 2007, Texas Instruments Incorporated
Product Folder Link(s): SN74SSTV32852-EP
SN74SSTV32852-EP
24-BIT TO 48-BIT REGISTERED BUFFER
WITH SSTL_2 INPUTS AND OUTPUTS
www.ti.com
SCES700–OCTOBER 2007
TIMING REQUIREMENTS
over operating free-air temperature range (unless otherwise noted) (see Figure 1)
VCC = 2.5 V
±0.2 V
UNIT
MIN
MAX
fclock
tw
Clock frequency
200
MHz
ns
Pulse duration, CLK, CLK high or low
Differential inputs active time(1)
Differential inputs inactive time(2)
2.5
tact
22
22
ns
tinact
ns
Fast slew rate(3)(4)
Slow slew rate(5)(4)
Fast slew rate(3)(4)
Slow slew rate(5)(4)
0.75
0.9
tsu
Setup time
Data before CLK↑, CLK↓
Data after CLK↑, CLK↓
ns
ns
0.75
0.9
th
Hold time
(1) VREF must be held at a valid input level, and data inputs must be held low for a minimum time of tact max, after RESET is taken high.
(2) VREF, data, and clock inputs must be held at valid voltage levels (not floating) for a minimum time of tinact max, after RESET is taken low.
(3) Data signal input slew rate ≥1 V/ns
(4) CLK, CLK input slew rates are ≥1 V/ns.
(5) Data signal input slew rate ≥0.5 V/ns and <1 V/ns
SWITCHING CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted) (see Figure 1)
VCC = 2.5 V
±0.2 V
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN
MAX
fmax
tpd
200
MHz
ns
CLK and CLK
RESET
Q
Q
1.1
3.1
5
tPHL
ns
Copyright © 2007, Texas Instruments Incorporated
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Product Folder Link(s): SN74SSTV32852-EP
SN74SSTV32852-EP
24-BIT TO 48-BIT REGISTERED BUFFER
WITH SSTL_2 INPUTS AND OUTPUTS
www.ti.com
SCES700–OCTOBER 2007
PARAMETER MEASUREMENT INFORMATION
VTT
50 Ω
Test Point
From Output
Under Test
CL = 30 pF
(see Note A)
LOAD CIRCUIT
tw
VIH
VREF
VREF
Input
VIL
VCC
0 V
LVCMOS
RESET
Input
VCC/2
VCC/2
VOLTAGE WAVEFORMS
PULSE DURATION
VI(PP)
tinact
tact
Timing
Input
VICR
VICR
ICC (operating)
ICC (standby)
ICC
(see
90%
Note B)
10%
tPLH
tPHL
VOLTAGE AND CURRENT WAVEFORMS
INPUTS ACTIVE AND INACTIVE TIMES
VOH
VOL
Output
VTT
VTT
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VI(PP)
VIH
VIL
Timing
Input
LVCMOS
RESET
Input
VICR
VCC/2
tPHL
tsu
th
VOH
VOL
VIH
VIL
VREF
Input
VREF
Output
VTT
VOLTAGE WAVEFORMS
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. ICC tested with clock and data inputs held at VCC or GND, and IO = 0 mA.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 Mhz, ZO = 50 Ω,
Input slew rate = 1 V/ns 20% (unless otherwise noted).
D. The outputs are measured one at a time with one transition per measurement.
E. VTT = VREF = VDDQ/2
F. VIH = VREF + 310 mV (ac voltage levels) for differential inputs. VIH = VCC for LVCMOS input.
G. VIL = VREF − 310 mV (ac voltage levels) for differential inputs. VIL = GND for LVCMOS input.
H. tPLH and tPHL are the same as tpd
.
Figure 1. Load Circuit and Voltage Waveforms
6
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Product Folder Link(s): SN74SSTV32852-EP
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Apr-2009
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) W1 (mm)
(mm) (mm) Quadrant
CSSTV32852GKFREP BGA MI
GKF
114
1000
330.0
24.4
5.8
16.3
1.8
8.0
24.0
Q1
CROSTA
R
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Apr-2009
*All dimensions are nominal
Device
Package Type Package Drawing Pins
GKF 114
SPQ
Length (mm) Width (mm) Height (mm)
346.0 346.0 41.0
CSSTV32852GKFREP BGA MICROSTAR
1000
Pack Materials-Page 2
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