SN74LVTH574PWRE4 [TI]
3.3V ABT OCTAL EDGE-TRIGGERED D-TYPE FLIP FLOPS WITH 3 STATE OUTPUTS; 3.3V ABT八路边沿触发D型触发器具有三态输出型号: | SN74LVTH574PWRE4 |
厂家: | TEXAS INSTRUMENTS |
描述: | 3.3V ABT OCTAL EDGE-TRIGGERED D-TYPE FLIP FLOPS WITH 3 STATE OUTPUTS |
文件: | 总23页 (文件大小:744K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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SCBS688G − MAY 1997 − REVISED SEPTEMBER 2003
D
D
D
D
Support Mixed-Mode Signal Operation (5-V
Input and Output Voltages With 3.3-V V
D
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
)
CC
Support Unregulated Battery Operation
Down to 2.7 V
D
D
Latch-Up Performance Exceeds 500 mA Per
JESD 17
Typical V
<0.8 V at V
(Output Ground Bounce)
OLP
CC
= 3.3 V, T = 25°C
ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
A
I
and Power-Up 3-State Support Hot
off
Insertion
SN54LVTH574 . . . FK PACKAGE
(TOP VIEW)
SN74LVTH574 . . . RGY PACKAGE
(TOP VIEW)
SN54LVTH574 . . . J OR W PACKAGE
SN74LVTH574 . . . DB, DW, NS,
OR PW PACKAGE
(TOP VIEW)
1
20
3
2
1 20 19
18
OE
1D
2D
3D
4D
5D
6D
7D
8D
V
CC
1
2
3
4
5
6
7
8
9
10
20
19
18
17
2Q
3Q
4Q
5Q
6Q
3D
4D
5D
6D
7D
4
5
6
7
8
19
18
17
16
15
14
13
12
2
3
4
5
6
7
8
9
1D
2D
3D
4D
5D
6D
7D
8D
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
1Q
2Q
3Q
17
16
15
14
16 4Q
15 5Q
9 10 11 12 13
14
13
12
11
6Q
7Q
8Q
CLK
10
11
GND
description/ordering information
These octal flip-flops are designed specifically for low-voltage (3.3-V) V
provide a TTL interface to a 5-V system environment.
operation, but with the capability to
CC
ORDERING INFORMATION
ORDERABLE
TOP-SIDE
MARKING
†
PACKAGE
T
A
PART NUMBER
SN74LVTH574RGYR
SN74LVTH574DW
SN74LVTH574DWR
SN74LVTH574NSR
SN74LVTH574DBR
SN74LVTH574PW
SN74LVTH574PWR
SN74LVTH574GQNR
SN74LVTH574ZQNR
SNJ54LVTH574J
QFN − RGY
SOIC − DW
Tape and reel
Tube
LXH574
LVTH574
Tape and reel
Tape and reel
Tape and reel
Tube
SOP − NS
LVTH574
LXH574
SSOP − DB
−40°C to 85°C
TSSOP − PW
LXH574
LXH574
Tape and reel
VFBGA − GQN
Tape and reel
VFBGA − ZQN (Pb-free)
CDIP − J
Tube
Tube
Tube
SNJ54LVTH574J
SNJ54LVTH574W
SNJ54LVTH574FK
CFP − W
SNJ54LVTH574W
SNJ54LVTH574FK
−55°C to 125°C
LCCC − FK
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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Copyright 2003, Texas Instruments Incorporated
ꢏ ꢜ ꢧ ꢟ ꢞꢪ ꢥꢤ ꢢꢣ ꢤꢞ ꢠꢧ ꢩꢛ ꢡꢜ ꢢ ꢢꢞ ꢰꢕ ꢄꢌ ꢗꢔ ꢘ ꢌꢊꢱꢂ ꢊꢂꢉ ꢡꢩꢩ ꢧꢡ ꢟ ꢡ ꢠꢦ ꢢꢦꢟ ꢣ ꢡ ꢟ ꢦ ꢢꢦ ꢣꢢꢦ ꢪ
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1
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ꢊꢋ ꢊꢌꢅ ꢍ ꢎꢆ ꢏꢐ ꢆꢍꢄ ꢑ ꢒꢓ ꢑꢌꢆ ꢔꢕ ꢓꢓ ꢑꢔ ꢑꢒ ꢒꢌꢆ ꢖꢗ ꢑ ꢘ ꢄꢕ ꢗꢌꢘ ꢄ ꢏ ꢗꢀ
ꢙꢕ ꢆ ꢇ ꢊ ꢌꢀꢆꢍꢆ ꢑ ꢏꢚꢆ ꢗꢚ ꢆꢀ
SCBS688G − MAY 1997 − REVISED SEPTEMBER 2003
description/ordering information (continued)
The eight flip-flops of the ’LVTH574 devices are edge-triggered D-type flip-flops. On the positive transition of
the clock (CLK) input, the Q outputs are set to the logic levels set up at the data (D) inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high
or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive
the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus
lines without need for interface or pullup components.
OE does not affect the internal operations of the flip-flops. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to V
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
through a pullup
CC
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. Use of pullup
or pulldown resistors with the bus-hold circuitry is not recommended.
These devices are fully specified for hot-insertion applications using I and power-up 3-state. The I circuitry
off
off
disables the outputs, preventing damaging current backflow through the devices when they are powered down.
The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,
which prevents driver conflict.
SN74LVTH574 . . . GQN OR ZQN PACKAGE
(TOP VIEW)
terminal assignments
1
2
3
4
1
1D
2
3
4
A
B
C
D
E
A
B
C
D
E
OE
3Q
4D
7Q
8D
V
1Q
2Q
4Q
6Q
8Q
CC
3D
2D
5Q
5D
7D
6D
GND
CLK
FUNCTION TABLE
(each flip-flop)
INPUTS
OUTPUT
Q
OE
L
CLK
D
H
L
↑
↑
H
L
L
L
H or L
X
X
X
Q
0
H
Z
2
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ꢙ ꢕꢆ ꢇ ꢊ ꢌꢀꢆꢍꢆ ꢑ ꢏ ꢚꢆ ꢗ ꢚꢆ
SCBS688G − MAY 1997 − REVISED SEPTEMBER 2003
logic diagram (positive logic)
1
OE
11
CLK
C1
1D
19
1Q
2
1D
To Seven Other Channels
Pin numbers shown are for the DB, DW, FK, J, NS, PW, RGY, and W packages.
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
I
Voltage range applied to any output in the high-impedance
or power-off state, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
O
Voltage range applied to any output in the high state, V (see Note 1) . . . . . . . . . . . . . −0.5 V to V
+ 0.5 V
O
CC
Current into any output in the low state, I : SN54LVTH574 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA
O
SN74LVTH574 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Current into any output in the high state, I (see Note 2): SN54LVTH574 . . . . . . . . . . . . . . . . . . . . . . . 48 mA
O
SN74LVTH574 . . . . . . . . . . . . . . . . . . . . . . . 64 mA
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
IK
OK
I
Output clamp current, I
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
O
Package thermal impedance, θ (see Note 3): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W
JA
(see Note 3): DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
(see Note 3): GQN/ZQN package . . . . . . . . . . . . . . . . . . . . . . . . . . . 78°C/W
(see Note 3): NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60°C/W
(see Note 3): PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83°C/W
(see Note 4): RGY package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This current flows only when the output is in the high state and V > V
.
CC
O
3. The package thermal impedance is calculated in accordance with JESD 51-7.
4. The package thermal impedance is calculated in accordance with JESD 51-5.
3
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ꢀ ꢁꢂ ꢃꢄꢅꢆ ꢇ ꢂ ꢈ ꢃꢉ ꢀ ꢁꢈ ꢃ ꢄꢅ ꢆꢇ ꢂꢈ ꢃ
ꢊꢋ ꢊꢌꢅ ꢍ ꢎꢆ ꢏꢐ ꢆꢍꢄ ꢑ ꢒꢓ ꢑꢌꢆ ꢔꢕ ꢓꢓ ꢑꢔ ꢑꢒ ꢒꢌꢆ ꢖꢗ ꢑ ꢘ ꢄꢕ ꢗꢌꢘ ꢄ ꢏ ꢗꢀ
ꢙꢕ ꢆ ꢇ ꢊ ꢌꢀꢆꢍꢆ ꢑ ꢏꢚꢆ ꢗꢚ ꢆꢀ
SCBS688G − MAY 1997 − REVISED SEPTEMBER 2003
recommended operating conditions (see Note 5)
SN54LVTH574 SN74LVTH574
UNIT
MIN
2.7
2
MAX
MIN
2.7
2
MAX
V
V
V
V
Supply voltage
3.6
3.6
V
V
CC
High-level input voltage
Low-level input voltage
Input voltage
IH
0.8
5.5
−24
48
0.8
5.5
−32
64
V
IL
V
I
I
I
High-level output current
Low-level output current
Input transition rise or fall rate
Power-up ramp rate
mA
mA
ns/V
µs/V
°C
OH
OL
∆t/∆v
∆t/∆V
Outputs enabled
10
10
200
−55
200
−40
CC
T
A
Operating free-air temperature
125
85
NOTE 5: All unused control inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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ꢙ ꢕꢆ ꢇ ꢊ ꢌꢀꢆꢍꢆ ꢑ ꢏ ꢚꢆ ꢗ ꢚꢆ
SCBS688G − MAY 1997 − REVISED SEPTEMBER 2003
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54LVTH574
SN74LVTH574
PARAMETER
TEST CONDITIONS
I = −18 mA
UNIT
†
†
MIN TYP
MAX
MIN TYP
MAX
V
V
V
V
V
= 2.7 V,
−1.2
−1.2
V
IK
CC
CC
CC
I
= 2.7 V to 3.6 V,
= 2.7 V,
I
I
I
I
I
I
I
I
I
I
= −100 µA
= −8 mA
= −24 mA
= −32 mA
= 100 µA
= 24 mA
= 16 mA
= 32 mA
= 48 mA
= 64 mA
V
−0.2
CC
2.4
V
−0.2
CC
2.4
OH
OH
OH
OH
OL
OL
OL
OL
OL
OL
V
V
OH
2
V
= 3 V
CC
CC
2
0.2
0.5
0.2
0.5
0.4
0.5
V
= 2.7 V
0.4
V
OL
0.5
V
CC
= 3 V
0.55
0.55
10
1
V
V
= 0 or 3.6 V,
= 3.6 V,
V = 5.5 V
10
1
CC
I
Control inputs
V = V
or GND
CC
I
CC
I
I
µA
V = V
1
1
I
CC
Data inputs
V
V
= 3.6 V
= 0,
CC
V = 0
I
−5
−5
100
I
I
V or V = 0 to 4.5 V
µA
µA
off
CC
I
O
V = 0.8 V
I
75
75
V
CC
= 3 V
V = 2 V
I
−75
−75
Data inputs
I(hold)
‡
V
V
V
V
= 3.6 V ,
V = 0 to 3.6 V
500
5
CC
CC
CC
CC
I
I
I
= 3.6 V,
= 3.6 V,
V
O
V
O
= 3 V
5
µA
µA
OZH
= 0.5 V
−5
−5
OZL
= 0 to 1.5 V, V = 0.5 V to 3 V,
OE = don’t care
O
100*
100*
100
100
µA
µA
I
OZPU
OZPD
V
= 1.5 V to 0, V = 0.5 V to 3 V,
CC
OE = don’t care
O
I
Outputs high
Outputs low
0.19
5
0.19
5
V
I
= 3.6 V,
CC
= 0,
I
mA
mA
O
CC
V = V
I
or GND
CC
Outputs disabled
0.19
0.19
V
= 3 V to 3.6 V, One input at V − 0.6 V,
CC
CC
Other inputs at V
§
0.2
0.2
∆I
CC
or GND
CC
C
C
V = 3 V or 0
3
7
3
7
pF
pF
i
I
V
O
= 3 V or 0
o
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
†
All typical values are at V
= 3.3 V, T = 25°C.
A
CC
‡
§
This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another.
This is the increase in supply current for each input that is at the specified TTL voltage level, rather than V
or GND.
CC
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄꢅꢆ ꢇ ꢂ ꢈ ꢃꢉ ꢀ ꢁꢈ ꢃ ꢄꢅ ꢆꢇ ꢂꢈ ꢃ
ꢊꢋ ꢊꢌꢅ ꢍ ꢎꢆ ꢏꢐ ꢆꢍꢄ ꢑ ꢒꢓ ꢑꢌꢆ ꢔꢕ ꢓꢓ ꢑꢔ ꢑꢒ ꢒꢌꢆ ꢖꢗ ꢑ ꢘ ꢄꢕ ꢗꢌꢘ ꢄ ꢏ ꢗꢀ
ꢙꢕ ꢆ ꢇ ꢊ ꢌꢀꢆꢍꢆ ꢑ ꢏꢚꢆ ꢗꢚ ꢆꢀ
SCBS688G − MAY 1997 − REVISED SEPTEMBER 2003
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figure 1)
SN54LVTH574
SN74LVTH574
V
= 3.3 V
V
CC
= 3.3 V
CC
V
= 2.7 V
V
= 2.7 V
UNIT
CC
CC
0.3 V
MIN MAX
150
0.3 V
MIN MAX
150
MIN
MAX
MIN
MAX
f
t
t
t
Clock frequency
150
150
MHz
ns
clock
Pulse duration, CLK high or low
Setup time, data before CLK↑
Hold time, data after CLK↑
3.3
2
3.3
2.4
0.9
3.3
2
3.3
2.4
0
w
ns
su
h
0.9
0.3
ns
switching characteristics over recommended free-air temperature, C = 50 pF (unless otherwise
L
noted) (see Figure 1)
SN54LVTH574
= 3.3 V
SN74LVTH574
V
V
CC
= 3.3 V
V
FROM
(INPUT)
TO
(OUTPUT)
CC
V
= 2.7 V
MAX
= 2.7 V
MAX
PARAMETER
UNIT
CC
CC
0.3 V
0.3 V
†
MIN
MAX
MIN
MIN TYP
MAX
MIN
f
t
t
t
t
t
t
150
1.7
1.7
1.4
1.4
1
150
150
150
MHz
ns
max
PLH
PHL
PZH
PZL
PHZ
PLZ
4.9
4.9
5.1
5.1
5.9
4.8
5.9
5.5
6.5
6.1
6.4
5.3
1.8
3
3
4.5
4.5
4.8
4.8
4.8
4.4
5.3
5.3
5.9
5.9
5.1
4.4
CLK
OE
Q
Q
Q
1.8
1.5
1.5
2
3.2
3.5
3.5
3.2
ns
ns
OE
0.8
2
†
All typical values are at V
CC
= 3.3 V, T = 25°C.
A
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
ꢇ
ꢂ
ꢈ
ꢃ
ꢉ
ꢀ
ꢁ
ꢈ
ꢃ
ꢊ ꢋꢊ ꢌꢅ ꢍꢎꢆ ꢏ ꢐꢆꢍꢄ ꢑꢒꢓ ꢑ ꢌꢆꢔ ꢕꢓ ꢓꢑ ꢔꢑꢒ ꢒꢌꢆ ꢖꢗ ꢑ ꢘ ꢄꢕ ꢗ ꢌꢘ ꢄꢏ ꢗ
ꢄ
ꢅ
ꢆ
ꢇ
ꢂ
ꢈ
ꢃ
ꢀ
ꢀ
ꢙ ꢕꢆ ꢇ ꢊ ꢌꢀꢆꢍꢆ ꢑ ꢏ ꢚꢆ ꢗ ꢚꢆ
SCBS688G − MAY 1997 − REVISED SEPTEMBER 2003
PARAMETER MEASUREMENT INFORMATION
6 V
TEST
S1
S1
Open
GND
500 Ω
From Output
Under Test
t
/t
PLH PHL
Open
6 V
t
/t
PLZ PZL
C
= 50 pF
t
/t
GND
L
PHZ PZH
500 Ω
(see Note A)
2.7 V
0 V
LOAD CIRCUIT
Timing Input
Data Input
1.5 V
t
w
t
t
h
su
2.7 V
0 V
2.7 V
0 V
Input
1.5 V
1.5 V
1.5 V
1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
2.7 V
0 V
2.7 V
0 V
Output
Control
1.5 V
1.5 V
1.5 V
1.5 V
Input
t
t
PLZ
PZL
t
t
t
PHL
PLH
PHL
Output
Waveform 1
S1 at 6 V
3 V
V
V
OH
1.5 V
1.5 V
1.5 V
1.5 V
t
Output
V
V
+ 0.3 V
OL
V
OL
OL
(see Note B)
t
t
PZH
PHZ
PLH
Output
Waveform 2
S1 at GND
V
OH
V
V
OH
− 0.3 V
OH
1.5 V
1.5 V
Output
≈0 V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. includes probe and jig capacitance.
C
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
E. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
1-Jun-2007
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
LCCC
CDIP
CFP
Drawing
5962-9583201Q2A
5962-9583201QRA
5962-9583201QSA
5962-9583201VRA
5962-9583201VSA
SN74LVTH574DBLE
SN74LVTH574DBR
ACTIVE
ACTIVE
FK
J
20
20
20
20
20
20
20
1
1
1
1
1
TBD
TBD
TBD
TBD
TBD
TBD
POST-PLATE N / A for Pkg Type
A42 SNPB
A42
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
Call TI
ACTIVE
W
J
ACTIVE
CDIP
CFP
A42 SNPB
A42
ACTIVE
W
DB
DB
OBSOLETE
ACTIVE
SSOP
SSOP
Call TI
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LVTH574DBRE4
SN74LVTH574DBRG4
SN74LVTH574DW
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
NRND
SSOP
SSOP
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
DB
DB
20
20
20
20
20
20
20
20
20
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
DW
DW
DW
DW
DW
DW
GQN
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LVTH574DWE4
SN74LVTH574DWG4
SN74LVTH574DWR
SN74LVTH574DWRE4
SN74LVTH574DWRG4
SN74LVTH574GQNR
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
BGA MI
CROSTA
R JUNI
OR
1000
TBD
SNPB
Level-1-240C-UNLIM
SN74LVTH574NSR
ACTIVE
ACTIVE
SO
NS
NS
20
20
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LVTH574NSRE4
SO
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LVTH574NSRG4
SN74LVTH574PW
ACTIVE
ACTIVE
SO
NS
20
20
2000
TBD
Call TI
Call TI
TSSOP
PW
70 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LVTH574PWE4
SN74LVTH574PWG4
ACTIVE
ACTIVE
TSSOP
TSSOP
PW
PW
20
20
70 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
70 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LVTH574PWLE
SN74LVTH574PWR
OBSOLETE TSSOP
PW
PW
20
20
TBD
Call TI
Call TI
ACTIVE
ACTIVE
ACTIVE
ACTIVE
TSSOP
TSSOP
TSSOP
QFN
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LVTH574PWRE4
SN74LVTH574PWRG4
SN74LVTH574RGYR
PW
PW
20
20
20
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
RGY
1000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
1-Jun-2007
Orderable Device
SN74LVTH574RGYRG4
SN74LVTH574ZQNR
Status (1)
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
QFN
RGY
20
1000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
BGA MI
CROSTA
R JUNI
OR
ZQN
20
1000 Green (RoHS &
no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
SNJ54LVTH574FK
SNJ54LVTH574J
SNJ54LVTH574W
ACTIVE
ACTIVE
ACTIVE
LCCC
CDIP
CFP
FK
J
20
20
20
1
1
1
TBD
TBD
TBD
POST-PLATE N / A for Pkg Type
A42 SNPB
A42
N / A for Pkg Type
N / A for Pkg Type
W
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
19-May-2007
TAPE AND REEL INFORMATION
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
19-May-2007
Device
Package Pins
Site
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) (mm) Quadrant
(mm)
330
330
330
330
330
330
180
330
330
(mm)
16
SN74LVTH574DBR
SN74LVTH574DWR
SN74LVTH574GQNR
SN74LVTH574GQNR
SN74LVTH574NSR
SN74LVTH574PWR
SN74LVTH574RGYR
SN74LVTH574ZQNR
SN74LVTH574ZQNR
DB
DW
20
20
20
20
20
20
20
20
20
MLA
MLA
HIJ
8.2
10.8
3.3
7.5
13.0
4.3
2.5
2.7
1.5
1.6
2.5
1.6
1.6
1.5
1.6
12
12
8
16
24
12
12
24
16
12
12
12
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
24
GQN
GQN
NS
12
TAI
12
3.3
4.3
8
MLA
MLA
MLA
HIJ
24
8.2
13.0
7.1
12
8
PW
16
6.95
3.8
RGY
ZQN
ZQN
12
4.8
8
12
3.3
4.3
8
TAI
12
3.3
4.3
8
TAPE AND REEL BOX INFORMATION
Device
Package
Pins
Site
Length (mm) Width (mm) Height (mm)
SN74LVTH574DBR
SN74LVTH574DWR
SN74LVTH574GQNR
SN74LVTH574GQNR
SN74LVTH574NSR
SN74LVTH574PWR
SN74LVTH574RGYR
SN74LVTH574ZQNR
SN74LVTH574ZQNR
DB
DW
20
20
20
20
20
20
20
20
20
MLA
MLA
HIJ
342.9
333.2
346.0
338.1
333.2
342.9
190.0
346.0
338.1
336.6
333.2
346.0
340.5
333.2
336.6
212.7
346.0
340.5
28.58
31.75
29.0
GQN
GQN
NS
TAI
20.64
31.75
28.58
31.75
29.0
MLA
MLA
MLA
HIJ
PW
RGY
ZQN
ZQN
TAI
20.64
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
19-May-2007
Pack Materials-Page 3
MECHANICAL DATA
MLCC006B – OCTOBER 1996
FK (S-CQCC-N**)
LEADLESS CERAMIC CHIP CARRIER
28 TERMINAL SHOWN
A
B
NO. OF
TERMINALS
**
18 17 16 15 14 13 12
MIN
MAX
MIN
MAX
0.342
(8,69)
0.358
(9,09)
0.307
(7,80)
0.358
(9,09)
19
20
11
10
9
20
28
44
52
68
84
0.442
(11,23)
0.458
(11,63)
0.406
(10,31)
0.458
(11,63)
21
B SQ
22
0.640
(16,26)
0.660
(16,76)
0.495
(12,58)
0.560
(14,22)
8
A SQ
23
0.739
(18,78)
0.761
(19,32)
0.495
(12,58)
0.560
(14,22)
7
24
25
6
0.938
(23,83)
0.962
(24,43)
0.850
(21,6)
0.858
(21,8)
5
1.141
(28,99)
1.165
(29,59)
1.047
(26,6)
1.063
(27,0)
26 27 28
1
2
3
4
0.080 (2,03)
0.064 (1,63)
0.020 (0,51)
0.010 (0,25)
0.020 (0,51)
0.010 (0,25)
0.055 (1,40)
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.045 (1,14)
0.035 (0,89)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
4040140/D 10/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid.
D. The terminals are gold plated.
E. Falls within JEDEC MS-004
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
M
0,15
15
0,25
0,09
5,60
5,00
8,20
7,40
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
0,10
2,00 MAX
0,05 MIN
PINS **
14
16
20
24
28
30
38
DIM
6,50
5,90
6,50
5,90
7,50
8,50
7,90
10,50
9,90
10,50 12,90
A MAX
A MIN
6,90
9,90
12,30
4040065 /E 12/01
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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相关型号:
SN74LVTH646DBR
LVT SERIES, 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO24, GREEN, PLASTIC, SSOP-24
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SN74LVTH646DBRG4
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