SN74LVTH646 [TI]
3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS; 3.3 -V ABT八路总线收发器和寄存器具有三态输出型号: | SN74LVTH646 |
厂家: | TEXAS INSTRUMENTS |
描述: | 3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS |
文件: | 总10页 (文件大小:139K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
SN54LVTH646, SN74LVTH646
3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCBS705E – AUGUST 1997 – REVISED APRIL 1999
SN54LVTH646 . . . JT OR W PACKAGE
SN74LVTH646 . . . DB, DGV, DW, OR PW PACKAGE
(TOP VIEW)
State-of-the-Art Advanced BiCMOS
Technology (ABT) Design for 3.3-V
Operation and Low Static-Power
Dissipation
CLKAB
SAB
DIR
A1
A2
A3
A4
A5
A6
A7
A8
GND
V
CC
1
24
23
22
21
20
19
18
17
16
15
14
13
I
and Power-Up 3-State Support Hot
CLKBA
SBA
OE
B1
B2
B3
B4
B5
B6
B7
2
off
Insertion
3
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
4
5
6
7
Support Mixed-Mode Signal Operation
(5-V Input and Output Voltages With
8
9
3.3-V V
)
CC
10
11
12
Support Unregulated Battery Operation
Down to 2.7 V
B8
Typical V
< 0.8 V at V
(Output Ground Bounce)
OLP
= 3.3 V, T = 25°C
CC
A
SN54LVTH646 . . . FK PACKAGE
(TOP VIEW)
Latch-Up Performance Exceeds 500 mA Per
JESD 17
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
4
3
2
1
28 27 26
25
Package Options Include Plastic
5
A1
A2
A3
NC
A4
A5
A6
OE
B1
B2
NC
B3
B4
B5
Small-Outline (DW), Shrink Small-Outline
(DB), Thin Shrink Small-Outline (PW), and
Thin Very Small-Outline (DGV) Packages,
Ceramic Chip Carriers (FK), Ceramic Flat
(W) Package, and Ceramic (JT) DIPs
24
23
22
21
20
19
6
7
8
9
10
11
12 13 14 15 16 17 18
description
These bus transceivers and registers are
designed specifically for low-voltage (3.3-V) V
operation, but with the capability to provide a TTL
interface to a 5-V system environment.
CC
NC – No internal connection
The ’LVTH646 devices consist of bus transceiver circuits, D-type flip-flops, and control circuitry arranged for
multiplexed transmission of data directly from the input bus or from the internal registers. Data on the A or B
bus is clocked into the registers on the low-to-high transition of the appropriate clock (CLKAB or CLKBA) input.
Figure 1 illustrates the four fundamental bus-management functions that can be performed with the ’LVTH646.
Output-enable (OE) and direction-control (DIR) inputs are provided to control the transceiver functions. In the
transceiver mode, data present at the high-impedance port can be stored in either register or in both.
The select-control (SAB and SBA) inputs can multiplex stored and real-time (transparent mode) data. The
direction control (DIR) determines which bus receives data when OE is low. In the isolation mode (OE high),
A data can be stored in one register and/or B data can be stored in the other register.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 1999, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LVTH646, SN74LVTH646
3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCBS705E – AUGUST 1997 – REVISED APRIL 1999
description (continued)
When an output function is disabled, the input function is still enabled and can be used to store and transmit
data. Only one of the two buses, A or B, can be driven at a time.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
When V is between 0 and 1.5 V, the devices are in the high-impedance state during power up or power down.
CC
However, to ensure the high-impedance state above 1.5 V, OE should be tied to V
through a pullup resistor;
CC
the minimum value of the resistor is determined by the current-sinking capability of the driver.
These devices are fully specified for hot-insertion applications using I and power-up 3-state. The I circuitry
off
off
disables the outputs, preventing damaging current backflow through the devices when they are powered down.
The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,
which prevents driver conflict.
The SN54LVTH646 is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74LVTH646 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
INPUTS
DATA I/Os
OPERATION OR FUNCTION
OE
X
X
H
H
L
DIR
X
CLKAB
CLKBA
SAB
X
SBA
X
A1–A8
Input
B1–B8
†
†
†
↑
X
Unspecified
Store A, B unspecified
Store B, A unspecified
Store A and B data
†
X
X
↑
X
X
Unspecified
Input
X
↑
H or L
X
↑
H or L
X
X
X
Input
Input
X
X
X
Input disabled
Output
Input disabled
Input
Isolation, hold storage
Real-time B data to A bus
Stored B data to A bus
Real-time A data to B bus
Stored A data to B bus
L
X
L
L
L
X
H or L
X
X
H
Output
Input
L
H
H
X
L
X
Input
Output
L
H or L
X
H
X
Input
Output
†
The data-output functions can be enabled or disabled by various signals at OE and DIR. Data-input functions are always enabled; i.e., data at
the bus terminals is stored on every low-to-high transition of the clock inputs.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LVTH646, SN74LVTH646
3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCBS705E – AUGUST 1997 – REVISED APRIL 1999
21
OE
L
3
1
23
2
22
SBA
L
21
OE
L
3
DIR
H
1
23
CLKAB CLKBA SAB
L
2
22
SBA
X
DIR CLKAB CLKBA SAB
L
X
X
X
X
X
REAL-TIME TRANSFER
BUS B TO BUS A
REAL-TIME TRANSFER
BUS A TO BUS B
21
3
1
23
2
22
21
OE
L
3
DIR
L
1
23
2
22
SBA
H
DIR CLKAB CLKBA SAB
SBA
X
CLKAB CLKBA SAB
OE
X
X
X
X
X
↑
X
X
X
↑
X
X
L
L
X
H
X
H
X
X
L
H
X
X
↑
↑
STORAGE FROM
A, B, OR A AND B
TRANSFER STORED DATA
TO A AND/OR B
Pin numbers shown are for the DB, DGV, DW, JT, PW, and W packages.
Figure 1. Bus-Management Functions
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LVTH646, SN74LVTH646
3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCBS705E – AUGUST 1997 – REVISED APRIL 1999
†
logic symbol
21
OE
G3
3
DIR
3 EN1 [BA]
3 EN2 [AB]
23
22
1
CLKBA
SBA
C4
G5
C6
CLKAB
SAB
2
G7
20
4D
2
B1
5
5
≥1
4
A1
1
1
6D
7
7
≥1
1
5
19
18
17
16
15
14
13
B2
B3
B4
B5
B6
B7
B8
A2
A3
A4
A5
A6
A7
A8
6
7
8
9
10
11
†
ThissymbolisinaccordancewithANSI/IEEEStd91-1984andIECPublication617-12.
Pin numbers shown are for the DB, DGV, DW, JT, PW, and W packages.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LVTH646, SN74LVTH646
3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCBS705E – AUGUST 1997 – REVISED APRIL 1999
logic diagram (positive logic)
21
OE
3
DIR
23
CLKBA
22
SBA
1
CLKAB
2
SAB
One of Eight Channels
1D
C1
4
A1
20
B1
1D
C1
To Seven Other Channels
Pin numbers shown are for the DB, DGV, DW, JT, PW, and W packages.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LVTH646, SN74LVTH646
3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCBS705E – AUGUST 1997 – REVISED APRIL 1999
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
I
Voltage range applied to any output in the high-impedance
or power-off state, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
O
Voltage range applied to any output in the high state, V (see Note 1) . . . . . . . . . . . . . –0.5 V to V
+ 0.5 V
O
CC
Current into any output in the low state, I : SN54LVTH646 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA
O
SN74LVTH646 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Current into any output in the high state, I (see Note 2): SN54LVTH646 . . . . . . . . . . . . . . . . . . . . . . . 48 mA
O
SN74LVTH646 . . . . . . . . . . . . . . . . . . . . . . . 64 mA
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
IK
OK
I
Output clamp current, I
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
O
Package thermal impedance, θ (see Note 3): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104°C/W
JA
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139°C/W
DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This current flows only when the output is in the high state and V > V
.
CC
O
3. The package thermal impedance is calculated in accordance with JESD 51.
recommended operating conditions (see Note 4)
SN54LVTH646 SN74LVTH646
UNIT
MIN
2.7
2
MAX
MIN
2.7
2
MAX
V
V
V
V
Supply voltage
3.6
3.6
V
V
CC
High-level input voltage
Low-level input voltage
Input voltage
IH
0.8
5.5
–24
48
0.8
5.5
–32
64
V
IL
V
I
I
I
High-level output current
Low-level output current
Input transition rise or fall rate
Power-up ramp rate
mA
mA
ns/V
µs/V
°C
OH
OL
∆t/∆v
∆t/∆V
Outputs enabled
10
10
200
–55
200
–40
CC
T
A
Operating free-air temperature
125
85
NOTE 4: All unused control inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LVTH646, SN74LVTH646
3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCBS705E – AUGUST 1997 – REVISED APRIL 1999
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54LVTH646
SN74LVTH646
PARAMETER
TEST CONDITIONS
UNIT
†
†
MIN TYP
MAX
MIN TYP
MAX
V
V
V
V
V
= 2.7 V,
I = –18 mA
–1.2
–1.2
V
IK
CC
CC
CC
I
= 2.7 V to 3.6 V,
= 2.7 V,
I
I
I
I
I
I
I
I
I
I
= –100 µA
= –8 mA
= –24 mA
= –32 mA
= 100 µA
= 24 mA
= 16 mA
= 32 mA
= 48 mA
= 64 mA
V
–0.2
V
–0.2
OH
OH
OH
OH
OL
OL
OL
OL
OL
OL
CC
2.4
CC
2.4
V
V
OH
2
V
= 3 V
CC
CC
2
0.2
0.5
0.2
0.5
0.4
0.5
V
= 2.7 V
0.4
V
OL
0.5
V
CC
= 3 V
0.55
0.55
±1
V
V
= 3.6 V,
V = V
I
or GND
±1
10
20
1
CC
CC
Control inputs
= 0 or 3.6 V,
V = 5.5 V
I
10
CC
I
I
V = 5.5 V
I
20
µA
‡
V
CC
= 3.6 V
V = V
I CC
1
A or B ports
A or B ports
V = 0
I
–5
–5
I
I
V
V
= 0,
V or V = 0 to 4.5 V
±100
µA
µA
off
CC
I
O
V = 0.8 V
I
75
75
= 3 V
CC
V = 2 V
I
–75
–75
I(hold)
§
V
V
= 3.6 V ,
V = 0 to 3.6 V
±500
±100
CC
I
= 0 to 1.5 V, V = 0.5 V to 3 V,
OE = don’t care
CC
O
±100
±100
µA
µA
I
I
OZPU
V
= 1.5 V to 0, V = 0.5 V to 3 V,
CC
OE = don’t care
O
±100
OZPD
Outputs high
Outputs low
0.19
5
0.19
5
V
I
= 3.6 V,
CC
= 0,
I
mA
CC
O
V = V
I
or GND
CC
Outputs disabled
0.19
0.19
V
= 3 V to 3.6 V, One input at V – 0.6 V,
CC
CC
Other inputs at V
¶
∆I
CC
0.2
0.2
mA
or GND
CC
C
C
V = 3 V or 0
4
9
4
9
pF
pF
i
I
V
O
= 3 V or 0
io
†
‡
§
¶
All typical values are at V
= 3.3 V, T = 25°C.
A
CC
or GND
Unused terminals at V
CC
This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another.
This is the increase in supply current for each input that is at the specified TTL voltage level rather than V
or GND.
CC
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LVTH646, SN74LVTH646
3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCBS705E – AUGUST 1997 – REVISED APRIL 1999
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figure 2)
SN54LVTH646
= 3.3 V
SN74LVTH646
= 3.3 V
V
CC
V
CC
V
= 2.7 V
V
= 2.7 V
UNIT
CC
CC
± 0.3 V
± 0.3 V
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
f
t
Clock frequency
150
150
150
150
MHz
ns
clock
Pulse duration, CLK high or low
3.3
1.3
1.9
1.2
3.3
1.6
2.6
1.2
3.3
1.2
1.6
0.8
3.3
1.5
2.2
0.8
w
Data high
Data low
Setup time,
A or B before CLKAB↑ or CLKBA↑
t
ns
ns
su
h
t
Hold time, A or B after CLKAB↑ or CLKBA↑
switching characteristics over recommended operating free-air temperature range, C = 50 pF
L
(unless otherwise noted) (see Figure 2)
SN54LVTH646
= 3.3 V
SN74LVTH646
FROM
(INPUT)
TO
(OUTPUT)
V
V
= 3.3 V
V
CC
CC
V
CC
= 2.7 V
= 2.7 V
MAX
PARAMETER
UNIT
CC
± 0.3 V
± 0.3 V
†
MIN
150
1
MAX
MIN
MAX
MIN TYP
MAX
MIN
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
150
150
150
MHz
ns
max
PLH
PHL
PLH
PHL
PLH
PHL
PZH
PZL
PHZ
PLZ
PZH
PZL
PHZ
PLZ
5.3
5
5.9
5.9
5.6
5
1.8
1.8
1.3
1.3
1.5
1.5
1.1
1.1
2.3
2.3
1.3
1.3
1.5
1.5
3.1
3.1
2.3
2.4
3
4.7
4.7
3.5
3.5
4.9
4.9
5.2
5.2
5.5
5.5
5.2
5.2
5.6
5.6
5.6
5.6
4.1
4.1
6
CLKBA or
CLKAB
A or B
B or A
A or B
A or B
A or B
A or B
A or B
1.5
1
4.9
4.8
5.3
5.3
5.4
5.6
6.3
6.3
5.6
6.7
7.2
6.1
A or B
SBA or SAB
OE
ns
ns
ns
ns
ns
ns
1.2
1
6.3
6.3
6.7
6.7
6.5
6.5
6.8
6.8
8.1
6.6
‡
1.3
1
3.3
3.1
3.4
3.9
4
6
6.5
6.5
6.1
5.9
6.6
6.6
6.7
6.3
1
1.7
2.2
1.2
1.2
1.1
1.4
OE
3.4
3.6
3.2
3.8
DIR
DIR
†
‡
All typical values are at V
= 3.3 V, T = 25°C.
A
CC
These parameters are measured with the internal output state of the storage register opposite that of the bus input.
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LVTH646, SN74LVTH646
3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCBS705E – AUGUST 1997 – REVISED APRIL 1999
PARAMETER MEASUREMENT INFORMATION
6 V
S1
TEST
/t
S1
Open
GND
500 Ω
From Output
Under Test
t
Open
6 V
PLH PHL
t
/t
PLZ PZL
C
= 50 pF
L
t
/t
GND
500 Ω
PHZ PZH
(see Note A)
2.7 V
0 V
LOAD CIRCUIT
1.5 V
Timing Input
Data Input
t
w
t
t
h
su
2.7 V
0 V
2.7 V
0 V
Input
1.5 V
1.5 V
1.5 V
1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
2.7 V
0 V
2.7 V
Output
Control
1.5 V
1.5 V
1.5 V
1.5 V
Input
0 V
V
t
t
PLZ
t
t
t
PZL
PLH
PHL
Output
Waveform 1
S1 at 6 V
3 V
OH
1.5 V
1.5 V
1.5 V
1.5 V
Output
V
V
+ 0.3 V
OL
V
OL
(see Note B)
V
OL
t
t
t
PHL
PLH
PZH
PHZ
Output
Waveform 2
S1 at GND
V
OH
V
V
OH
– 0.3 V
OH
1.5 V
1.5 V
Output
≈ 0 V
(see Note B)
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A.
C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
Figure 2. Load Circuit and Voltage Waveforms
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1999, Texas Instruments Incorporated
相关型号:
SN74LVTH646DBR
LVT SERIES, 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO24, GREEN, PLASTIC, SSOP-24
TI
SN74LVTH646DBRE4
LVT SERIES, 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO24, GREEN, PLASTIC, SSOP-24
TI
SN74LVTH646DBRG4
LVT SERIES, 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO24, GREEN, PLASTIC, SSOP-24
TI
SN74LVTH646DGVR
LVT SERIES, 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO24, GREEN, PLASTIC, TVSOP-24
TI
SN74LVTH646DGVRG4
IC LVT SERIES, 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO24, GREEN, PLASTIC, TVSOP-24, Bus Driver/Transceiver
TI
SN74LVTH646DWE4
LVT SERIES, 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO24, GREEN, PLASTIC, SOIC-24
TI
SN74LVTH646DWR
LVT SERIES, 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO24, GREEN, PLASTIC, SOIC-24
TI
©2020 ICPDF网 联系我们和版权申明