SN74LVCHR16245A_17 [TI]
16-Bit Bus Transceiver With 3-State Outputs;
| 型号： | SN74LVCHR16245A_17 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 16-Bit Bus Transceiver With 3-State Outputs |
| 文件： | 总19页 (文件大小：606K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74LVCHR16245A
16-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCAS582P–NOVEMBER 1996–REVISED DECEMBER 2005
FEATURES
DGG, DGV, OR DL PACKAGE
(TOP VIEW)
•
Member of the Texas Instruments Widebus™
Family
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1DIR
1B1
1B2
GND
1B3
1B4
1OE
1A1
1A2
GND
1A3
1A4
•
•
•
•
Operates From 1.65 V to 3.6 V
Inputs Accept Voltages to 5.5 V
Max tpd of 4.8 ns at 3.3 V
2
3
4
Typical VOLP (Output Ground Bounce)
<0.8 V at VCC = 3.3 V, TA = 25°C
5
6
•
•
Typical VOHV (Output VOH Undershoot)
>2 V at VCC = 3.3 V, TA = 25°C
7
V
CC
V
CC
8
1B5
1B6
GND
1B7
1B8
2B1
2B2
GND
2B3
2B4
1A5
1A6
GND
1A7
1A8
2A1
2A2
GND
2A3
2A4
9
Supports Mixed-Mode Signal Operation on All
Ports (5-V Input/Output Voltage
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
With 3.3-V VCC
)
•
•
Bus Hold on Data Inputs Eliminates the Need
for External Pullup/Pulldown Resistors
All Outputs Have Equivalent 26-Ω Series
Resistors, So No External Resistors Are
Required
•
•
•
Ioff Supports Partial-Power-Down Mode
Operation
V
CC
V
CC
2B5
2B6
GND
2B7
2B8
2DIR
2A5
2A6
GND
2A7
2A8
2OE
Latch-Up Performance Exceeds 250 mA Per
JESD 17
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
DESCRIPTION/ORDERING INFORMATION
This 16-bit (dual-octal) noninverting bus transceiver is designed for 1.65-V to 3.6-V VCC operation.
The SN74LVCHR16245A is designed for asynchronous communication between data buses. The
control-function implementation minimizes external-timing requirements.
ORDERING INFORMATION
TA
PACKAGE(1)
ORDERABLE PART NUMBER
74LVCHR16245AGRDR
74LVCHR16245AZRDR
SN74LVCHR16245ALR
74LVCHR16245ALRG4
SN74LVCHR16245AGR
74LVCHR16245AGRG4
SN74LVCHR16245AVR
74LVCHR16245AVRE4
SN74LVCHR16245AKR
74LVCHR16245AZQLR
TOP-SIDE MARKING
LR245A
FBGA – GRD
Tape and reel
Tape and reel
Tape and reel
Tape and reel
Tape and reel
FBGA – ZRD (Pb-free)
SSOP – DL
LVCHR16245A
LVCHR16245A
LDR245A
TSSOP – DGG
TVSOP – DGV
–40°C to 85°C
VFBGA – GQL
LR245A
VFBGA – ZQL (Pb-free)
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines areavailable at
www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 1996–2005, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
SN74LVCHR16245A
16-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCAS582P–NOVEMBER 1996–REVISED DECEMBER 2005
DESCRIPTION/ORDERING INFORMATION (CONTINUED)
This device can be used as two 8-bit transceivers or one 16-bit transceiver. It allows data transmission from the
A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR)
input. The output-enable (OE) input can disable the device so that the buses are effectively isolated.
All outputs, which are designed to sink up to 12 mA, include equivalent 26-Ω series resistors to reduce overshoot
and undershoot.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of this device as a translator in
a mixed 3.3-V/5-V system environment.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. Use of pullup or
pulldown resistors with the bus-hold circuitry is not recommended. The bus-hold circuitry is part of the input
circuit and is not disabled by OE or DIR.
GQL OR ZQL PACKAGE
TERMINAL ASSIGNMENTS(1)
(56-Ball GQL/ZQL Package)
(TOP VIEW)
1
2 3 4 5 6
1
2
3
4
5
6
A
B
C
D
E
F
G
H
J
A
B
C
D
E
F
1DIR
1B2
1B4
1B6
1B8
2B1
G2B3
2B5
2B7
2DIR
NC
NC
NC
NC
1OE
1A2
1A4
1A6
1A8
2A1
2A3
2A5
2A7
2OE
1B1
1B3
1B5
1B7
2B2
2B4
2B6
2B8
NC
GND
VCC
GND
GND
VCC
GND
1A1
1A3
1A5
1A7
2A2
2A4
2A6
2A8
NC
GND
VCC
GND
NC
GND
VCC
GND
NC
K
H
J
xxxxx
K
(1) NC – No internal connection
GRD OR ZRD PACKAGE
(TOP VIEW)
TERMINAL ASSIGNMENTS(1)
(54-Ball GRD/ZRD Package)
1
2
3
4
5
6
1
2
3
4
5
6
A
B
C
D
E
F
1B1
1B3
1B5
1B7
2B1
2B3
2B5
2B7
2B8
NC
1DIR
NC
1OE
NC
NC
1A1
1A3
1A5
1A7
2A1
2A3
2A5
2A7
2A8
A
B
C
D
1B2
1B4
1B6
1B8
2B2
2B4
2B6
NC
1A2
1A4
1A6
1A8
2A2
2A4
2A6
NC
VCC
GND
GND
GND
VCC
NC
VCC
GND
GND
GND
VCC
NC
E
F
G
H
J
G
H
J
2DIR
2OE
(1) NC – No internal connection
2
SN74LVCHR16245A
16-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCAS582P–NOVEMBER 1996–REVISED DECEMBER 2005
FUNCTION TABLE(1)
(EACH 8-BIT SECTION)
CONTROL INPUTS
OUTPUT CIRCUITS
OPERATION
OE
L
DIR
L
A PORT
Enabled
Hi-Z
B PORT
Hi-Z
B data to A bus
A data to B bus
Isolation
L
H
Enabled
Hi-Z
H
X
Hi-Z
(1) Input circuits of the data I/Os always are active.
LOGIC DIAGRAM (POSITIVE LOGIC)
24
1
2DIR
1DIR
48
25
13
1OE
2OE
2B1
36
47
1A1
2A1
2
1B1
To Seven Other Channels
To Seven Other Channels
3
SN74LVCHR16245A
16-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCAS582P–NOVEMBER 1996–REVISED DECEMBER 2005
Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
MIN
–0.5
–0.5
–0.5
–0.5
MAX
6.5
UNIT
VCC
VI
Supply voltage range
Input voltage range(2)
Voltage range applied to any output in the high-impedance or power-off state(2)
Voltage range applied to any output in the high or low state(2)(3)
V
6.5
6.5
V
VO
VO
IIK
V
VCC + 0.5
–50
V
Input clamp current
VI < 0
mA
mA
mA
mA
IOK
IO
Output clamp current
VO < 0
–50
Continuous output current
Continuous current through each VCC or GND
±50
±100
70
DGG package
DGV package
58
θJA
Package thermal impedance(4)
DL package
63
°C/W
°C
GQL/ZQL package
GRD/ZRD package
42
36
Tstg
Storage temperature range
–65
150
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The value of VCC is provided in the recommended operating conditions table.
(4) The package thermal impedance is calculated in accordance with JESD 51-7.
Recommended Operating Conditions(1)
MIN
MAX UNIT
Operating
1.65
3.6
V
VCC
Supply voltage
Data retention only
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
1.5
0.65 × VCC
VIH
High-level input voltage
1.7
2
V
0.35 × VCC
0.7
VIL
Low-level input voltage
V
0.8
5.5
VCC
5.5
–2
–4
–8
–12
2
VI
Input voltage
0
0
0
V
V
High or low state
3-state
VO
Output voltage
VCC = 1.65 V
VCC = 2.3 V
VCC = 2.7 V
VCC = 3 V
IOH
High-level output current
Low-level output current
mA
mA
VCC = 1.65 V
VCC = 2.3 V
VCC = 2.7 V
VCC = 3 V
4
IOL
8
12
10
85
∆t/∆v
Input transition rise or fall rate
Operating free-air temperature
ns/V
°C
TA
–40
(1) All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
4
SN74LVCHR16245A
16-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCAS582P–NOVEMBER 1996–REVISED DECEMBER 2005
Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
1.65 V to 3.6 V
1.65 V
2.3 V
MIN
TYP(1) MAX
UNIT
IOH = –100 µA
VCC – 0.2
IOH = –2 mA
1.2
1.7
2.2
2.4
2
IOH = –4 mA
VOH
2.7 V
V
IOH = –6 mA
IOH = –8 mA
IOH = –12 mA
IOL = 100 µA
IOL = 2 mA
3 V
2.7 V
3 V
2
1.65 V to 3.6 V
1.65 V
2.3 V
0.2
0.45
0.7
IOL = 4 mA
VOL
2.7 V
0.4
V
IOL = 6 mA
IOL = 8 mA
IOL = 12 mA
3 V
0.55
0.6
2.7 V
3 V
0.8
II
Control inputs VI = 0 to 5.5 V
VI = 0.58 V
3.6 V
±5
µA
µA
(2)
(2)
1.65 V
2.3 V
3 V
VI = 1.07 V
VI = 0.7 V
45
–45
75
II(hold)
A or B port
VI = 1.7 V
VI = 0.8 V
VI = 2 V
–75
VI = 0 to 3.6 V(3)
3.6 V
0
±500
Ioff
VI or VO = 5.5 V
±10
µA
µA
(4)
IOZ
VO = 0 V or (VCC to 5.5 V)
VI = VCC or GND
3.6 V ≤ VI ≤ 5.5 V(5)
2.3 V to 3.6 V
±5
20
ICC
IO = 0
3.6 V
µA
20
∆ICC
Ci
One input at VCC – 0.6 V, Other inputs at VCC or GND 2.7 V to 3.6 V
500
µA
pF
pF
Control inputs VI = VCC or GND
A or B port VO = VCC or GND
3.3 V
3.3 V
3
Cio
12
(1) All typical values are at VCC = 3.3 V, TA = 25°C.
(2) This information was not available at the time of publication.
(3) This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to
another.
(4) For the total leakage current in an I/O port, please consult the II(hold) specification for the input voltage condition 0 V < VI < VCC, and the
IOZ specification for the input voltage conditions VI = 0 V or VI = VCC to 5.5 V. The bus-hold current, at input voltages greater than VCC
,
is negligible.
(5) This applies in the disabled state only.
5
SN74LVCHR16245A
16-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCAS582P–NOVEMBER 1996–REVISED DECEMBER 2005
Switching Characteristics
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
VCC = 2.7 V
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN
1
MAX
MIN
1
MAX
MIN
1
MAX
MIN MAX
tpd
ten
tdis
A or B
OE
B or A
A or B
A or B
12.5
15.8
19.2
9.5
12.2
11.9
5.7
7.9
8.3
1.5
1.5
2.2
4.8
6.3
7.4
ns
ns
ns
1
1
1
OE
1
1
1
Operating Characteristics
TA = 25°C
VCC = 1.8 V
VCC = 2.5 V
VCC = 3.3 V
TEST
CONDITIONS
PARAMETER
UNIT
TYP
TYP
TYP
39
4
(1)
(1)
Outputs enabled
Outputs disabled
Power dissipation capacitance
per transceiver
Cpd
f = 10 MHz
pF
(1)
(1)
(1) This information was not available at the time of publication.
6
SN74LVCHR16245A
16-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCAS582P–NOVEMBER 1996–REVISED DECEMBER 2005
PARAMETER MEASUREMENT INFORMATION
V
LOAD
S1
Open
R
L
From Output
Under Test
TEST
/t
S1
GND
t
Open
PLH PHL
C
L
t
t
/t
V
R
L
PLZ PZL
LOAD
GND
(see Note A)
/t
PHZ PZH
LOAD CIRCUIT
INPUT
V
CC
V
M
V
LOAD
C
L
R
L
V
∆
V
I
t /t
r f
1.8 V ± 0.15 V
2.5 V ± 0.2 V
2.7 V
V
V
2.7 V
2.7 V
V
V
1.5 V
1.5 V
/2
V
V
6 V
6 V
1 kΩ
500 Ω
500 Ω
500 Ω
0.15 V
0.15 V
0.3 V
≤2 ns
≤2 ns
≤2.5 ns
≤2.5 ns
30 pF
30 pF
50 pF
50 pF
CC
CC
CC
/2
CC
CC
CC
3.3 V ± 0.3 V
0.3 V
V
I
Timing Input
Data Input
V
M
0 V
t
w
t
t
h
su
V
I
V
I
V
M
V
M
Input
V
M
V
M
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
V
V
I
I
Output
Control
V
M
V
M
V
M
V
M
Input
0 V
0 V
t
t
t
t
t
PHL
PZL
PLZ
PLH
Output
Waveform 1
S1 at V
LOAD
(see Note B)
V
V
/2
LOAD
V
OH
V
V
V
V
V
M
M
M
Output
V
V
+ V
∆
OL
V
OL
OL
t
t
t
PHL
PLH
PZH
PHZ
Output
Waveform 2
S1 at GND
V
OH
V
OH
− V
∆
OH
M
V
M
M
Output
≈0 V
V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω.
O
D. The outputs are measured one at a time, with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
are the same as t
.
dis
.
PLZ
PZL
PLH
PHZ
are the same as t
PZH
en
are the same as t .
PHL pd
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
7
PACKAGE OPTION ADDENDUM
www.ti.com
6-Aug-2007
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
74LVCHR16245AGRDR
ACTIVE
BGA MI
CROSTA
R JUNI
OR
GRD
54
1000
TBD
SNPB
Level-1-240C-UNLIM
74LVCHR16245AGRG4
74LVCHR16245ALRG4
74LVCHR16245AVRE4
74LVCHR16245AVRG4
74LVCHR16245AZQLR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
TSSOP
DGG
DL
48
48
48
48
56
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SSOP
1000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TVSOP
TVSOP
DGV
DGV
ZQL
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
BGA MI
CROSTA
R JUNI
OR
1000 Green (RoHS &
no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
74LVCHR16245AZRDR
ACTIVE
BGA MI
CROSTA
R JUNI
OR
ZRD
54
1000 Green (RoHS &
no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
SN74LVCHR16245AGR
SN74LVCHR16245AKR
ACTIVE
ACTIVE
TSSOP
DGG
GQL
48
56
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
BGA MI
CROSTA
R JUNI
OR
1000
TBD
SNPB
Level-1-240C-UNLIM
SN74LVCHR16245ALR
SN74LVCHR16245AVR
ACTIVE
ACTIVE
SSOP
DL
48
48
1000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TVSOP
DGV
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
6-Aug-2007
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
4-Oct-2007
TAPE AND REEL BOX INFORMATION
Device
Package Pins
Site
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) (mm) Quadrant
(mm)
330
330
330
330
330
330
330
330
330
(mm)
16
74LVCHR16245AGRDR
74LVCHR16245AZQLR
74LVCHR16245AZQLR
74LVCHR16245AZRDR
SN74LVCHR16245AGR
SN74LVCHR16245AKR
SN74LVCHR16245AKR
SN74LVCHR16245ALR
SN74LVCHR16245AVR
GRD
ZQL
ZQL
ZRD
DGG
GQL
GQL
DL
54
56
56
54
48
56
56
48
48
SITE 32
SITE 32
SITE 60
SITE 32
SITE 41
SITE 32
SITE 60
SITE 41
SITE 41
5.8
4.8
8.3
7.3
1.55
1.45
1.5
8
8
16
16
16
16
24
16
16
32
24
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
16
16
4.8
7.3
8
16
5.8
8.3
1.55
1.8
8
24
8.6
15.8
7.3
12
8
16
4.8
1.45
1.5
16
4.8
7.3
8
32
11.35
6.8
16.2
10.1
3.1
16
12
DGV
24
1.6
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
4-Oct-2007
Device
Package
Pins
Site
Length (mm) Width (mm) Height (mm)
74LVCHR16245AGRDR
74LVCHR16245AZQLR
74LVCHR16245AZQLR
74LVCHR16245AZRDR
SN74LVCHR16245AGR
SN74LVCHR16245AKR
SN74LVCHR16245AKR
SN74LVCHR16245ALR
SN74LVCHR16245AVR
GRD
ZQL
ZQL
ZRD
DGG
GQL
GQL
DL
54
56
56
54
48
56
56
48
48
SITE 32
SITE 32
SITE 60
SITE 32
SITE 41
SITE 32
SITE 60
SITE 41
SITE 41
346.0
346.0
342.9
346.0
346.0
346.0
342.9
346.0
346.0
346.0
346.0
336.6
346.0
346.0
346.0
336.6
346.0
346.0
33.0
33.0
28.58
33.0
41.0
33.0
28.58
49.0
41.0
DGV
Pack Materials-Page 2
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,23
0,13
M
0,07
0,40
24
13
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–ā8°
0,75
1
12
0,50
A
Seating Plane
0,08
0,15
0,05
1,20 MAX
PINS **
14
16
20
24
38
48
56
DIM
A MAX
A MIN
3,70
3,50
3,70
3,50
5,10
4,90
5,10
4,90
7,90
7,70
9,80
9,60
11,40
11,20
4073251/E 08/00
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
D. Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001
DL (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0.025 (0,635)
48
0.0135 (0,343)
0.008 (0,203)
0.005 (0,13)
M
25
0.010 (0,25)
0.005 (0,13)
0.299 (7,59)
0.291 (7,39)
0.420 (10,67)
0.395 (10,03)
Gage Plane
0.010 (0,25)
0°–ā8°
1
24
0.040 (1,02)
0.020 (0,51)
A
Seating Plane
0.004 (0,10)
0.008 (0,20) MIN
PINS **
0.110 (2,79) MAX
28
48
0.630
56
DIM
0.380
(9,65)
0.730
A MAX
A MIN
(16,00) (18,54)
0.370
(9,40)
0.620
0.720
(15,75) (18,29)
4040048/E 12/01
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
D. Falls within JEDEC MO-118
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
M
0,08
0,50
48
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
0,25
1
24
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
48
56
64
DIM
A MAX
12,60
12,40
14,10
13,90
17,10
16,90
A MIN
4040078/F 12/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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