SN74LVCR162245 [TI]
16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS; 具有三态输出的16位总线收发器
| 型号： | SN74LVCR162245 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS |
| 文件： | 总6页 (文件大小：102K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74LVCR162245
16-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES047 - AUGUST 1995
DGG OR DL PACKAGE
(TOP VIEW)
Member of the Texas Instruments
Widebus Family
EPIC (Enhanced-Performance Implanted
CMOS) Submicron Process
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1DIR
1B1
1B2
GND
1B3
1B4
1OE
1A1
1A2
GND
1A3
1A4
2
Typical V
< 0.8 V at V
(Output Ground Bounce)
OLP
3
= 3.3 V, T = 25°C
CC
A
4
Typical V
> 2 V at V
(Output V
Undershoot)
OHV
CC
OH
5
= 3.3 V, T = 25°C
A
6
ESD Protection Exceeds 2000 V Per
MIL-STD-883C, Method 3015; Exceeds
200 V Using Machine Model
(C = 200 pF, R = 0)
7
V
V
CC
CC
8
1B5
1B6
GND
1B7
1B8
2B1
2B2
GND
2B3
2B4
1A5
1A6
GND
1A7
1A8
2A1
2A2
GND
2A3
2A4
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Latch-Up Performance Exceeds 250 mA Per
JEDEC Standard JESD-17
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
All Outputs Have Equivalent 26-Ω Series
Resistors, So No External Resistors Are
Required
V
V
CC
CC
2B5
2B6
GND
2B7
2B8
2A5
2A6
GND
2A7
2A8
2OE
Package Options Include Plastic Shrink
Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages
description
2DIR
This 16-bit (dual-octal) noninverting bus
transceiver is designed for 2.7-V to 3.6-V V
operation.
CC
The SN74LVCR162245 is designed for asynchronous communication between data buses. The control
function implementation minimizes external timing requirements.
This device can be used as two 8-bit transceivers or one 16-bit transceiver. It allows data transmission from the
A bus to the B bus or from the B bus to the A bus, depending upon the logic level at the direction-control (DIR)
input. The output-enable (OE) input can be used to disable the device so that the buses are effectively isolated.
All outputs, which are designed to sink up to 12 mA, include 26-Ω resistors to reduce overshoot and undershoot.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup
CC
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN74LVCR162245 is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC and Widebus are a trademarks of Texas Instruments Incorporated.
Copyright 1995, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74LVCR162245
16-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES047 - AUGUST 1995
FUNCTION TABLE
(each 8-bit section)
INPUTS
OPERATION
OE
L
DIR
L
B data to A bus
A data to B bus
Isolation
L
H
H
X
†
logic symbol
logic diagram (positive logic)
48
1
G3
1OE
1DIR
1
1DIR
3 EN1 [BA]
3 EN2 [AB]
48
25
24
1OE
1B1
G6
2OE
2DIR
6 EN4 [BA]
6 EN5 [AB]
47
1A1
47
2
1
1A1
1B1
2
2
46
44
43
41
40
38
37
36
3
5
1A2
1A3
1A4
1A5
1A6
1A7
1A8
2A1
1B2
1B3
1B4
1B5
1B6
1B7
1B8
2B1
6
8
To Seven Other Channels
9
11
12
13
24
36
2DIR
2A1
4
25
13
5
2OE
2B1
35
33
32
30
29
27
26
14
16
17
19
20
22
23
2A2
2A3
2A4
2A5
2A6
2A7
2A8
2B2
2B3
2B4
2B5
2B6
2B7
2B8
†
This symbol is in accordance with ANSI/IEEE Std 91-1984
and IEC Publication 617-12.
To Seven Other Channels
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74LVCR162245
16-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES047 - AUGUST 1995
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
CC
Input voltage range, VI: Except I/O ports (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
I/O ports (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
+ 4.6 V
+ 0.5 V
+ 0.5 V
CC
CC
CC
Output voltage range, V (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
O
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
IK
OK
I
Output clamp current, I
(V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
O O CC
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through V
Maximum power dissipation at T = 55°C (in still air) (see Note 3): DGG package . . . . . . . . . . . . . . . 0.85 W
O
O
CC
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
A
DL package . . . . . . . . . . . . . . . . . . 1.2 W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This value is limited to 4.6 V maximum.
3. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils.
Formoreinformation,refertothePackageThermalConsiderationsapplicationnoteinthe1994ABTAdvancedBiCMOSTechnology
Data Book, literature number SCBD002B.
recommended operating conditions (see Note 4)
MIN
2.7
2
MAX
UNIT
V
V
V
V
V
Supply voltage
3.6
V
V
V
V
V
CC
IH
IL
I
High-level input voltage
Low-level input voltage
Input voltage
V
V
= 2.7 V to 3.6 V
= 2.7 V to 3.6 V
CC
0.8
CC
0
0
V
V
CC
Output voltage
O
CC
–8
V
CC
V
CC
V
CC
V
CC
= 2.7 V
= 3 V
I
High-level output current
Low-level output current
mA
mA
OH
OL
–12
8
= 2.7 V
= 3 V
I
12
10
85
∆t/∆V
Input transition rise or fall rate
Operating free-air temperature
0
ns/V
T
A
–40
°C
NOTE 4: Unused control inputs must be held high or low to prevent them from floating.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74LVCR162245
16-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES047 - AUGUST 1995
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
†
‡
PARAMETER
TEST CONDITIONS
V
CC
MIN TYP
–0.2
MAX
UNIT
I
I
I
I
I
I
I
I
I
I
= –100 µA
= –4 mA,
= –8 mA,
= –6 mA,
= –12 mA,
= –100 µA
= –4 mA,
= –8 mA,
= –6 mA,
= –12 mA,
MIN to MAX
2.7 V
V
OH
OH
OH
OH
OH
OH
OH
OH
OH
OH
CC
2.2
V
IH
V
IH
V
IH
V
IH
= 2 V
= 2 V
= 2 V
= 2 V
V
2.7 V
2
V
OH
OL
3 V
2.4
2
3 V
MIN to MAX
2.7 V
0.2
0.4
V
IL
V
IL
V
IL
V
IL
= 0.8 V
= 0.8 V
= 0.8 V
= 0.8 V
V
2.7 V
0.6
V
3 V
0.55
0.8
3 V
I
I
V = V
or GND
3.6 V
±5
µA
µA
l
I
CC
V = 0.8 V
I
75
3 V
V = 2 V
I
–75
l(hold)
V = 0 to 3.6 V
3.6 V
3.6 V
±500
±10
20
µA
µA
µA
µA
pF
pF
I
§
I
I
V
= V
or GND
OZ
O
CC
or GND,
V = V
I
I = 0
O
3.6 V
CC
CC
I
One input at V
– 0.6 V,
Other inputs at V
CC
or GND
2.7 V to 3.6 V
3.3 V
500
CC
CC
or GND
C
C
Control inputs V = V
2.5
3.5
i
I
CC
= V or GND
CC
A or B ports
V
O
3.3 V
io
†
‡
§
For conditions shown as MIN or MAX, use the appropriate values under recommended operating conditions.
All typical values are at V = 3.3 V, T = 25°C.
CC
For I/O ports, the parameter I
A
includes the input leakage current.
OZ
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C = 50 pF (unless otherwise noted) (see Figure 1)
L
V
= 3.3 V
CC
± 0.3 V
V
= 2.7 V
FROM
(INPUT)
TO
(OUTPUT)
CC
PARAMETER
UNIT
MIN
MAX
MIN
MAX
t
t
t
A or B
B or A
A or B
A or B
1.5
7.5
1.5
8.5
ns
ns
ns
pd
en
dis
1.5
1.5
9
1.5
1.5
10
OE
OE
7.5
8.5
operating characteristics, V
= 3.3 V, T = 25 C
A
CC
PARAMETER
TEST CONDITIONS
= 50 pF, f = 10 MHz
L
TYP
20
2
UNIT
Outputs enabled
Outputs enabled
C
Power dissipation capacitance per transceiver
C
pF
pd
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74LVCR162245
16-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES047 - AUGUST 1995
PARAMETER MEASUREMENT INFORMATION
6 V
Open
TEST
S1
t
/t
Open
6 V
S1
500 Ω
PLH PHL
From Output
Under Test
t
/t
PLZ PZL
GND
t
/t
PHZ PZH
GND
C
= 50 pF
L
500 Ω
(see Note A)
2.7 V
0 V
LOAD CIRCUIT FOR OUTPUTS
1.5 V
Timing Input
Data Input
t
w
t
t
h
su
2.7 V
0 V
2.7 V
0 V
Input
1.5 V
1.5 V
1.5 V
1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
2.7 V
0 V
2.7 V
0 V
Input
Output
Control
1.5 V
1.5 V
1.5 V
1.5 V
t
PZL
t
t
t
PHL
PLH
t
PLZ
Output
Waveform 1
S1 at 6 V
3 V
V
V
OH
1.5 V
1.5 V
1.5 V
1.5 V
Output
Output
V
OL
+ 0.3 V
– 0.3 V
V
OL
OL
(see Note B)
t
PHZ
t
PLH
t
PHL
PZH
Output
Waveform 2
S1 at GND
V
OH
V
V
OH
V
OH
1.5 V
1.5 V
0 V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
E. t
F. t
G. t
and t
and t
and t
are the same as t
are the same as t
are the same as t
.
PLZ
PZL
PHL
PHZ
PZH
PLH
dis
.
den
.
pd
Figure 1. Load Circuit and Voltage Waveforms
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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pertaining to warranty, patent infringement, and limitation of liability.
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accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
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Copyright 1998, Texas Instruments Incorporated
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