SN74LVCHR32245AKR [TI]
32-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS; 具有三态输出的32位总线收发器
| 型号： | SN74LVCHR32245AKR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 32-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS |
| 文件： | 总11页 (文件大小：249K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74LVCHR32245A
32-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCES601–AUGUST 2004–REVISED SEPTEMBER 2005
FEATURES
•
Member of the Texas Instruments Widebus+™
Family
•
•
Ioff Supports Partial-Power-Down Mode
Operation
•
•
•
•
Operates From 1.65 V to 3.6 V
Inputs Accept Voltages to 5.5 V
Max tpd of 4.8 ns at 3.3 V
Supports Mixed-Mode Signal Operation on All
Ports (5-V Input/Output Voltage With 3.3-V
VCC
)
•
•
•
Other Products to Consider: SN74LVC32245,
SN74LVCH32245A, SN74LVCR32245A
Input and Output Ports Have Equivalent 26-Ω
Series Resistors, So No External Resistors
Are Required
Latch-Up Performance Exceeds 250 mA Per
JESD 17
•
•
•
Typical VOLP (Output Ground Bounce) <0.8 V
at VCC = 3.3 V, TA = 25°C
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
Typical VOHV (Output VOH Undershoot) >2 V at
VCC = 3.3 V, TA = 25°C
Bus Hold on Data Inputs Eliminates the Need
for External Pullup/Pulldown Resistors
– 1000-V Charged-Device Model (C101)
DESCRIPTION/ORDERING INFORMATION
This 32-bit (quad-octal) noninverting bus transceiver is designed for 1.65-V to 3.6-V VCC operation.
The SN74LVCHR32245A is designed for asynchronous communication between data buses. The
control-function implementation minimizes external timing requirements.
This device can be used as four 8-bit transceivers, two 16-bit transceivers, or one 32-bit transceiver. It allows
data transmission from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the
direction-control (DIR) input. The output-enable (OE) input can be used to disable the device so that the buses
are effectively isolated.
The data I/Os and control inputs are overvoltage tolerant. This feature allows the use of this device for down
translation in a mixed-voltage environment.
The outputs, which are designed to sink up to 12 mA, include equivalent 26-Ω resistors to reduce overshoot and
undershoot.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. Use of pullup or
pulldown resistors with the bus-hold circuitry is not recommended. The bus-hold circuitry is part of the input
circuit and is not disabled by OE or DIR.
ORDERING INFORMATION
TA
PACKAGE(1)
ORDERABLE PART NUMBER
SN74LVCHR32245AKR
TOP-SIDE MARKING
LFBGA – GKE
LFBGA – ZKE (Pb-free)
–40°C to 85°C
Tape and reel
LQ245A
74LVCHR32245AZKER
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus+ is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 2004–2005, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
SN74LVCHR32245A
32-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCES601–AUGUST 2004–REVISED SEPTEMBER 2005
GKE OR ZKE PACKAGE
(TOP VIEW)
1
2
3
4
5
6
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
TERMINAL ASSIGNMENTS
1
2
3
4
5
6
A
B
C
D
E
F
1B2
1B4
1B6
1B8
2B2
2B4
2B6
2B7
3B2
3B4
3B6
3B8
4B2
4B4
4B6
4B7
1B1
1B3
1B5
1B7
2B1
2B3
2B5
2B8
3B1
3B3
3B5
3B7
4B1
4B3
4B5
4B8
1DIR
GND
VCC
1OE
GND
VCC
1A1
1A3
1A5
1A7
2A1
2A3
2A5
2A8
3A1
3A3
3A5
3A7
4A1
4A3
4A5
4A8
1A2
1A4
1A6
1A8
2A2
2A4
2A6
2A7
3A2
3A4
3A6
3A8
4A2
4A4
4A6
4A7
GND
GND
VCC
GND
GND
VCC
G
H
J
GND
2DIR
3DIR
GND
VCC
GND
2OE
3OE
GND
VCC
K
L
M
N
P
R
T
GND
GND
VCC
GND
GND
VCC
GND
4DIR
GND
4OE
2
SN74LVCHR32245A
32-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCES601–AUGUST 2004–REVISED SEPTEMBER 2005
FUNCTION TABLE
(EACH 8-BIT SECTION)
INPUTS
OPERATION
OE
DIR
L
L
L
B data to A bus
A data to B bus
Isolation
H
H
X
LOGIC DIAGRAM (POSITIVE LOGIC)
A3
H3
1DIR
2DIR
A4
H4
E2
1OE
2OE
2B1
A5
E5
1A1
2A1
A2
1B1
To Seven Other Channels
To Seven Other Channels
J3
T3
N5
3DIR
4DIR
4A1
J4
J2
T4
N2
3OE
3B1
4OE
4B1
J5
3A1
To Seven Other Channels
To Seven Other Channels
3
SN74LVCHR32245A
32-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCES601–AUGUST 2004–REVISED SEPTEMBER 2005
Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
MIN
–0.5
–0.5
–0.5
MAX
6.5
UNIT
VCC
VI
Supply voltage range
V
Input voltage range
6.5
6.5
V
V
VO
VO
IIK
Voltage range applied to any output in the high-impedance or power-off state(2)
Voltage range applied to any output in the high or low state(2)(3)
–0.5 VCC + 0.5
V
Input clamp current
VI < 0
–50
–50
±50
±100
40
mA
mA
mA
mA
°C/W
°C
IOK
IO
Output clamp current
VO < 0
Continuous output current
Continuous current through each VCC or GND
Package thermal impedance(4)
Storage temperature range
θJA
GKE/ZKE package
Tstg
–65
150
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The value of VCC is provided in the recommended operating conditions table.
(4) The package thermal impedance is calculated in accordance with JESD 51-7.
Recommended Operating Conditions(1)
MIN
MAX UNIT
Operating
1.65
3.6
V
VCC
Supply voltage
Data retention only
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
1.5
0.65 × VCC
VIH
High-level input voltage
1.7
2
V
0.35 × VCC
0.7
VIL
Low-level input voltage
V
0.8
5.5
VCC
5.5
–2
–4
–8
–12
2
VI
Input voltage
0
0
0
V
V
High or low state
3-state
VO
Output voltage
VCC = 1.65 V
VCC = 2.3 V
VCC = 2.7 V
VCC = 3 V
IOH
High-level output current
Low-level output current
mA
mA
VCC = 1.65 V
VCC = 2.3 V
VCC = 2.7 V
VCC = 3 V
4
IOL
8
12
10
85
∆t/∆v
Input transition rise or fall rate
Operating free-air temperature
ns/V
TA
–40
°C
(1) All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
4
SN74LVCHR32245A
32-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCES601–AUGUST 2004–REVISED SEPTEMBER 2005
Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
1.65 V to 3.6 V VCC – 0.2
MIN TYP(1)
MAX UNIT
IOH = –100 µA
IOH = –2 mA
IOH = –4 mA
1.65 V
2.3 V
1.2
1.7
2
VOH
V
2.7 V
IOH = –8 mA
3 V
2.4
2
IOH = –12 mA
IOL = 100 µA
IOL = 2 mA
IOL = 4 mA
IOL = 8 mA
IOL = 12 mA
3 V
1.65 V to 3.6 V
1.65 V
2.3 V
0.2
0.45
VOL
0.7
0.6
0.8
±5
V
2.7 V
3 V
II
Control inputs VI = 0 to 5.5 V
VI = 0.58 V
3.6 V
µA
25
–25
45
1.65 V
2.3 V
3 V
VI = 1.07 V
VI = 0.7 V
II(hold)
VI = 1.7 V
–45
75
µA
VI = 0.8 V
VI = 2 V
–75
VI = 0 to 3.6 V(2)
3.6 V
0
±500
±10
±5
Ioff
VI or VO = 5.5 V
µA
µA
(3)
IOZ
VO = 0 V or (VCC to 5.5 V)
2.3 V to 3.6 V
VI = VCC or GND
3.6 V ≤ VI ≤ 5.5 V(4)
40
ICC
IO = 0
3.6 V
µA
40
∆ICC
Ci
One input at VCC – 0.6 V,
Control inputs VI = VCC or GND
A or B port VO = VCC or GND
Other inputs at VCC or GND
2.7 V to 3.6 V
3.3 V
500
µA
pF
pF
3
Cio
3.3 V
12
(1) All typical values are at VCC = 3.3 V, TA = 25°C.
(2) This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to
another.
(3) For the total leakage current in an I/O port, please consult the II(hold) specification for the input voltage condition 0 V < VI < VCC, and the
IOZ specification for the input voltage conditions VI = 0 V or VI = VCC to 5.5 V. The bus-hold current, at input voltage greater than VCC, is
negligible.
(4) This applies in the disabled state only.
Switching Characteristics
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
VCC = 2.7 V
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN
1
MAX
MIN
1
MAX
MIN
1
MAX
MIN
1.5
1.5
2.2
MAX
tpd
ten
tdis
A or B
OE
B or A
A or B
A or B
12.5
15.8
19.2
9.5
12.2
11.9
5.7
7.9
8.3
4.8
6.3
7.4
ns
ns
ns
1
1
1
OE
1
1
1
5
SN74LVCHR32245A
32-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCES601–AUGUST 2004–REVISED SEPTEMBER 2005
Operating Characteristics
TA = 25°C
VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V
TEST
CONDITIONS
PARAMETER
UNIT
TYP
TYP
TYP
39
4
(1)
(1)
Outputs enabled
Outputs disabled
Cpd
Power dissipation capacitance
f = 10 MHz
pF
(1)
(1)
(1) This information was not available at the time of publication.
6
SN74LVCHR32245A
32-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCES601–AUGUST 2004–REVISED SEPTEMBER 2005
PARAMETER MEASUREMENT INFORMATION
V
LOAD
S1
Open
R
L
From Output
Under Test
TEST
/t
S1
GND
t
t
Open
PLH PHL
C
L
t
/t
V
R
L
PLZ PZL
LOAD
GND
(see Note A)
/t
PHZ PZH
LOAD CIRCUIT
INPUTS
V
CC
V
M
V
LOAD
C
L
R
L
V
∆
V
I
t /t
r f
1.8 V ± 0.15 V
2.5 V ± 0.2 V
2.7 V
V
V
2.7 V
2.7 V
≤2 ns
≤2 ns
≤2.5 ns
≤2.5 ns
V
/2
/2
2 × V
2 × V
6 V
6 V
30 pF
30 pF
50 pF
50 pF
1 kΩ
500 Ω
500 Ω
500 Ω
0.15 V
0.15 V
0.3 V
CC
CC
CC
V
CC
CC
CC
1.5 V
1.5 V
3.3 V ± 0.3 V
0.3 V
V
I
Timing Input
Data Input
V
M
0 V
t
w
t
t
h
su
V
I
V
I
Input
V
M
V
M
V
V
M
M
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
V
I
V
I
Output
Control
V
M
V
M
Input
V
M
V
M
0 V
0 V
t
t
t
t
t
PHL
PZL
PLZ
PLH
Output
Waveform 1
V
V
OH
V
V
/2
LOAD
V
V
V
M
M
Output
V
V
M
S1 at V
LOAD
V
OL
+ V
∆
OL
(see Note B)
OL
t
PHL
PLH
t
t
PHZ
PZH
Output
Waveform 2
S1 at GND
V
V
OH
V
OH
V
- V
∆
V
M
OH
M
Output
M
≈0 V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω.
O
D. The outputs are measured one at a time, with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
are the same as t
.
dis
.
PLZ
PZL
PLH
PHZ
are the same as t
PZH
en
are the same as t .
PHL pd
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
7
PACKAGE OPTION ADDENDUM
www.ti.com
24-Jun-2005
PACKAGING INFORMATION
Orderable Device
74LVCHR32245AZKER
SN74LVCHR32245AKR
Status (1)
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
LFBGA
ZKE
96
1000 Green (RoHS &
no Sb/Br)
SNAGCU
Level-3-250C-168 HR
LFBGA
GKE
96
1000
TBD
SNPB
Level-3-220C-168 HR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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Addendum-Page 1
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