SN74LVCHR162245ALR [TI]
LVC/LCX/Z SERIES, DUAL 8-BIT TRANSCEIVER, TRUE OUTPUT, PDSO48, 0.300 INCH, PLASTIC, SSOP-48;
| 型号： | SN74LVCHR162245ALR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | LVC/LCX/Z SERIES, DUAL 8-BIT TRANSCEIVER, TRUE OUTPUT, PDSO48, 0.300 INCH, PLASTIC, SSOP-48 光电二极管 输出元件 逻辑集成电路 |
| 文件： | 总7页 (文件大小：579K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74LVCHR162245A
16-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCAS582E – NOVEMBER 1996 – REVISED JUNE 1998
G OR L PACKAGE
(TOP VIEW)
D
D
D
D
D
Member of the Texas Instruments
Widebus Family
EPIC (Enhanced-Performance Implanted
CMOS) Submicron Process
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1DIR
1B1
1B2
GND
1B3
1B4
1OE
1A1
1A2
GND
1A3
1A4
2
Typical V
< 0.8 V at V
(Output Ground Bounce)
OLP
3
= 3.3 V, T = 25°C
CC
A
4
Typical V
> 2 V at V
(Output V
Undershoot)
OHV
CC
OH
5
= 3.3 V, T = 25°C
A
6
Supports Mixed-Mode Signal Operation on
All Ports (5-V Input/Output Voltage With
7
V
V
CC
CC
8
1B5
1B6
GND
1B7
1B8
2B1
2B2
GND
2B3
2B4
1A5
1A6
GND
1A7
1A8
2A1
2A2
GND
2A3
2A4
3.3-V V
)
9
CC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
D
D
Power Off Disables Inputs/Outputs,
Permitting Live Insertion
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
D
D
Latch-Up Performance Exceeds 250 mA Per
JESD 17
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
V
V
CC
2B5
CC
2A5
2A6
GND
2A7
2A8
2OE
2B6
GND
2B7
2B8
2DIR
D
D
All Outputs Have Equivalent 26-Ω Series
Resistors, So No External Resistors Are
Required
Package Options Include Plastic 300-mil
Shrink Small-Outline (L) and Thin Shrink
Small-Outline (G) Packages
NOTE: G is the abbreviated alias for the DGG package, and
L is the abbreviated alias for the DL package.
description
This 16-bit (dual-octal) noninverting bus transceiver is designed for 1.65-V to 3.6-V V
operation.
CC
The SN74LVCHR162245A is designed for asynchronous communication between data buses. The
control-function implementation minimizes external timing requirements.
This device can be used as two 8-bit transceivers or one 16-bit transceiver. It allows data transmission from the
A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR)
input. The output-enable (OE) input can be used to disable the device so that the buses are effectively isolated.
All outputs, which are designed to sink up to 12 mA, include equivalent 26-W resistors to reduce overshoot and
undershoot.
To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup
CC
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
EPIC and Widebus are trademarks of Texas Instruments Incorporated.
Copyright 1998, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
5–155
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74LVCHR162245A
16-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCAS582E – NOVEMBER 1996 – REVISED JUNE 1998
description (continued)
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators
in a mixed 3.3-V/5-V system environment.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN74LVCHR162245A is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
(each 8-bit section)
INPUTS
OPERATION
OE
L
DIR
L
B data to A bus
A data to B bus
Isolation
L
H
H
X
†
logic symbol
48
1
G3
1OE
1DIR
3 EN1 [BA]
3 EN2 [AB]
25
24
G6
2OE
2DIR
6 EN4 [BA]
6 EN5 [AB]
47
2
1A1
1B1
1
2
46
44
43
41
40
38
37
36
3
5
1A2
1A3
1A4
1A5
1A6
1A7
1A8
2A1
1B2
1B3
1B4
1B5
1B6
1B7
1B8
2B1
6
8
9
11
12
13
4
5
35
33
32
30
29
27
26
14
16
17
19
20
22
23
2A2
2A3
2A4
2A5
2A6
2A7
2A8
2B2
2B3
2B4
2B5
2B6
2B7
2B8
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
5–156
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74LVCHR162245A
16-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCAS582E – NOVEMBER 1996 – REVISED JUNE 1998
logic diagram (positive logic)
1
24
36
1DIR
2DIR
2A1
48
25
1OE
1B1
2OE
47
1A1
2
13
2B1
To Seven Other Channels
To Seven Other Channels
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6.5 V
CC
Input voltage range, V :(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6.5 V
I
Voltage range applied to any output in the high-impedance or power-off state, V
O
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6.5 V
Voltage range applied to any output in the high or low state, V
O
(see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
+ 0.5 V
CC
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Continuous output current, I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
IK
I
Output clamp current, I
OK
O
O
Continuous current through each V
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
CC
Package thermal impedance, q (see Note 3): G package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89°C/W
JA
L package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The value of V is provided in the recommended operating conditions table.
CC
3. The package thermal impedance is calculated in accordance with JESD 51.
5–157
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74LVCHR162245A
16-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCAS582E – NOVEMBER 1996 – REVISED JUNE 1998
recommended operating conditions (see Note 4)
MIN
1.65
1.5
MAX
UNIT
Operating
3.6
V
Supply voltage
V
CC
IH
Data retention only
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 1.65 V to 1.95 V
= 2.3 V to 2.7 V
= 2.7 V to 3.6 V
= 1.65 V to 1.95 V
= 2.3 V to 2.7 V
= 2.7 V to 3.6 V
0.65 × V
1.7
CC
V
High-level input voltage
V
V
2
0.35 × V
0.7
CC
V
IL
Low-level input voltage
0.8
V
V
Input voltage
0
0
0
5.5
V
V
I
High or low state
3 state
V
CC
5.5
Output voltage
O
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 1.65 V
= 2.3 V
= 2.7 V
= 3 V
–2
–4
–8
I
High-level output current
Low-level output current
mA
mA
OH
OL
–12
2
= 1.65 V
= 2.3 V
= 2.7 V
= 3 V
4
I
8
12
10
85
∆t/∆v
Input transition rise or fall rate
Operating free-air temperature
0
ns/V
T
–40
°C
A
NOTE 4: All unused control inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
5–158
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74LVCHR162245A
16-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCAS582E – NOVEMBER 1996 – REVISED JUNE 1998
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
†
PARAMETER
MIN TYP
–0.2
MAX
UNIT
V
CC
I
I
= –100 µA
= –2 mA
1.65 V to 3.6 V
1.65 V
2.3 V
V
OH
CC
1.2
OH
1.7
2.2
2.4
2
I
= –4 mA
OH
V
OH
2.7 V
V
I
I
I
I
I
= –6 mA
= –8 mA
= –12 mA
= 100 µA
= 2 mA
3 V
OH
OH
OH
OL
OL
2.7 V
3 V
2
1.65 V to 3.6 V
1.65 V
2.3 V
0.2
0.45
0.7
I
= 4 mA
OL
V
OL
2.7 V
0.4
V
I
I
I
= 6 mA
= 8 mA
= 12 mA
3 V
0.55
0.6
OL
OL
OL
2.7 V
3 V
0.8
I
Control inputs V = 0 to 5.5 V
3.6 V
±5
µA
µA
I
I
V = 0.58 V
I
‡
‡
1.65 V
2.3 V
3 V
V = 1.07 V
I
V = 0.7 V
I
45
I
A or B ports
V = 1.7 V
I
–45
75
I(hold)
V = 0.8 V
I
V = 2 V
I
–75
§
V = 0 to 3.6 V
3..6 V
0
±500
±10
±10
20
I
I
I
V or V = 5.5 V
µA
µA
off
I
O
¶
V
O
= 0 to 5.5 V
3.6 V
OZ
V = V
I
or GND,
CC
I
I
O
= 0
3.6 V
µA
CC
#
3.6 V ≤ V ≤ 5.5 V
20
I
∆I
CC
One input at V
– 0.6 V, Other inputs at V
CC
or GND
2.7 V to 3.6 V
3.3 V
500
µA
pF
pF
CC
C
C
Control inputs V = V
or GND
3
i
I
CC
= V
A or B ports
V
O
or GND
3.3 V
12
io
CC
†
‡
§
¶
#
All typical values are at V
This information was not available at the time of publication.
= 3.3 V, T = 25°C.
CC
A
This is the bus-hold maximum dynamic current required to switch the input from one state to another.
For I/O ports, the parameter I includes the input leakage current, but not I
.
I(hold)
OZ
This applies in the disabled state only.
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figures 1 through 3)
V
= 1.8 V
V
= 2.5 V
V
= 3.3 V
CC
± 0.15 V
CC
± 0.2 V
CC
± 0.3 V
V
= 2.7 V
FROM
(INPUT)
TO
(OUTPUT)
CC
PARAMETER
UNIT
MIN
‡
MAX
MIN
‡
MAX
MIN
MAX
5.7
MIN
1.5
1.5
2.2
MAX
4.8
t
t
t
A or B
OE
B or A
A or B
A or B
‡
‡
‡
‡
‡
‡
ns
ns
ns
pd
en
dis
‡
‡
7.9
6.3
‡
‡
8.3
7.4
OE
‡
This information was not available at the time of publication.
5–159
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74LVCHR162245A
16-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCAS582E – NOVEMBER 1996 – REVISED JUNE 1998
operating characteristics, T = 25°C
A
V
CC
= 1.8 V
V
= 2.5 V
V
= 3.3 V
CC
± 0.2 V
CC
± 0.3 V
TEST
CONDITIONS
± 0.15 V
TYP
†
PARAMETER
UNIT
TYP
TYP
Outputs enabled
Outputs disabled
†
39
Power dissipation capacitance
per transceiver
C
f = 10 MHz
pF
pd
†
†
4
†
This information was not available at the time of publication.
5–160
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74LVCHR162245A
16-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCAS582E – NOVEMBER 1996 – REVISED JUNE 1998
PARAMETER MEASUREMENT INFORMATION
= 1.8 V ± 0.15 V
V
CC
2 × V
CC
Open
S1
1k Ω
From Output
Under Test
TEST
S1
GND
t
Open
pd
/t
C
= 30 pF
t
2 × V
CC
Open
L
PLZ PZL
1k Ω
(see Note A)
t
/t
PHZ PZH
LOAD CIRCUIT
t
w
V
CC
V
CC
V
CC
/2
V
CC
/2
Input
Timing
Input
V
/2
CC
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
t
t
h
su
V
CC
Output
Control
(low-level
enabling)
Data
Input
V
CC
V
/2
V
CC
/2
CC
V
CC
/2
V
CC
/2
0 V
0 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
t
t
PZL
PLZ
Output
Waveform 1
V
CC
V
CC
V
/2
CC
Input
V
CC
/2
V
CC
/2
S1 at 2 × V
(see Note B)
V
V
+ 0.15 V
V
CC
OL
0 V
OL
t
t
PZH
PHZ
t
t
PLH
PHL
Output
Waveform 2
S1 at Open
(see Note B)
V
OH
V
V
OH
– 0.15 V
OH
V
/2
CC
Output
V
CC
/2
V
CC
/2
0 V
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A.
C
includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR≤10 MHz, Z = 50 Ω, t ≤2 ns, t ≤2 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
are the same as t
are the same as t
are the same as t
.
dis
en
.
pd
PLZ
PZL
PLH
PHZ
PZH
PHL
.
Figure 1. Load Circuit and Voltage Waveforms
5–161
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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