SN74GTLPH16912VR [TI]
18-BIT LVTTL-TO-GTLP UNIVERSAL BUS TRANSCEIVER; 18位LVTTL至GTLP通用总线收发器
| 型号： | SN74GTLPH16912VR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 18-BIT LVTTL-TO-GTLP UNIVERSAL BUS TRANSCEIVER |
| 文件： | 总14页 (文件大小：219K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74GTLPH16912
18-BIT LVTTL-TO-GTLP UNIVERSAL BUS TRANSCEIVER
SCES288C – OCTOBER 1999 – REVISED JULY 2001
DGG OR DGV PACKAGE
Member of Texas Instruments’ Widebus
Family
(TOP VIEW)
UBT Transceiver Combines D-Type
Latches and D-Type Flip-Flops for
Operation in Transparent, Latched,
Clocked, and Clock-Enabled Modes
OEAB
LEAB
A1
GND
A2
CEAB
CLKAB
B1
GND
B2
B3
BIAS V
B4
B5
B6
GND
B7
1
56
55
54
53
52
51
50
49
48
47
46
45
2
3
4
TI-OPC Circuitry Limits Ringing on
Unevenly Loaded Backplanes
5
A3
6
OEC Circuitry Improves Signal Integrity
and Reduces Electromagnetic Interference
V
7
CC
CC
A4
A5
A6
GND
A7
8
Bidirectional Interface Between GTLP
Signal Levels and LVTTL Logic Levels
9
10
11
12
LVTTL Interfaces Are 5-V Tolerant
Medium-Drive GTLP Outputs (50 mA)
LVTTL Outputs (–24 mA/24 mA)
A8 13
A9 14
44 B8
43 B9
GTLP Rise and Fall Times Designed for
Optimal Data-Transfer Rate and Signal
Integrity in Distributed Loads
A10 15
A11 16
A12 17
GND 18
42 B10
41 B11
40 B12
39 GND
I
, Power-Up 3-State, and BIAS V
CC
off
Support Live Insertion
A13
B13
19
38
A14 20
A15 21
37 B14
36 B15
Bus Hold on A-Port Data Inputs
Distributed V
High-Speed Switching Noise
and GND Pins Minimize
CC
V
22
35
V
CC
REF
A16 23
34 B16
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
A17 24
33 B17
GND 25
A18 26
32 GND
31 B18
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
OEBA 27
LEBA 28
30 CLKBA
29 CEBA
– 1000-V Charged-Device Model (C101)
description
The SN74GTLPH16912 is a medium-drive, 18-bit UBT transceiver that provides LVTTL-to-GTLP and
GTLP-to-LVTTL signal-level translation. It allows for transparent, latched, clocked, and clock-enabled modes
of data transfer. The device provides a high-speed interface between cards operating at LVTTL logic levels and
a backplane operating at GTLP signal levels. High-speed (about three times faster than standard TTL or LVTTL)
backplane operation is a direct result of GTLP’s reduced output swing (<1 V), reduced input threshold levels,
improved differential input, OEC circuitry, and TI-OPC circuitry. Improved GTLP OEC and TI-OPC circuits
minimize bus-settling time and have been designed and tested using several backplane models. The medium
drive allows incident-wave switching in heavily loaded backplanes with equivalent load impedance down
to 19 Ω.
GTLP is the Texas Instruments (TI ) derivative of the Gunning Transceiver Logic (GTL) JEDEC standard
JESD 8-3. The ac specification of the SN74GTLPH16912 is given only at the preferred higher noise-margin
GTLP, but the user has the flexibility of using this device at either GTL (V = 1.2 V and V
= 0.8 V) or GTLP
TT
REF
(V = 1.5 V and V
= 1 V) signal levels.
TT
REF
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
OEC, TI, TI-OPC, UBT, and Widebus are trademarks of Texas Instruments.
Copyright 2001, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74GTLPH16912
18-BIT LVTTL-TO-GTLP UNIVERSAL BUS TRANSCEIVER
SCES288C – OCTOBER 1999 – REVISED JULY 2001
description (continued)
Normally, the B port operates at GTLP signal levels. The A-port and control inputs operate at LVTTL logic levels,
but are 5-V tolerant and are compatible with TTL and 5-V CMOS inputs. V
reference voltage.
is the B-port differential input
REF
This device is fully specified for live-insertion applications using I , power-up 3-state, and BIAS V . The I
off
off
CC
circuitry disables the outputs, preventing damaging current backflow through the device when it is powered
down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power
down, which prevents driver conflict. The BIAS V
circuitry precharges and preconditions the B-port
CC
input/output connections, preventing disturbance of active data on the backplane during card insertion or
removal, and permits true live-insertion capability.
This GTLP device features TI-OPC circuitry, which actively limits overshoot caused by improperly terminated
backplanes, unevenly distributed cards, or empty slots during low-to-high signal transitions. This improves
signal integrity, which allows adequate noise margin to be maintained at higher frequencies.
Active bus-hold circuitry holds unused or undriven LVTTL data inputs at a valid logic state. Use of pullup or
pulldown resistors with the bus-hold circuitry is not recommended.
When V
is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down.
CC
However, to ensure the high-impedance state above 1.5 V, the output-enable (OE) input should be tied to V
CC
through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of
the driver.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
PACKAGE
T
A
TSSOP – DGG Tape and reel
TVSOP – DGV Tape and reel
SN74GTLPH16912GR
SN74GTLPH16912VR
GTLPH16912
GL912
–40°C to 85°C
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74GTLPH16912
18-BIT LVTTL-TO-GTLP UNIVERSAL BUS TRANSCEIVER
SCES288C – OCTOBER 1999 – REVISED JULY 2001
functional description
The SN74GTLPH16912 is a medium-drive (50 mA), 18-bit UBT transceiver containing D-type latches and
D-type flip-flops for data-path operation in transparent, latched, clocked, or clock-enabled modes and can
replace any of the functions shown in Table 1. Data polarity is noninverting.
Table 1. SN74GTLPH16912 UBT Transceiver Replacement Functions
FUNCTION
8 BIT
’245, ’623, ’645
’241, ’244, ’541
’543
9 BIT
10 BIT
’861
16 BIT
’16245, ’16623
’16241, ’16244, ’16541
’16543
18 BIT
’16863
’16825
’16472
’16843
’16474
Transceiver
Buffer/driver
’863
’827
Latched transceiver
Latch
’373, ’573
’646, ’652
’374, ’574
’843
’841
’821
’16373
Registered transceiver
Flip-flop
’16646, ’16652
’16374
Standard UBT
’16500, ’16501
’16835
Universal bus driver
Registered transceiver with clock enable
Flip-flop with clock enable
Standard UBT with clock enable
’2952
’377
’16470, ’16952
’823
’16823
’16600, ’16601
SN74GTLPH16912 UBT transceiver replaces all above functions
Data flow in each direction is controlled by clock enables (CEAB and CEBA), latch enables (LEAB and LEBA),
clock (CLKAB and CLKBA), and output enables (OEAB and OEBA). CEAB and CEBA and OEAB and OEBA
control the 18 bits of data for the A-to-B and B-to-A directions, respectively.
For A-to-B data flow, when CEAB is low, the device operates on the low-to-high transition of CLKAB for the
flip-flop and on the high-to-low transition of LEAB for the latch path, i.e., if CEAB and LEAB are low, the A data
is latched, regardless of the state of CLKAB (high or low). If LEAB is high, the device is in transparent mode.
When OEAB is low, the outputs are active. When OEAB is high, the outputs are in the high-impedance state.
The data flow for B to A is similar to that of A to B, except CEBA, OEBA, LEBA, and CLKBA are used.
†
FUNCTION TABLE
INPUTS
OUTPUT
B
MODE
Isolation
CEAB OEAB LEAB CLKAB
A
X
X
X
L
X
L
H
L
L
L
L
L
L
L
X
L
X
H
L
Z
‡
B
0
§
B
0
Latched storage of A data
L
L
X
X
L
H
H
L
X
X
↑
L
H
L
True transparent
H
L
Clocked storage of A data
Clock inhibit
L
L
↑
H
X
H
§
B
0
H
L
X
†
A-to-B data flow is shown. B-to-A data flow is similar, but uses CEBA, OEBA, LEBA, and
CLKBA. The condition when OEAB and OEBA are both low at the same time is not
recommended.
‡
§
Output level before the indicated steady-state input conditions were established, provided
that CLKAB was high before LEAB went low
Output level before the indicated steady-state input conditions were established
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74GTLPH16912
18-BIT LVTTL-TO-GTLP UNIVERSAL BUS TRANSCEIVER
SCES288C – OCTOBER 1999 – REVISED JULY 2001
logic diagram (positive logic)
35
V
REF
1
OEAB
CEAB
56
55
CLKAB
2
LEAB
LEBA
28
30
29
27
3
CLKBA
CEBA
OEBA
A1
CE
1D
54
B1
C1
CLK
CE
1D
C1
CLK
To 17 Other Channels
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74GTLPH16912
18-BIT LVTTL-TO-GTLP UNIVERSAL BUS TRANSCEIVER
SCES288C – OCTOBER 1999 – REVISED JULY 2001
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
and BIAS V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
CC
CC
Input voltage range, V (see Note 1): A-port and control inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
I
B port and V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
REF
Voltage range applied to any output in the high-impedance or power-off state, V
O
(see Note 1): A port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
B port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
Current into any output in the low state, I : A port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 mA
O
B port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA
Current into any A port output in the high state, I (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 mA
O
Continuous current through each V
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
CC
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Package thermal impedance, θ (see Note 3): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W
IK
I
Output clamp current, I
OK
O
JA
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This current flows only when the output is in the high state and V > V
.
CC
O
3. The package thermal impedance is calculated in accordance with JESD 51-7.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74GTLPH16912
18-BIT LVTTL-TO-GTLP UNIVERSAL BUS TRANSCEIVER
SCES288C – OCTOBER 1999 – REVISED JULY 2001
recommended operating conditions (see Notes 4 through 7)
MIN
NOM
MAX
UNIT
V
,
CC
BIAS V
Supply voltage
3.15
3.3
3.45
V
CC
GTL
1.14
1.35
0.74
0.87
1.2
1.5
0.8
1
1.26
1.65
0.87
1.1
V
V
V
V
V
Termination voltage
V
V
V
V
V
TT
REF
I
GTLP
GTL
Reference voltage
Input voltage
GTLP
B port
V
TT
5.5
Except B port
B port
V
CC
V
+0.05
REF
High-level input voltage
Low-level input voltage
IH
IL
Except B port
B port
2
V
–0.05
REF
Except B port
0.8
–18
–24
24
I
I
Input clamp current
mA
mA
IK
High-level output current
A port
OH
OL
A port
I
Low-level output current
mA
B port
50
∆t/∆v
∆t/∆V
Input transition rise or fall rate
Power-up ramp rate
Outputs enabled
10
ns/V
µs/V
°C
20
CC
T
A
Operating free-air temperature
–40
85
NOTES: 4. All unused inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
5. Proper connection sequence for use of the B-port I/O precharge feature is GND and BIAS V
= 3.3 V first, I/O second, and
CC
pin is connected. The control and V
REF
V
CC
= 3.3 V last, because the BIAS V
precharge circuitry is disabled when any V
CC
CC
inputs can be connected anytime, but normally are connected during the I/O stage. If B-port precharge is not required, any
connection sequence is acceptable, but generally, GND is connected first.
6.
7.
V
V
and R can be adjusted to accommodate backplane impedances if the dc recommended I
ratings are not exceeded.
can be adjusted to optimize noise margins, but normally is two-thirds V . TI-OPC circuitry is enabled in the A-to-B direction
TT
TT OL
REF
TT
and is activated when V > 0.7 V above V
minimize current drain.
. If operated in the A-to-B direction, V
should be set to within 0.6 V of V to
TT
TT
REF REF
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74GTLPH16912
18-BIT LVTTL-TO-GTLP UNIVERSAL BUS TRANSCEIVER
SCES288C – OCTOBER 1999 – REVISED JULY 2001
electrical characteristics over recommended operating free-air temperature range for GTLP
(unless otherwise noted)
†
TYP
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
V
V
V
= 3.15 V,
I = –18 mA
–1.2
V
IK
CC
I
= 3.15 V to 3.45 V,
I
I
I
I
I
I
I
I
I
I
= –100 µA
= –12 mA
= –24 mA
= 100 µA
= 12 mA
= 24 mA
= 100 µA
= 10 mA
= 40 mA
= 50 mA
V
CC
–0.2
CC
OH
OH
OH
OL
OL
OL
OL
OL
OL
OL
V
OH
A port
2.4
2
V
V
CC
V
CC
V
CC
V
CC
= 3.15 V
= 3.15 V to 3.45 V,
= 3.15 V
0.2
0.4
A port
0.5
V
OL
= 3.15 V to 3.45 V,
0.2
V
0.2
B port
V
= 3.15 V
= 3.45 V
0.4
CC
CC
0.55
±10
±20
±10
V = 0 or V
I
A-port and
control inputs
CC
‡
I
I
V = 5.5 V
I
V
µA
V = 0 to 1.5 V
I
B port
A port
A port
§
I
I
I
I
V
CC
V
CC
V
CC
V
CC
= 3.15 V,
= 3.15 V,
= 3.45 V,
= 3.45 V,
V = 0.8 V
I
75
–75
µA
µA
µA
µA
BHL
¶
V = 2 V
I
BHH
#
A port
A port
V = 0 to V
500
BHLO
BHHO
I
CC
CC
||
V = 0 to V
I
–500
Outputs high
Outputs low
50
50
50
V
= 3.45 V, I = 0,
O
CC
I
A or B port
mA
V (A-port or control input) = V
or GND,
CC
I
CC
V (B port) = V or GND
I
TT
Outputs disabled
V
= 3.45 V, One A-port or control input at V
– 0.6 V,
CC
CC
1.5
mA
pF
∆I
CC
Other A-port or control inputs at V
or GND
CC
C
C
Control inputs
A port
V = 3.15 V or 0
I
4
7
5.5
8.5
9.5
i
V
= 3.15 V or 0
= 1.5 V or 0
O
O
pF
io
B port
V
8.5
†
‡
§
All typical values are at V
= 3.3 V, T = 25°C.
A
I
CC
For I/O ports, the parameter I includes the off-state output leakage current.
The bus-hold circuit can sink at least the minimum low sustaining current at V max. I
then raising it to V max.
IL
The bus-hold circuit can source at least the minimum high sustaining current at V min. I
should be measured after lowering V to GND and
IN
IL
BHL
¶
should be measured after raising V to V
IN
and
CC
IH
BHH
then lowering it to V min.
IH
#
||
An external driver must source at least I
to switch this node from low to high.
BHLO
to switch this node from high to low.
An external driver must sink at least I
BHHO
This is the increase in supply current for each input that is at the specified TTL voltage level rather than V
or GND.
CC
hot-insertion specifications for A port over recommended operating free-air temperature range
PARAMETER
TEST CONDITIONS
BIAS V = 0,
MIN
MAX
10
UNIT
µA
I
I
I
V
CC
V
CC
V
CC
= 0,
V or V = 0 to 5.5 V
I O
off
CC
= 0 to 1.5 V,
= 1.5 V to 0,
V
= 0.5 V to 3 V,
= 0.5 V to 3 V,
OE = 0
OE = 0
±30
±30
µA
OZPU
OZPD
O
O
V
µA
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74GTLPH16912
18-BIT LVTTL-TO-GTLP UNIVERSAL BUS TRANSCEIVER
SCES288C – OCTOBER 1999 – REVISED JULY 2001
live-insertion specifications for B port over recommended operating free-air temperature range
PARAMETER
TEST CONDITIONS
MIN
MAX
10
UNIT
µA
µA
µA
mA
µA
V
I
I
I
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 0,
BIAS V
BIAS V
BIAS V
= 0,
= 0,
= 0,
V or V = 0 to 1.5 V
off
CC
CC
CC
I
O
= 0 to 1.5 V,
= 1.5 V to 0,
= 0 to 3.15 V
= 3.15 V to 3.45 V
= 0,
V
= 0.5 V to 1.5 V, OE = 0
±30
±30
5
OZPU
OZPD
O
O
V
= 0.5 V to 1.5 V, OE = 0
I
(BIAS V
)
BIAS V
= 3.15 V to 3.45 V,
V
O
(B port) = 0 to 1.5 V
CC
CC
CC
10
V
BIAS V
BIAS V
= 3.3 V,
I
O
= 0
0.95
1.05
O
CC
I
= 0,
= 3.15 V to 3.45 V,
V
O
(B port) = 0.6 V
–1
µA
O
CC
timing requirements over recommended ranges of supply voltage and operating free-air
temperature, V = 1.5 V and V
= 1 V for GTLP (unless otherwise noted)
TT
REF
MIN
MAX
UNIT
f
t
Clock frequency
Pulse duration
175
MHz
clock
LEAB or LEBA high
CLKAB or CLKBA high or low
A before CLKAB↑
B before CLKBA↑
A before LEAB↓
2.8
2.8
1.8
1.5
1
ns
ns
w
t
su
Setup time
B before LEBA↓
2
CEAB before CLKAB↑
CEBA before CLKBA↑
A after CLKAB↑
1.5
1.4
0.3
0.4
1.1
0.4
1
B after CLKBA↑
A after LEAB↓
t
h
Hold time
ns
B after LEBA↓
CEAB after CLKAB↑
CEBA after CLKBA↑
1
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74GTLPH16912
18-BIT LVTTL-TO-GTLP UNIVERSAL BUS TRANSCEIVER
SCES288C – OCTOBER 1999 – REVISED JULY 2001
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, V = 1.5 V and V
= 1 V for GTLP (see Figure 1)
TT
REF
FROM
(INPUT)
TO
(OUTPUT)
†
PARAMETER
MIN TYP
MAX
UNIT
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
175
2.1
2.1
2.2
2.2
2.2
2.2
2
MHz
max
PLH
PHL
PLH
PHL
PLH
PHL
en
6
6
A
B
B
B
B
ns
ns
ns
ns
6.3
6.3
6.5
6.5
6.5
6.1
LEAB
CLKAB
OEAB
2
dis
Rise time, B outputs (20% to 80%)
Fall time, B outputs (80% to 20%)
2.4
2
ns
ns
r
f
1.8
1.8
0.4
0.4
.6
5.8
5.8
5.3
5.3
5.6
5.7
6.2
5.9
PLH
PHL
PLH
PHL
PLH
PHL
en
B
A
A
A
A
ns
ns
ns
ns
LEBA
CLKBA
OEBA
.6
0.3
0.3
dis
†
All typical values are at V
= 3.3 V, T = 25°C.
A
CC
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74GTLPH16912
18-BIT LVTTL-TO-GTLP UNIVERSAL BUS TRANSCEIVER
SCES288C – OCTOBER 1999 – REVISED JULY 2001
PARAMETER MEASUREMENT INFORMATION
1.5 V
25 Ω
6 V
Open
GND
S1
500 Ω
From Output
Under Test
TEST
/t
S1
Open
6 V
From Output
Under Test
Test
Point
t
t
PLH PHL
C
= 50 pF
t
/t
L
PLZ PZL
500 Ω
(see Note A)
C
= 30 pF
(see Note A)
/t
GND
L
PHZ PZH
LOAD CIRCUIT FOR A OUTPUTS
LOAD CIRCUIT FOR B OUTPUTS
t
w
3 V
3 V
0 V
Timing
Input
1.5 V
1.5 V
1.5 V
Input
0 V
t
t
h
su
VOLTAGE WAVEFORMS
PULSE DURATION
V
OH
Data
Input
V
V
M
M
0 V
3 V
0 V
Input
1.5 V
1.5 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
(V = 1.5 V for A port and 1 V for B port)
M
t
t
PHL
PLH
(V
OH
= 3 V for A port and 1.5 V for B port)
V
V
OH
Output
1 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
(A port to B port)
1 V
3 V
Output
Control
OL
1.5 V
1.5 V
0 V
3 V
t
t
PLZ
PZL
Output
Waveform 1
S1 at 6 V
1.5 V
0 V
1.5 V
1 V
1 V
V
OL
+ 0.3 V
Input
V
OL
OH
(see Note B)
t
t
PHZ
PZH
t
t
PHL
PLH
Output
Waveform 2
S1 at GND
V
V
V
OH
V
OH
– 0.3 V
1.5 V
1.5 V
1.5 V
Output
≈0 V
(see Note B)
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
(B port to A port)
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
(A port)
NOTES: A.
C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≈ 10 MHz, Z = 50 Ω, t ≈ 2 ns, t ≈ 2 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuits and Voltage Waveforms
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74GTLPH16912
18-BIT LVTTL-TO-GTLP UNIVERSAL BUS TRANSCEIVER
SCES288C – OCTOBER 1999 – REVISED JULY 2001
DISTRIBUTED-LOAD BACKPLANE SWITCHING CHARACTERISTICS
The preceding switching characteristics table shows the switching characteristics of the device into a lumped load
(Figure 1). However, the designer’s backplane application probably is a distributed load. The physical representation
is shown in Figure 2. This backplane, or distributed load, can be approximated closely to a resistor inductance
capacitance (RLC) circuit, as shown in Figure 3. This device has been designed for optimum performance in this RLC
circuit. The following switching characteristics table shows the switching characteristics of the device into the RLC
load, to help the designer better understand the performance of the GTLP device in this typical backplane. See
www.ti.com/sc/gtlp for more information.
1.5 V
1.5 V
Z
O
= 70 Ω
.25”
2”
2”
.25”
1.5 V
19 Ω
Conn.
Conn.
Conn.
Conn.
L
L
= 19 nH
From Output
Under Test
Test
Point
1”
1”
1”
1”
C
= 9 pF
Rcvr
Rcvr
Rcvr
L
Drvr
Slot 1
Slot 2
Slot 9
Slot 10
Figure 2. Medium-Drive Test Backplane
Figure 3. Medium-Drive RLC Network
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, V = 1.5 V and V
= 1 V for GTLP (see Figure 3)
TT
REF
FROM
(INPUT)
TO
(OUTPUT)
†
TYP
PARAMETER
UNIT
t
t
t
t
t
t
t
t
t
t
4.5
4.5
4.7
4.7
4.7
4.7
4.8
4.4
1.2
2.5
PLH
PHL
PLH
PHL
PLH
PHL
en
A
B
B
B
B
ns
LEAB
CLKAB
OEAB
ns
ns
ns
dis
Rise time, B outputs (20% to 80%)
Fall time, B outputs (80% to 20%)
ns
ns
r
f
†
All typical values are at V
= 3.3 V, T = 25°C. All values are derived from TI-SPICE models.
CC
A
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,23
0,13
M
0,07
0,40
24
13
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–ā8°
0,75
1
12
0,50
A
Seating Plane
0,08
0,15
0,05
1,20 MAX
PINS **
14
16
20
24
38
48
56
DIM
A MAX
A MIN
3,70
3,50
3,70
3,50
5,10
4,90
5,10
4,90
7,90
7,70
9,80
9,60
11,40
11,20
4073251/E 08/00
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
D. Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
M
0,08
0,50
48
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
0,25
1
24
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
48
56
64
DIM
A MAX
12,60
12,40
14,10
13,90
17,10
16,90
A MIN
4040078/F 12/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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相关型号：
SN74GTLPH16927ZQLR
GTLP SERIES, 18-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PBGA56, GREEN, PLASTIC, VFBGA-56
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