SN74GTLPH16927DGG [TI]
18-BIT LVTTL-TO-GTLP BUS TRANSCEIVER WITH SOURCE-SYNCHRONOUS CLOCK OUTPUTS; 18位LVTTL至GTLP带源同步时钟输出总线收发器
| 型号： | SN74GTLPH16927DGG |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 18-BIT LVTTL-TO-GTLP BUS TRANSCEIVER WITH SOURCE-SYNCHRONOUS CLOCK OUTPUTS |
| 文件： | 总19页 (文件大小：361K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74GTLPH16927
18-BIT LVTTL-TO-GTLP BUS TRANSCEIVER
WITH SOURCE-SYNCHRONOUS CLOCK OUTPUTS
SCES413 – OCTOBER 2002
DGG OR DGV PACKAGE
(TOP VIEW)
Member of the Texas Instruments
Widebus Family
TI-OPC Circuitry Limits Ringing on
Unevenly Loaded Backplanes
1
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
DIR
OE
A1
GND
A2
A3
FSTA
BIAS V
B1
GND
B2
2
CC
OEC Circuitry Improves Signal Integrity
and Reduces Electromagnetic Interference
3
4
Bidirectional Interface Between GTLP
Signal Levels and LVTTL Logic Levels
5
6
B3
7
V
V
GTLP Buffered SYSCLK Signal (SSCLK) for
Source-Synchronous Applications
CC
REF
8
A4
A5
A6
GND
A7
B4
B5
B6
GND
B7
9
LVTTL Interfaces Are 5-V Tolerant
Medium-Drive GTLP Outputs (50 mA)
LVTTL Outputs (–24 mA/24 mA)
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
GTLP Rise and Fall Times Designed for
Optimal Data-Transfer Rate and Signal
Integrity in Distributed Loads
A8
A9
B8
B9
A10
A11
A12
GND
A13
A14
A15
B10
B11
B12
GND
B13
B14
B15
CMS
B16
B17
GND
B18
SSCLK
I
, Power-Up 3-State, and BIAS V
CC
off
Support Live Insertion
Bus Hold on A-Port Data Inputs
Distributed V
High-Speed Switching Noise
and GND Pins Minimize
CC
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
V
CC
A16
A17
GND
A18
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
CLKOUT
CKOE
SYSCLK
description/ordering information
The SN74GTLPH16927 is a medium-drive, 18-bit bus transceiver that provides LVTTL-to-GTLP and
GTLP-to-LVTTL signal-level translation. The device allows for transparent and latched modes of data transfer.
Additionally, with the use of the clock-mode select (CMS) input, the device can be used in source-synchronous
and clock-synchronous applications. Source-synchronous applications require the skew between the clock
output and data output to be minimized for optimum maximum-frequency system performance. In order to
reduce this skew, a flexible setup-time adjustment (FSTA) feature is incorporated into the device that sets a
predetermined delay between the clock and data. The CMS and direction (DIR) inputs control the mode of the
device.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
T
PACKAGE
TSSOP – DGG
A
Tape and reel
Tape and reel
Tape and reel
SN74GTLPH16927GR
SN74GTLPH16927VR
SN74GTLPH16927KR
GTLPH16927
GL927
–40°C to 85°C TVSOP – DGV
VFBGA – GQL
GL927
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
OEC, TI-OPC, and Widebus are trademarks of Texas Instruments.
Copyright 2002, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74GTLPH16927
18-BIT LVTTL-TO-GTLP BUS TRANSCEIVER
WITH SOURCE-SYNCHRONOUS CLOCK OUTPUTS
SCES413 – OCTOBER 2002
description/ordering information (continued)
The system clock (SYSCLK) and CLKOUT pins are LVTTL compatible, while the source-synchronous I/O is
GTLP compatible. The benefits include compensation for output-to-output skew coming from the driver itself,
and compensation for process skew if more than one driver is used. The device provides a high-speed interface
between cards operating at LVTTL logic levels and a backplane operating at GTLP signal levels. High-speed
(about three times faster than standard TTL or LVTTL) backplane operation is a direct result of GTLP’s reduced
output swing (<1 V), reduced input threshold levels, improved differential input, OEC circuitry, and TI-OPC
circuitry. Improved GTLP OEC and TI-OPC circuits minimize bus-settling time and have been designed and
tested using several backplane models. The medium drive allows incident-wave switching in heavily loaded
backplanes with equivalent load impedance down to 11 Ω.
GTLP is the Texas Instruments derivative of the Gunning Transceiver Logic (GTL) JEDEC standard JESD 8-3.
The ac specification of the SN74GTLPH16927 is given only at the preferred higher noise-margin GTLP, but the
user has the flexibility of using this device at either GTL (V = 1.2 V and V
= 0.8 V) or GTLP (V = 1.5 V
TT
REF
TT
and V
= 1 V) signal levels. For information on using GTLP devices in FB+/BTL applications, refer to TI
REF
application reports, Texas Instruments GTLP Frequently Asked Questions, literature number SCEA019, and
GTLP in BTL Applications, literature number SCEA017.
Normally, the B port operates at GTLP signal levels. The A-port and control inputs operate at LVTTL logic levels,
but are 5-V tolerant and are compatible with TTL and 5-V CMOS inputs. V
reference voltage.
is the B-port differential input
REF
This device is fully specified for live-insertion applications using I , power-up 3-state, and BIAS V . The I
off
off
CC
circuitry disables the outputs, preventing damaging current backflow through the device when it is powered
down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power
down, which prevents driver conflict. The BIAS V
circuitry precharges and preconditions the B-port
CC
input/output connections, preventing disturbance of active data on the backplane during card insertion or
removal, and permits true live-insertion capability.
This GTLP device features TI-OPC circuitry, which actively limits the overshoot caused by improperly
terminated backplanes, unevenly distributed cards, or empty slots during low-to-high signal transitions. This
improves signal integrity, which allows adequate noise margin to be maintained at higher frequencies.
Active bus-hold circuitry holds unused or undriven LVTTL data inputs at a valid logic state. Use of pullup or
pulldown resistors with the bus-hold circuitry is not recommended.
When V
is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down.
CC
However, to ensure the high-impedance state above 1.5 V, the output-enable (OE) input should be tied to V
CC
through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of
the driver.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74GTLPH16927
18-BIT LVTTL-TO-GTLP BUS TRANSCEIVER
WITH SOURCE-SYNCHRONOUS CLOCK OUTPUTS
SCES413 – OCTOBER 2002
GQL PACKAGE
(TOP VIEW)
terminal assignments
1
2
3
4
5
6
1
2
OE
3
4
5
BIAS V
B2
6
A
B
C
D
E
F
A1
DIR
GND
FSTA
GND
B1
CC
A
B
C
D
A3
A2
B3
A5
A4
V
V
B4
B5
CC
REF
A7
A6
GND
GND
B6
B7
A9
A8
B8
B9
E
F
A10
A12
A14
A16
A18
A11
A13
A15
A17
CLKOUT
B11
B13
B15
B17
B10
B12
B14
B16
B18
G
H
J
GND
GND
CMS
G
H
J
V
CC
GND
GND
K
CKOE
SYSCLK
SSCLK
K
functional description
TheSN74GTLPH16927isamedium-drive(50mA), 18-bitbustransceivercontainingD-typelatchesandD-type
flip-flops for data-path operation in transparent or latched modes and can replace any of the functions shown
in Table 1. Data polarity is noninverting.
Table 1. SN74GTLPH16927 Bus-Transceiver Replacement Functions
FUNCTION
Transceiver
8 BIT
’245, ’623, ’645
’241, ’244, ’541
’543
9 BIT
10 BIT
’861
16 BIT
18 BIT
’863
’16245, ’16623
’16863
Buffer/driver
Latched transceiver
Latch
’827
’16241, ’16244, ’16541 ’16825
’16543
’16373
’16472
’16843
’373, ’573
’843
’841
SN74GTLPH16927 bus transceiver replaces all above functions
Additionally, the device allows for conversion of the system clock (SYSCLK) to GTLP signal levels (SSCLK) and
LVTTL signal levels (CLKOUT). It also provides conversion of a GTLP source-synchronous clock to LVTTL
signal levels (CLKOUT).
The device allows for conversion of the LVTTL system clock (SYSCLK) to GTLP (SSCLK) and LVTTL
(CLKOUT) signal levels when used as the transmitter and GTLP source-synchronous clock (SSCLK) to LVTTL
(CLKOUT) signal levels when used as the receiver in source-synchronous applications. Source-synchronous
operation removes time-of-flight restrictions and allows for increased data throughput. CMS is used to switch
between system-synchronous mode and clock-synchronous mode. The clock output-enable (CKOE) input is
used to switch between latched and transparent mode.
Data flow in each direction is controlled by CKOE, clock (SYSCLK or SSCLK), DIR, and OE. OE controls the
18 bits of data. The CLKOUT/SSCLK buffered clock path for the A-to-B and B-to-A directions is controlled by
CKOE. In the data-isolation mode (OE high, CKOE low), A data can be stored in one register and/or B data can
be stored in the other register.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74GTLPH16927
18-BIT LVTTL-TO-GTLP BUS TRANSCEIVER
WITH SOURCE-SYNCHRONOUS CLOCK OUTPUTS
SCES413 – OCTOBER 2002
logic diagram (positive logic)
2
OE
1
DIR
35
CMS
28
CKOE
27
CLKOUT
56
FSTA
30
SSCLK
29
SYSCLK
MUX
One of Eighteen
Channels
3
A1
1D
C1
54
50
B1
CLK
1D
C1
V
REF
CLK
To 17 Other Channels
Pin numbers shown are for the DGG and DGV packages.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74GTLPH16927
18-BIT LVTTL-TO-GTLP BUS TRANSCEIVER
WITH SOURCE-SYNCHRONOUS CLOCK OUTPUTS
SCES413 – OCTOBER 2002
Function Tables
A-TO-B DIRECTION
INPUTS
CMS DIR
OUTPUTS
MODE
CKOE
OE
L
SYSCLK
A
X
L
SSCLK CLKOUT
SYSCLK SYSCLK
SYSCLK SYSCLK
SYSCLK SYSCLK
SYSCLK SYSCLK
B
L
L
X
X
X
X
X
X
X
H
H
L
L
L
L
L
L
X
X
X
H or L
B
Latched storage of A
Clocked storage of A
1
Source
synchronous
L
↑
L
H
Z
L
L
L
↑
H
X
L
L
H
L
X
Data isolation
H
H
H
L
X
Z
Z
Z
Z
Z
Z
Transparent transmission of A
Isolation
L
X
X
H
X
X
X
H
Z
Z
Z
H
H
H
↑
SYSCLK SYSCLK
SYSCLK SYSCLK
Transmit SYSCLK
L
H or L
B-TO-A DIRECTION
INPUTS
OUTPUTS
SSCLK CLKOUT
MODE
CKOE
OE
L
CMS
DIR
H
H
H
H
H
H
H
H
H
H
X
SYSCLK SSCLK
B
X
L
A
L
L
L
L
L
L
L
L
H
H
H
L
L
L
L
X
H or L
↑
Input
Input
Input
Input
SSCLK
SSCLK
SSCLK
SSCLK
A
1
Latched storage of B
Source
synchronous
L
X
L
H
Z
Clocked storage of B
L
L
X
↑
H
X
X
L
H
L
L
X
X
Data isolation
H
H
H
H
X
X
X
L
H or L
Output
Output
Output
Output
Output
Output
Output
↑
SYSCLK SYSCLK
SYSCLK SYSCLK
SYSCLK SYSCLK
SYSCLK SYSCLK
A
1
Latched storage of B
Clock
synchronous
L
↑
L
H
Z
L
Clocked storage of B
L
↑
H
X
L
H
L
X
X
X
X
X
X
Data isolation
Z
Z
Z
Z
Transparent transmission of B
Isolation
L
H
X
X
X
H
Z
Z
Z
H
H
H
Z
Z
X
Input
Input
SSCLK
SSCLK
Receive SSCLK
L
X
H or L
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74GTLPH16927
18-BIT LVTTL-TO-GTLP BUS TRANSCEIVER
WITH SOURCE-SYNCHRONOUS CLOCK OUTPUTS
SCES413 – OCTOBER 2002
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
and BIAS V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
CC
CC
Input voltage range, V (see Note 1): A-port and control inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
I
B port and V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
REF
Voltage range applied to any output in the high-impedance or power-off state, V
O
(see Note 1): A port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
B port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
Current into any output in the low state, I : A port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 mA
O
B port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA
Current into any A-port output in the high state, I (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 mA
O
Continuous current through each V
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
CC
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Package thermal impedance, θ (see Note 3): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W
IK
I
Output clamp current, I
OK
O
JA
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48°C/W
GQL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This current flows only when the output is in the high state and V > V
.
CC
O
3. The package thermal impedance is calculated in accordance with JESD 51-7.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74GTLPH16927
18-BIT LVTTL-TO-GTLP BUS TRANSCEIVER
WITH SOURCE-SYNCHRONOUS CLOCK OUTPUTS
SCES413 – OCTOBER 2002
recommended operating conditions (see Notes 4 through 7)
MIN
NOM
MAX
UNIT
V
,
CC
BIAS V
Supply voltage
3.15
3.3
3.45
V
CC
GTL
1.14
1.35
0.74
0.87
1.2
1.5
0.8
1
1.26
1.65
0.87
1.1
V
V
V
V
V
Termination voltage
V
V
V
V
V
TT
REF
I
GTLP
GTL
Reference voltage
Input voltage
GTLP
B port and SSCLK
Except B port and SSCLK
B port and SSCLK
Except B port, FSTA, and SSCLK
B port and SSCLK
Except B port, FSTA, and SSCLK
V
TT
5.5
V
CC
V
+0.05
REF
High-level input voltage
Low-level input voltage
IH
IL
2
V
–0.05
REF
0.8
–18
–24
24
I
I
Input clamp current
mA
mA
IK
High-level output current
A port and CLKOUT
A port and CLKOUT
B port and SSCLK
Outputs enabled
OH
OL
I
Low-level output current
mA
50
∆t/∆v
∆t/∆V
Input transition rise or fall rate
Power-up ramp rate
10
ns/V
µs/V
°C
20
CC
T
A
Operating free-air temperature
–40
85
NOTES: 4. All unused inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
5. Proper connection sequence for use of the B-port I/O precharge feature is GND and BIAS V
= 3.3 V first, I/O second, and
CC
V
CC
=3.3Vlast,becausetheBIASV
prechargecircuitryisdisabledwhenanyV
pinisconnected.ThecontrolandV inputs
CC
CC
REF
can be connected anytime, but normally are connected during the I/O stage. If B-port precharge is not required, any connection
sequence is acceptable but, generally, GND is connected first.
6.
7.
V
V
and R can be adjusted to accommodate backplane impedances if the dc recommended I
ratings are not exceeded.
can be adjusted to optimize noise margins, but normally is two-thirds V . TI-OPC circuitry is enabled in the A-to-B direction
TT
TT OL
REF
TT
and is activated when V > 0.7 V above V
minimize current drain.
. If operated in the A-to-B direction, V
should be set to within 0.6 V of V to
TT
TT
REF REF
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74GTLPH16927
18-BIT LVTTL-TO-GTLP BUS TRANSCEIVER
WITH SOURCE-SYNCHRONOUS CLOCK OUTPUTS
SCES413 – OCTOBER 2002
electrical characteristics over recommended operating free-air temperature range for GTLP
(unless otherwise noted)
†
TYP
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
V
V
V
= 3.15 V,
I = –18 mA
–1.2
V
IK
CC
I
= 3.15 V to 3.45 V,
I
I
I
I
I
I
I
I
I
I
= –100 µA
= –12 mA
= –24 mA
= 100 µA
= 12 mA
= 24 mA
= 100 µA
= 10 mA
= 40 mA
= 50 mA
V
–0.2
CC
OH
OH
OH
OL
OL
OL
OL
OL
OL
OL
CC
A port and
CLKOUT
V
OH
2.4
2
V
V
CC
V
CC
V
CC
V
CC
= 3.15 V
= 3.15 V to 3.45 V,
= 3.15 V
0.2
0.4
A port and
CLKOUT
0.5
V
OL
= 3.15 V to 3.45 V,
0.2
V
0.2
B port and SSCLK
V
CC
= 3.15 V
0.4
0.55
SYSCLK and
control inputs
I
I
V
= 3.45 V,
V = 0 to 5.5 V
±10
µA
µA
I
CC
I
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 3.45 V, V
= 3.45 V,
= 3.45 V,
= 3.45 V,
= 3.15 V,
= 3.15 V,
= 3.45 V,
= 3.45 V,
within 0.6 V of V
,
V
O
V
O
V
O
V
O
= 0 to 2.3 V
= 0 to 5.5 V
±10
±10
10
B port and SSCLK
CLKOUT
A port
REF
TT
‡
OZ
‡
I
I
I
I
I
I
= V
CC
µA
µA
µA
µA
µA
µA
OZH
‡
= GND
–10
A port
OZL
BHL
BHH
§
A port
V = 0.8 V
I
75
–75
¶
A port
V = 2 V
I
#
A port
V = 0 to V
500
BHLO
I
CC
CC
||
A port
V = 0 to V
I
–500
BHHO
Outputs high
Outputs low
50
50
50
V
= 3.45 V, I = 0,
O
CC
A port, B port, or
SSCLK
I
mA
V (A-port or control input) = V
or GND,
CC
I
CC
V (B port) = V or GND
I
TT
Outputs disabled
V
= 3.45 V, One A-port or control input at V
– 0.6 V,
CC
CC
1.5
mA
pF
∆I
CC
Other A-port or control inputs at V
or GND
CC
SYSCLK inputs
Control inputs
A port
V = 3.15 V or 0
I
3.5
3.5
7.5
9
5
5.5
10
C
i
V = 3.15 V or 0
I
V
O
V
O
V
O
= 3.15 V or 0
= 1.5 V or 0
= 3.15 V or 0
C
C
pF
pF
io
o
B port or SSCLK
CLKOUT
11
6
7.5
†
‡
§
All typical values are at V
= 3.3 V, T = 25°C.
A
I
CC
For I/O ports, the parameter I includes the off-state output leakage current.
The bus-hold circuit can sink at least the minimum low sustaining current at V max. I
then raising it to V max.
IL
The bus-hold circuit can source at least the minimum high sustaining current at V min. I
should be measured after lowering V to GND and
IN
IL
BHL
¶
should be measured after raising V to V
IN
and
CC
IH
BHH
then lowering it to V min.
IH
#
||
An external driver must source at least I
to switch this node from low to high.
BHLO
to switch this node from high to low.
An external driver must sink at least I
This is the increase in supply current for each input that is at the specified TTL voltage level, rather than V
BHHO
or GND.
CC
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74GTLPH16927
18-BIT LVTTL-TO-GTLP BUS TRANSCEIVER
WITH SOURCE-SYNCHRONOUS CLOCK OUTPUTS
SCES413 – OCTOBER 2002
hot-insertion specifications for A port over recommended operating free-air temperature range
PARAMETER
TEST CONDITIONS
BIAS V = 0,
MIN
MAX
10
UNIT
µA
I
I
I
V
CC
V
CC
V
CC
= 0,
V or V = 0 to 5.5 V
I O
off
CC
= 0 to 1.5 V,
= 1.5 V to 0,
V
= 0.5 V to 3 V,
= 0.5 V to 3 V,
OE = 0
OE = 0
±30
±30
µA
OZPU
OZPD
O
O
V
µA
live-insertion specifications for B port over recommended operating free-air temperature range
PARAMETER
TEST CONDITIONS
MIN
MAX
10
UNIT
µA
µA
µA
mA
µA
V
I
I
I
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 0,
BIAS V
BIAS V
BIAS V
= 0,
= 0,
= 0,
V or V = 0 to 1.5 V
off
CC
CC
CC
I
O
= 0 to 1.5 V,
= 1.5 V to 0,
= 0 to 3.15 V
= 3.15 V to 3.45 V
= 0,
V
= 0.5 V to 1.5 V, OE = 0
±30
±30
5
OZPU
OZPD
O
O
V
= 0.5 V to 1.5 V, OE = 0
I
(BIAS V
CC
)
BIAS V
= 3.15 V to 3.45 V,
V
O
(B port) = 0 to 1.5 V
CC
CC
10
V
BIAS V
BIAS V
= 3.3 V,
I
O
= 0
0.95
1.05
O
CC
I
= 0,
= 3.15 V to 3.45 V,
V
O
(B port) = 0.6 V
–1
µA
O
CC
timing requirements over recommended ranges of supply voltage and operating free-air
temperature, V = 1.5 V and V
= 1 V for GTLP (unless otherwise noted)
TT
REF
MIN
MAX
UNIT
f
t
Clock frequency
Pulse duration
175
MHz
clock
CKOE high
2.8
3.3
1.2
2.6
1.2
2.6
0.3
0.8
1.1
0.3
ns
ns
w
SYSCLK or SSCLK high or low
A before SYSCLK↑
B before SYSCLK↑ or SSCLK↑
A before CKOE↓
t
Setup time
Hold time
su
h
B before CKOE↓
A after SYSCLK↑
B after SYSCLK↑ or SSCLK↑
A after CKOE↓
t
ns
B after CKOE↓
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74GTLPH16927
18-BIT LVTTL-TO-GTLP BUS TRANSCEIVER
WITH SOURCE-SYNCHRONOUS CLOCK OUTPUTS
SCES413 – OCTOBER 2002
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, V = 1.5 V and V
= 1 V for GTLP (see Figure 1)
TT
REF
FROM
(INPUT)
TO
(OUTPUT)
†
PARAMETER
MIN TYP
MAX
UNIT
f
t
t
t
t
t
t
t
t
A
B
175
3.1
3.1
3.6
3.6
3.7
3.7
3.3
3.3
MHz
max
PLH
PHL
PLH
PHL
PLH
PHL
en
6.5
6.5
7.1
7.1
7.3
7.3
7
A
B
ns
ns
ns
ns
B
B
B
CKOE
SYSCLK
OE
7
dis
Rise time, B and SSCLK outputs
t
r
t
f
2.2
1.5
ns
ns
(20% to 80%)
Fall time, B and SSCLK outputs
(80% to 20%)
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
2
2
5.3
5.3
5.9
5.9
5.9
5.9
6.7
6.7
7.5
7.5
8.5
8.5
5.8
6.9
5.9
6
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
en
B
A
ns
ns
ns
ns
ns
ns
ns
ns
2.5
2.5
2.4
2.4
2.9
2.9
3.6
3.6
4
A
CKOE
SYSCLK
SSCLK
A
A
SYSCLK
SSCLK
CLKOUT
CLKOUT
A
4
2.1
2.6
2.2
1.8
OE
dis
en
CKOE
CLKOUT
dis
†
All typical values are at V
= 3.3 V, T = 25°C
A
CC
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74GTLPH16927
18-BIT LVTTL-TO-GTLP BUS TRANSCEIVER
WITH SOURCE-SYNCHRONOUS CLOCK OUTPUTS
SCES413 – OCTOBER 2002
skew characteristics over recommended ranges of supply voltage and operating free-air
temperature, V
= 1 V (unless otherwise noted); standard lumped loads, C = 30 pF for B port
REF
L
†
(see Figure 1)
FROM
(INPUT)
TO
(OUTPUT)
TEST
CONDITIONS
PARAMETER
FSTA
MIN
MAX
UNIT
‡
‡
t
t
0.5
0.5
4.7
4.5
4.4
4.6
4.1
3.7
8.9
8.4
8
sk(LH)
sk(HL)
SYSCLK
SYSCLK
ns
B
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 3.15 V, T = 85°C
= 3.3 V, T = 25°C
= 3.45 V, T = –40°C
= 3.15 V, T = 85°C
= 3.3 V, T = 25°C
= 3.45 V, T = –40°C
= 3.15 V, T = 85°C
= 3.3 V, T = 25°C
= 3.45 V, T = –40°C
= 3.15 V, T = 85°C
= 3.3 V, T = 25°C
= 3.45 V, T = –40°C
3.4
3.2
3.1
3.2
2.8
2.4
7.1
6.6
6.3
7.2
6.5
6
SSCLK → B
(see Figure 2)
n
‡
‡
‡
‡
t
t
t
t
GND
GND
ns
ns
ns
ns
sk(LH)
sk(HL)
sk(LH)
sk(HL)
SSCLK → B
(see Figure 2)
n
SYSCLK
SYSCLK
SYSCLK
SSCLK → B
(see Figure 2)
n
V
CC
9
SSCLK → B
(see Figure 2)
n
V
CC
8.2
7.6
‡
SYSCLK
SYSCLK
1.3
1.8
2.8
ns
ns
t
t
t
B
B
sk(t)
§
§
sk(prLH)
sk(prHL)
†
‡
Actual skew values between the GTLP outputs could vary on the backplane due to the loading and impedance seen by the device.
/t and t – Output-to-output skew is defined as the absolute value of the difference between the actual propagation delay for all
t
sk(LH) sk(HL)
sk(t)
outputs with the same packaged device. The specifications are given for specific worst-case V
and temperature. The specifications apply to
CC
], or in opposite directions, both low to high and high
any outputs switching in the same direction, either high to low [t
], low to high [t
sk(LH)
sk(HL)
to low [t
].
or t
sk(t)
§
t
– Part-to-part skew is designed as the absolute value of the difference between the actual propagation delay for all outputs
sk(prLH)
sk(prHL)
from device to device. The parameter is specified for a specific worst-case V
TI SPICE simulations.
and temperature. Furthermore, these values are provided by
CC
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74GTLPH16927
18-BIT LVTTL-TO-GTLP BUS TRANSCEIVER
WITH SOURCE-SYNCHRONOUS CLOCK OUTPUTS
SCES413 – OCTOBER 2002
PARAMETER MEASUREMENT INFORMATION
1.5 V
25 Ω
6 V
Open
GND
S1
500 Ω
From Output
Under Test
TEST
/t
S1
Open
6 V
From Output
Under Test
Test
Point
t
t
PLH PHL
t
/t
C
= 50 pF
PLZ PZL
L
500 Ω
/t
GND
(see Note A)
C
= 30 pF
(see Note A)
PHZ PZH
L
LOAD CIRCUIT FOR A OUTPUTS
LOAD CIRCUIT FOR B OUTPUTS
t
w
3 V
3 V
Timing
Input
1.5 V
1.5 V
1.5 V
Input
0 V
0 V
t
t
h
su
VOLTAGE WAVEFORMS
PULSE DURATION
V
OH
Data
Input
V
M
V
M
0 V
3 V
0 V
Input
1.5 V
1.5 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
(V = 1.5 V for A port and 1 V for B port)
M
t
t
PHL
PLH
(V
OH
= 3 V for A port and 1.5 V for B port)
V
V
OH
Output
1 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
(A port to B port)
1 V
3 V
Output
Control
OL
1.5 V
1.5 V
0 V
3 V
t
t
PLZ
PZL
Output
Waveform 1
S1 at 6 V
1.5 V
0 V
1.5 V
1 V
1 V
V
OL
+ 0.3 V
Input
V
OL
OH
(see Note B)
t
t
PHZ
PZH
t
t
PHL
PLH
Output
Waveform 2
S1 at GND
V
V
V
OH
V
OH
– 0.3 V
1.5 V
1.5 V
1.5 V
Output
≈0 V
(see Note B)
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
(B port to A port)
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
(A port)
NOTES: A.
C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2 ns, t ≤ 2 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
E. Load circuit for A outputs is also used for CLKOUT; load circuit for B outputs is also used for SSCLK.
Figure 1. Load Circuits and Voltage Waveforms
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74GTLPH16927
18-BIT LVTTL-TO-GTLP BUS TRANSCEIVER
WITH SOURCE-SYNCHRONOUS CLOCK OUTPUTS
SCES413 – OCTOBER 2002
1.5 V
25 Ω
From Output
Under Test
Test
Point
C
= 30 pF
L
(see Note A)
LOAD CIRCUIT FOR B OUTPUTS
A
SYSCLK
B
1
t
t
sk(LH)
SYSCLK to B
sk(HL)
SYSCLK to B
through
B
18
SSCLK
t
min
t
min
sk(HL)
SYSCLK to SSCLK → B
sk(LH)
SYSCLK to SSCLK → B
n
n
FSTA (Fast)
FSTA (Fast)
t
max
t max
sk(LH)
SYSCLK to SSCLK → B
sk(HL)
SYSCLK to SSCLK → B
n
n
FSTA (Fast)
FSTA (Fast)
t
min
t
min
sk(LH)
SYSCLK to SSCLK → B
sk(HL)
SYSCLK to SSCLK → B
n
n
FSTA (Slow)
FSTA (Slow)
t
max
t
max
sk(LH)
SYSCLK to SSCLK → B
sk(HL)
SYSCLK to SSCLK → B
n
n
FSTA (Slow)
FSTA (Slow)
NOTES: A.
C
includes probe and jig capacitance.
L
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2 ns, t ≤ 2 ns.
O
r
f
C. The outputs are measured one at a time with one transition per measurement.
D. Load circuit for B outputs also is used for SSCLK.
Figure 2. Load Circuit and SYSCLK to SSCLK → B Skew Waveforms
n
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74GTLPH16927
18-BIT LVTTL-TO-GTLP BUS TRANSCEIVER
WITH SOURCE-SYNCHRONOUS CLOCK OUTPUTS
SCES413 – OCTOBER 2002
DISTRIBUTED-LOAD BACKPLANE SWITCHING CHARACTERISTICS
The preceding switching characteristics table shows the switching characteristics of the device into a lumped load
(Figure 1). However, the designer’s backplane application probably is a distributed load. The physical representation
is shown in Figure 3. This backplane, or distributed load, can be closely approximated to a resistor inductance
capacitance (RLC) circuit, as shown in Figure 4. This device has been designed for optimum performance in this RLC
circuit. The following switching characteristics table shows the switching characteristics of the device into the RLC
load, to help the designer to better understand the performance of the GTLP device in this typical backplane. See
www.ti.com/sc/gtlp for more information.
1.5 V
1.5 V
1.5 V
Z
O
= 70 Ω
.25”
2”
2”
.25”
19 Ω
Conn.
Conn.
Conn.
Conn.
L
L
= 19 nH
From Output
Under Test
Test
Point
1”
1”
1”
1”
Rcvr
Rcvr
Rcvr
C
= 9 pF
L
Drvr
Slot 1
Slot 2
Slot 19
Slot 20
Figure 4. Medium-Drive RLC Network
Figure 3. Medium-Drive Test Backplane
switching characteristics over recommended operating conditions for the bus transceiver
function (unless otherwise noted) (see Figure 4)
FROM
(INPUT)
TO
(OUTPUT)
†
TYP
PARAMETER
UNIT
t
t
t
t
4.3
4.3
5
PLH
PHL
PLH
PHL
A
B
B
ns
SYSCLK
ns
5
Rise time, B and SSCLK outputs
t
1.2
1.8
ns
ns
r
f
(20% to 80%)
Fall time, B and SSCLK outputs
(80% to 20%)
t
†
All typical values are at V
= 3.3 V, T = 25°C. All values are derived from TI SPICE models.
CC
A
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
25-Feb-2005
PACKAGING INFORMATION
Orderable Device
SN74GTLPH16927DGG
SN74GTLPH16927GR
Status (1)
PREVIEW
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
TSSOP
DGG
56
35
Pb-Free
(RoHS)
CU NIPDAU Level-1-250C-UNLIM
TSSOP
DGG
56
2000
Pb-Free
(RoHS)
CU NIPDAU Level-1-250C-UNLIM
SN74GTLPH16927KR
SN74GTLPH16927VR
ACTIVE
ACTIVE
VFBGA
TVSOP
GQL
DGV
56
56
1000
2000
None
SNPB
Level-1-240C-UNLIM
Pb-Free
(RoHS)
CU NIPDAU Level-1-250C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional
product content details.
None: Not yet available Lead (Pb-Free).
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,
including bromine (Br) or antimony (Sb) above 0.1% of total product weight.
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,23
0,13
M
0,07
0,40
24
13
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–ā8°
0,75
1
12
0,50
A
Seating Plane
0,08
0,15
0,05
1,20 MAX
PINS **
14
16
20
24
38
48
56
DIM
A MAX
A MIN
3,70
3,50
3,70
3,50
5,10
4,90
5,10
4,90
7,90
7,70
9,80
9,60
11,40
11,20
4073251/E 08/00
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
D. Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
M
0,08
0,50
48
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
0,25
1
24
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
48
56
64
DIM
A MAX
12,60
12,40
14,10
13,90
17,10
16,90
A MIN
4040078/F 12/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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Copyright 2005, Texas Instruments Incorporated
相关型号：
SN74GTLPH16927ZQLR
GTLP SERIES, 18-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PBGA56, GREEN, PLASTIC, VFBGA-56
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