SN74GTLPH16912_07 [TI]
18-BIT LVTTL-TO-GTLP UNIVERSAL BUS TRANSCEIVER; 18位LVTTL至GTLP通用总线收发器型号: | SN74GTLPH16912_07 |
厂家: | TEXAS INSTRUMENTS |
描述: | 18-BIT LVTTL-TO-GTLP UNIVERSAL BUS TRANSCEIVER |
文件: | 总18页 (文件大小:324K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
SN74GTLPH16912
18-BIT LVTTL-TO-GTLP UNIVERSAL BUS TRANSCEIVER
www.ti.com
SCES288C–OCTOBER 1999–REVISED JUNE 2005
FEATURES
DGG OR DGV PACKAGE
•
Member of the Texas Instruments Widebus™
(TOP VIEW)
Family
OEAB
LEAB
A1
GND
A2
CEAB
CLKAB
1
2
3
4
5
6
7
8
9
56
55
•
UBT™ Transceiver Combines D-Type Latches
and D-Type Flip-Flops for Operation in
Transparent, Latched, Clocked, and
Clock-Enabled Modes
54 B1
GND
B2
B3
BIAS V
53
52
51
50
•
•
•
TI-OPC™ Circuitry Limits Ringing on
Unevenly Loaded Backplanes
A3
V
CC
CC
OEC™ Circuitry Improves Signal Integrity and
Reduces Electromagnetic Interference
A4
A5
A6 10
GND
A7
A8
49 B4
48 B5
47 B6
Bidirectional Interface Between GTLP Signal
Levels and LVTTL Logic Levels
GND
B7
B8
11
12
13
46
45
44
•
•
•
•
LVTTL Interfaces Are 5-V Tolerant
Medium-Drive GTLP Outputs (50 mA)
LVTTL Outputs (–24 mA/24 mA)
A9 14
A10 15
A11 16
A12 17
43 B9
42 B10
41 B11
40 B12
GTLP Rise and Fall Times Designed for
Optimal Data-Transfer Rate and Signal
Integrity in Distributed Loads
GND
GND
18
39
•
Ioff, Power-Up 3-State, and BIAS VCC Support
Live Insertion
A13 19
A14 20
A15 21
38 B13
37 B14
36 B15
•
•
Bus Hold on A-Port Data Inputs
Distributed VCC and GND Pins Minimize
High-Speed Switching Noise
V
CC
22
35
V
REF
A16 23
A17 24
34 B16
33 B17
32 GND
31 B18
•
•
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
GND 25
A18 26
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
OEBA 27
LEBA 28
30 CLKBA
29 CEBA
– 1000-V Charged-Device Model (C101)
DESCRIPTION/ORDERING INFORMATION
The SN74GTLPH16912 is a medium-drive, 18-bit UBT™ transceiver that provides LVTTL-to-GTLP and
GTLP-to-LVTTL signal-level translation. It allows for transparent, latched, clocked, and clock-enabled modes of
data transfer. The device provides a high-speed interface between cards operating at LVTTL logic levels and a
backplane operating at GTLP signal levels. High-speed (about three times faster than standard TTL or LVTTL)
backplane operation is a direct result of GTLP's reduced output swing (<1 V), reduced input threshold levels,
improved differential input, OEC™ circuitry, and TI-OPC™ circuitry. Improved GTLP OEC and TI-OPC circuits
minimize bus-settling time and have been designed and tested using several backplane models. The medium
drive allows incident-wave switching in heavily loaded backplanes with equivalent load impedance down to 19 Ω.
GTLP is the Texas Instruments (TI™) derivative of the Gunning Transceiver Logic (GTL) JEDEC standard
JESD 8-3. The ac specification of the SN74GTLPH16912 is given only at the preferred higher noise-margin
GTLP, but the user has the flexibility of using this device at either GTL (VTT = 1.2 V and VREF = 0.8 V) or GTLP
(VTT = 1.5 V and VREF = 1 V) signal levels.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus, UBT, TI-OPC, OEC, TI are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 1999–2005, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
SN74GTLPH16912
18-BIT LVTTL-TO-GTLP UNIVERSAL BUS TRANSCEIVER
www.ti.com
SCES288C–OCTOBER 1999–REVISED JUNE 2005
DESCRIPTION/ORDERING INFORMATION (CONTINUED)
Normally, the B port operates at GTLP signal levels. The A-port and control inputs operate at LVTTL logic levels,
but are 5-V tolerant and are compatible with TTL and 5-V CMOS inputs. VREF is the B-port differential input
reference voltage.
This device is fully specified for live-insertion applications using Ioff, power-up 3-state, and BIAS VCC. The Ioff
circuitry disables the outputs, preventing damaging current backflow through the device when it is powered
down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power
down, which prevents driver conflict. The BIAS VCC circuitry precharges and preconditions the B-port input/output
connections, preventing disturbance of active data on the backplane during card insertion or removal, and
permits true live-insertion capability.
This GTLP device features TI-OPC circuitry, which actively limits overshoot caused by improperly terminated
backplanes, unevenly distributed cards, or empty slots during low-to-high signal transitions. This improves signal
integrity, which allows adequate noise margin to be maintained at higher frequencies.
Active bus-hold circuitry holds unused or undriven LVTTL data inputs at a valid logic state. Use of pullup or
pulldown resistors with the bus-hold circuitry is not recommended.
When VCC is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down.
However, to ensure the high-impedance state above 1.5 V, the output-enable (OE) input should be tied to VCC
through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the
driver.
ORDERING INFORMATION
TA
PACKAGE(1)
ORDERABLE PART NUMBER
SN74GTLPH16912GR
TOP-SIDE MARKING
GTLPH16912
GL912
TSSOP – DGG
TVSOP – DGV
Tape and reel
Tape and reel
–40°C to 85°C
SN74GTLPH16912VR
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
2
SN74GTLPH16912
18-BIT LVTTL-TO-GTLP UNIVERSAL BUS TRANSCEIVER
www.ti.com
SCES288C–OCTOBER 1999–REVISED JUNE 2005
FUNCTIONAL DESCRIPTION
The SN74GTLPH16912 is a medium-drive (50-mA), 18-bit UBT transceiver containing D-type latches and D-type
flip-flops for data-path operation in transparent, latched, clocked, or clock-enabled modes and can replace any of
the functions shown in Table 1. Data polarity is noninverting.
Table 1. SN74GTLPH16912 UBT Transceiver Replacement Functions
FUNCTION
8 BIT
'245, '623, '645
'241, '244, '541
'543
9 BIT
10 BIT
'861
16 BIT
'16245, '16623
'16241, '16244, '16541
'16543
18 BIT
'16863
'16825
'16472
'16843
'16474
Transceiver
Buffer/driver
'863
'827
Latched transceiver
Latch
'373, '573
'646, '652
'374, '574
'843
'823
'841
'821
'16373
Registered transceiver
Flip-flop
'16646, '16652
'16374
Standard UBT
'16500, '16501
'16835
Universal bus driver
Registered transceiver with clock enable
Flip-flop with clock enable
Standard UBT with clock enable
'2952
'377
'16470, '16952
'16823
'16600, '16601
SN74GTLPH16912 UBT transceiver replaces all above functions
Data flow in each direction is controlled by clock enables (CEAB and CEBA), latch enables (LEAB and LEBA),
clock (CLKAB and CLKBA), and output enables (OEAB and OEBA). CEAB and CEBA and OEAB and OEBA
control the 18 bits of data for the A-to-B and B-to-A directions, respectively.
For A-to-B data flow, when CEAB is low, the device operates on the low-to-high transition of CLKAB for the
flip-flop and on the high-to-low transition of LEAB for the latch path, i.e., if CEAB and LEAB are low, the A data is
latched, regardless of the state of CLKAB (high or low). If LEAB is high, the device is in transparent mode. When
OEAB is low, the outputs are active. When OEAB is high, the outputs are in the high-impedance state.
The data flow for B to A is similar to that of A to B, except CEBA, OEBA, LEBA, and CLKBA are used.
FUNCTION TABLE(1)
INPUTS
OUTPUT
B
MODE
Isolation
CEAB
OEAB
LEAB
CLKAB
A
X
X
X
L
X
L
H
L
L
L
L
L
L
L
X
L
X
H
L
Z
(2)
B0
Latched storage of A data
(3)
L
L
B0
X
X
L
H
H
L
X
X
↑
L
H
L
True transparent
H
L
Clocked storage of A data
Clock inhibit
L
L
↑
H
X
H
(3)
H
L
X
B0
(1) A-to-B data flow is shown. B-to-A data flow is similar, but uses CEBA, OEBA, LEBA, and CLKBA.
The condition when OEAB and OEBA are both low at the same time is not recommended.
(2) Output level before the indicated steady-state input conditions were established, provided that
CLKAB was high before LEAB went low
(3) Output level before the indicated steady-state input conditions were established
3
SN74GTLPH16912
18-BIT LVTTL-TO-GTLP UNIVERSAL BUS TRANSCEIVER
www.ti.com
SCES288C–OCTOBER 1999–REVISED JUNE 2005
LOGIC DIAGRAM (POSITIVE LOGIC)
35
1
V
REF
OEAB
CEAB
56
55
CLKAB
2
LEAB
LEBA
28
30
29
27
3
CLKBA
CEBA
OEBA
A1
CE
1D
54
B1
C1
CLK
CE
1D
C1
CLK
To 17 Other Channels
4
SN74GTLPH16912
18-BIT LVTTL-TO-GTLP UNIVERSAL BUS TRANSCEIVER
www.ti.com
SCES288C–OCTOBER 1999–REVISED JUNE 2005
Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
VCC
Supply voltage range
BIAS VCC
–0.5
4.6
V
A-port and control inputs
–0.5
–0.5
–0.5
–0.5
7
4.6
7
VI
Input voltage range(2)
V
V
B port and VREF
A port
Voltage range applied to any output in the
high-impedance or power-off state
VO
B port
4.6
48
A port
IO
IO
Current into any output in the low state
mA
B port
100
48
Current into any A-port output in the high state(3)
Continuous current through each VCC or GND
Input clamp current
mA
mA
mA
mA
±100
–50
–50
64
IIK
VI < 0
IOK
Output clamp current
VO < 0
DGG package
DGV package
θJA
Package thermal impedance(4)
Storage temperature range
°C/W
°C
48
Tstg
–65
150
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
(3) This current flows only when the output is in the high state and VO > VCC
.
(4) The package thermal impedance is calculated in accordance with JESD 51-7.
5
SN74GTLPH16912
18-BIT LVTTL-TO-GTLP UNIVERSAL BUS TRANSCEIVER
www.ti.com
SCES288C–OCTOBER 1999–REVISED JUNE 2005
Recommended Operating Conditions(1)(2)(3)(4)
MIN
NOM
MAX
3.45
UNIT
VCC
Supply voltage
BIAS VCC
3.15
3.3
V
GTL
1.14
1.35
0.74
0.87
1.2
1.5
0.8
1
1.26
1.65
0.87
1.1
VTT
VREF
VI
Termination voltage
Reference voltage
Input voltage
V
V
V
V
V
GTLP
GTL
GTLP
B port
VTT
5.5
Except B port
B port
VCC
VREF + 0.05
2
VIH
VIL
High-level input voltage
Low-level input voltage
Except B port
B port
VREF – 0.05
Except B port
0.8
–18
–24
24
IIK
Input clamp current
mA
mA
IOH
High-level output current
A port
A port
IOL
Low-level output current
mA
B port
50
∆t/∆V
∆t/∆VCC
TA
Input transition rise or fall rate
Power-up ramp rate
Outputs enabled
10
ns/V
µs/V
°C
20
Operating free-air temperature
–40
85
(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
(2) Proper connection sequence for use of the B-port I/O precharge feature is GND and BIAS VCC = 3.3 V first, I/O second, and VCC = 3.3 V
last, because the BIAS VCC precharge circuitry is disabled when any VCC pin is connected. The control and VREF inputs can be
connected anytime, but normally are connected during the I/O stage. If B-port precharge is not required, any connection sequence is
acceptable, but generally, GND is connected first.
(3) VTT and RTT can be adjusted to accommodate backplane impedances if the dc recommended IOL ratings are not exceeded.
(4) VREF can be adjusted to optimize noise margins, but normally is two-thirds VTT. TI-OPC circuitry is enabled in the A-to-B direction and is
activated when VTT > 0.7 V above VREF. If operated in the A-to-B direction, VREF should be set to within 0.6 V of VTT to minimize current
drain.
6
SN74GTLPH16912
18-BIT LVTTL-TO-GTLP UNIVERSAL BUS TRANSCEIVER
www.ti.com
SCES288C–OCTOBER 1999–REVISED JUNE 2005
Electrical Characteristics
over recommended operating free-air temperature range for GTLP (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP(1)
MAX UNIT
VIK
VCC = 3.15 V,
II = –18 mA
IOH = –100 µA
IOH = –12 mA
IOH = –24 mA
IOL = 100 µA
IOL = 12 mA
IOL = 24 mA
IOL = 100 µA
IOL = 10 mA
IOL = 40 mA
IOL = 50 mA
VI = 0 or VCC
VI = 5.5 V
–1.2
V
VCC = 3.15 V to 3.45 V,
VCC – 0.2
VOH
A port
2.4
2
V
VCC = 3.15 V
VCC = 3.15 V to 3.45 V,
VCC = 3.15 V
0.2
0.4
A port
0.5
VOL
VCC = 3.15 V to 3.45 V,
0.2
V
0.2
B port
VCC = 3.15 V
VCC = 3.45 V
0.4
0.55
±10
±20
±10
A-port and
control inputs
II(2)
µA
B port
A port
A port
VI = 0 to 1.5 V
VI = 0.8 V
(3)
(4)
IBHL
IBHH
VCC = 3.15 V,
VCC = 3.15 V,
VCC = 3.45 V,
VCC = 3.45 V,
75
–75
µA
µA
µA
µA
VI = 2 V
(5)
IBHLO
A port
A port
VI = 0 to VCC
VI = 0 to VCC
Outputs high
Outputs low
Outputs disabled
500
(6)
IBHHO
–500
50
50
50
VCC = 3.45 V, IO = 0,
VI (A-port or control input) = VCC or GND,
VI (B port) = VTT or GND
ICC
A or B port
mA
VCC = 3.45 V, One A-port or control input at VCC – 0.6 V,
Other A-port or control inputs at VCC or GND
(7)
∆ICC
1.5
mA
pF
Ci
Control inputs
A port
VI = 3.15 V or 0
VO = 3.15 V or 0
VO = 1.5 V or 0
4
7
5.5
8.5
9.5
Cio
pF
B port
8.5
(1) All typical values are at VCC = 3.3 V, TA = 25°C.
(2) For I/O ports, the parameter II includes the off-state output leakage current.
(3) The bus-hold circuit can sink at least the minimum low sustaining current at VILmax. IBHL should be measured after lowering VIN to GND
and then raising it to VILmax.
(4) The bus-hold circuit can source at least the minimum high sustaining current at VIHmin. IBHH should be measured after raising VIN to VCC
and then lowering it to VIHmin.
(5) An external driver must source at least IBHLO to switch this node from low to high.
(6) An external driver must sink at least IBHHO to switch this node from high to low.
(7) This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND.
Hot-Insertion Specifications for A Port
over recommended operating free-air temperature range
PARAMETER
Ioff
TEST CONDITIONS
BIAS VCC = 0,
MIN
MAX UNIT
VCC = 0,
VI or VO = 0 to 5.5 V
OE = 0
10
±30
±30
µA
µA
µA
IOZPU
VCC = 0 to 1.5 V,
VCC = 1.5 V to 0,
VO = 0.5 V to 3 V,
VO = 0.5 V to 3 V,
IOZPD
OE = 0
7
SN74GTLPH16912
18-BIT LVTTL-TO-GTLP UNIVERSAL BUS TRANSCEIVER
www.ti.com
SCES288C–OCTOBER 1999–REVISED JUNE 2005
Live-Insertion Specifications for B Port
over recommended operating free-air temperature range
PARAMETER
Ioff
TEST CONDITIONS
BIAS VCC = 0,
MIN
MAX UNIT
VCC = 0,
VI or VO = 0 to 1.5 V
10
±30
±30
5
µA
µA
µA
mA
µA
V
IOZPU
VCC = 0 to 1.5 V,
VCC = 1.5 V to 0,
VCC = 0 to 3.15 V
VCC = 3.15 V to 3.45 V
VCC = 0,
BIAS VCC = 0,
BIAS VCC = 0,
VO = 0.5 V to 1.5 V, OE = 0
VO = 0.5 V to 1.5 V, OE = 0
IOZPD
ICC (BIAS VCC
)
BIAS VCC = 3.15 V to 3.45 V,
VO (B port) = 0 to 1.5 V
10
VO
IO
BIAS VCC = 3.3 V,
IO = 0
0.95
–1
1.05
VCC = 0,
BIAS VCC = 3.15 V to 3.45 V,
VO (B port) = 0.6 V
µA
Timing Requirements
over recommended ranges of supply voltage and operating free-air temperature,
VTT = 1.5 V and VREF = 1 V for GTLP (unless otherwise noted)
MIN
MAX
175
UNIT
fclock
tw
Clock frequency
Pulse duration
MHz
LEAB or LEBA high
CLKAB or CLKBA high or low
A before CLKAB↑
B before CLKBA↑
A before LEAB↓
2.8
2.8
1.8
1.5
1
ns
tsu
Setup time
ns
B before LEBA↓
2
CEAB before CLKAB↑
CEBA before CLKBA↑
A after CLKAB↑
1.5
1.4
0.3
0.4
1.1
0.4
1
B after CLKBA↑
A after LEAB↓
th
Hold time
ns
B after LEBA↓
CEAB after CLKAB↑
CEBA after CLKBA↑
1
8
SN74GTLPH16912
18-BIT LVTTL-TO-GTLP UNIVERSAL BUS TRANSCEIVER
www.ti.com
SCES288C–OCTOBER 1999–REVISED JUNE 2005
Switching Characteristics
over recommended ranges of supply voltage and operating free-air temperature,
VTT = 1.5 V and VREF = 1 V for GTLP (see Figure 1)
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
MIN TYP(1)
MAX
UNIT
fmax
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
ten
175
2.1
2.1
2.2
2.2
2.2
2.2
2
MHz
6
6
A
B
B
B
B
ns
ns
ns
ns
6.3
6.3
6.5
6.5
6.5
6.1
LEAB
CLKAB
OEAB
tdis
2
tr
Rise time, B outputs (20% to 80%)
Fall time, B outputs (80% to 20%)
2.4
2
ns
ns
tf
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
ten
1.8
1.8
0.4
0.4
0.6
0.6
0.3
0.3
5.8
5.8
5.3
5.3
5.6
5.7
6.2
5.9
B
A
A
A
A
ns
ns
ns
ns
LEBA
CLKBA
OEBA
tdis
(1) All typical values are at VCC = 3.3 V, TA = 25°C.
9
SN74GTLPH16912
18-BIT LVTTL-TO-GTLP UNIVERSAL BUS TRANSCEIVER
www.ti.com
SCES288C–OCTOBER 1999–REVISED JUNE 2005
PARAMETER MEASUREMENT INFORMATION
1.5 V
6 V
Open
GND
S1
500 Ω
25 Ω
From Output
Under Test
TEST
/t
S1
Open
6 V
From Output
Under Test
Test
Point
t
t
PLH PHL
C = 50 pF
(see Note A)
L
/t
PLZ PZL
500 Ω
C = 30 pF
L
t
/t
GND
PHZ PZH
(see Note A)
LOAD CIRCUIT FOR A OUTPUTS
LOAD CIRCUIT FOR B OUTPUTS
t
w
3 V
3 V
0 V
Timing
Input
1.5 V
1.5 V
1.5 V
Input
0 V
t
su
t
h
VOLTAGE WAVEFORMS
PULSE DURATION
V
OH
Data
Input
V
M
V
M
0 V
3 V
0 V
Input
1.5 V
1.5 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
(V = 1.5 V for A port and 1 V for B port)
M
t
t
PHL
PLH
(V = 3 V for A port and 1.5 V for B port)
OH
V
V
OH
Output
1 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
(A port to B port)
1 V
3 V
Output
Control
OL
1.5 V
1.5 V
0 V
t
t
PLZ
PZL
Output
Waveform 1
S1 at 6 V
3 V
V
1.5 V
0 V
1.5 V
1 V
1 V
V
OL
+ 0.3 V
Input
OL
(see Note B)
t
t
PZH
PHZ
t
t
PHL
PLH
Output
Waveform 2
S1 at GND
V
OH
V
V
OH
V
OH
− 0.3 V
1.5 V
1.5 V
1.5 V
Output
≈0 V
(see Note B)
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
(B port to A port)
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
(A port)
NOTES: A. C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≈ 10 MHz, Z = 50 Ω, t ≈ 2 ns, t ≈ 2 ns.
O
r
f
D. The outputs are measured one at a time, with one transition per measurement.
Figure 1. Load Circuits and Voltage Waveforms
10
SN74GTLPH16912
18-BIT LVTTL-TO-GTLP UNIVERSAL BUS TRANSCEIVER
www.ti.com
SCES288C–OCTOBER 1999–REVISED JUNE 2005
Distributed-Load Backplane Switching Characteristics
The preceding switching characteristics table shows the switching characteristics of the device into a lumped
load (Figure 1). However, the designer's backplane application probably is a distributed load. The physical
representation is shown in Figure 2. This backplane, or distributed load, can be approximated closely to a
resistor inductance capacitance (RLC) circuit, as shown in Figure 3. This device has been designed for optimum
performance in this RLC circuit. The following switching characteristics table shows the switching characteristics
of the device into the RLC load, to help the designer better understand the performance of the GTLP device in
this typical backplane. See www.ti.com/sc/gtlp for more information.
1.5 V
1.5 V
Z
O
= 70 Ω
0.25”
2”
2”
0.25”
Conn.
Conn.
Conn.
Conn.
1”
1”
1”
1”
Rcvr
Rcvr
Rcvr
Drvr
Slot 1
Slot 2
Slot 9
Slot 10
Figure 2. Medium-Drive Test Backplane
1.5 V
19 Ω
L = 19 nH
L
From Output
Under Test
Test
Point
C = 9 pF
L
Figure 3. Medium-Drive RLC Network
11
SN74GTLPH16912
18-BIT LVTTL-TO-GTLP UNIVERSAL BUS TRANSCEIVER
www.ti.com
SCES288C–OCTOBER 1999–REVISED JUNE 2005
Switching Characteristics
over recommended ranges of supply voltage and operating free-air temperature,
VTT = 1.5 V and VREF = 1 V for GTLP (see Figure 3)
FROM
TO
(OUTPUT)
PARAMETER
(INPUT)
TYP(1) UNIT
tPLH
4.5
ns
A
B
B
B
B
tPHL
4.5
tPLH
4.7
ns
LEAB
tPHL
4.7
tPLH
4.7
ns
CLKAB
tPHL
4.7
ten
4.8
ns
OEAB
tdis
4.4
tr
tf
Rise time, B outputs (20% to 80%)
Fall time, B outputs (80% to 20%)
1.2
2.5
ns
ns
(1) All typical values are at VCC = 3.3 V, TA = 25°C. All values are derived from TI-SPICE models.
12
PACKAGE OPTION ADDENDUM
www.ti.com
27-Sep-2007
PACKAGING INFORMATION
Orderable Device
74GTLPH16912GRE4
74GTLPH16912GRG4
74GTLPH16912VRE4
74GTLPH16912VRG4
SN74GTLPH16912GR
SN74GTLPH16912VR
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
TSSOP
DGG
56
56
56
56
56
56
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TSSOP
TVSOP
TVSOP
TSSOP
TVSOP
DGG
DGV
DGV
DGG
DGV
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
4-Oct-2007
TAPE AND REEL BOX INFORMATION
Device
Package Pins
Site
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) (mm) Quadrant
(mm)
330
(mm)
24
SN74GTLPH16912GR
SN74GTLPH16912VR
DGG
DGV
56
56
SITE 41
SITE 41
8.6
6.8
15.6
10.1
1.8
1.6
12
12
24
24
Q1
Q1
330
24
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
4-Oct-2007
Device
Package
Pins
Site
Length (mm) Width (mm) Height (mm)
SN74GTLPH16912GR
SN74GTLPH16912VR
DGG
DGV
56
56
SITE 41
SITE 41
346.0
346.0
346.0
346.0
41.0
41.0
Pack Materials-Page 2
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,23
0,13
M
0,07
0,40
24
13
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–ā8°
0,75
1
12
0,50
A
Seating Plane
0,08
0,15
0,05
1,20 MAX
PINS **
14
16
20
24
38
48
56
DIM
A MAX
A MIN
3,70
3,50
3,70
3,50
5,10
4,90
5,10
4,90
7,90
7,70
9,80
9,60
11,40
11,20
4073251/E 08/00
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
D. Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
M
0,08
0,50
48
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
0,25
1
24
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
48
56
64
DIM
A MAX
12,60
12,40
14,10
13,90
17,10
16,90
A MIN
4040078/F 12/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements,
improvements, and other changes to its products and services at any time and to discontinue any product or service without notice.
Customers should obtain the latest relevant information before placing orders and should verify that such information is current and
complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s
standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this
warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily
performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and
applications using TI components. To minimize the risks associated with customer products and applications, customers should
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TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask
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Applications
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amplifier.ti.com
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www.ti.com/automotive
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Copyright © 2007, Texas Instruments Incorporated
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