SN74GTL2007PWRG4 [TI]
12-BIT GTL-/GTL/GTL+ TO LVTTL TRANSLATOR; 12位GTL- / GTL / GTL +至LVTTL翻译
| 型号： | SN74GTL2007PWRG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 12-BIT GTL-/GTL/GTL+ TO LVTTL TRANSLATOR |
| 文件： | 总10页 (文件大小：173K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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SCLS609 − MARCH 2005
PW PACKAGE
(TOP VIEW)
D
Operates as a GTL-/GTL/GTL+ to LVTTL or
LVTTL to GTL-/GTL/GTL+ Translator
D
Series Termination on TTL Outputs of 30
ꢀ
ꢁ
V
V
CC
1BI
1
2
3
4
5
6
7
8
9
28
27
26
25
REF
D
Latch-Up Testing Done to JEDEC Standard
JESD 78
1AO
2AO
5A
2BI
7BO1
D
ESD Performance Tested Per JESD 22
− 2000-V Human-Body Model
(A114-B, Class II)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)
6A
24 7BO2
EN1
11BI
11A
9BI
EN2
11BO
23
22
21 5BI
20 6BI
description/ordering information
3AO 10
4AO 11
19 3BI
18 4BI
The SN74GTL2007 is a 12-bit translator to
interface between the 3.3-V LVTTL chip set I/O
and the Xeon processor GTL-/GTL/GTL+ I/O.
The device is designed for platform health
management in dual-processor applications.
10AI1 12
10AI2 13
GND 14
17 10BO1
16 10BO2
15 9AO
PIN DESCRIPTION
PIN NUMBER SYMBOL
NAME AND FUNCTION
GTL reference voltage
1
V
REF
2-6, 8, 10-13,
15, 23
ENn
nAn
Data and enable inputs/outputs (LVTTL)
Data inputs/outputs (GTL−/GTL/GTL+)
7, 9, 16,
17−22, 24−27
nBn
14
28
GND
Ground (0 V)
V
CC
Positive supply voltage
ORDERING INFORMATION
ORDERABLE
TOP-SIDE
MARKING
†
PACKAGE
T
A
PART NUMBER
SN74GTL2007PW
SN74GTL2007PWR
Tube
−40°C to 85°C TSSOP − PW
GK2007
Tape and reel
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
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Copyright 2005, Texas Instruments Incorporated
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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SCLS609 − MARCH 2005
Function Tables
INPUTS
OUTPUT
1AO/2AO
EN1
1BI/2BI
H
H
L
L
H
X
L
H
H
INPUTS
OUTPUT
3AO/4AO
EN2
H
3BI/4BI
L
L
H
H
H
L
X
H
INPUT
OUTPUT
9BI
9AO
L
L
H
H
INPUTS
OUTPUT
10BO1/10BO2
10AI1/10AI2
9BI
L
L
L
L
L
H
H
H
L
L
H
H
INPUT/OUTPUT
5A/6A
(OPEN DRAIN)
INPUTS
5BI/6BI
OUTPUT
7BO1/7BO2
EN2
†
H
H
H
H
L
L
H
H
H
H
L
L
‡
L
L
H
H
L
‡
L
L
H
H
H
H
L
H
‡
L
L
L
INPUT/OUTPUT
11A
(OPEN DRAIN)
INPUT
11BI
OUTPUT
11BO
L
L
H
L
H
H
‡
L
H
L
H = High voltage level
L = Low voltage level
†
The enable on 7BO1/7BO2 includes a
delay that prevents a transient condition
(where 5BI/6BI goes from low to high, and
the low to high on 5A/6A lags up to 100 ns)
from causing
a
low glitch on the
7BO1/7BO2 outputs.
Open-drain input/output terminal is driven
to a logic-low state by an external driver.
‡
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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SCLS609 − MARCH 2005
logic symbol
GTL2007
1
2
3
4
GTL V
REF
27
26
1BI
1AO
2AO
GTL
INPUTS
LVTTL OUTPUTS
2BI
25
24
5A (OPEN DRAIN)
6A (OPEN DRAIN)
7BO1
7BO2
LVTTL I/O
GTL
OUTPUTS
5
23
22
6
7
LVTTL INPUT EN1
GTL INPUT 11BI
EN2 LVTTL INPUT
11BO GTL OUTPUT
1
DELAY
8
9
LVTTL I/O 11A (OPEN DRAIN)
GTL INPUT 9BI
21
5BI
6BI
1
DELAY
20
19
18
GTL
INPUTS
3BI
10
11
3AO
LVTTL OUTPUTS
4AO
4BI
17
16
10BO1
10BO2
12
13
10AI1
LVTTL INPUTS
10AI2
GTL
OUTPUTS
15
9AO LVTTL OUTPUT
NOTE A: The enable on 7BO1/7BO2 includes a delay that prevents a transient conditon (where 5BI/6BI go from low to high, and the low to high
on 5A/6A lags up to 100 ns) from causing a low glitch on the 7BO1/7BO2 outputs.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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SCLS609 − MARCH 2005
†‡
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 to 4.6 V
CC
Input voltage range, V (see Note 2): A port (LVTTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 to 4.6 V
I
B port (GTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 to 4.6 V
Output voltage range, V (output in OFF or HIGH state)(see Note 2): A port . . . . . . . . . . . . . . . . −0.5 to 4.6 V
O
B port . . . . . . . . . . . . . . . . −0.5 to 4.6 V
Input diode current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
IK
OK
I
Output diode current, I
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
O
Current into any output in the LOW state: A port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 mA
B port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 mA
Current into any output in the HIGH state, A port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −32 mA
Package thermal impedance, θ (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62°C/W
JA
stg
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −60 to 150°C
†
‡
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Voltages are referenced to GND (ground = 0 V).
NOTES: 1. The performance capability of a high-performance integrated circuit, in conjunction with its thermal environment, can create junction
temperatures that are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.
2. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.
recommended operating conditions
MIN
NOM
MAX
UNIT
V
Supply voltage
3
0.85
1.14
1.35
0.5
0.5
0.76
0.87
0
3.3
0.9
1.2
1.5
3.6
0.95
1.26
1.65
1.8
V
CC
TT
GTL−
GTL
V
Termination voltage
V
V
GTL+
Overall
GTL−
GTL
2/3 V
TT
0.6
0.63
0.84
1.1
V
REF
Reference voltage
0.8
1
GTL+
A port
B port
A port
B port
A port
B port
A port
A port
B port
3.3
3.6
V
V
V
Input voltage
V
V
I
0
V
TT
3.6
2
HIGH-level input voltage
IH
IL
V
+ 50 mV
REF
0.8
LOW-level input voltage
HIGH-level output current
V
V
− 50 mV
REF
I
−16
16
mA
OH
OL
I
LOW-level output current
mA
15
T
A
Operating free-air temperature range
−40
85
°C
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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SCLS609 − MARCH 2005
electrical characteristics over recommended operating conditions
–40ꢀC TO +85ꢀC
PARAMETER
TEST CONDITIONS
UNIT
V
†
TYP
MIN
V – 0.2
MAX
V
V
V
V
V
V
V
V
V
V
V
= 3 V to 3.6 V, I
OH
= –100 mA
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
2.1
‡
V
V
A port
OH
= 3 V, I
= 3 V, I
= 3 V, I
= –16 mA
= 16 mA
= 15 mA
OH
OL
OL
A port
B port
0.8
0.4
1
‡
V
OL
= 3.6 V, V = V
I
CC
A port
= 3.6, V = 0 V
I
1
I
I
mA
B port
= 3.6 V, V = V or GND
1
I
TT
I
A or B port
A port or control inputs
A port
= 3.6 V, V = V
or GND, I = 0
O
12
500
mA
CC
I
CC
§
DI
CC
= 3.6 V, V = V
– 0.6 V
mA
I
CC
= 3 V or 0
5
4
O
O
C
pF
IO
B port
= V or 0
TT
†
‡
§
All typical values are measured at V
CC
= 3.3 V and T = 25°C.
A
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
This is the increase in supply current for each input that is at the specified LVTTL voltage, rather than V
or GND.
CC
switching characteristics over recommended operating free-air temperature range
GTL−
GTL
GTL+
V
CC
V
= 3.3 V ꢁ 0.3 V
V
CC
V
= 3.3 V ꢁ 0.3 V
V
CC
= 3.3 V ꢁ 0.3 V
PARAMETER
WAVEFORM
UNIT
= 0.6 V
= 0.8 V
V
REF
= 1 V
REF
REF
†
†
†
MIN TYP
MAX
8
MIN TYP
MAX
8
MIN TYP
MAX
8
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
2
4
2
4
2
4
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
PLZ
PZL
PLZ
PZL
An to Bn
1
2
3
3
3
4
5
6
ns
ns
ns
ns
ns
ns
ns
ns
2
2
5.5
5.5
5.5
6
10
10
10
11
11
13
21
11
350
7
2
2
5.5
5.5
5.5
6
10
10
10
11
11
13
21
11
350
7
2
2
5.5
5.5
5.5
6
10
10
10
11
11
13
21
11
350
7
Bn to An
2
2
2
2
2
2
9BI to 10BOn
11BI to 11BO
Bn to Bn
2
6
2
6
2
6
2
8
2
8
2
8
¶
2
14
7
2
14
7
2
14
7
4
4
4
120
1
205
3
120
1
205
3
120
1
205
3
ENn to An
1
3
7
1
3
7
1
3
7
2
5
10
10
7
2
5
10
10
7
2
5
10
10
7
Bn to An (I/O)
EN2 to An (I/O)
2
5
2
5
2
5
1
3
1
3
1
3
1
3
7
1
3
7
1
3
7
†
¶
All typical values are measured at V
CC
= 3.3 V and T = 25°C.
A
Includes ∼7.6-ns RC rise time of test-load pullup on 11-A, 1.5-kΩ pullup, and 21-pF load on 11 A has approximately 23-ns RC rise time.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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SCLS609 − MARCH 2005
PARAMETER MEASUREMENT INFORMATION
V
= 1.2 V, V
= 0.8 V FOR GTL AND V = 1.5 V, V
= 1 V FOR GTL+
TT
REF
TT
REF
V
TT
2 ꢂ V
CC
S1
Open
500 Ω
From Output
Under Test
50 Ω
TEST
S1
Open
GND
From Output
Under Test
Test
Point
t
t
/t
PLH PHL
/t
C
= 50 pF
L
2 ꢂ V
500 Ω
PLZ PZL
CC
(see Note A)
C
= 30 pF
(see Note A)
L
LOAD CIRCUIT FOR A OUTPUTS
Input
LOAD CIRCUIT FOR B OUTPUTS
V
TT
3 V
0 V
Input
(see Note B)
1.5 V
1.5 V
V
REF
V
REF
(see Note B)
0 V
t
t
PHL
t
t
PHL
PLH
PLH
V
V
V
V
TT
OH
Output
Output
V
V
REF
1.5 V
VOLTAGE WAVEFORM 2
1.5 V
REF
OL
OL
VOLTAGE WAVEFORM 1
PROPAGATION DELAY TIMES
PROPAGATION DELAY TIMES
†
†
(B port to A port)
(A port to B port)
V
TT
3 V
0 V
Input
(see Note B)
Input
(see Note B)
V
REF
V
REF
1.5 V
1.5 V
0 V
t
t
t
t
PHL
PHL
PLH
PLH
V
OH
V
TT
Output
Output
V
REF
V
REF
1.5 V
1.5 V
V
OL
V
OL
VOLTAGE WAVEFORM 3
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORM 4
PROPAGATION DELAY TIMES
†
†
(B port to B port)
(ENn to A port)
V
3 V
0 V
TT
Input
(see Note B)
Input
(see Note B)
1.5 V
1.5 V
V
REF
V
REF
0 V
t
t
t
t
PZL
PZL
PLZ
PLZ
Output
S1 at 2 ꢂ V
CC
Output
S1 at 2 ꢂ V
CC
V
V
CC
CC
1.5 V
1.5 V
V
OL
+ 0.3 V
V
OL
+ 0.3 V
V
OL
V
OL
VOLTAGE WAVEFORM 5
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORM 6
ENABLE AND DISABLE TIMES
†
†
(EN2 to A (I/O) port)
(B port to A (I/O) port)
†
All control inputs are LVTTL levels.
NOTES: A.
C includes probe and jig capacitance.
L
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
C. The outputs are measured one at a time, with one transition per measurement.
Figure 1. Load Circuits and Voltage Waveforms
6
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ꢀꢁ ꢂꢃ ꢄ ꢅꢆꢇ ꢈꢈ ꢂ
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SCLS609 − MARCH 2005
APPLICATION INFORMATION
V
TT
V
TT
56 ꢁ
R
56 ꢁ
V
CC
1.5 kꢁ to 1.2 kꢁ
1.5 kꢁ
2R
Platform
Health
V
CC
Management
CPU1
V
V
CC
REF
CPU1 1ERR_L
1AO
2AO
5A
1BI
2BI
1ERR_L
CPU1 THRMTRIP L
CPU1 PROCHOT L
CPU2 PROCHOT L
THRMTRIP L
FORCEPR_L
PROCHOT L
NMI
7BO1
6A
7BO2
EN2
EN1
11BI
11A
9BI
CPU1 SMI L
11B0
NMI_L
5BI
6BI
FORCEPR_L
PROCHOT L
1ERR_L
CPU2 1ERR_L
3AO
3BI
4BI
CPU2 THRMTRIP L
4AO
THRMTRIP L
NMI
10AI1
10AI2
10BO1
10BO2
9AO
CPU2 SMI L
CPU1 SMI L
CPU2 SMI L
GND
CPU2
SMI_BUFF_L
GTL2007
Southbridge NMI
PWR GD
Southbridge SMI_L
Optional Signal Line
Power Supervisor
Frequently Asked Questions
Question 1: On the GTL2007 LVTTL input, specifically 10AI1 and 10AI2, when the GTL2007 is powered down,
these inputs may be pulled up to 3.3 V, and we want to ensure that there is no leakage path to the power rail
under this condition. Are the LVTTL inputs high impedance when the device is powered down, and will there
be any leakage?
Answer 1: When the device is powered down, the LVTTL inputs are in a high-impedance state and do not leak
to V
if they are pulled high while the device is powered down.
DD
Question 2: Do all the LVTTL inputs have the same powered-down characteristic?
Answer 2: Yes
Question 3: What is the condition of the other GTL I/O and LVTTL output pins when the device is powered
down?
Answer 3: The open-drain outputs, both GTL and LVTTL, do not leak to the power supply if they are pulled high
while the device is powered down. The GTL inputs also do not leak to the power supply under the same
conditions. The LVTTL totem-pole outputs, however, are not open-drain type outputs, and there is no current
flow on these pins if they are pulled high when V
is at ground.
DD
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
5-Dec-2005
PACKAGING INFORMATION
Orderable Device
SN74GTL2007PW
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
TSSOP
PW
28
28
28
28
28
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74GTL2007PWE4
SN74GTL2007PWR
SN74GTL2007PWRE4
SN74GTL2007PWRG4
TSSOP
TSSOP
TSSOP
TSSOP
PW
PW
PW
PW
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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