SN74GTL2010PWR [TI]
10-BIT BIDIRECTIONAL LOW-VOLTAGE TRANSLATOR; 10位双向低电压转换
| 型号： | SN74GTL2010PWR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 10-BIT BIDIRECTIONAL LOW-VOLTAGE TRANSLATOR |
| 文件： | 总15页 (文件大小：149K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
GTL2010
10-BIT BIDIRECTIONAL LOW-VOLTAGE TRANSLATOR
www.ti.com
SCDS221–SEPTEMBER 2006
FEATURES
PW PACKAGE
•
•
•
•
Provides Bidirectional Voltage Translation
With No Direction Control Required
(TOP VIEW)
GND
G
D
1
2
24
23
22
REF
Allows Voltage Level Translation From 1 V up
to 5 V
S
REF
REF
Provides Direct Interface With GTL, GTL+,
LVTTL/TTL, and 5-V CMOS Levels
S1 3
D1
S2
S3
S4
D2
D3
D4
D5
D6
D7
D8
D9
D10
4
5
6
21
20
Low On-State Resistance Between Input and
Output Pins (Sn/Dn)
19
18
17
•
•
Supports Hot Insertion
S5 7
No Power Supply Required – Will Not Latch
Up
8
S6
S7
9
•
•
•
5-V-Tolerant Inputs
16
15
10
11
12
Low Standby Current
S8
Flow-Through Pinout for Ease of Printed
Circuit Board Trace Routing
14
13
S9
S10
•
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-4)
– 1000-V Charged-Device Model (C101)
APPLICATIONS
•
Bidirectional or Unidirectional Applications
Requiring Voltage-Level Translation From
Any Voltage (1 V to 5 V) to Any Voltage (1 V
to 5 V)
•
•
Low Voltage Processor I2C Port Translation
to 3.3-V and/or 5-V I2C Bus Signal Levels
GTL/GTL+ Translation to LVTTL/TTL Signal
Levels
DESCRIPTION/ORDERING INFORMATION
The GTL2010 provides ten NMOS pass transistors (Sn and Dn) with a common gate (GREF) and a reference
transistor (SREF and DREF). The low ON-state resistance of the switch allows connections to be made with
minimal propagation delay. With no direction control pin required, the device allows bidirectional voltage
translations any voltage (1 V to 5 V) to any voltage (1 V to 5 V).
When the Sn or Dn port is LOW, the clamp is in the ON state and a low-resistance connection exists between
the Sn and Dn ports. Assuming the higher voltage is on the Dn port, when the Dn port is HIGH, the voltage on
the Sn port is limited to the voltage set by the reference transistor (SREF). When the Sn port is HIGH, the Dn port
is pulled to VCC by the pullup resistors.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2006, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
GTL2010
10-BIT BIDIRECTIONAL LOW-VOLTAGE TRANSLATOR
www.ti.com
SCDS221–SEPTEMBER 2006
DESCRIPTION/ORDERING INFORMATION (CONTINUED)
All transistors in the GTL2010 have the same electrical characteristics, and there is minimal deviation from one
output to another in voltage or propagation delay. This offers superior matching over discrete transistor
voltage-translation solutions where the fabrication of the transistors is not symmetrical. With all transistors being
identical, the reference transistor (SREF/DREF) can be located on any of the other ten matched Sn/Dn transistors,
allowing for easier board layout. The translator transistors with integrated ESD circuitry provides excellent ESD
protection.
ORDERING INFORMATION
TA
PACKAGE(1)
ORDERABLE PART NUMBER
TOP-SIDE MARKING
GK2010
–40°C to 85°C
TSSOP – PW
Tape and reel
SN74GTL2010PWR
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
PIN DESCRIPTION
PIN NO.
NAME
GND
SREF
Sn
DESCRIPTION
1
2
Ground (0 V)
Source of reference transistor
Ports S1–10
3–12
13–22
23
Dn
Ports D10–D1
DREF
GREF
Drain of reference transistor
Gate of reference transistor
24
2
Submit Documentation Feedback
GTL2010
10-BIT BIDIRECTIONAL LOW-VOLTAGE TRANSLATOR
www.ti.com
SCDS221–SEPTEMBER 2006
FUNCTION TABLES(1)
ABC
HIGH-to-LOW Translation (Assuming Dn is at the Higher Voltage Level)
INPUTS
D10–D1
OUTPUTS
S10–S1
(2)
GREF
DREF
SREF
TRANSISTOR
H
H
H
L
H
H
H
L
0 V
X
H
L
X
Off
On
On
Off
(3)
(4)
VTT
VTT
L(5)
VTT
0 – VTT
X
X
(1) H = HIGH voltage level, L = LOW voltage level, X = don't care
(2) GREF should be at least 1.5 V higher than SREF for best translator operation.
(3) VTT is equal to the SREF voltage.
(4) Sn is not pulled up or pulled down.
(5) Sn follows the Dn input LOW.
LOW-to-HIGH Translation (Assuming Dn is at the Higher Voltage Level)(1)
INPUTS
D10–D1
OUTPUTS
S10–S1
(2)
GREF
DREF
SREF
TRANSISTOR
H
H
H
L
H
H
H
L
0 V
X
VTT
L
X
H(4)
L(5)
X
Off
Nearly off
On
(3)
VTT
VTT
0 – VTT
X
Off
(1) H = HIGH voltage level, L = LOW voltage level, X = don't care
(2) GREF should be at least 1.5 V higher than SREF for best translator operation.
(3) VTT is equal to the SREF voltage.
(4) Dn is pulled up to VCC through an external resistor.
(5) Dn follows the Sn input LOW.
CLAMP SCHEMATIC
D
REF
G
D1
D10
REF
S
S1
S10
REF
SA00647
3
Submit Documentation Feedback
GTL2010
10-BIT BIDIRECTIONAL LOW-VOLTAGE TRANSLATOR
www.ti.com
SCDS221–SEPTEMBER 2006
Absolute Maximum Ratings(1)(2)(3)
MIN
–0.5
–0.5
–0.5
–0.5
–0.5
MAX
UNIT
VSREF
VDREF
VGREF
VSn
DC source reference voltage
DC drain reference voltage
DC gate reference voltage
DC voltage port Sn
7
V
7
7
V
V
7
V
VDn
DC voltage port Dn
7
V
IREFK
ISK
DC diode current on reference pins
DC diode current port Sn
DC diode current port Dn
DC clamp current per channel
Package thermal impedance
Storage temperature range
VI < 0 V
–50
–50
–50
±128
88
mA
mA
mA
mA
°C/W
°C
VI < 0 V
IDK
VI < 0 V
IMAX
θJA
Channel in ON state
Tstg
–65
150
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures that are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.
(3) The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.
Recommended Operating Conditions
MIN
0
MAX UNIT
VI/O
Input/output voltage (Sn, Dn)
DC source reference voltage(1)
DC drain reference voltage
5.5
5.5
5.5
5.5
64
V
V
VSREF
VDREF
VGREF
IPASS
Tamb
0
0
V
DC gate reference voltage
0
V
Pass transistor current
mA
°C
Operating ambient temperature range (in free air)
–40
85
(1) VSREF = VDREF – 1.5 V for best results in level-shifting applications.
4
Submit Documentation Feedback
GTL2010
10-BIT BIDIRECTIONAL LOW-VOLTAGE TRANSLATOR
www.ti.com
SCDS221–SEPTEMBER 2006
Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP(1)
MAX UNIT
VDD = 3 V, VSREF = 1.365 V, VSn or VDn = 0.175 V,
Iclamp = 15.2 mA
VOL
Low-level output voltage
260
350
mV
VIK
IIH
Input clamp voltage
Gate input leakage
II = –18 mA,
VGREF = 0 V
VGREF = 0 V
–1.2
5
V
VI = 5 V,
µA
pF
pF
pF
CI(GREF) Gate capacitance
CIO(OFF) OFF capacitance
VI = 3 V or 0 V
VO = 3 V or 0 V,
VO = 3 V or 0 V,
56
7.4
18.6
3.5
4.4
5.5
67
VGREF = 0 V
VGREF = 3 V
VGREF = 4.5 V
VGREF = 3 V
VGREF = 2.3 V
VGREF = 1.5 V
VGREF = 1.5 V,
VGREF = 4.5 V
VGREF = 3 V
VGREF = 2.3 V
CIO(ON)
ON capacitance
5
7
IO = 64 mA
VI = 0 V
9
105
15
10
80
70
(2)
ron
ON-state resistance
Ω
IO = 30 mA
IO = 15 mA
9
7
VI = 2.4 V
VI = 1.7 V
58
50
(1) All typical values are measured at Tamb = 25°C.
(2) Measured by the voltage drop between the Sn and the Dn terminals at the indicated current through the switch. On-state resistance is
determined by the lowest voltage of the two (Sn or Dn) terminals.
5
Submit Documentation Feedback
GTL2010
10-BIT BIDIRECTIONAL LOW-VOLTAGE TRANSLATOR
www.ti.com
SCDS221–SEPTEMBER 2006
AC Characteristics for Translator-Type Applications(1)
VREF = 1.365 V to 1.635 V, VDD1 = 3 V to 3.6 V, VDD2 = 2.36 V to 2.64 V, GND = 0 V, tr = tf ≤ 3 ns, Tamb = –40°C to 85°C
(see Figure 5)
PARAMETER
MIN TYP(2)
0.5 1.5
MAX UNIT
5.5 ns
(3)
tPLH
Propagation delay (Sn to Dn, Dn to Sn)
(1) CON(max) of 30 pF and a COFF(max) of 15 pF is specified by design.
(2) All typical values are measured at VDD1 = 3.3 V, VDD2 = 2.5 V, VREF = 1.5 V and Tamb = 25°C.
(3) Propagation delay specified by characterization.
AC Waveforms
Vm = 1.5 V, V = GND to 3 V
IN
V
I
V
V
M
Input
GND
M
t
t
PHL0
PLH0
V
DD2
V
M
Low-to-High
V
M
V
OL
t
t
PHL
PLH
PLH1
t
t
PHL1
V
DD2
V
M
V
M
Low-to-High
V
OL
Figure 1. Input (Sn) to Output (Dn) Propagation Delays
V
DD2
V
DD2
V
DD2
V
DD2
200 W
150 W
150 W
150 W
DUT
G
D
REF
REF
D1 . . . D10
S
REF
S1 . . . S10
Test
Jig
V
REF
Pulse
Generator
Figure 2. Load Circuit
6
Submit Documentation Feedback
GTL2010
10-BIT BIDIRECTIONAL LOW-VOLTAGE TRANSLATOR
www.ti.com
SCDS221–SEPTEMBER 2006
AC Characteristics for CBT-Type Applications
GND = 0 V, tR, CL = 50 pF, GREF = 5 V ± 0.5 V, Tamb = –40°C to 85°C
PARAMETER
MIN
MAX UNIT
250 ps
tpd
Propagation delay(1)
(1) This parameter is warranted but not production tested. The propagation delay is based on the RC time constant of the typical on-state
resistance of the switch and a load capacitance of 50 pF, when driven by an ideal voltage source (zero output impedance).
AC Waveforms
3 V
1.5 V
1.5 V
Input
0 V
t
t
PHL
PLH
V
OH
1.5 V
1.5 V
Output
V
OL
Figure 3. Input (Sn) to Output (Dn) Propagation Delays
7 V
500 W
From Ouput
Under Test
S1
C
L
= 50 pF
500 W
Load Circuit
TEST
S1
t
Open
7 V
pd
t
/t
PLZ PZL
t
/t
Open
PHZ PZH
C = Load capacitance, includes jig and probe capacitance
L
(see AC Characteristics for value).
Figure 4. Load Circuit
7
Submit Documentation Feedback
GTL2010
10-BIT BIDIRECTIONAL LOW-VOLTAGE TRANSLATOR
www.ti.com
SCDS221–SEPTEMBER 2006
APPLICATION INFORMATION
Bidirectional Translation
For the bidirectional clamping configuration (higher voltage to lower voltage or lower voltage to higher voltage),
the GREF input must be connected to DREF and both pins pulled to HIGH-side VCC through a pullup resistor
(typically 200 kΩ). A filter capacitor on DREF is recommended. The processor output can be totem pole or open
drain (pullup resistors) and the chipset output can be totem pole or open drain (pullup resistors are required to
pull the Dn outputs to VCC). However, if either output is totem pole, data must be unidirectional or the outputs
must be 3-statable, and the outputs must be controlled by some direction-control mechanism to prevent
HIGH-to-LOW contentions in either direction. If both outputs are open drain, no direction control is needed. The
opposite side of the reference transistor (SREF) is connected to the processor core power-supply voltage. When
DREF is connected through a 200-kΩ resistor to a 3.3-V to 5.5-V VCC supply and SREF is set between 1 V to VCC
1.5 V, the output of each Sn has a maximum output voltage equal to SREF, and the output of each Dn has a
maximum output voltage equal to VCC
.
8
Submit Documentation Feedback
GTL2010
10-BIT BIDIRECTIONAL LOW-VOLTAGE TRANSLATOR
www.ti.com
SCDS221–SEPTEMBER 2006
APPLICATION INFORMATION (continued)
VDPU = 5V
200K Ω
VREF = 1.8V
GTL2010
GREF
DREF
RPU
RPU
SREF
RPU
RPU
S1
S2
D1
D2
SW
SW
CPU I/O
Chipset
I/O
VDPU = 3.3V
RPU
RPU
S9
D9
Chipset
I/O
S10
D10
GND
Figure 5. Bidirectional Translation to Multiple Higher Voltage Levels (Such as an I2C or SMBus
Applications)
9
Submit Documentation Feedback
GTL2010
10-BIT BIDIRECTIONAL LOW-VOLTAGE TRANSLATOR
www.ti.com
SCDS221–SEPTEMBER 2006
APPLICATION INFORMATION (continued)
Unidirectional Down Translation
For unidirectional clamping (higher voltage to lower voltage), the GREF input must be connected to DREF and both
pins pulled to the higher-side VCC through a pullup resistor (typically 200 kΩ). A filter capacitor on DREF is
recommended. Pullup resistors are required if the chipset I/Os are open drain. The opposite side of the
reference transistor (SREF) is connected to the processor core power-supply voltage. When DREF is connected
through a 200-kΩ resistor to a 3.3-V to 5.5-V VCC supply and SREF is set between 1 V to VCC – 1.5 V, the output
of each Sn has a maximum output voltage equal to SREF
.
VDPU = 5V
200K Ω
GTL2010
VREF = 1.8V
GREF
DREF
SREF
S1
S2
D1
SW
SW
CPU I/O
Chipset
I/O
D2
Dn
Sn
GND
Figure 6. Unidirectional Down Translation to Protect Low-Voltage Processor Pins
10
Submit Documentation Feedback
GTL2010
10-BIT BIDIRECTIONAL LOW-VOLTAGE TRANSLATOR
www.ti.com
SCDS221–SEPTEMBER 2006
APPLICATION INFORMATION (continued)
Unidirectional Up Translation
For unidirectional up translation (lower voltage to higher voltage), the reference transistor is connected the same
as for a down translation. A pullup resistor is required on the higher voltage side (Dn or Sn) to get the full HIGH
level, since the GTL device only passes the reference source (SREF) voltage as a HIGH when doing an up
translation. The driver on the lower voltage side only needs pullup resistors if it is open drain.
VDPU = 5V
200K Ω
GTL2010
VREF = 1.8V
GREF
DREF
RPU
RPU
SREF
RPU
RPU
S1
D1
SW
SW
CPU I/O
Chipset
I/O
S2
Sn
D2
Dn
GND
Figure 7. Unidirectional Up Translation to Higher-Voltage Chipsets
11
Submit Documentation Feedback
GTL2010
10-BIT BIDIRECTIONAL LOW-VOLTAGE TRANSLATOR
www.ti.com
SCDS221–SEPTEMBER 2006
APPLICATION INFORMATION (continued)
Sizing Pullup Resistor
The pullup resistor value should limit the current through the pass transistor when it is in the on state to about
15 mA. This ensures a pass voltage of 260 mV to 350 mV. If the current through the pass transistor is higher
than 15 mA, the pass voltage also is higher in the on state. To set the current through each pass transistor at
15 mA, the pullup resistor value is calculated as:
Pullup voltage (V) * 0.35 V
( )
Resistor value W +
0.015 A
Table 1 shows resistor values for various reference voltages and currents at 15 mA, 10 mA, and 3 mA. The
resistor value shown in the +10% column, or a larger value, should be used to ensure that the pass voltage of
the transistor would be 350 mV or less. The external driver must be able to sink the total current from the
resistors on both sides of the GTL device at 0.175 V, although the 15 mA only applies to current flowing through
the GTL2010.
Table 1. Pullup Resistor Values(1)(2)(3)
PULLUP RESISTOR VALUE (Ω)
15 mA
10 mA
3 mA
VOLTAGE
NOMINAL
310
+10%
341
217
158
106
85
NOMINAL
465
+10%
512
325
237
160
127
94
NOMINAL
1550
983
+10%
1705
1082
788
5.0 V
3.3 V
2.5 V
1.8 V
1.5 V
1.2 V
197
295
143
215
717
97
145
483
532
77
115
383
422
57
63
85
283
312
(1) Calculated for VOL = 0.35 V
(2) Assumes output driver VOL = 0.175 V at stated current
(3) +10% to compensate for VDD range and resistor tolerance
12
Submit Documentation Feedback
PACKAGE OPTION ADDENDUM
www.ti.com
6-Dec-2006
PACKAGING INFORMATION
Orderable Device
SN74GTL2010PW
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
TSSOP
PW
24
24
24
24
60 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74GTL2010PWE4
SN74GTL2010PWR
SN74GTL2010PWRE4
TSSOP
TSSOP
TSSOP
PW
PW
PW
60 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
orders and should verify that such information is current and complete. All products are sold subject to TI’s terms
and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for
their products and applications using TI components. To minimize the risks associated with customer products
and applications, customers should provide adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,
copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process
in which TI products or services are used. Information published by TI regarding third-party products or services
does not constitute a license from TI to use such products or services or a warranty or endorsement thereof.
Use of such information may require a license from a third party under the patents or other intellectual property
of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of information in TI data books or data sheets is permissible only if reproduction is without
alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction
of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for
such altered documentation.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that
product or service voids all express and any implied warranties for the associated TI product or service and
is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.
Following are URLs where you can obtain information on other Texas Instruments products and application
solutions:
Products
Applications
Audio
Amplifiers
amplifier.ti.com
www.ti.com/audio
Data Converters
dataconverter.ti.com
Automotive
www.ti.com/automotive
DSP
dsp.ti.com
Broadband
Digital Control
Military
www.ti.com/broadband
www.ti.com/digitalcontrol
www.ti.com/military
Interface
Logic
interface.ti.com
logic.ti.com
Power Mgmt
Microcontrollers
power.ti.com
Optical Networking
Security
www.ti.com/opticalnetwork
www.ti.com/security
www.ti.com/telephony
www.ti.com/video
microcontroller.ti.com
Low Power Wireless www.ti.com/lpw
Telephony
Video & Imaging
Wireless
www.ti.com/wireless
Mailing Address:
Texas Instruments
Post Office Box 655303 Dallas, Texas 75265
Copyright 2006, Texas Instruments Incorporated
相关型号：
©2020 ICPDF网 联系我们和版权申明