SN74GTL2014 [TI]

4 位 LVTTL 至 GTL 收发器;


型号：	SN74GTL2014
厂家：	TEXAS INSTRUMENTS
描述：	4 位 LVTTL 至 GTL 收发器
文件：	总19页 (文件大小：670K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

Sample &

Buy

Support &

Community

Product

Folder

Tools &

Software

Technical

Documents

SN74GTL2014

ZHCSCJ4A –FEBRUARY 2014–REVISED OCTOBER 2014

SN74GTL2014 4 通道 LVTTL 至 GTL 收发器

1 特性

2 应用

•

可用作 GTL–/GTL/GTL+ 至 LVTTL 转换器或

LVTTL 至 GTL–/GTL/GTL+ 转换器

•

服务器

基站

LVTTL 输入最高可承受 5.5V 电压，允许直接访问

TTL 或 5V CMOS

有线通信

GTL 输入/输出工作电压高达 3.6V，这使得器件可

在高压开漏应用中使用

3 说明

SN74GTL2014 是一款 4 通道转换器，用于连接 3.3V

LVTTL 芯片组 I/O 与 Xeon 处理器 GTL–/GTL/GTL+

I/O。

•

VREF 可降至 0.5V，以实现低电压 CPU 使用率

支持局部断电

锁断保护超过 500mA，符合 JESD78 规范的要求

封装选项：TSSOP14

SN74GTL2014 在所有端子上集成了 ESD 保护单元，

并且采用 TSSOP 封装 (5.0mm × 4.4mm)。器件在自

然通风环境下的额定工作温度范围为 -40°C 至 85°C。

-40°C 至 + 85°C 工作温度范围

所有端子上具备静电放电 (ESD) 保护

器件信息⁽¹⁾

–

2000V 人体模型 (HBM)，JESD22-A114

1000V 充电器件模型 (CDM)，IEC61000-4-2

部件号

封装

封装尺寸（标称值）

薄型小外形尺寸封装

(TSSOP) (14)

SN74GTL2014

5.00mm x 4.40mm

(1) 要了解所有可用封装，请见数据表末尾的可订购产品附录。

GTL2014

–

002aab139

VREF

DIR

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

English Data Sheet: SCLS746

SN74GTL2014

ZHCSCJ4A –FEBRUARY 2014–REVISED OCTOBER 2014

www.ti.com.cn

8.2 Functional Block Diagram ......................................... 8

8.3 Feature Description................................................... 8

8.4 Device Functional Modes.......................................... 8

Application and Implementation .......................... 9

9.1 Application Information.............................................. 9

9.2 Typical Application .................................................... 9

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Pin Configuration and Functions......................... 3

Specifications......................................................... 4

6.1 Absolute Maximum Ratings ...................................... 4

6.2 Handling Ratings....................................................... 4

6.3 Recommended Operating Conditions....................... 4

6.4 Thermal Information.................................................. 5

6.5 Electrical Characteristics........................................... 5

6.6 Dynamic Electrical Characteristics............................ 6

6.7 Typical Characteristics.............................................. 6

Parameter Measurement Information .................. 7

Detailed Description .............................................. 8

8.1 Overview ................................................................... 8

10 Power Supply Recommendations ..................... 12

11 Layout................................................................... 12

11.1 Layout Guidelines ................................................. 12

11.2 Layout Example .................................................... 12

12 器件和文档支持 ..................................................... 13

12.1 商标....................................................................... 13

12.2 静电放电警告......................................................... 13

12.3 术语表 ................................................................... 13

13 机械封装和可订购信息 .......................................... 13

4 修订历史记录

Changes from Original (February 2014) to Revision A

Page

•

已添加添加了处理额定值表，特性描述部分，器件功能模式，应用和实施部分，电源相关建议部分，布局部分，器件

和文档支持部分以及机械、封装和可订购信息部分。 ............................................................................................................ 1

•

Updated Specifications section .............................................................................................................................................. 4

Updated LVTTL/TTL to GTL–/GTL/GTL+ application schematic. ......................................................................................... 9

Updated LVTTL/TTL to GTL–/GTL/GTL+ application schematic. ....................................................................................... 11

Added Power Supply Recommendations ............................................................................................................................ 12

SN74GTL2014

www.ti.com.cn

ZHCSCJ4A –FEBRUARY 2014–REVISED OCTOBER 2014

5 Pin Configuration and Functions

TSSOP Package (14 Pin)

(Top View)

VCC

DIR

GND

VREF

GTL2014

GND

Pin Functions

DESCRIPTION

NAME

NUMBER

A01

A02

A03

LVTTL data input/output

B01

B02

B03

DIR

GTL data input/output

Direction control input (LVTTL)

Ground

GND

VCC

Supply voltage

VREF

GTL reference voltage

SN74GTL2014

ZHCSCJ4A –FEBRUARY 2014–REVISED OCTOBER 2014

www.ti.com.cn

6 Specifications

6.1 Absolute Maximum Ratings

Specified at T_A= –40°C to 85°C unless otherwise noted⁽¹⁾

MIN

MAX

UNIT

V_CC

I_IK

Supply voltage

–0.5

4.6

–50

Input clamping current, VI < 0 V

Input control voltages SEL⁽²⁾⁽³⁾

V_SEL

–0.5

A port

B port

V_I

Input voltage

4.6

–50

I_OK

V_O

Control input clamp current, V_O< 0 V

Output voltage

A port

B port

A port

B port

–0.5

4.6

–40

I_OL

I_OH

Current into any output in the low state

Current into any output in the high state

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only and functional operation of the device at these conditions is not implied. Exposure to absolute-maximum-rated conditions for

extended periods may affect device reliability.

(2) All voltages are with respect to ground, unless otherwise specified

(3) V_Iand V_Oare used to denote specific conditions for V_I/O

6.2 Handling Ratings

MIN

–55

MAX

150

UNIT

T_stg

Storage temperature range

°C

Human Body Model (HBM), JEDEC: JESD22-A114⁽²⁾

IEC61000-4-2 contact discharge⁽³⁾

All pins

(1)

V_ESD

(1) Electrostatic discharge (ESD) to measure device sensitivity/immunity to damage caused by assembly line electrostatic discharges into

the device.

(2) Level listed above is the passing level per ANSI/ESDA/JEDEC JS-001. JEDEC document JEP155 states that 500-V HBM allows safe

manufacturing with a standard ESD control process. Pins listed as 250 V may actually have higher performance.

(3) Level listed above is the passing level per EIA-JEDEC JESD22-C101. JEDEC document JEP157 states that 250-V CDM allows safe

manufacturing with a standard ESD control process. Pins listed as 250 V may actually have higher performance.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

NOM

3.3

MAX UNIT

V_CCSupply voltage

3.6

0.95

1.26

1.65

V_CC/ 2

0.63

0.84

1.1

GTL–

0.85

0.9

V_TT

Termination voltage

GTL

1.14

1.2

GTL+

1.35

1.5

Overall

GTL–

0.5

2 / 3 V_TT

0.6

0.5

V_REFReference voltage

GTL

0.76

0.8

GTL+

0.87

A port

B port

A port and DIR

B port

3.3

5.5⁽²⁾

V_I

Input voltage

V_TT

3.6

V_IH

High-level input voltage

V_REF+ 50 mV

(1) All unused control inputs of the device must be held at V_CCor GND to ensure proper device operation. Refer to the TI application report,

Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

(2) The V_I(max) of LVTTL port is 3.6 V if configured as output (DIR=L)

SN74GTL2014

www.ti.com.cn

ZHCSCJ4A –FEBRUARY 2014–REVISED OCTOBER 2014

Recommended Operating Conditions (continued)

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

NOM

MAX UNIT

A port and DIR

0.8

V_IL

I_OH

I_OL

Low-level input voltage

High-level input current

Low-level output current

B port

A port

B port

V_REF– 50 mV

–20

6.4 Thermal Information

SN74GTL2014

THERMAL METRIC⁽¹⁾

UNIT

14 PINS

136.8

R_θJA

R_θJC(top)

R_θJB

ψ_JT

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

63.0

78.6

°C/W

Junction-to-top characterization parameter

Junction-to-board characterization parameter

11.9

ψ_JB

77.9

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

Specified at T_A= –40°C to 85°C (unless otherwise noted)

–40°C TO 85°C

PARAMETER

TEST CONDITIONS

UNIT

MIN

V_CC– 0.2

TYP

MAX

V_CC= 3 to 3.6 V, I_OH= –100 µA

V_CC= 3 V, I_OH= –16 mA

V_CC= 3 V, I_OL= 8 mA

V_OHA port

A port

0.28

0.55

0.23

0.4

0.8

0.4

±1

V_OL

A port

B port

V_CC= 3 V, I_OL= 16 mA

V_CC= 3 V, I_OL = 40 mA

V_CC= 3.6 V, V_I= V_CC

A port

B port

V_CC= 3.6, V_I= 0 V

±1

µA

I_I

V_CC= 3.6, V_I= 5.5 V

V_CC= 3.6 V, V_I= V_TTor GND

V_CC= 3.6 V, V_I= V_CCor 0 V

V_CC= 0 V, V_IO= 0 to 3.6 V

V_CC= 0 V, V_IO3.6 to 5.5V

V_CC= 0 V, V_IO= 0 to 3.6 V

V_CC= 3.6 V, V_I= V_CCor GND, I_O= 0

V_CC= 3.6 V, V_I= V_TTor GND, I_O= 0

V_CC= 3.6 V, V_I= V_CC– 0.6 V

V_I= 3.0 V or 0 V

±1

µA

Control pin

±1

OFF-state output current on A port

OFF-state output current on B port

A port

±10

±100

±10

I_off

µA

I_CC

B port

∆I_CCA port or control input

500

2.5

C_I

Input capacitance of control pin

A port

B port

V_O= 3 V or 0

C_IO

V_O= V_TTor 0

5.46

5.55

SN74GTL2014

ZHCSCJ4A –FEBRUARY 2014–REVISED OCTOBER 2014

www.ti.com.cn

6.6 Dynamic Electrical Characteristics

over operating range, T_A= –40°C to 85°C, V_CC= 1.65 to 4.6 V, GND = 0 V for GTL (see Functional Block Diagram)

GTL−

GTL

GTL+

V_CC= 3.3 V ± 0.3 V

V_REF= 0.6 V

V_CC= 3.3 V ± 0.3 V

V_REF= 0.8 V

V_CC= 3.3 V ± 0.3 V

V_REF= 1 V

PARAMETER

UNIT

V_TT= 0.9 V

V_TT= 1.2 V

V_TT= 1.5 V

MIN

TYP

2.8

3.3

5.3

5.2

MAX

MIN TYP

MAX

MIN TYP MAX

t_PLH(low to high propagation delay)

t_PHL(high to low propagation delay)

t_PLH(low to high propagation delay)

t_PHL(high to low propagation delay)

2.8

3.4

5.2

4.9

2.8

3.4

5.1

An to Bn

Bn to An

7.16

4.7 7.16

6.7 Typical Characteristics

1.2

1.1

VREF

VTH+

1.1

VTH+

VTH-

0.9

0.8

0.7

0.6

0.5

0.4

0.9

0.8

0.7

0.6

0.5

0.4

0.5

0.6

0.7

0.8

0.9

1.1

1.2

0.4

0.5

0.6

0.7

0.8

0.9

1.1

1.2

VREF (V)

C001

C002

Figure 1. GTL Vth+ and Vth– vs VREF (25°C)

Figure 2. GTL Vth+ and Vth– vs VREF (–40°C)

1.2

VREF

VTH+

VTH-

1.1

0.9

0.8

0.7

0.6

0.5

0.4

0.5

0.6

0.7

0.8

VREF (V)

0.9

1.1

1.2

C003

Figure 3. GTL Vth+ and Vth– vs VREF (125°C)

SN74GTL2014

www.ti.com.cn

ZHCSCJ4A –FEBRUARY 2014–REVISED OCTOBER 2014

7 Parameter Measurement Information

V_TT= 1.2 V, V_REF= 0.8 V for GTL and V_TT= 1.5 V, V_REF= 1 V FOR GTL+

From Output

Under Test

25 Ω

From Output

Under Test

= 30 pF

Test

= 50 pF

Point

(see Note A)

500 Ω

(see Note A)

LOAD CIRCUIT FOR A OUTPUTS

LOAD CIRCUIT FOR B OUTPUTS

3 V

0 V

Input

(see Note B)

Input

1.5 V

REF

(see Note B)

0 V

PHL

PLH

Output

REF

1.5 V

VOLTAGE WAVEFORM 2

1.5 V

REF

VOLTAGE WAVEFORM 1

PROPAGATION DELAY TIMES

†

PROPAGATION DELAY TIMES

†

(B port to A port)

(A port to B port)

3 V

0 V

Input

REF

1.5 V

(see Note B)

0 V

PHL

PLH

Output

REF

1.5 V

VOLTAGE WAVEFORM 3

VOLTAGE WAVEFORM 4

PROPAGATION DELAY TIMES

†

PROPAGATION DELAY TIMES

†

(B port to B port)

(ENn to A port)

3 V

0 V

Input

1.5 V

(see Note B)

REF

0 V

PZL

PLZ

PZL

PLZ

Output

S1 at 2 xV

1.5 V

+ 0.3 V

V + 0.3 V

VOLTAGE WAVEFORM 5

VOLTAGE WAVEFORM 6

PROPAGATION DELAY TIMES

†

ENABLE AND DISABLE TIMES

†

(B port to A (I/O) port)

(EN2 to A (I/O) port)

†

All control inputs are LVTTL levels.

includes probe and jig capacitance.

NOTES: A.

B. All input pulses are supplied by generators having the following characteristics: PRR≤ 10 MHz, Z_O= 50 Ω, t_r≤ 2.5 ns, t_f≤ 2.5 ns.

C. The outputs are measured one at a time, with one transition per measurement.

Figure 4. Load Circuits and Voltage Waveforms

SN74GTL2014

ZHCSCJ4A –FEBRUARY 2014–REVISED OCTOBER 2014

www.ti.com.cn

8 Detailed Description

8.1 Overview

The GTL2014 is a 4-channel translating transceiver designed for 3.3-V LVTTL system interface with a

GTL–/GTL/GTL+ bus, where GTL–/GTL/GTL+ refers to the reference voltage of the GTL bus and the

input/output voltage thresholds associated with it.

The direction pin allows the part to function as either a GTL-to-LVTTL sampling receiver or as a LVTTL-to-GTL

interface.

8.2 Functional Block Diagram

GTL2014

–

002aab139

VREF

DIR

8.3 Feature Description

8.3.1 5 V tolerance on LVTTL input

The GTL2014 LVTTL inputs (only) are tolerant up to 5.5 V and allows direct access to TTL or 5 V CMOS inputs.

The LVTTL outputs are not 5.5 V tolerant.

8.3.2 3.6 V tolerance on GTL Input/Output

The GTL2014 GTL inputs and outputs operate up to 3.6 V, allowing the device to be used in higher voltage

open-drain output applications.

8.3.3 Ultra-Low VREF and High Bandwidth

GTL2014’s VREF tracks down to 0.5 V for low voltage CPUs with excellent propagation delay performance. This

feature allows the GTL2014 to support high data rates with the GTL– bus.

8.4 Device Functional Modes

The GTL2014 performs translation in two directions. One direction is GTL–/GTL/GTL+ to LVTTL when DIR is tied

to GND. With appropriate VREF set up, the GTL input can be compliant with GTL–/GTL/GTL+. Another direction

is LVTTL to GTL–/GTL/GTL+ when DIR is tied to VCC. 3.6 V tolerance on the GTL output allows the GTL

outputs to pull up to any voltage level under 3.6 V.

SN74GTL2014

www.ti.com.cn

ZHCSCJ4A –FEBRUARY 2014–REVISED OCTOBER 2014

9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

9.1 Application Information

GTL2014 is the voltage translator for GTL–/GTL/GTL+ to LVTTL or LVTTL to GTL–/GTL/GTL+. Please find the

reference schematic and recommend value for passive component in the Typical Application.

9.2 Typical Application

9.2.1 GTL–/GTL/GTL+ to LVTTL

Select appropriate VTT/VREF based upon GTL–/GTL/GTL+. The parameters in Recommended Operating

Conditions are compliant to the GTL specification.

3.3 V

DIR

GTL

VCC 14

A0 13

LVTTL

A1 12

VREF

GTL2014PW

GND 11

Chipset

FPGA

A2 10

GND

Port_B to Port_A

GTL to LVTTL

3.3 V

VCC

Vref

VTT

2*VTT/3

1.0 V

VTT

DIR

GND

75 Ω

49.9 Ω

100 Ω

Figure 5. Application Diagram for GTL to LVTTL

SN74GTL2014

ZHCSCJ4A –FEBRUARY 2014–REVISED OCTOBER 2014

www.ti.com.cn

Typical Application (continued)

9.2.1.1 Design Requirements

The GTL2014 requires industrial standard LVTTL and GTL inputs. The design example in Application Information

show standard voltage level and typical resistor values.

NOTE

Only LVTTL terminals (A1/A2/A3/A4) are tolerant to 5 V.

9.2.1.2 Detailed Design Procedure

To begin the design process, determine the following:

1. Select direction base upon application (GTL–/GTL/GTL+ to LVTTL or LVTTL to GTL–/GTL/GTL+).

2. Set up appropriate DIR pin and VREF/VTT.

3. Choose correct pullup resistor value base upon data rate and driving current requirement (for LVTTL to

GTL–/GTL/GTL+).

9.2.1.3 Application Curve

3.30

Input

Output

2.80

2.30

1.80

1.30

0.80

0.30

±0.20

1.25

2.5

3.75

6.25

7.5

8.75

Time (ns)

C005

Figure 6. GTL-to-LVTTL, VREF = 1 V, VIN = 1.5 V, 100 MHz

SN74GTL2014

www.ti.com.cn

ZHCSCJ4A –FEBRUARY 2014–REVISED OCTOBER 2014

Typical Application (continued)

9.2.2 LVTTL/TTL to GTL–/GTL/GTL+

Because GTL is an open-drain interface, the selection of pullup resistor depends on the application requirement

(for example, data rate) and PCB trace capacitance.

3.3 V

DIR

GTL

VCC 14

A0 13

LVTTL

A1 12

VREF

GTL2014PW

GND 11

Chipset

FPGA

A2 10

GND

Port_A to Port_B

LVTTL to GTL

VCC

Vref

VTT

3.3 V

GND

1.0 V

VTT

DIR

3.3 V

75 Ω

Not Avaliable

Figure 7. Application Diagram for LVTTL to GTL

9.2.2.1 Design Requirements

The GTL2014 requires industrial standard LVTTL and GTL inputs. The design example in the Application

Information section show standard voltage level and typical resistor values.

NOTE

Only LVTTL terminals (A1/A2/A3/A4) are tolerant to 5 V.

9.2.2.2 Detailed Design Procedure

To begin the design process, determine the following:

1. Select direction based upon application (GTL–/GTL/GTL+ to LVTTL or LVTTL to GTL–/GTL/GTL+).

2. Set up appropriate DIR pin and VREF/VTT.

3. Choose correct pullup resistor value base upon data rate and driving current requirement (for LVTTL to

GTL–/GTL/GTL+).

SN74GTL2014

ZHCSCJ4A –FEBRUARY 2014–REVISED OCTOBER 2014

www.ti.com.cn

Typical Application (continued)

9.2.2.3 Application Curve

2.80E+00

Input (V)

Output (V)

2.30E+00

1.80E+00

1.30E+00

8.00E-01

3.00E-01

-2.00E-01

Time (ns)

C001

Figure 8. LVTTL-to-GTL, VREF = 1 V, VTT = 1.5 V, 10 MHz

10 Power Supply Recommendations

Because GTL is a low voltage interface, TI recommends a 0.1-µF decoupling capacitor for VREF.

11 Layout

11.1 Layout Guidelines

Typically, GTL/LVTTL is running at a low data rate; however, the GTL2014 is optimized for excellent propagation

delay, slew rate, bandwidth, and is able support 100-MHz frequencies.

11.2 Layout Example

Short Signal Trace as possible

VCC

DIR

GND

VREF

GTL2014

Minimize Stub as possible

GND

Figure 9. Layout Example for GTL Trace

SN74GTL2014

www.ti.com.cn

ZHCSCJ4A –FEBRUARY 2014–REVISED OCTOBER 2014

12 器件和文档支持

12.1 商标

All trademarks are the property of their respective owners.

12.2 静电放电警告

ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可

能会损坏集成电路。

ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可

能会导致器件与其发布的规格不相符。

12.3 术语表

SLYZ022 — TI 术语表。

这份术语表列出并解释术语、首字母缩略词和定义。

13 机械封装和可订购信息

以下页中包括机械封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不对

本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本，请查阅左侧的导航栏。

PACKAGE OPTION ADDENDUM

www.ti.com

10-Dec-2020

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

SN74GTL2014PWR

ACTIVE

TSSOP

2000 RoHS & Green

NIPDAU | SN

Level-1-260C-UNLIM

-40 to 85

GT14

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

3-Jun-2022

TAPE AND REEL INFORMATION

REEL DIMENSIONS

TAPE DIMENSIONS

Reel

Diameter

Cavity

A0 Dimension designed to accommodate the component width

B0 Dimension designed to accommodate the component length

K0 Dimension designed to accommodate the component thickness

Overall width of the carrier tape

P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2

Q3 Q4

Q1 Q2

Q3 Q4

User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

SN74GTL2014PWR

TSSOP

2000

330.0

12.4

6.9

5.6

1.6

8.0

12.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

3-Jun-2022

TAPE AND REEL BOX DIMENSIONS

Width (mm)

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

SN74GTL2014PWR

TSSOP

2000

356.0

364.0

356.0

364.0

35.0

27.0

Pack Materials-Page 2

重要声明和免责声明

TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担

保。

这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验

证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。

这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。

您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成

本、损失和债务，TI 对此概不负责。

TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改

TI 针对 TI 产品发布的适用的担保或担保免责声明。

TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

SN74GTL2014 [TI]

相关型号：

SN74GTL2014PWR

SN74GTL2107

SN74GTL2107PW

SN74GTL2107PWG4

SN74GTL2107PWR

SN74GTL2107PWRG4

SN74GTL3004

SN74GTL3004DCKR

SN74GTL3004DCKRG4

SN74GTLP1394

SN74GTLP1394D

SN74GTLP1394DE4