SN74GTL16616DGG [TI]
17-BIT LVTTL-TO-GTL/GTL UNIVERSAL BUS TRANSCEIVERS WITH BUFFERED CLOCK OUTPUTS; 用缓冲时钟输出的17位LVTTL - TO- GTL / GTL通用总线收发器
| 型号： | SN74GTL16616DGG |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 17-BIT LVTTL-TO-GTL/GTL UNIVERSAL BUS TRANSCEIVERS WITH BUFFERED CLOCK OUTPUTS |
| 文件： | 总11页 (文件大小：177K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN54GTL16616, SN74GTL16616
17-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVERS
WITH BUFFERED CLOCK OUTPUTS
SCBS481F – JUNE 1994 – REVISED NOVEMBER 1999
SN54GTL16616 . . . WD PACKAGE
SN74GTL16616 . . . DGG OR DL PACKAGE
(TOP VIEW)
Members of the Texas Instruments
Widebus Family
Universal Bus Transceiver (UBT
)
Combines D-Type Latches and D-Type
Flip-Flops for Operation in Transparent,
Latched, Clocked, or Clock-Enabled Mode
OEAB
LEAB
A1
GND
A2
A3
(3.3 V)
A4
CEAB
CLKAB
B1
GND
B2
1
2
3
4
5
6
7
8
9
56
55
54
53
52
51
50
49
48
GTL Buffered CLKAB Signal (CLKOUT)
Translate Between GTL/GTL+ Signal Levels
and LVTTL Logic Levels
B3
V
V
(5 V)
CC
CC
Support Mixed-Mode (3.3 V and 5 V) Signal
Operation on A-Port and Control Inputs
B4
B5
A5
Equivalent to ’16601 Function
A6 10
47 B6
I
Supports Partial-Power-Down Mode
off
GND
A7
GND
B7
11
12
46
45
Operation
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors on A Port
A8 13
A9 14
44 B8
43 B9
A10 15
A11 16
42 B10
41 B11
40 B12
39 GND
38 B13
37 B14
36 B15
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
A12 17
GND 18
A13 19
A14 20
A15 21
(3.3 V) 22
A16 23
A17 24
GND 25
CLKIN 26
OEBA 27
LEBA 28
Distributed V
Minimizes High-Speed Switching Noise
and GND-Pin Configuration
CC
Package Options Include Plastic Shrink
Small-Outline (DL), Thin Shrink
Small-Outline (DGG), and Ceramic Flat
(WD) Packages
V
35
V
CC
REF
34 B16
33 B17
32 GND
31 CLKOUT
30 CLKBA
29 CEBA
description
The ’GTL16616 devices are 17-bit universal
bus transceivers (UBTs) that provide
LVTTL-to-GTL/GTL+ and GTL/GTL+-to-LVTTL
signal-level translation. They combine D-type
flip-flops and D-type latches to allow for transparent, latched, clocked, and clocked-enabled modes of data
transfer identical to the ’16601 function. Additionally, they provide for a copy of CLKAB at GTL/GTL+ signal
levels (CLKOUT) and conversion of a GTL/GTL+ clock to LVTTL logic levels (CLKIN). The devices provide an
interface between cards operating at LVTTL logic levels and a backplane operating at GTL/GTL+ signal levels.
Higher-speed operation is a direct result of the reduced output swing (<1 V), reduced input threshold levels, and
output edge control (OEC ).
The user has the flexibility of using this device at either GTL (V = 1.2 V and V
= 0.8 V) or the preferred
TT
REF
higher noise margin GTL+ (V = 1.5 V and V
= 1 V) signal levels. GTL+ is the Texas Instruments derivative
TT
REF
of the Gunning transceiver logic (GTL) JEDEC standard JESD 8-3. The B port normally operates at GTL or
GTL+ signal levels, while the A-port and control inputs are compatible with LVTTL logic levels and are 5-V
tolerant. V
isthereferenceinputvoltagefortheBport. V (5V)suppliestheinternalandGTLcircuitrywhile
REF
CC
V
(3.3 V) supplies the LVTTL output buffers.
CC
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus, OEC, and UBT are trademarks of Texas Instruments Incorporated.
Copyright 1999, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54GTL16616, SN74GTL16616
17-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVERS
WITH BUFFERED CLOCK OUTPUTS
SCBS481F – JUNE 1994 – REVISED NOVEMBER 1999
description (continued)
Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA),
and clock (CLKAB and CLKBA) inputs. The clock can be controlled by the clock-enable (CEAB and CEBA)
inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is high. When LEAB is
low, the A data is latched if CEAB is low and CLKAB is held at a high or low logic level. If LEAB is low, the A-bus
data is stored in the latch/flip-flop on the low-to-high transition of CLKAB if CEAB also is low. When OEAB is
low, the outputs are active. When OEAB is high, the outputs are in the high-impedance state. Data flow for B
to A is similar to that of A to B, but uses OEBA, LEBA, CLKBA, and CEBA.
These devices are fully specified for partial-power-down applications using I . The I circuitry disables the
off
off
outputs, preventing damaging current backflow through the device when it is powered down.
Active bus-hold circuitry holds unused or undriven LVTTL inputs at a valid logic state. Use of pullup or pulldown
resistors with the bus-hold circuitry is not recommended.
To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup
CC
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN54GTL16616 is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74GTL16616 is characterized for operation from –40°C to 85°C.
†
FUNCTION TABLE
INPUTS
OUTPUT
B
MODE
Isolation
CEAB OEAB LEAB CLKAB
A
X
X
X
L
X
L
H
L
L
L
L
L
L
L
X
L
X
Z
‡
B
0
§
B
0
H or L
Latched storage of A data
L
L
H or L
X
X
L
H
H
L
X
X
↑
L
H
L
Transparent
H
L
Clocked storage of A data
Clock inhibit
L
L
↑
H
X
H
§
B
0
H
L
X
†
‡
§
A-to-B data flow is shown. B-to-A data flow is similar, but uses OEBA, LEBA, CLKBA,
and CEBA.
Output level before the indicated steady-state input conditions were established, provided
that CLKAB was high before LEAB went low
Output level before the indicated steady-state input conditions were established
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54GTL16616, SN74GTL16616
17-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVERS
WITH BUFFERED CLOCK OUTPUTS
SCBS481F – JUNE 1994 – REVISED NOVEMBER 1999
logic diagram (positive logic)
35
V
REF
1
OEAB
CEAB
56
55
2
CLKAB
LEAB
28
30
29
27
LEBA
CLKBA
CEBA
OEBA
CE
3
A1
1D
C1
54
B1
CLK
CE
1D
C1
CLK
1 of 17 Channels
31
CLKOUT
26
CLKIN
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54GTL16616, SN74GTL16616
17-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVERS
WITH BUFFERED CLOCK OUTPUTS
SCBS481F – JUNE 1994 – REVISED NOVEMBER 1999
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V : 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
CC
5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Input voltage range, V (see Note 1): A-port and control inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
I
B port and V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
REF
Voltage range applied to any output in the high or power-off state, V
O
(see Note 1): A port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
B port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
Current into any output in the low state, I : A port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
O
B port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 mA
Current into any A-port output in the high state, I (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 mA
O
Continuous current through each V
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
CC
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Package thermal impedance, θ (see Note 3): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W
IK
I
Output clamp current, I
OK
O
JA
DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This current flows only when the output is in the high state and V > V
.
CC
O
3. The package thermal impedance is calculated in accordance with JESD 51.
recommended operating conditions (see Notes 4 through 6)
SN54GTL16616
SN74GTL16616
UNIT
V
MIN
3.15
4.75
1.14
1.35
0.74
0.87
NOM
3.3
5
MAX
3.45
5.25
1.26
1.65
0.87
1.1
MIN
3.15
4.75
1.14
1.35
0.74
0.87
NOM
3.3
5
MAX
3.45
5.25
1.26
1.65
0.87
1.1
3.3 V
V
V
V
V
V
V
Supply voltage
CC
TT
REF
I
5 V
GTL
1.2
1.5
0.8
1
1.2
1.5
0.8
1
Termination
voltage
V
GTL+
GTL
Supply voltage
Input voltage
V
GTL+
B port
V
V
TT
TT
V
Except B port
B port
5.5
5.5
V
+50 mV
2
V +50 mV
REF
2
High-level
input voltage
REF
V
IH
Except B port
B port
V
REF
–50 mV
0.8
V
REF
–50 mV
0.8
Low-level
input voltage
V
IL
Except B port
I
I
Input clamp current
–18
–18
mA
mA
IK
High-level
output current
A port
–32
–32
OH
OL
A port
B port
64
40
64
40
85
Low-level
output current
I
mA
T
Operating free-air temperature
–55
125
–40
°C
A
NOTES: 4. All unused inputs of the device must be held at V
CC
or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
5. Normal connection sequence is GND first, V = 5 V second, and V = 3.3 V, I/O, control inputs, V and V
(any order) last.
ratings.
CC CC TT REF
6.
V
and R can be adjusted to accommodate backplane impedances as long as they do not exceed the DC absolute I
TT
Similarly, V
T
T
O
L
can be adjusted to optimize noise margins, but normally is 2/3 V
.
TT
REF
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54GTL16616, SN74GTL16616
17-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVERS
WITH BUFFERED CLOCK OUTPUTS
SCBS481F – JUNE 1994 – REVISED NOVEMBER 1999
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54GTL16616
SN74GTL16616
PARAMETER
TEST CONDITIONS
(3.3 V) = 3.15 V, V
UNIT
†
TYP
†
TYP
MIN
MAX
MIN
MAX
V
IK
V
V
(5 V) = 4.75 V, I = –18 mA
–1.2
–1.2
V
CC
CC
I
(3.3 V)= 3.15 V to
CC
3.45 V,
I
= –100 µA
V
–0.2
V
–0.2
OH
CC
CC
V
CC
(5 V) = 4.75 V to 5.25 V
V
OH
A port
V
V
I
I
I
I
I
I
= –8 mA
= –32 mA
= 100 µA
= 16 mA
= 32 mA
= 64 mA
2.4
2
2.4
2
V
CC
V
CC
(3.3 V) = 3.15 V,
(5 V) = 4.75 V
OH
OH
OL
OL
OL
OL
0.2
0.4
0.2
0.4
V
CC
V
CC
(3.3 V) = 3.15 V,
(5 V) = 4.75 V
A port
B port
0.5
0.5
V
OL
0.55
0.55
V
CC
V
CC
(3.3 V) = 3.15 V,
(5 V) = 4.75 V
I
= 40 mA
0.4
10
0.4
10
OL
Control
inputs
V
CC
V
CC
= 0 or 3.45 V,
(5 V) = 0 or 5.25 V
V = 5.5 V
I
V = 5.5 V
I
20
1
20
1
V
V
(3.3 V) = 3.45 V,
(5 V) = 5.25 V
CC
CC
V = V
I
(3.3 V)
(3.3 V)
A port
B port
I
I
CC
µA
V = 0
I
–30
5
–30
5
V = V
I
V
CC
V
CC
(3.3 V) = 3.45 V,
(5 V) = 5.25 V
CC
V = 0
I
–5
100
–5
100
I
I
V
CC
= 0, V or V = 0 to 4.5 V
µA
µA
off
I
O
V = 0.8 V
75
75
I
V
V
(3.3 V) = 3.15 V,
(5 V) = 4.75 V
CC
CC
A port
V = 2 V
I
–75
–75
I(hold)
‡
V = 0 to V
I
(3.3 V)
±500
1
±500
1
CC
A port
B port
A port
B port
V
CC
V
CC
V
CC
V
CC
(3.3 V) = 3.45 V, V
(3.3 V) = 3.45 V, V
(3.3 V) = 3.45 V, V
(3.3 V) = 3.45 V, V
(5 V) = 5.25 V, V = 3 V
CC
CC
CC
CC
O
I
I
µA
µA
OZH
(5 V) = 5.25 V, V = 1.2 V
10
–1
–10
1
10
–1
–10
1
O
(5 V) = 5.25 V, V = 0.5 V
O
OZL
(5 V) = 5.25 V, V = 0.4 V
O
Outputs high
Outputs low
V
V
(3.3 V) = 3.45 V,
CC
CC
I
A or B
CC
5
5
mA
(5 V) = 5.25 V, I = 0,
O
(3.3 V) port
V = V
I
(3.3 V) or GND
CC
Outputs disabled
Outputs high
1
1
120
120
120
120
120
120
V
V
(3.3 V) = 3.45 V,
CC
CC
I
A or B
port
CC
(5 V)
Outputs low
mA
mA
(5 V) = 5.25 V, I = 0,
O
V = V
I
(3.3 V) or GND
CC
Outputs disabled
(5 V) = 5.25 V,
CC
V
CC
(3.3 V) = 3.45 V, V
§
∆I
CC
A-port or control inputs at V
One input at 2.7 V
(3.3 V) or GND,
1
1
CC
Control
inputs
C
C
V = 3.15 V or 0
3.5
12
3.5
12
pF
pF
i
I
A port
B port
V
O
= 3.15 V or 0
io
Per IEEE Std 1194.1
(3.3 V) = 3.3 V, V
5
5
†
‡
§
All typical values are at V
(5 V) = 5 V, T = 25°C.
A
CC
This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another.
This is the increase in supply current for each input that is at the specified TTL voltage level rather than V or GND.
CC
CC
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54GTL16616, SN74GTL16616
17-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVERS
WITH BUFFERED CLOCK OUTPUTS
SCBS481F – JUNE 1994 – REVISED NOVEMBER 1999
timing requirements over recommended ranges of supply voltage and operating free-air
temperature, V = 1.2 V and V
= 0.8 V for GTL (unless otherwise noted) (see Figure 1)
TT
REF
SN54GTL16616 SN74GTL16616
UNIT
MHz
ns
MIN
MAX
MIN
MAX
f
t
Clock frequency
Pulse duration
95
95
clock
LEAB or LEBA high
CLKAB or CLKBA high or low
A before CLKAB↑
B before CLKBA↑
A before LEAB↓
3.3
5.5
1.3
2.5
0
3.3
5.5
1.3
2.5
0
w
t
su
Setup time
ns
B before LEBA↓
1.1
2.2
2.7
1.6
0.4
4
1.1
2.2
2.7
1.6
0.4
4
CEAB before CLKAB↑
CEBA before CLKBA↑
A after CLKAB↑
B after CLKBA↑
A after LEAB↓
t
h
Hold time
ns
B after LEBA↓
3.5
1.1
0.9
3.5
1.1
0.9
CEAB after CLKAB↑
CEBA after CLKBA↑
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54GTL16616, SN74GTL16616
17-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVERS
WITH BUFFERED CLOCK OUTPUTS
SCBS481F – JUNE 1994 – REVISED NOVEMBER 1999
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, V = 1.2 V and V
= 0.8 V for GTL (see Figure 1)
TT
REF
SN54GTL16616
SN74GTL16616
†
MAX
FROM
PARAMETER
TO
(OUTPUT)
UNIT
MHz
ns
†
(INPUT)
MIN TYP
MAX
MIN TYP
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
95
95
max
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
dis
1.4
3
4.6
4.7
5.6
5.6
5.9
5.7
8.2
11.4
5.8
5.2
1.7
3
4.4
4.5
5.4
5.3
5.7
5.4
8.1
11.3
5.6
5.1
A
B
1.2
2.1
1.9
2.2
1.8
4.5
5.5
2
2.8
3.8
3.7
4
1.4
2.3
2.2
2.4
2.1
4.7
5.7
2.1
2.1
2.8
3.8
3.7
4
LEAB
CLKAB
CLKAB
OEAB
B
B
ns
ns
ns
ns
3.7
6.1
7.9
3.8
3.6
1.2
0.7
4
3.7
6.1
7.9
3.8
3.6
1.2
0.7
4
CLKOUT
B or CLKOUT
2
en
Transition time, B outputs (0.5 V to 1 V)
Transition time, B outputs (1 V to 0.5 V)
ns
ns
r
f
1.6
1.3
2.3
1.9
2.5
2.1
7.2
5.9
2.7
2.6
6.8
4.7
1.7
1.4
2.4
2
6.7
4.7
5.8
4.6
6
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
en
B
A
ns
ns
ns
ns
ns
2.9
3.8
3
2.9
3.8
3
6.1
LEBA
A
A
4.8
4
6.3
2.6
2.2
7.4
6.1
2.8
2.7
4
CLKBA
CLKOUT
3.4
10
8.1
5.3
4.3
5.1
3.4
10
8.1
5.3
4.3
4.9
14.4
11.7
7.8
6.4
14.7
11.8
8.1
CLKIN
A or CLKIN
OEBA
6.7
dis
†
All typical values are at V
(3.3 V) = 3.3 V, V
(5 V) = 5 V, T = 25°C.
CC A
CC
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54GTL16616, SN74GTL16616
17-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVERS
WITH BUFFERED CLOCK OUTPUTS
SCBS481F – JUNE 1994 – REVISED NOVEMBER 1999
timing requirements over recommended ranges of supply voltage and operating free-air
temperature, V = 1.5 V and V
= 1 V for GTL+ (unless otherwise noted) (see Figure 1)
TT
REF
SN54GTL16616 SN74GTL16616
UNIT
MHz
ns
MIN
MAX
MIN
MAX
f
t
Clock frequency
Pulse duration
95
95
clock
LEAB or LEBA high
CLKAB or CLKBA high or low
A before CLKAB↑
B before CLKBA↑
A before LEAB↓
3.3
5.5
1.3
2.3
0
3.3
5.5
1.3
2.3
0
w
t
su
Setup time
ns
B before LEBA↓
1.3
2.2
2.7
1.6
0.6
4
1.3
2.2
2.7
1.6
0.6
4
CEAB before CLKAB↑
CEBA before CLKBA↑
A after CLKAB↑
B after CLKBA↑
A after LEAB↓
t
h
Hold time
ns
B after LEBA↓
3.5
1.1
0.9
3.5
1.1
0.9
CEAB after CLKAB↑
CEBA after CLKBA↑
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54GTL16616, SN74GTL16616
17-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVERS
WITH BUFFERED CLOCK OUTPUTS
SCBS481F – JUNE 1994 – REVISED NOVEMBER 1999
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, V = 1.5 V and V
= 1 V for GTL+ (see Figure 1)
TT
REF
SN54GTL16616
SN74GTL16616
†
MAX
FROM
PARAMETER
TO
(OUTPUT)
UNIT
MHz
ns
†
(INPUT)
MIN TYP
MAX
MIN TYP
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
95
95
max
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
r
1.4
3
4.6
4.8
5.6
5.7
5.9
5.8
8.2
11.5
5.2
5.9
1.7
3
4.4
4.6
5.4
5.4
5.7
5.5
8.1
11.4
5.1
5.7
A
B
1.2
2.1
1.9
2.2
1.8
4.5
5.5
2
2.9
3.8
3.7
4
1.4
2.3
2.2
2.4
2.1
4.7
5.7
2.1
2.1
2.9
3.8
3.7
4
LEAB
CLKAB
CLKAB
OEAB
B
B
ns
ns
ns
ns
3.8
6.1
8
3.8
6.1
8
CLKOUT
B or CLKOUT
3.6
3.8
1.4
1
3.6
3.8
1.4
1
2
Transition time, B outputs (0.5 V to 1 V)
Transition time, B outputs (1 V to 0.5 V)
ns
ns
f
1.5
1.2
2.3
1.9
2.5
2.1
7.1
5.8
2.7
2.6
3.9
2.8
3.8
3
6.8
4.5
1.6
1.3
2.4
2
3.9
2.8
3.8
3
6.6
4.5
5.8
4.6
6
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
en
B
A
ns
ns
ns
ns
ns
6.1
LEBA
A
A
4.8
4
6.3
2.6
2.2
7.3
6
4
CLKBA
CLKOUT
3.4
9.9
8
5.1
3.4
9.9
8
4.9
14.3
11.5
7.8
6.4
14.7
11.6
8.1
CLKIN
A or CLKIN
5.3
4.3
2.8
2.7
5.3
4.3
OEBA
6.7
dis
†
All typical values are at V
(3.3 V) = 3.3 V, V
(5 V) = 5 V, T = 25°C.
CC A
CC
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54GTL16616, SN74GTL16616
17-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVERS
WITH BUFFERED CLOCK OUTPUTS
SCBS481F – JUNE 1994 – REVISED NOVEMBER 1999
PARAMETER MEASUREMENT INFORMATION
V
= 1.2 V , V
= 0.8 V FOR GTL AND V = 1.5 V , V = 1 V FOR GTL+
TT
REF
TT REF
V
TT
6 V
S1
Open
500 Ω
From Output
Under Test
TEST
S1
Open
6 V
25 Ω
GND
t
t
t
/t
PLH PHL
/t
From Output
Under Test
Test
Point
PLZ PZL
/t
C
= 50 pF
L
500 Ω
GND
PHZ PZH
C
= 30 pF
(see Note A)
L
(see Note A)
LOAD CIRCUIT FOR A OUTPUTS
LOAD CIRCUIT FOR B OUTPUTS
t
w
3 V
Timing
Input
3 V
0 V
1.5 V
0 V
V
M
V
V
M
V
Input
t
t
h
su
3 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
Data Input
A Port
1.5 V
1.5 V
†
(V = 1.5 V for A port and V
for B port)
M
REF
V
TT
Data Input
B Port
3 V
0 V
V
V
REF
Input
(see Note B)
REF
1.5 V
1.5 V
0 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
t
t
PHL
PLH
V
V
TT
3 V
0 V
Output
V
V
REF
REF
Output
Control
(see Note B)
1.5 V
1.5 V
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
†
t
t
PLZ
(A port to B port)
PZL
Output
Waveform 1
S1 at 6 V
3 V
V
TT
Input
(see Note B)
1.5 V
V
REF
V
REF
V
+ 0.3 V
OL
V
(see Note C)
0 V
PHL
OL
OH
t
t
PHZ
PZH
t
t
PLH
Output
Waveform 2
S1 at GND
V
V
OH
OL
V
OH
– 0.3 V
1.5 V
1.5 V
1.5 V
Output
≈0 V
V
(see Note C)
VOLTAGE WAVEFORMS
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
(B port to A port)
ENABLE AND DISABLE TIMES
(A port and CLKIN)
†
All control inputs are TTL levels.
NOTES: A. includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
C
L
O
r
f
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuits and Voltage Waveforms
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
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pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
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In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
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Copyright 1999, Texas Instruments Incorporated
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