SN74GTL16622ADGGE4 [TI]
GTL/TVC SERIES, DUAL 9-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO64, PLASTIC, TSSOP-64;
| 型号： | SN74GTL16622ADGGE4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | GTL/TVC SERIES, DUAL 9-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO64, PLASTIC, TSSOP-64 信息通信管理 光电二极管 输出元件 逻辑集成电路 电视 |
| 文件： | 总13页 (文件大小：452K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74GTL16622A
18-BIT LVTTL-TO-GTL/GTL+ BUS TRANSCEIVER
www.ti.com
SCBS673F–AUGUST 1996–REVISED APRIL 2005
FEATURES
DGG PACKAGE
(TOP VIEW)
•
•
•
•
•
•
•
Member of Texas Instruments Widebus™
Family
OEAB
1A1
CLKAB
1CEAB
1CEBA
1B1
GND
1B2
1
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
OEC™ Circuitry Improves Signal Integrity and
Reduces Electromagnetic Interference
2
GND
1A2
1A3
3
D-Type Flip-Flops With Qualified Storage
Enable
4
5
Translates Between GTL/GTL+ Signal Levels
and LVTTL Logic Levels
GND
6
V
CC
1B3
7
Supports Mixed-Mode (3.3 V and 5 V) Signal
Operation on A-Port and Control Inputs
1A4
GND
1A5
1A6
GND
1A7
1A8
GND
1A9
2A1
GND
2A2
2A3
GND
2A4
2A5
GND
2A6
V
8
CC
1B4
1B5
1B6
GND
1B7
1B8
GND
1B9
2B1
GND
2B2
2B3
GND
2B4
2B5
2B6
9
Ioff Supports Partial-Power-Down Mode
Operation
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
Bus Hold on Data Inputs Eliminates the Need
for External Pullup/Pulldown Resistors on
A Port
•
•
•
Distributed VCC and GND Pins Minimize
High-Speed Noise
Latch-Up Performance Exceeds 250 mA Per
JESD 17
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
DESCRIPTION/ORDERING INFORMATION
V
REF
V
CC
2B7
2B8
GND
2B9
The SN74GTL16622A is an 18-bit registered bus
transceiver that provides LVTTL-to-GTL/GTL+ and
GTL/GTL+-to-LVTTL signal-level translation. This
device is partitioned as two separate 9-bit
transceivers with individual clock-enable controls and
contains D-type flip-flops for temporary storage of
data flowing in either direction. This device provides
an interface between cards operating at LVTTL logic
levels and a backplane operating at GTL/GTL+ signal
levels. Higher-speed operation is a direct result of the
reduced output swing (<1 V), reduced input threshold
levels, and OEC™ circuitry.
GND
2A7
2A8
GND 30
2A9 31
35 2CEBA
34 2CEAB
OEBA
CLKBA
32
33
The user has the flexibility of using this device at either GTL (VTT = 1.2 V and VREF = 0.8 V) or the preferred
higher noise margin GTL+ (VTT = 1.5 V and VREF = 1 V) signal levels. GTL+ is the Texas Instruments derivative
of the Gunning Transceiver Logic (GTL) JEDEC standard JESD 8-3. The B port normally operates at GTL or
GTL+ signal levels, while the A-port and control inputs are compatible with LVTTL logic levels and are 5-V
tolerant. VREF is the reference input voltage for the B port.
Data flow in each direction is controlled by the output-enable (OEAB and OEBA) and clock (CLKAB and CLKBA)
inputs. The clock-enable (CEAB and CEBA) inputs control each 9-bit transceiver independently, which makes the
device more versatile.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus, OEC are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 1996–2005, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
SN74GTL16622A
18-BIT LVTTL-TO-GTL/GTL+ BUS TRANSCEIVER
www.ti.com
SCBS673F–AUGUST 1996–REVISED APRIL 2005
DESCRIPTION/ORDERING INFORMATION (CONTINUED)
For A-to-B data flow, the device operates on the low-to-high transition of CLKAB if CEAB is low. When OEAB is
low, the outputs are active. When OEAB is high, the outputs are in the high-impedance state. Data flow for B to
A is similar to that of A to B, but uses OEBA, CLKBA, and CEBA.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
Active bus-hold circuitry holds unused or undriven LVTTL inputs at a valid logic state. Use of pullup or pulldown
resistors with the bus-hold circuitry is not recommended.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
ORDERING INFORMATION
TA
PACKAGE(1)
ORDERABLE PART NUMBER
TOP-SIDE MARKING
GTL16622A
–40°C to 85°C
TSSOP – DGG
Tape and reel
SN74GTL16622ADGGR
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
FUNCTION TABLE(1)
INPUTS
OUTPUT
B
MODE
Isolation
CEAB
OEAB
CLKAB
A
X
X
X
L
X
H
X
L
H
L
L
L
L
X
Z
(2)
X
B0
Latched storage of A data
(2)
H or L
B0
↑
↑
L
Clocked storage of A data
L
H
H
(1) A-to-B data flow is shown. B-to-A data flow is similar, but uses OEBA, CLKBA, and CEBA.
(2) Output level before the indicated steady-state input conditions are established
2
SN74GTL16622A
18-BIT LVTTL-TO-GTL/GTL+ BUS TRANSCEIVER
www.ti.com
SCBS673F–AUGUST 1996–REVISED APRIL 2005
LOGIC DIAGRAM (POSITIVE LOGIC)
40
V
REF
1
OEAB
63
64
33
62
1CEAB
CLKAB
CLKBA
1CEBA
32
2
OEBA
1A1
CE
1D
CLK
61
1B1
CE
1D
CLK
To Eight Other Channels
34
2CEAB
35
17
2CEBA
2A1
CE
1D
48
2B1
CLK
CE
1D
CLK
To Eight Other Channels
3
SN74GTL16622A
18-BIT LVTTL-TO-GTL/GTL+ BUS TRANSCEIVER
www.ti.com
SCBS673F–AUGUST 1996–REVISED APRIL 2005
Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
MIN
–0.5
–0.5
–0.5
–0.5
–0.5
MAX
UNIT
VCC
VI
Supply voltage range
Input voltage range(2)
4.6
6.5
V
A-port and control inputs
V
V
B port and VREF
A port
4.6
6.5
VO
Voltage range applied to any output in the high or power-off state(2)
B port
4.6
A port
48
IO
IO
Current into any output in the low state
mA
B port
100
48
Current into any A-port output in the high state(3)
Continuous current through each VCC or GND
Input clamp current
mA
mA
mA
mA
°C/W
°C
±100
–50
–50
55
IIK
VI < 0
IOK
θJA
Tstg
Output clamp current
Package thermal impedance(4)
VO < 0
Storage temperature range
–65
150
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
(3) The current flows only when the output is in the high state and VO > VCC
.
(4) The package thermal impedance is calculated in accordance with JESD 51-7.
Recommended Operating Conditions(1)(2)(3)(4)
MIN NOM
MAX UNIT
VCC
VTT
Supply voltage
3.15
1.14
1.35
0.74
0.87
3.3
1.2
1.5
0.8
1
3.45
1.26
1.65
0.87
1.1
V
GTL
Termination voltage
V
GTL+
GTL
VREF
Reference voltage
Input voltage
V
V
V
V
GTL+
B port
VTT
5.5
VI
Except B port
B port
VREF + 50 mV
2
VIH
VIL
High-level input voltage
Low-level input voltage
Except B port
B port
VREF – 50 mV
Except B port
0.8
–18
–24
24
IIK
Input clamp current
mA
mA
IOH
High-level output current
A port
A port
B port
IOL
TA
Low-level output current
mA
°C
50
Operating free-air temperature
–40
85
(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
(2) Normal connection sequence is GND first and VCC = 3.3 V, I/O, control inputs, VTT and VREF (any order) last.
(3) VTT and RTT can be adjusted to accommodate backplane impedances if the dc recommended IOL ratings are not exceeded.
(4) VREF can be adjusted to optimize noise margins, but normally is two-thirds VTT
.
4
SN74GTL16622A
18-BIT LVTTL-TO-GTL/GTL+ BUS TRANSCEIVER
www.ti.com
SCBS673F–AUGUST 1996–REVISED APRIL 2005
Electrical Characteristics
over recommended operating free-air temperature range for GTL/GTL+ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP(1)
MAX UNIT
VIK
VCC = 3.15 V,
II = –18 mA
–1.2
V
VCC = 3.15 V to 3.45 V,
IOH = –100 µA
IOH = –12 mA
IOH = –24 mA
IOL = 100 µA
IOL = 12 mA
VCC – 0.2
VOH
A port
2.4
2
V
VCC = 3.15 V
VCC = 3.15 V to 3.45 V,
VCC = 3.15 V
0.2
0.4
0.5
0.2
0.2
0.4
0.55
±5
A port
B port
IOL = 24 mA
VOL
VCC = 3.15 V to 3.45 V,
IOL = 100 µA
IOL = 10 mA
V
VCC = 3.15 V
IOL = 40 mA
IOL = 50 mA
B port
VCC = 3.45 V,
VCC = 3.45 V
VCC = 0,
VI = VTT or GND
VI = VCC or GND
VI = 5.5 V or GND
VI or VO = 0 to 5.5 V
VI = 0.8 V
II
±5
µA
µA
µA
A-port and control inputs
±20
100
Ioff
75
VCC = 3.15 V
II(hold)
A port
VI = 2 V
–75
VCC = 3.45 V(2)
VCC = 3.45 V,
VCC = 3.45 V,
,
VI = 0.8 V to 2 V
VO = VCC or GND
VO = 1.5 V
±500
±10
10
(3)
IOZ
A port
B port
µA
µA
IOZH
Outputs high
Outputs low
60
VCC = 3.45 V,
IO = 0,
ICC
A or B port
60
mA
VI = VCC or GND
Outputs disabled
60
VCC = 3.45 V, A-port or control inputs at VCC or GND,
One input at VCC – 0.6 V
(4)
∆ICC
500
µA
Ci
Control inputs
A port
VI = 3.15 V or 0
2.5
6
3
8
pF
Cio
VO = 3.15 V or 0
pF
B port
6.5
8.5
(1) All typical values are at VCC = 3.3 V, TA = 25°C.
(2) This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to
another.
(3) For I/O ports, the parameter IOZ includes the input leakage current.
(4) This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND.
5
SN74GTL16622A
18-BIT LVTTL-TO-GTL/GTL+ BUS TRANSCEIVER
www.ti.com
SCBS673F–AUGUST 1996–REVISED APRIL 2005
Timing Requirements
over recommended ranges of supply voltage and operating free-air temperature for GTL (unless otherwise noted)
MIN
MAX UNIT
fclock
tw
Clock frequency
200
MHz
ns
Pulse duration, CLK high or low
2.5
2.1
3.3
0.3
0
Data before CLK↑
CE before CLK↑
Data after CLK↑
CE after CLK↑
tsu
Setup time
Hold time
ns
ns
th
Switching Characteristics
over recommended ranges of supply voltage and operating free-air temperature for GTL (see Figure 1)
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
MIN TYP(1) MAX
UNIT
fmax
tPLH
tPHL
tdis
200
MHz
2.5
2.2
1.7
2.2
5.5
5.5
4.8
5.2
CLKAB
OEAB
B
B
ns
ns
ten
Slew rate
tr
Both transitions (B port)
0.5
V/ns
ns
Transition time, B outputs (0.6 V to 1 V)
Transition time, B outputs (1 V to 0.6 V)
0.6
0.4
2.1
2.1
1.7
2.3
2.2
1.5
5.3
5
tf
ns
tPLH
tPHL
ten
CLKBA
OEBA
A
A
ns
ns
5
tdis
5.5
(1) All typical values are at VCC = 3.3 V, TA = 25°C.
6
SN74GTL16622A
18-BIT LVTTL-TO-GTL/GTL+ BUS TRANSCEIVER
www.ti.com
SCBS673F–AUGUST 1996–REVISED APRIL 2005
Timing Requirements
over recommended ranges of supply voltage and operating free-air temperature for GTL+ (unless otherwise noted)
MIN
MAX UNIT
fclock
tw
Clock frequency
200
MHz
ns
Pulse duration, CLK high or low
2.5
2.4
3.2
0.2
0
Data before CLK↑
CE before CLK↑
Data after CLK↑
CE after CLK↑
tsu
Setup time
Hold time
ns
ns
th
Switching Characteristics
over recommended ranges of supply voltage and operating free-air temperature for GTL+ (see Figure 1)
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
MIN TYP(1) MAX UNIT
fmax
tPLH
tPHL
tPLH
tPHL
Slew rate
tr
200
2.6
2.3
2.4
1.8
MHz
ns
4
4
5.6
5.7
5.2
5
CLKAB
OEAB
B
B
3.8
3.4
0.5
1.6
1.1
3.8
3.6
3.6
4
ns
Both transitions (B port)
V/ns
ns
Transition time, B outputs (0.6 V to 1.3 V)
Transition time, B outputs (1.3 V to 0.6 V)
1
0.5
2
2.7
3.2
5.3
5
tf
ns
tPLH
tPHL
ten
CLKBA
OEBA
A
A
ns
ns
1.9
1.9
2.1
5
tdis
5.5
(1) All typical values are at VCC = 3.3 V, TA = 25°C.
7
SN74GTL16622A
18-BIT LVTTL-TO-GTL/GTL+ BUS TRANSCEIVER
www.ti.com
SCBS673F–AUGUST 1996–REVISED APRIL 2005
PARAMETER MEASUREMENT INFORMATION
V
6 V
Open
GND
TT
S1
500 Ω
From Output
Under Test
TEST
/t
S1
Open
6 V
25 Ω
t
t
t
PLH PHL
From Output
Under Test
Test
Point
/t
PLZ PZL
C = 50 pF
(see Note A)
L
500 Ω
/t
GND
PHZ PZH
C = 30 pF
L
(see Note A)
LOAD CIRCUIT FOR A OUTPUTS
LOAD CIRCUIT FOR B OUTPUTS
t
w
3 V
Timing
Input
3 V
0 V
1.5 V
0 V
1.5 V
1.5 V
Input
t
su
t
h
3 V
0 V
Data Input
A Port
VOLTAGE WAVEFORMS
PULSE DURATION
1.5 V
1.5 V
V
TT
3 V
0 V
Data Input
B Port
Input
(see Note B)
V
REF
V
REF
1.5 V
1.5 V
0 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
t
t
PHL
PLH
V
V
OH
Output
V
V
REF
REF
3 V
0 V
Output
Control
(see Note B)
OL
1.5 V
1.5 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
(CLKAB to B port)
t
t
PLZ
PZL
Output
Waveform 1
S1 at 6 V
3 V
V
3 V
0 V
Input
(see Note B)
1.5 V
1.5 V
1.5 V
V
OL
+ 0.3 V
(see Note C)
OL
t
t
PZH
PHZ
t
t
PHL
PLH
Output
Waveform 2
S1 at GND
V
OH
V
V
OH
V
OH
− 0.3 V
1.5 V
1.5 V
1.5 V
Output
≈0 V
(see Note C)
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
(CLKBA to A port)
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
(OEBA to A port)
NOTES: A. C includes probe and jig capacitance.
L
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
C. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
D. The outputs are measured one at a time, with one transition per measurement.
Figure 1. Load Circuits and Voltage Waveforms
8
PACKAGE OPTION ADDENDUM
www.ti.com
20-Jul-2011
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
74GTL16622ADGGRE4
74GTL16622ADGGRG4
SN74GTL16622ADGGR
ACTIVE
ACTIVE
ACTIVE
TSSOP
TSSOP
TSSOP
DGG
DGG
DGG
64
64
64
2000
2000
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
Green (RoHS
& no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74GTL16622ADGGR TSSOP
DGG
64
2000
330.0
24.4
8.4
17.3
1.7
12.0
24.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
TSSOP DGG 64
SPQ
Length (mm) Width (mm) Height (mm)
367.0 367.0 45.0
SN74GTL16622ADGGR
2000
Pack Materials-Page 2
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
M
0,08
0,50
48
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
0,25
1
24
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
48
56
64
DIM
A MAX
12,60
12,40
14,10
13,90
17,10
16,90
A MIN
4040078/F 12/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should
obtain the latest relevant information before placing orders and should verify that such information is current and complete. All
semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time
of order acknowledgment.
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
performed.
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