SN74GTL16616DLRG4 [TI]
17-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVER WITH BUFFERED CLOCK OUTPUTS; 17位LVTTL - TO- GTL / GTL +通用总线，提供缓冲时钟输出收发器
| 型号： | SN74GTL16616DLRG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 17-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVER WITH BUFFERED CLOCK OUTPUTS |
| 文件： | 总14页 (文件大小：161K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74GTL16616
17-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVER
WITH BUFFERED CLOCK OUTPUTS
www.ti.com
SCBS481H–JUNE 1994–REVISED APRIL 2005
FEATURES
DGG OR DL PACKAGE
•
Member of the Texas Instruments Widebus™
(TOP VIEW)
Family
OEAB
LEAB
A1
GND
A2
A3
(3.3 V)
A4
CEAB
CLKAB
1
2
3
4
5
6
7
8
9
56
55
•
UBT™ Transceiver Combines D-Type Latches
and D-Type Flip-Flops for Operation in
Transparent, Latched, Clocked, or
Clock-Enabled Modes
54 B1
GND
53
52
51
50
B2
B3
V
•
OEC™ Circuitry Improves Signal Integrity and
Reduces Electromagnetic Interference
V
CC
(5 V)
CC
•
•
GTL Buffered CLKAB Signal (CLKOUT)
49 B4
48 B5
47 B6
Translates Between GTL/GTL+ Signal Levels
and LVTTL Logic Levels
A5
A6 10
•
Supports Mixed-Mode (3.3 V and 5 V) Signal
Operation on A-Port and Control Inputs
GND
A7
A8
GND
B7
B8
11
12
13
46
45
44
•
•
Equivalent to '16601 Function
A9 14
A10 15
A11 16
A12 17
43 B9
Ioff Supports Partial-Power-Down Mode
Operation
42 B10
41 B11
40 B12
•
Bus Hold on Data Inputs Eliminates the Need
for External Pullup/Pulldown Resistors on
A Port
GND
GND
18
39
A13 19
A14 20
38 B13
37 B14
36 B15
•
•
•
Distributed VCC and GND Pins Minimize
High-Speed Switching Noise
A15 21
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
V
CC
(3.3 V) 22
A16 23
35
V
REF
34 B16
ESD Protection Exceeds JESD 22
A17 24
33 B17
GND 25
CLKIN 26
OEBA 27
LEBA 28
32 GND
31 CLKOUT
30 CLKBA
29 CEBA
– 2000-V Human-Body Model (A114-A)
DESCRIPTION/ORDERING INFORMATION
The SN74GTL16616 is a 17-bit UBT™ transceiver that provides LVTTL-to-GTL/GTL+ and GTL/GTL+-to-LVTTL
signal-level translation. Combined D-type flip-flops and D-type latches allow for transparent, latched, clocked,
and clocked-enabled modes of data transfer identical to the '16601 function. Additionally, this device provides for
a copy of CLKAB at GTL/GTL+ signal levels (CLKOUT) and conversion of a GTL/GTL+ clock to LVTTL logic
levels (CLKIN). This device provides an interface between cards operating at LVTTL logic levels and a backplane
operating at GTL/GTL+ signal levels. Higher-speed operation is a direct result of the reduced output swing
(<1 V), reduced input threshold levels, and OEC™ circuitry.
ORDERING INFORMATION
TA
PACKAGE(1)
ORDERABLE PART NUMBER
SN74GTL16616DL
TOP-SIDE MARKING
GTL16616
Tube
SSOP – DL
TSSOP – DGG
–40°C to 85°C
Tape and reel
Tape and reel
SN74GTL16616DLR
GTL16616
GTL16616
SN74GTL16616DGGR
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus, UBT, OEC are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 1994–2005, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
SN74GTL16616
17-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVER
WITH BUFFERED CLOCK OUTPUTS
www.ti.com
SCBS481H–JUNE 1994–REVISED APRIL 2005
DESCRIPTION/ORDERING INFORMATION (CONTINUED)
The user has the flexibility of using this device at either GTL (VTT = 1.2 V and VREF = 0.8 V) or the preferred
higher noise margin GTL+ (VTT = 1.5 V and VREF = 1 V) signal levels. GTL+ is the Texas Instruments derivative
of the Gunning Transceiver Logic (GTL) JEDEC standard JESD 8-3. The B port normally operates at GTL or
GTL+ signal levels, while the A-port and control inputs are compatible with LVTTL logic levels and are 5-V
tolerant. VREF is the reference input voltage for the B port. VCC (5 V) supplies the internal and GTL circuitry, while
VCC (3.3 V) supplies the LVTTL output buffers.
Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA),
and clock (CLKAB and CLKBA) inputs. The clock can be controlled by the clock-enable (CEAB and CEBA)
inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is high. When LEAB is low,
the A data is latched if CEAB is low and CLKAB is held at a high or low logic level. If LEAB is low, the A-bus data
is stored in the latch/flip-flop on the low-to-high transition of CLKAB if CEAB also is low. When OEAB is low, the
outputs are active. When OEAB is high, the outputs are in the high-impedance state. Data flow for B to A is
similar to that of A to B, but uses OEBA, LEBA, CLKBA, and CEBA.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
Active bus-hold circuitry holds unused or undriven LVTTL inputs at a valid logic state. Use of pullup or pulldown
resistors with the bus-hold circuitry is not recommended.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
FUNCTION TABLE(1)
INPUTS
OUTPUT
B
MODE
Isolation
CEAB
OEAB
LEAB
CLKAB
A
X
X
X
L
X
L
H
L
L
L
L
L
L
L
X
L
X
H
L
Z
(2)
B0
Latched storage of A data
(3)
L
L
B0
X
X
L
H
H
L
X
X
↑
L
H
L
Transparent
H
L
Clocked storage of A data
Clock inhibit
L
L
↑
H
X
H
(3)
H
L
X
B0
(1) A-to-B data flow is shown. B-to-A data flow is similar, but uses OEBA, LEBA, CLKBA, and CEBA.
The condition when OEAB and OEBA are both low at the same time is not recommended.
(2) Output level before the indicated steady-state input conditions were established, provided that
CLKAB was high before LEAB went low
(3) Output level before the indicated steady-state input conditions were established
2
SN74GTL16616
17-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVER
WITH BUFFERED CLOCK OUTPUTS
www.ti.com
SCBS481H–JUNE 1994–REVISED APRIL 2005
LOGIC DIAGRAM (POSITIVE LOGIC)
35
V
REF
1
OEAB
CEAB
56
55
2
CLKAB
LEAB
28
30
29
27
LEBA
CLKBA
CEBA
OEBA
CE
3
A1
1D
C1
54
B1
CLK
CE
1D
C1
CLK
1 of 17 Channels
31
CLKOUT
26
CLKIN
3
SN74GTL16616
17-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVER
WITH BUFFERED CLOCK OUTPUTS
www.ti.com
SCBS481H–JUNE 1994–REVISED APRIL 2005
Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
MIN
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
MAX UNIT
3.3 V
4.6
V
VCC
Supply voltage range
5 V
7
A-port and control inputs
7
VI
Input voltage range(2)
V
B port and VREF
A port
4.6
7
VO
Voltage range applied to any output in the high or power-off state(2)
V
B port
4.6
A port
128
mA
80
IO
IO
Current into any output in the low state
B port
Current into any A-port output in the high state(3)
Continuous current through each VCC or GND
Input clamp current
64
±100
–50
–50
64
mA
mA
mA
mA
IIK
VI < 0
IOK
Output clamp current
VO < 0
DGG package
DL package
θJA
Package thermal impedance(4)
Storage temperature range
°C/W
°C
56
Tstg
–65
150
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
(3) This current flows only when the output is in the high state and VO > VCC
.
(4) The package thermal impedance is calculated in accordance with JESD 51-7.
Recommended Operating Conditions(1)(2)(3)(4)
MIN
3.15
4.75
1.14
1.35
0.74
0.87
NOM
3.3
5
MAX
3.45
5.25
1.26
1.65
0.87
1.1
UNIT
3.3 V
VCC
VTT
VREF
VI
Supply voltage
V
5 V
GTL
1.2
1.5
0.8
1
Termination voltage
Reference voltage
Input voltage
V
V
V
V
V
GTL+
GTL
GTL+
B port
VTT
Except B port
B port
5.5
VREF + 50 mV
2
VIH
VIL
High-level input voltage
Low-level input voltage
Except B port
B port
VREF – 50 mV
Except B port
0.8
–18
–32
64
IIK
Input clamp current
mA
mA
IOH
High-level output current
A port
A port
B port
IOL
TA
Low-level output current
mA
°C
40
Operating free-air temperature
–40
85
(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
(2) Normal connection sequence is GND first, VCC = 5 V second, and VCC = 3.3 V, I/O, control inputs, VTT and VREF (any order) last.
(3) VTT and RTT can be adjusted to accommodate backplane impedances if the dc recommended IOL ratings are not exceeded.
(4) VREF can be adjusted to optimize noise margins, but normally is two-thirds VTT
.
4
SN74GTL16616
17-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVER
WITH BUFFERED CLOCK OUTPUTS
www.ti.com
SCBS481H–JUNE 1994–REVISED APRIL 2005
Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP(1) MAX UNIT
VIK
VCC (3.3 V) = 3.15 V,
VCC (5 V) = 4.75 V,
II = –18 mA
–1.2
V
VCC (3.3 V) = 3.15 V to 3.45 V,
VCC (5 V) = 4.75 V to 5.25 V,
IOH = –100 µA
VCC – 0.2
VOH
A port
V
IOH = –8 mA
IOH = –32 mA
IOL = 100 µA
IOL = 16 mA
IOL = 32 mA
IOL = 64 mA
IOL = 40 mA
2.4
2
VCC (3.3 V) = 3.15 V,
VCC (5 V) = 4.75 V
0.2
0.4
0.5
0.55
0.4
10
A port
B port
VCC (3.3 V) = 3.15 V,
VCC (3.3 V) = 3.15 V,
VCC (5 V) = 4.75 V
VCC (5 V) = 4.75 V,
VOL
V
Control inputs VCC = 0 or 3.45 V,
VCC (5 V) = 0 or 5.25 V, VI = 5.5 V
VI = 5.5 V
20
A port
B port
VCC (3.3 V) = 3.45 V,
VCC (5 V) = 5.25 V
VI = VCC (3.3 V)
1
II
µA
VI = 0
–30
5
VI = VCC (3.3 V)
VI = 0
VCC (3.3 V) = 3.45 V,
VCC = 0,
VCC (5 V) = 5.25 V
–5
Ioff
VI or VO = 0 to 4.5 V
100 µA
VI = 0.8 V
75
II(hold)
A port
VCC (3.3 V) = 3.15 V,
VCC (5 V) = 4.75 V
VI = 2 V
–75
µA
VI = 0 to VCC (3.3 V)(2)
±500
A port
B port
A port
B port
VCC (3.3 V) = 3.45 V,
VCC (3.3 V) = 3.45 V,
VCC (3.3 V) = 3.45 V,
VCC (3.3 V) = 3.45 V,
VCC (5 V) = 5.25 V,
VCC (5 V) = 5.25 V,
VCC (5 V) = 5.25 V,
VCC (5 V) = 5.25 V,
VO = 3 V
1
µA
10
IOZH
VO = 1.2 V
VO = 0.5 V
–1
µA
IOZL
VO = 0.4 V
–10
Outputs high
Outputs low
Outputs disabled
Outputs high
Outputs low
Outputs disabled
1
VCC (3.3 V) = 3.45 V,
VCC (5 V) = 5.25 V, IO = 0,
VI = VCC (3.3 V) or GND
ICC
(3.3 V)
A or B port
A or B port
5
1
mA
120
VCC (3.3 V) = 3.45 V,
VCC (5 V) = 5.25 V, IO = 0,
VI = VCC (3.3 V) or GND
ICC
(5 V)
120 mA
120
VCC (3.3 V) = 3.45 V, VCC (5 V) = 5.25 V,
A-port or control inputs at VCC (3.3 V) or GND, One input at 2.7 V
(3)
∆ICC
1
mA
pF
Ci
Control inputs VI = 3.15 V or 0
3.5
12
A port
B port
VO = 3.15 V or 0
Cio
pF
Per IEEE Std 1194.1
5
(1) All typical values are at VCC (3.3 V) = 3.3 V, VCC (5 V) = 5 V, TA = 25°C.
(2) This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to
another.
(3) This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND.
5
SN74GTL16616
17-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVER
WITH BUFFERED CLOCK OUTPUTS
www.ti.com
SCBS481H–JUNE 1994–REVISED APRIL 2005
Timing Requirements
over recommended ranges of supply voltage and operating free-air temperature,
VTT = 1.2 V and VREF = 0.8 V for GTL (unless otherwise noted) (see Figure 1)
MIN
MAX UNIT
fclock
tw
Clock frequency
Pulse duration
95
MHz
LEAB or LEBA high
CLKAB or CLKBA high or low
A before CLKAB↑
B before CLKBA↑
A before LEAB↓
3.3
5.5
1.3
2.5
0
ns
tsu
Setup time
ns
ns
B before LEBA↓
1.1
2.2
2.7
1.6
0.4
4
CEAB before CLKAB↑
CEBA before CLKBA↑
A after CLKAB↑
B after CLKBA↑
A after LEAB↓
th
Hold time
B after LEBA↓
3.5
1.1
0.9
CEAB after CLKAB↑
CEBA after CLKBA↑
6
SN74GTL16616
17-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVER
WITH BUFFERED CLOCK OUTPUTS
www.ti.com
SCBS481H–JUNE 1994–REVISED APRIL 2005
Switching Characteristics
over recommended ranges of supply voltage and operating free-air temperature,
VTT = 1.2 V and VREF = 0.8 V for GTL (see Figure 1)
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
MIN TYP(1)
MAX
UNIT
fmax
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPHL
tPLH
tr
95
MHz
1.7
1.4
2.3
2.2
2.4
2.1
4.7
5.7
2.1
2.1
3
2.8
3.8
3.7
4
4.4
4.5
5.4
5.3
5.7
5.4
8.1
11.3
5.1
5.6
A
B
ns
ns
ns
ns
ns
LEAB
CLKAB
CLKAB
OEAB
B
B
3.7
6.1
7.9
3.6
3.8
1.2
0.7
4
CLKOUT
B or CLKOUT
Transition time, B outputs (0.5 V to 1 V)
Transition time, B outputs (1 V to 0.5 V)
ns
ns
tf
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
ten
1.7
1.4
2.4
2
6.7
4.7
5.8
4.6
6
B
A
ns
ns
ns
ns
ns
2.9
3.8
3
LEBA
A
A
2.6
2.2
7.4
6.1
2.8
2.7
4
CLKBA
CLKOUT
OEBA
3.4
10
4.9
14.4
11.7
7.8
6.4
CLKIN
A or CLKIN
8.1
5.3
4.3
tdis
(1) All typical values are at VCC (3.3 V) = 3.3 V, VCC (5 V) = 5 V, TA = 25°C.
7
SN74GTL16616
17-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVER
WITH BUFFERED CLOCK OUTPUTS
www.ti.com
SCBS481H–JUNE 1994–REVISED APRIL 2005
Timing Requirements
over recommended ranges of supply voltage and operating free-air temperature,
VTT = 1.5 V and VREF = 1 V for GTL+ (unless otherwise noted) (see Figure 1)
MIN
MAX
95
UNIT
fclock
tw
Clock frequency
Pulse duration
MHz
LEAB or LEBA high
CLKAB or CLKBA high or low
A before CLKAB↑
B before CLKBA↑
A before LEAB↓
3.3
5.5
1.3
2.3
0
ns
tsu
Setup time
ns
ns
B before LEBA↓
1.3
2.2
2.7
1.6
0.6
4
CEAB before CLKAB↑
CEBA before CLKBA↑
A after CLKAB↑
B after CLKBA↑
A after LEAB↓
th
Hold time
B after LEBA↓
3.5
1.1
0.9
CEAB after CLKAB↑
CEBA after CLKBA↑
8
SN74GTL16616
17-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVER
WITH BUFFERED CLOCK OUTPUTS
www.ti.com
SCBS481H–JUNE 1994–REVISED APRIL 2005
Switching Characteristics
over recommended ranges of supply voltage and operating free-air temperature,
VTT = 1.5 V and VREF = 1 V for GTL+ (see Figure 1)
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
MIN TYP(1)
MAX UNIT
fmax
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tr
95
MHz
1.7
1.4
2.3
2.2
2.4
2.1
4.7
5.7
2.1
2.1
3
2.9
3.8
3.7
4
4.4
ns
A
B
4.6
5.4
ns
LEAB
CLKAB
CLKAB
OEAB
B
B
5.4
5.7
ns
3.8
6.1
8
5.5
8.1
ns
CLKOUT
B or CLKOUT
11.4
3.6
3.8
1.4
1
5.1
ns
5.7
Transition time, B outputs (0.5 V to 1 V)
Transition time, B outputs (1 V to 0.5 V)
ns
ns
tf
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
ten
1.6
1.3
2.4
2
3.9
2.8
3.8
3
6.6
ns
B
A
4.5
5.8
ns
LEBA
A
A
4.6
2.6
2.2
7.3
6
4
6
ns
CLKBA
CLKOUT
OEBA
3.4
9.9
8
4.9
14.3
ns
CLKIN
A or CLKIN
11.5
2.8
2.7
5.3
4.3
7.8
ns
tdis
6.4
(1) All typical values are at VCC (3.3 V) = 3.3 V, VCC (5 V) = 5 V, TA = 25°C.
9
SN74GTL16616
17-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVER
WITH BUFFERED CLOCK OUTPUTS
www.ti.com
SCBS481H–JUNE 1994–REVISED APRIL 2005
PARAMETER MEASUREMENT INFORMATION
VTT = 1.2 V, VREF = 0.8 V FOR GTL AND VTT = 1.5 V, VREF = 1 V FOR GTL+
V
6 V
S1
TT
Open
500 Ω
From Output
Under Test
TEST
/t
S1
Open
6 V
25 Ω
GND
t
t
t
PLH PHL
From Output
Under Test
Test
Point
/t
PLZ PZL
C = 50 pF
(see Note A)
L
500 Ω
/t
GND
PHZ PZH
C = 30 pF
L
(see Note A)
LOAD CIRCUIT FOR A OUTPUTS
LOAD CIRCUIT FOR B OUTPUTS
t
w
3 V
Timing
Input
3 V
0 V
1.5 V
0 V
V
M
V
V V
M
Input
t
su
t
h
3 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
Data Input
A Port
1.5 V
1.5 V
†
(V = 1.5 V for A port and V
for B port)
M
REF
V
TT
Data Input
B Port
3 V
0 V
V
V
REF
Input
(see Note B)
REF
1.5 V
1.5 V
0 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
t
t
PHL
PLH
V
V
TT
3 V
0 V
Output
V
V
REF
REF
Output
Control
(see Note B)
1.5 V
1.5 V
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
†
t
t
PLZ
(A port to B port)
PZL
Output
Waveform 1
S1 at 6 V
3 V
V
V
TT
Input
(see Note B)
1.5 V
V
REF
V
REF
V
OL
+ 0.3 V
(see Note C)
OL
0 V
t
t
PZH
PHZ
t
t
PHL
PLH
Output
Waveform 2
S1 at GND
V
OH
V
V
OH
V
OH
− 0.3 V
1.5 V
1.5 V
1.5 V
Output
≈0 V
(see Note C)
OL
VOLTAGE WAVEFORMS
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
(B port to A port)
ENABLE AND DISABLE TIMES
(A port and CLKIN)
†
All control inputs are TTL levels.
NOTES: A. C includes probe and jig capacitance.
L
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
C. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
D. The outputs are measured one at a time, with one transition per measurement.
Figure 1. Load Circuits and Voltage Waveforms
10
PACKAGE OPTION ADDENDUM
www.ti.com
18-Jul-2006
PACKAGING INFORMATION
Orderable Device
74GTL16616DGGRE4
SN74GTL16616DGGR
SN74GTL16616DL
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
TSSOP
DGG
56
56
56
56
56
56
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TSSOP
SSOP
SSOP
SSOP
SSOP
DGG
DL
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
20 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74GTL16616DLG4
SN74GTL16616DLR
SN74GTL16616DLRG4
DL
20 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
DL
1000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
DL
1000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001
DL (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0.025 (0,635)
48
0.0135 (0,343)
0.008 (0,203)
0.005 (0,13)
M
25
0.010 (0,25)
0.005 (0,13)
0.299 (7,59)
0.291 (7,39)
0.420 (10,67)
0.395 (10,03)
Gage Plane
0.010 (0,25)
0°–ā8°
1
24
0.040 (1,02)
0.020 (0,51)
A
Seating Plane
0.004 (0,10)
0.008 (0,20) MIN
PINS **
0.110 (2,79) MAX
28
48
0.630
56
DIM
0.380
(9,65)
0.730
A MAX
A MIN
(16,00) (18,54)
0.370
(9,40)
0.620
0.720
(15,75) (18,29)
4040048/E 12/01
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
D. Falls within JEDEC MO-118
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
M
0,08
0,50
48
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
0,25
1
24
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
48
56
64
DIM
A MAX
12,60
12,40
14,10
13,90
17,10
16,90
A MIN
4040078/F 12/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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相关型号：
SN74GTL16622ADGGE4
GTL/TVC SERIES, DUAL 9-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO64, PLASTIC, TSSOP-64
TI
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