SN54LVTH162244-SP [TI]
具有总线保持、TTL 兼容型 CMOS 输入和三态输出的航天类 16 通道、2.7V 至 3.6V 缓冲器;型号: | SN54LVTH162244-SP |
厂家: | TEXAS INSTRUMENTS |
描述: | 具有总线保持、TTL 兼容型 CMOS 输入和三态输出的航天类 16 通道、2.7V 至 3.6V 缓冲器 驱动 总线驱动器 总线收发器 |
文件: | 总15页 (文件大小:476K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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SCBS258M − JUNE 1993 − REVISED SEPTEMBER 2003
SN54LVTH162244 . . . WD PACKAGE
SN74LVTH162244 . . . DGG OR DL PACKAGE
(TOP VIEW)
D
D
Members of the Texas Instruments
Widebus Family
Output Ports Have Equivalent 22-Ω Series
Resistors, So No External Resistors Are
Required
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
2OE
1A1
1A2
GND
1A3
1A4
1OE
1Y1
1Y2
GND
1Y3
1Y4
2
D
Support Mixed-Mode Signal Operation
(5-V Input and Output Voltages With
3
4
3.3-V V
)
5
CC
6
D
D
D
D
Support Unregulated Battery Operation
Down to 2.7 V
7
V
V
CC
CC
8
2A1
2A2
GND
2A3
2A4
3A1
3A2
GND
3A3
3A4
2Y1
2Y2
GND
2Y3
2Y4
3Y1
3Y2
GND
3Y3
3Y4
Typical V
<0.8 V at V
(Output Ground Bounce)
OLP
CC
9
= 3.3 V, T = 25°C
A
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
I
and Power-Up 3-State Support Hot
off
Insertion
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
D
D
D
D
Distributed V
High-Speed Switching Noise
and GND Pins Minimize
CC
Flow-Through Architecture Optimizes PCB
Layout
V
V
CC
CC
4A1
4A2
GND
4A3
4A4
3OE
4Y1
4Y2
GND
4Y3
4Y4
Latch-Up Performance Exceeds 500 mA Per
JESD 17
ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
4OE
description/ordering information
The ’LVTH162244 devices are 16-bit buffers and line drivers designed for low-voltage (3.3-V) V
operation,
CC
but with the capability to provide a TTL interface to a 5-V system environment. These devices can be used as
four 4-bit buffers, two 8-bit buffers, or one 16-bit buffer. These devices provide true outputs and symmetrical
active-low output-enable (OE) inputs.
ORDERING INFORMATION
ORDERABLE
†
T
PACKAGE
TOP-SIDE MARKING
A
PART NUMBER
SN74LVTH162244DL
SN74LVTH162244DLR
SN74LVTH162244DGGR
SN74LVTH162244KR
74LVTH162244ZQLR
SNJ54LVTH162244WD
Tube
SSOP − DL
LVTH162244
LVTH162244
Tape and reel
Tape and reel
TSSOP − DGG
VFBGA − GQL
VFBGA − ZQL (Pb-free)
CFP − WD
−40°C to 85°C
−55°C to 125°C
Tape and reel
Tube
LL2244
SNJ54LVTH162244WD
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments.
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Copyright 2003, Texas Instruments Incorporated
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄꢅꢆ ꢇ ꢈ ꢉ ꢊꢊ ꢃꢃ ꢋ ꢀ ꢁꢌ ꢃ ꢄꢅ ꢆꢇ ꢈꢉ ꢊ ꢊ ꢃ ꢃ
ꢍꢎ ꢍꢏꢅ ꢐ ꢑꢆ ꢈ ꢉꢏ ꢑꢒ ꢆ ꢑꢓ ꢔꢔ ꢕꢖ ꢀꢗ ꢘ ꢖꢒ ꢅ ꢕꢖ ꢀ
ꢙꢒ ꢆ ꢇ ꢍ ꢏꢀꢆꢐꢆ ꢕ ꢚꢓꢆ ꢛ ꢓꢆꢀ
SCBS258M − JUNE 1993 − REVISED SEPTEMBER 2003
description/ordering information (continued)
The outputs, which are designed to source or sink up to 12 mA, include equivalent 22-Ω series resistors to
reduce overshoot and undershoot.
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors
with the bus-hold circuitry is not recommended.
When V
is between 0 and 1.5 V, the devices are in the high-impedance state during power up or power down.
CC
However, to ensure the high-impedance state above 1.5 V, OE should be tied to V
the minimum value of the resistor is determined by the current-sinking capability of the driver.
through a pullup resistor;
CC
These devices are fully specified for hot-insertion applications using I and power-up 3-state. The I circuitry
off
off
disables the outputs, preventing damaging current backflow through the devices when they are powered down.
The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,
which prevents driver conflict.
GQL OR ZQL PACKAGE
(TOP VIEW)
terminal assignments
1
2
3
4
5
6
1
2
3
4
5
6
A
B
C
D
A
B
C
D
E
F
1OE
1Y2
1Y4
2Y2
2Y4
3Y1
3Y3
4Y1
4Y3
4OE
NC
NC
NC
NC
2OE
1A2
1A4
2A2
2A4
3A1
3A3
4A1
4A3
3OE
1Y1
1Y3
2Y1
2Y3
3Y2
3Y4
4Y2
4Y4
NC
GND
GND
1A1
1A3
2A1
2A3
3A2
3A4
4A2
4A4
NC
V
CC
V
CC
GND
GND
E
F
G
H
J
GND
GND
G
H
J
V
CC
V
CC
GND
NC
GND
NC
K
K
NC − No internal connection
FUNCTION TABLE
(each 4-bit buffer)
INPUTS
OUTPUT
Y
OE
L
A
H
L
H
L
L
H
X
Z
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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SCBS258M − JUNE 1993 − REVISED SEPTEMBER 2003
logic diagram (positive logic)
1
25
36
1OE
3OE
3A1
47
2
3
5
6
13
1A1
1Y1
1Y2
1Y3
1Y4
3Y1
46
35
33
32
14
1A2
3A2
3A3
3A4
3Y2
44
16
1A3
3Y3
43
17
1A4
3Y4
48
24
30
2OE
4OE
4A1
41
8
9
19
2A1
2Y1
2Y2
2Y3
2Y4
4Y1
40
29
27
26
20
2A2
4A2
4A3
4A4
4Y2
38
11
12
22
2A3
4Y3
37
23
2A4
4Y4
Pin numbers shown are for the DGG, DL, and WD packages.
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
I
Voltage range applied to any output in the high-impedance
or power-off state, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
O
Voltage range applied to any output in the high state, V (see Note 1) . . . . . . . . . . . . . −0.5 V to V
+ 0.5 V
O
CC
Current into any output in the low state, I
Current into any output in the high state, I (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 mA
O
O
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
IK
OK
I
Output clamp current, I
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
O
Package thermal impedance, θ (see Note 3): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W
JA
DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63°C/W
GQL/ZQL package . . . . . . . . . . . . . . . . . . . . . . . . . . . 42°C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Storage temperature range, T
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This current flows only when the output is in the high state and V > V
.
CC
O
3. The package thermal impedance is calculated in accordance with JESD 51-7.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄꢅꢆ ꢇ ꢈ ꢉ ꢊꢊ ꢃꢃ ꢋ ꢀ ꢁꢌ ꢃ ꢄꢅ ꢆꢇ ꢈꢉ ꢊ ꢊ ꢃ ꢃ
ꢍꢎ ꢍꢏꢅ ꢐ ꢑꢆ ꢈ ꢉꢏ ꢑꢒ ꢆ ꢑꢓ ꢔꢔ ꢕꢖ ꢀꢗ ꢘ ꢖꢒ ꢅ ꢕꢖ ꢀ
ꢙꢒ ꢆ ꢇ ꢍ ꢏꢀꢆꢐꢆ ꢕ ꢚꢓꢆ ꢛ ꢓꢆꢀ
SCBS258M − JUNE 1993 − REVISED SEPTEMBER 2003
recommended operating conditions (see Note 4)
SN54LVTH162244 SN74LVTH162244
UNIT
MIN
2.7
2
MAX
MIN
2.7
2
MAX
V
V
V
V
Supply voltage
3.6
3.6
V
V
CC
High-level input voltage
Low-level input voltage
Input voltage
IH
0.8
5.5
−12
12
0.8
5.5
−12
12
V
IL
V
I
I
I
High-level output current
Low-level output current
Input transition rise or fall rate
Power-up ramp rate
mA
mA
ns/V
µs/V
°C
OH
OL
∆t/∆v
∆t/∆V
Outputs enabled
10
10
200
−55
200
−40
CC
T
A
Operating free-air temperature
125
85
NOTE 4: All unused control inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54LVTH162244
SN74LVTH162244
PARAMETER
TEST CONDITIONS
I = −18 mA
UNIT
†
†
MIN TYP
MAX
MIN TYP
MAX
V
V
V
V
V
V
V
V
= 2.7 V,
= 3 V,
−1.2
−1.2
V
V
V
IK
CC
CC
CC
CC
CC
I
I
I
= −12 mA
= 12 mA
2
2
OH
OL
OH
= 3 V,
0.8
10
1
0.8
10
1
OL
= 0 or 3.6 V,
= 3.6 V,
V = 5.5 V
I
Control inputs
Data inputs
V = V
or GND
I
CC
CC
I
I
I
µA
µA
µA
I
V = V
1
1
I
V
= 3.6 V
= 0,
CC
CC
V = 0
I
−5
−5
100
V
V or V = 0 to 4.5 V
off
I
O
V = 0.8 V
I
75
75
V
V
= 3 V
CC
V = 2 V
I
−75
−75
Data inputs
I(hold)
500
−750
‡
= 3.6 V ,
V = 0 to 3.6 V
I
CC
I
I
V
V
V
= 3.6 V,
= 3.6 V,
V
V
= 3 V
5
5
µA
µA
OZH
CC
CC
CC
O
= 0.5 V
−5
−5
OZL
O
= 0 to 1.5 V, V = 0.5 V to 3 V,
O
100*
100*
100
100
µA
µA
I
OZPU
OZPD
OE = don’t care
V
= 1.5 V to 0, V = 0.5 V to 3 V,
CC
OE = don’t care
O
I
Outputs high
Outputs low
0.19
5
0.19
5
V
I
= 3.6 V,
CC
= 0,
I
mA
mA
O
CC
V = V
I
or GND
CC
Outputs disabled
0.19
0.19
V
= 3 V to 3.6 V, One input at V − 0.6 V,
CC
CC
Other inputs at V
§
0.2
0.2
∆I
CC
or GND
CC
C
C
V = 3 V or 0
4
9
4
9
pF
pF
i
I
V
O
= 3 V or 0
o
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
†
All typical values are at V
= 3.3 V, T = 25°C.
A
CC
‡
§
This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another.
This is the increase in supply current for each input that is at the specified TTL voltage level, rather than V
or GND.
CC
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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SCBS258M − JUNE 1993 − REVISED SEPTEMBER 2003
switching characteristics over recommended operating free-air temperature range, C = 50 pF
L
(unless otherwise noted) (see Figure 1)
SN54LVTH162244
= 3.3 V
SN74LVTH162244
V
V
= 3.3 V
V
FROM
(INPUT)
TO
(OUTPUT)
CC
CC
V
CC
= 2.7 V
= 2.7 V
PARAMETER
UNIT
CC
MIN
0.3 V
0.3 V
†
MIN
1.1
1.1
1.1
1.3
1.6
1
MAX
4.6
3.9
5.4
4.9
5.9
5.9
MIN
MAX
5.1
4.5
6.7
6.1
6.5
5.8
MIN TYP
MAX
4
MAX
4.8
4.1
6.5
5.8
5.4
5.4
t
t
t
t
t
t
t
1.4
1.2
1.2
1.4
2.2
2
3.4
2.9
3.9
3.8
4.4
4.2
PLH
PHL
PZH
PZL
PHZ
PLZ
sk(o)
A
Y
Y
Y
ns
ns
3.6
5.1
4.5
5
OE
OE
ns
ns
5
0.5
†
All typical values are at V
CC
= 3.3 V, T = 25°C.
A
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄꢅꢆ ꢇ ꢈ ꢉ ꢊꢊ ꢃꢃ ꢋ ꢀ ꢁꢌ ꢃ ꢄꢅ ꢆꢇ ꢈꢉ ꢊ ꢊ ꢃ ꢃ
ꢍꢎ ꢍꢏꢅ ꢐ ꢑꢆ ꢈ ꢉꢏ ꢑꢒ ꢆ ꢑꢓ ꢔꢔ ꢕꢖ ꢀꢗ ꢘ ꢖꢒ ꢅ ꢕꢖ ꢀ
ꢙꢒ ꢆ ꢇ ꢍ ꢏꢀꢆꢐꢆ ꢕ ꢚꢓꢆ ꢛ ꢓꢆꢀ
SCBS258M − JUNE 1993 − REVISED SEPTEMBER 2003
PARAMETER MEASUREMENT INFORMATION
6 V
S1
Open
GND
500 Ω
TEST
/t
S1
From Output
Under Test
t
Open
6 V
PLH PHL
t
/t
PLZ PZL
C
= 50 pF
L
500 Ω
t
/t
GND
(see Note A)
PHZ PZH
2.7 V
0 V
LOAD CIRCUIT
Timing Input
Data Input
1.5 V
t
w
t
t
h
su
2.7 V
0 V
2.7 V
0 V
Input
1.5 V
1.5 V
1.5 V
1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
2.7 V
0 V
2.7 V
0 V
Output
Control
Input
1.5 V
1.5 V
1.5 V
1.5 V
t
t
PLZ
PZL
t
t
t
PHL
PLH
Output
Waveform 1
S1 at 6 V
V
V
3 V
OH
Output
1.5 V
1.5 V
1.5 V
1.5 V
t
V
+ 0.3 V
OL
V
OL
(see Note B)
OL
t
t
PZH
PHZ
PHL
PLH
Output
Waveform 2
S1 at GND
V
V
V
OH
OH
V
− 0.3 V
OH
1.5 V
1.5 V
Output
≈ 0 V
(see Note B)
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A.
C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
4-Oct-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
5962-9680901QXA
5962-9680901VXA
ACTIVE
ACTIVE
ACTIVE
CFP
WD
48
48
48
1
1
TBD
TBD
Call TI
Call TI
Level-NC-NC-NC
Level-NC-NC-NC
CFP
WD
74LVTH162244DGGRG4
TSSOP
DGG
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
74LVTH162244DLRG4
ACTIVE
SSOP
DL
48
1000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
74LVTH162244GRDR
74LVTH162244GRE4
ACTIVE
ACTIVE
LFBGA
TSSOP
GRD
DGG
54
48
1000
TBD
SNPB
Level-1-240C-UNLIM
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
74LVTH162244ZQLR
74LVTH162244ZRDR
SN74LVTH162244DGGR
SN74LVTH162244DL
SN74LVTH162244DLG4
SN74LVTH162244DLR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
VFBGA
LFBGA
TSSOP
SSOP
ZQL
ZRD
DGG
DL
56
54
48
48
48
48
1000 Green (RoHS &
no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
1000 Green (RoHS &
no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SSOP
DL
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SSOP
DL
1000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LVTH162244KR
SNJ54LVTH162244WD
ACTIVE
ACTIVE
VFBGA
CFP
GQL
WD
56
48
1000
1
TBD
TBD
SNPB
Call TI
Level-1-240C-UNLIM
Level-NC-NC-NC
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MCFP010B – JANUARY 1995 – REVISED NOVEMBER 1997
WD (R-GDFP-F**)
CERAMIC DUAL FLATPACK
48 LEADS SHOWN
0.120 (3,05)
0.075 (1,91)
0.009 (0,23)
0.004 (0,10)
1.130 (28,70)
0.870 (22,10)
0.370 (9,40)
0.250 (6,35)
0.390 (9,91)
0.370 (9,40)
0.370 (9,40)
0.250 (6,35)
1
48
0.025 (0,635)
A
0.014 (0,36)
0.008 (0,20)
24
25
NO. OF
LEADS**
48
56
0.740
0.640
(16,26) (18,80)
A MAX
A MIN
0.610 0.710
(15,49) (18,03)
4040176/D 10/97
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Index point is provided on cap for terminal identification only
E. Falls within MIL STD 1835: GDFP1-F48 and JEDEC MO-146AA
GDFP1-F56 and JEDEC MO-146AB
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001
DL (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0.025 (0,635)
48
0.0135 (0,343)
0.008 (0,203)
0.005 (0,13)
M
25
0.010 (0,25)
0.005 (0,13)
0.299 (7,59)
0.291 (7,39)
0.420 (10,67)
0.395 (10,03)
Gage Plane
0.010 (0,25)
0°–ā8°
1
24
0.040 (1,02)
0.020 (0,51)
A
Seating Plane
0.004 (0,10)
0.008 (0,20) MIN
PINS **
0.110 (2,79) MAX
28
48
0.630
56
DIM
0.380
(9,65)
0.730
A MAX
A MIN
(16,00) (18,54)
0.370
(9,40)
0.620
0.720
(15,75) (18,29)
4040048/E 12/01
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
D. Falls within JEDEC MO-118
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
M
0,08
0,50
48
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
0,25
1
24
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
48
56
64
DIM
A MAX
12,60
12,40
14,10
13,90
17,10
16,90
A MIN
4040078/F 12/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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相关型号:
SN54LVTH162245WDR
LVT SERIES, DUAL 8-BIT TRANSCEIVER, TRUE OUTPUT, CDFP48, 0.380 INCH, FINE PITCH, CERAMIC, FP-48
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