SN54LVTH162373 [TI]
3.3-V ABT 16-BIT TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS; 3.3 -V ABT 16位透明D类锁存器三态输出
| 型号： | SN54LVTH162373 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 3.3-V ABT 16-BIT TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS |
| 文件： | 总8页 (文件大小：106K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN54LVTH162373, SN74LVTH162373
3.3-V ABT 16-BIT TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS261J – JULY 1993 – REVISED APRIL 1999
SN54LVTH162373 . . . WD PACKAGE
SN74LVTH162373 . . . DGG OR DL PACKAGE
(TOP VIEW)
Members of the Texas Instruments
Widebus Family
State-of-the-Art Advanced BiCMOS
Technology (ABT) Design for 3.3-V
Operation and Low Static-Power
Dissipation
1OE
1Q1
1Q2
GND
1Q3
1Q4
1LE
1D1
1D2
GND
1D3
1D4
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
2
3
Output Ports Have Equivalent 22-Ω Series
Resistors, So No External Resistors Are
Required
4
5
6
Support Mixed-Mode Signal Operation
(5-V Input and Output Voltages With
V
V
7
CC
CC
1Q5
1Q6
GND
1Q7
1Q8
2Q1
2Q2
GND
2Q3
2Q4
1D5
1D6
GND
1D7
1D8
2D1
2D2
GND
2D3
2D4
8
3.3-V V
)
9
CC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Support Unregulated Battery Operation
Down to 2.7 V
Typical V
< 0.8 V at V
(Output Ground Bounce)
OLP
= 3.3 V, T = 25°C
CC
A
I
and Power-Up 3-State Support Hot
off
Insertion
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
V
V
CC
CC
2Q5
2Q6
GND
2Q7
2Q8
2OE
2D5
2D6
GND
2D7
2D8
2LE
Distributed V
Minimizes High-Speed Switching Noise
and GND Pin Configuration
CC
Flow-Through Architecture Optimizes PCB
Layout
Latch-Up Performance Exceeds 500 mA Per
JESD 17
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
Package Options Include Plastic Shrink
Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages and 380-mil
Fine-Pitch Ceramic Flat (WD) Package
Using 25-mil Center-to-Center Spacings
description
The ’LVTH162373 devices are16-bit transparent D-type latches with 3-state outputs designed for low-voltage
(3.3-V) V operation, but with the capability to provide a TTL interface to a 5-V system environment. These
CC
devices are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and
working registers.
These devices can be used as two 8-bit latches or one 16-bit latch. When the latch-enable (LE) input is high,
the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels set up
at the D inputs.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments Incorporated.
Copyright 1999, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LVTH162373, SN74LVTH162373
3.3-V ABT 16-BIT TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS261J – JULY 1993 – REVISED APRIL 1999
description (continued)
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high
or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive
the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus
lines without interface or pullup components.
OE does not affect internal operations of the latch. Old data can be retained or new data can be entered while
the outputs are in the high-impedance state.
The outputs, which are designed to source or sink up to 12 mA, include equivalent 22-Ω series resistors to
reduce overshoot and undershoot.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
When V is between 0 and 1.5 V, the devices are in the high-impedance state during power up or power down.
CC
However, to ensure the high-impedance state above 1.5 V, OE should be tied to V
through a pullup resistor;
CC
the minimum value of the resistor is determined by the current-sinking capability of the driver.
These devices are fully specified for hot-insertion applications using I and power-up 3-state. The I circuitry
off
off
disables the outputs, preventing damaging current backflow through the devices when they are powered down.
The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,
which prevents driver conflict.
TheSN54LVTH162373ischaracterizedforoperationoverthefullmilitarytemperaturerangeof–55°Cto125°C.
The SN74LVTH162373 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
(each 8-bit section)
INPUTS
OUTPUT
Q
LE
H
H
L
D
H
L
OE
L
H
L
L
L
X
X
Q
0
H
X
Z
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LVTH162373, SN74LVTH162373
3.3-V ABT 16-BIT TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS261J – JULY 1993 – REVISED APRIL 1999
†
logic symbol
1
1OE
1LE
2OE
2LE
1EN
C3
48
24
25
2EN
C4
47
46
44
43
41
40
38
37
36
35
33
32
30
29
27
26
2
1D1
1D2
1D3
1D4
1D5
1D6
1D7
1D8
2D1
2D2
2D3
2D4
2D5
2D6
2D7
2D8
3D
1
1Q1
1Q2
1Q3
1Q4
1Q5
1Q6
1Q7
1Q8
2Q1
2Q2
2Q3
2Q4
2Q5
2Q6
2Q7
2Q8
3
5
6
8
9
11
12
13
14
16
17
19
20
22
23
4D
2
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
logic diagram (positive logic)
1
24
25
2OE
2LE
1OE
48
1LE
C1
1D
C1
2
13
2Q1
1Q1
47
36
2D1
1D1
1D
To Seven Other Channels
To Seven Other Channels
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LVTH162373, SN74LVTH162373
3.3-V ABT 16-BIT TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS261J – JULY 1993 – REVISED APRIL 1999
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
I
Voltage range applied to any output in the high-impedance
or power-off state, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
O
Voltage range applied to any output in the high state, V (see Note 1) . . . . . . . . . . . . . –0.5 V to V
+ 0.5 V
O
CC
Current into any output in the low state, I
Current into any output in the high state, I (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 mA
O
O
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
IK
OK
I
Output clamp current, I
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
O
Package thermal impedance, θ (see Note 3): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89°C/W
JA
DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This current flows only when the output is in the high state and V > V
.
CC
O
3. The package thermal impedance is calculated in accordance with JESD 51.
recommended operating conditions (see Note 4)
SN54LVTH162373 SN74LVTH162373
UNIT
MIN
2.7
2
MAX
MIN
2.7
2
MAX
V
V
V
V
Supply voltage
3.6
3.6
V
V
CC
High-level input voltage
Low-level input voltage
Input voltage
IH
0.8
5.5
–12
12
0.8
5.5
–12
12
V
IL
V
I
I
High-level output current
Low-level output current
Input transition rise or fall rate
Power-up ramp rate
mA
mA
ns/V
µs/V
°C
OH
OL
I
∆t/∆v
∆t/∆V
Outputs enabled
10
10
200
–55
200
–40
CC
T
A
Operating free-air temperature
125
85
NOTE 4: All unused control inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LVTH162373, SN74LVTH162373
3.3-V ABT 16-BIT TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS261J – JULY 1993 – REVISED APRIL 1999
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54LVTH162373
SN74LVTH162373
PARAMETER
TEST CONDITIONS
I = –18 mA
UNIT
†
†
MIN TYP
MAX
MIN TYP
MAX
V
V
V
V
V
V
V
V
= 2.7 V,
= 3 V,
–1.2
–1.2
V
V
V
IK
CC
CC
CC
CC
CC
I
I
I
= –12 mA
= 12 mA
2
2
OH
OL
OH
OL
= 3 V,
0.8
10
±1
1
0.8
10
= 0 or 3.6 V,
= 3.6 V,
V = 5.5 V
I
Control inputs
V = V
or GND
±1
I
CC
CC
I
I
I
µA
µA
µA
I
V = V
1
I
V
CC
V
CC
V
CC
= 3.6 V
= 0,
Data inputs
V = 0
I
–5
–5
V or V = 0 to 4.5 V
±100
off
I
O
V = 0.8 V
I
75
75
= 3 V
V = 2 V
I
–75
–75
Data inputs
I(hold)
500
–750
‡
V
CC
= 3.6 V ,
V = 0 to 3.6 V
I
I
I
V
V
V
= 3.6 V,
= 3.6 V,
V
V
= 3 V
5
5
µA
µA
OZH
CC
CC
CC
O
= 0.5 V
–5
–5
OZL
O
= 0 to 1.5 V, V = 0.5 V to 3 V,
O
±100*
±100*
±100
±100
µA
µA
I
OZPU
OZPD
OE = don’t care
V
= 1.5 V to 0, V = 0.5 V to 3 V,
CC
OE = don’t care
O
I
Outputs high
Outputs low
0.19
5
0.19
5
V
I
= 3.6 V,
CC
= 0,
I
mA
CC
O
V = V
I
or GND
CC
Outputs disabled
0.19
0.19
V
= 3 V to 3.6 V, One input at V – 0.6 V,
CC
CC
Other inputs at V
§
0.2
0.2
mA
∆I
CC
or GND
CC
C
C
V = 3 V or 0
3
9
3
9
pF
pF
i
I
V
O
= 3 V or 0
o
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
†
‡
§
All typical values are at V
= 3.3 V, T = 25°C.
A
CC
This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another.
This is the increase in supply current for each input that is at the specified TTL voltage level rather than V or GND.
CC
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figure 1)
SN54LVTH162373
= 3.3 V
SN74LVTH162373
= 3.3 V
V
CC
V
CC
V
= 2.7 V
V
= 2.7 V
UNIT
CC
CC
± 0.3 V
± 0.3 V
MIN
3
MAX
MIN
3
MAX
MIN
3
MAX
MIN
3
MAX
t
w
t
su
t
h
Pulse duration, LE high
Setup time, data before LE↓
Hold time, data after LE↓
ns
ns
ns
1.3
1
0.6
1.1
1
0.6
1.1
1
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LVTH162373, SN74LVTH162373
3.3-V ABT 16-BIT TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS261J – JULY 1993 – REVISED APRIL 1999
switching characteristics over recommended operating free-air temperature range, C = 50 pF
L
(unless otherwise noted) (see Figure 1)
SN54LVTH162373
= 3.3 V
SN74LVTH162373
FROM
(INPUT)
TO
(OUTPUT)
V
V
= 3.3 V
V
CC
CC
V
CC
= 2.7 V
= 2.7 V
PARAMETER
UNIT
CC
MIN
± 0.3 V
± 0.3 V
†
MIN
1.8
1.8
2.1
2.1
1.7
1.7
2.3
1
MAX
5
MIN
MAX
5.7
4.8
6.2
4.7
7
MIN TYP
MAX
4.6
4
MAX
5.1
4.3
5.8
4.3
6.6
5.5
5.7
5
t
t
t
t
t
t
t
t
t
1.9
1.9
2.2
2.2
1.8
1.8
2.4
2.2
3.1
2.8
3.4
3.2
3.2
3.2
3.8
3.5
PLH
PHL
PLH
PHL
PZH
PZL
PHZ
PLZ
sk(o)
D
Q
Q
Q
Q
ns
ns
ns
4.4
5.4
4.9
5.6
5.3
6.3
7.4
5.1
4.6
5.4
4.9
5.4
5.1
0.5
LE
OE
OE
5.9
6.6
6.4
ns
ns
†
All typical values are at V
= 3.3 V, T = 25°C.
A
CC
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LVTH162373, SN74LVTH162373
3.3-V ABT 16-BIT TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS261J – JULY 1993 – REVISED APRIL 1999
PARAMETER MEASUREMENT INFORMATION
6 V
Open
S1
500 Ω
TEST
/t
S1
From Output
Under Test
GND
t
Open
6 V
PLH PHL
t
/t
PLZ PZL
C
= 50 pF
L
500 Ω
t
/t
GND
(see Note A)
PHZ PZH
2.7 V
0 V
LOAD CIRCUIT
Timing Input
Data Input
1.5 V
t
w
t
t
h
su
2.7 V
0 V
2.7 V
0 V
Input
1.5 V
1.5 V
1.5 V
1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
2.7 V
0 V
2.7 V
0 V
Output
Control
Input
1.5 V
1.5 V
1.5 V
1.5 V
t
t
PLZ
PZL
t
t
t
PHL
PLH
Output
Waveform 1
S1 at 6 V
V
V
3 V
OH
Output
1.5 V
1.5 V
1.5 V
1.5 V
V
+ 0.3 V
OL
V
OL
(see Note B)
OL
t
t
t
PZH
PHZ
PHL
PLH
Output
Waveform 2
S1 at GND
V
V
V
OH
OH
V
– 0.3 V
OH
1.5 V
VOLTAGE WAVEFORMS
1.5 V
Output
≈ 0 V
(see Note B)
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A.
C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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any product or service without notice, and advise customers to obtain the latest version of relevant information
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subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
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BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
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Copyright 1999, Texas Instruments Incorporated
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