SN54CBT16244WD [TI]
16-BIT FET BUS SWITCHES; 16 - BIT FET总线开关
| 型号： | SN54CBT16244WD |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 16-BIT FET BUS SWITCHES |
| 文件： | 总10页 (文件大小：182K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN54CBT16244, SN74CBT16244
16-BIT FET BUS SWITCHES
SCDS031I – MAY 1996 – REVISED OCTOBER 2000
SN54CBT16244 . . . WD PACKAGE
SN74CBT16244 . . . DGG, DGV, OR DL PACKAGE
(TOP VIEW)
Members of Texas Instruments’ Widebus
Family
Standard ’16244-Type Pinout
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1OE
1B1
1B2
GND
1B3
1B4
2OE
1A1
1A2
GND
1A3
1A4
5-Ω Switch Connection Between Two Ports
TTL-Compatible Input Levels
2
3
4
description
5
The ’CBT16244 devices provide 16 bits of
high-speed TTL-compatible bus switching in a
standard ’16244 device pinout. The low on-state
resistance of the switch allows connections to be
made with minimal propagation delay.
6
7
V
V
CC
CC
8
2B1
2B2
GND
2B3
2B4
3B1
3B2
GND
3B3
3B4
2A1
2A2
GND
2A3
2A4
3A1
3A2
GND
3A3
3A4
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
These devices are organized as four 4-bit
low-impedance
switches
with
separate
output-enable (OE) inputs. When OE is low, the
switch is on, and data can flow from port A to port
B, or vice versa. When OE is high, the switch is
open, and the high-impedance state exists
between the two ports.
V
V
CC
CC
4B1
4B2
GND
4B3
4B4
4A1
4A2
GND
4A3
4A4
3OE
4OE
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
T
A
PACKAGE
Tube
SN74CBT16244DL
SSOP – DL
CBT16244
Tape and reel SN74CBT16244DLR
Tape and reel SN74CBT16244DGGR
Tape and reel SN74CBT16244DGVR
–40°C to 85°C
–55°C to 125°C
TSSOP – DGG
TVSOP – DGV
CFP – WD
CBT16244
CY244
Tube
SNJ54CBT16244WD
SNJ54CBT16244WD
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
FUNCTION TABLE
(each 4-bit bus switch)
INPUT
OE
OUTPUTS
A, B
L
A port = B port
Disconnect
H
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments.
Copyright 2000, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54CBT16244, SN74CBT16244
16-BIT FET BUS SWITCHES
SCDS031I – MAY 1996 – REVISED OCTOBER 2000
logic diagram (positive logic)
47
2
6
41
8
1A1
1B1
1B4
2A1
2B1
2B4
43
37
48
12
2A4
2OE
1A4
1
1OE
36
13
17
30
19
23
3A1
3B1
3B4
4A1
4B1
4B4
32
26
24
3A4
4A4
4OE
25
3OE
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
I
Continuous channel current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
IK I/O
Package thermal impedance, θ (see Note 2): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W
JA
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
SN54CBT16244 SN74CBT16244
UNIT
MIN
4
MAX
MIN
4
MAX
V
V
V
Supply voltage
5.5
5.5
V
V
CC
IH
IL
High-level control input voltage
Low-level control input voltage
Operating free-air temperature
2
2
0.8
0.8
85
V
T
A
–55
125
–40
°C
NOTE 3: All unused control inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54CBT16244, SN74CBT16244
16-BIT FET BUS SWITCHES
SCDS031I – MAY 1996 – REVISED OCTOBER 2000
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54CBT16244
SN74CBT16244
PARAMETER
TEST CONDITIONS
I = –18 mA
UNIT
V
†
†
MIN TYP
MAX
–1.2
10
MIN TYP
MAX
–1.2
10
V
IK
V
V
V
V
= 4.5 V,
= 0
CC
CC
CC
CC
I
V = 5.5 V
I
I
µA
I
= 5.5 V
V = 5.5 V or GND
I
±1
±1
= 5.5 V,
I
O
= 0,
I
3.2
2.5
3
µA
CC
V = V
I
or GND
CC
= 5.5 V,
Control
inputs
V
One input at 3.4 V,
CC
Other inputs at V
‡
∆I
CC
2.5
mA
or GND
CC
Control
inputs
C
C
V = 3 V or 0
2.5
4.5
2.5
4.5
pF
pF
i
I
V
V
= 3 V or 0,
OE = V
io(OFF)
O
CC
V = 2.4 V,
= 4 V,
I = 15 mA
20
10
10
14
20
7
CC
I
I
V = 0,
I
I = 64 mA
I
5
5
8
5
5
8
§
r
on
Ω
V
CC
= 4.5 V
V = 0,
I
I = 30 mA
I
7
V = 2.4 V,
I
I = 15 mA
I
12
†
‡
§
All typical values are at V
= 5 V, T = 25°C.
A
CC
This is the increase in supply current for each input that is at the specified TTL voltage level rather than V
or GND.
CC
Measured by the voltage drop between the A and B terminals at the indicated current through the switch. On-state resistance is determined by
the lower of the voltages of the two (A or B) terminals.
switching characteristics over recommended operating free-air temperature range, C = 50 pF
L
(unless otherwise noted) (see Figure 1)
SN54CBT16244
SN74CBT16244
FROM
(INPUT)
TO
(OUTPUT)
V = 5 V
CC
± 0.5 V
V = 5 V
CC
± 0.5 V
V
CC
= 4 V
V
CC
= 4 V
PARAMETER
UNIT
MIN
MAX
MIN
MAX
0.8*
9.2
MIN
MAX
MIN
MAX
0.25
5.1
¶
t
t
t
A or B
OE
B or A
A or B
A or B
0.35
5.5
ns
ns
ns
pd
10.3
9.7
1
1
1
1
en
8.2
5.2
5.4
OE
dis
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
¶
Thepropagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load capacitance, when
driven by an ideal voltage source (zero output impedance).
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54CBT16244, SN74CBT16244
16-BIT FET BUS SWITCHES
SCDS031I – MAY 1996 – REVISED OCTOBER 2000
PARAMETER MEASUREMENT INFORMATION
TEST
S1
7 V
Open
S1
t
Open
7 V
pd
/t
500 Ω
From Output
Under Test
t
PLZ PZL
/t
GND
t
Open
PHZ PZH
C
= 50 pF
L
500 Ω
(see Note A)
3 V
0 V
Output
Control
1.5 V
1.5 V
LOAD CIRCUIT
t
t
PLZ
PZL
Output
Waveform 1
S1 at 7 V
3.5 V
3 V
0 V
1.5 V
Input
V
+ 0.3 V
1.5 V
1.5 V
OL
V
(see Note B)
OL
OH
t
t
PHZ
PZH
t
t
PHL
PLH
Output
Waveform 2
S1 at Open
(see Note B)
V
V
OH
V
OH
– 0.3 V
1.5 V
Output
1.5 V
1.5 V
0 V
V
OL
VOLTAGE WAVEFORMS
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
ENABLE AND DISABLE TIMES
NOTES: A.
C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
are the same as t
are the same as t
are the same as t
.
dis
en
.
pd
PLZ
PZL
PLH
PHZ
PZH
PHL
.
Figure 1. Load Circuit and Voltage Waveforms
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
26-Sep-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
5962-9855301QXA
ACTIVE
ACTIVE
CFP
WD
48
48
1
TBD
Call TI
Level-NC-NC-NC
74CBT16244DGGRE4
TSSOP
DGG
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
74CBT16244DGVRE4
SN74CBT16244DGGR
SN74CBT16244DGVR
SN74CBT16244DL
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
TVSOP
TSSOP
TVSOP
SSOP
SSOP
CFP
DGV
DGG
DGV
DL
48
48
48
48
48
48
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74CBT16244DLR
SNJ54CBT16244WD
DL
1000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
WD
1
TBD
Call TI
Level-NC-NC-NC
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MCFP010B – JANUARY 1995 – REVISED NOVEMBER 1997
WD (R-GDFP-F**)
CERAMIC DUAL FLATPACK
48 LEADS SHOWN
0.120 (3,05)
0.075 (1,91)
0.009 (0,23)
0.004 (0,10)
1.130 (28,70)
0.870 (22,10)
0.370 (9,40)
0.250 (6,35)
0.390 (9,91)
0.370 (9,40)
0.370 (9,40)
0.250 (6,35)
1
48
0.025 (0,635)
A
0.014 (0,36)
0.008 (0,20)
24
25
NO. OF
LEADS**
48
56
0.740
0.640
(16,26) (18,80)
A MAX
A MIN
0.610 0.710
(15,49) (18,03)
4040176/D 10/97
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Index point is provided on cap for terminal identification only
E. Falls within MIL STD 1835: GDFP1-F48 and JEDEC MO-146AA
GDFP1-F56 and JEDEC MO-146AB
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,23
0,13
M
0,07
0,40
24
13
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–ā8°
0,75
1
12
0,50
A
Seating Plane
0,08
0,15
0,05
1,20 MAX
PINS **
14
16
20
24
38
48
56
DIM
A MAX
A MIN
3,70
3,50
3,70
3,50
5,10
4,90
5,10
4,90
7,90
7,70
9,80
9,60
11,40
11,20
4073251/E 08/00
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
D. Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001
DL (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0.025 (0,635)
48
0.0135 (0,343)
0.008 (0,203)
0.005 (0,13)
M
25
0.010 (0,25)
0.005 (0,13)
0.299 (7,59)
0.291 (7,39)
0.420 (10,67)
0.395 (10,03)
Gage Plane
0.010 (0,25)
0°–ā8°
1
24
0.040 (1,02)
0.020 (0,51)
A
Seating Plane
0.004 (0,10)
0.008 (0,20) MIN
PINS **
0.110 (2,79) MAX
28
48
0.630
56
DIM
0.380
(9,65)
0.730
A MAX
A MIN
(16,00) (18,54)
0.370
(9,40)
0.620
0.720
(15,75) (18,29)
4040048/E 12/01
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
D. Falls within JEDEC MO-118
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
M
0,08
0,50
48
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
0,25
1
24
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
48
56
64
DIM
A MAX
12,60
12,40
14,10
13,90
17,10
16,90
A MIN
4040078/F 12/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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