SN54CBTD3384JT [TI]
10-BIT FET BUS SWITCHES WITH LEVEL SHIFTING; 10位FET总线开关，电平转换
| 型号： | SN54CBTD3384JT |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 10-BIT FET BUS SWITCHES WITH LEVEL SHIFTING |
| 文件： | 总6页 (文件大小：93K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN54CBTD3384, SN74CBTD3384
10-BIT FET BUS SWITCHES
WITH LEVEL SHIFTING
SCDS025K – MAY 1995 – REVISED NOVEMBER 1998
SN54CBTD3384 . . . JT OR W PACKAGE
SN74CBTD3384 . . . DB, DBQ, DGV, DW, OR PW PACKAGE
(TOP VIEW)
5-Ω Switch Connection Between Two Ports
TTL-Compatible Input Levels
Designed to Be Used in Level-Shifting
Applications
1OE
1B1
1A1
1A2
1B2
1B3
1A3
1A4
1B4
V
CC
1
2
3
4
5
6
7
8
9
24
23
22
21
20
19
18
17
16
2B5
2A5
2A4
2B4
2B3
2A3
2A2
2B2
Package Options Include Plastic
Small-Outline (DW), Shrink Small-Outline
(DB, DBQ), Thin Very Small-Outline (DGV),
and Thin Shrink Small-Outline (PW)
Packages, Ceramic Flat (W) Package,
Ceramic DIPs (JT), and Ceramic Chip
Carriers (FK)
1B5 10
15 2B1
description
1A5
GND
2A1
11
12
14
13
The ’CBTD3384 devices provide ten bits of
high-speed TTL-compatible bus switching. The
low on-state resistance of the switches allows
connections to be made without adding
2OE
SN54CBTD3384 . . . FK PACKAGE
(TOP VIEW)
propagation delay. A diode to V is integrated on
CC
the die to allow for level shifting between 5-V
inputs and 3.3-V outputs.
4
3
2 1
28 27 26
These devices are organized as two 5-bit
switches with separate output-enable (OE)
inputs. When OE is low, the switch is on and portA
is connected to port B. When OE is high, the
switch is open and a high-impedance state exists
between the two ports.
5
6
7
8
9
25
24
23
22
21
20
19
1A2
1B2
1B3
NC
2A4
2B4
2B3
NC
1A3
1A4
1B4
2A3
2A2
2B2
10
11
The SN54CBTD3384 is characterized for
operation over the full military temperature range
from –55°C to 125°C. The SN74CBTD3384 is
characterized for operation from –40°C to 85°C.
12 13 14 15 16 17 18
NC – No internal connection
FUNCTION TABLE
(each 5-bit bus switch)
INPUTS INPUTS/OUTPUTS
1OE
2OE
L
1B1–1B5
1A1–1A5
1A1–1A5
Z
2B1–2B5
2A1–2A5
Z
L
L
H
H
H
L
2A1–2A5
Z
H
Z
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 1998, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54CBTD3384, SN74CBTD3384
10-BIT FET BUS SWITCHES
WITH LEVEL SHIFTING
SCDS025K – MAY 1995 – REVISED NOVEMBER 1998
logic diagram (positive logic)
3
2
1B1
1B5
1A1
11
1
10
1A5
1OE
14
15
23
2B1
2B5
2A1
22
13
2A5
2OE
Pin numbers shown are for the DB, DBQ, DGV, DW, JT, PW, and W packages.
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
I
Continuous channel current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
IK I/O
Package thermal impedance, θ (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104°C/W
JA
DBQ package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139°C/W
DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51.
recommended operating conditions (see Note 3)
SN54CBTD3384 SN74CBTD3384
UNIT
MIN
4.5
2
MAX
MIN
4.5
2
MAX
V
V
V
Supply voltage
5.5
5.5
V
V
CC
IH
IL
High-level control input voltage
Low-level control input voltage
Operating free-air temperature
0.8
0.8
85
V
T
A
–55
125
–40
°C
NOTE 3: All unused control inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54CBTD3384, SN74CBTD3384
10-BIT FET BUS SWITCHES
WITH LEVEL SHIFTING
SCDS025K – MAY 1995 – REVISED NOVEMBER 1998
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54CBTD3384
SN74CBTD3384
PARAMETER
TEST CONDITIONS
I = –18 mA
UNIT
†
†
MIN TYP
MAX
MIN TYP
MAX
V
V
V
= 4.5 V,
–1.2
–1.2
V
IK
CC
See Figure 2
I
OH
I
V
V
V
= 5.5 V,
= 5.5 V,
V = 5.5 V or GND
±1
±1
µA
I
CC
CC
CC
I
I
I
O
= 0,
V = V or GND
I CC
1.5
1.5
mA
CC
= 5.5 V, One input at 3.4 V,
or GND
‡
Control inputs
2.5
2.5
mA
∆I
CC
Other inputs at V
CC
C
C
Control inputs V = 3 V or 0
3
3
pF
pF
i
I
V
O
= 3 V or 0, OE = V
CC
3.5
5
3.5
5
io(OFF)
I = 64 mA
I
7
7
V = 0
I
§
V
CC
= 4.5 V
I = 30 mA
I
5
5
Ω
r
on
V = 2.4 V,
I
I = 15 mA
I
35
35
50
†
‡
§
Typical values are at V
CC
= 5 V, T = 25°C.
A
This is the increase in supply current for each input that is at the specified TTL voltage level rather than V
or GND.
CC
Measured by the voltage drop between the A and B terminals at the indicated current through the switch. On-state resistance is determined by
the lowest voltage of the two (A or B) terminals.
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature range, C = 50 pF (unless otherwise noted) (see Figure 1)
L
SN54CBTD3384 SN74CBTD3384
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN
MAX
0.25
9.7
MIN
MAX
0.25
7
¶
t
pd
t
en
t
A or B
OE
B or A
A or B
A or B
ns
ns
ns
2.2
1.5
2.3
1.7
8.6
5.3
OE
dis
¶
Thepropagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load capacitance, when
driven by an ideal voltage source (zero output impedance).
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54CBTD3384, SN74CBTD3384
10-BIT FET BUS SWITCHES
WITH LEVEL SHIFTING
SCDS025K – MAY 1995 – REVISED NOVEMBER 1998
PARAMETER MEASUREMENT INFORMATION
7 V
Open
GND
TEST
S1
S1
500 Ω
t
pd
/t
Open
7 V
From Output
Under Test
t
PLZ PZL
t
/t
Open
PHZ PZH
C
= 50 pF
L
500 Ω
(see Note A)
3 V
0 V
Output
Control
(low-level
enabling)
1.5 V
1.5 V
LOAD CIRCUIT
t
t
PLZ
PZL
Output
Waveform 1
S1 at 7 V
3.5 V
3 V
0 V
1.5 V
Input
1.5 V
1.5 V
V
V
+ 0.3 V
OL
(see Note B)
V
OL
OH
t
t
PZH
PHZ
t
t
PHL
PLH
Output
Waveform 2
S1 at Open
(see Note B)
V
V
V
OH
– 0.3 V
OH
1.5 V
Output
1.5 V
1.5 V
0 V
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A.
C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
PHL
are the same as t
.
dis
PLZ
PZL
PLH
PHZ
PZH
are the same as t
.
en
are the same as t .
pd
Figure 1. Load Circuit and Voltage Waveforms
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54CBTD3384, SN74CBTD3384
10-BIT FET BUS SWITCHES
WITH LEVEL SHIFTING
SCDS025K – MAY 1995 – REVISED NOVEMBER 1998
TYPICAL CHARACTERISTICS
OUTPUT VOLTAGE HIGH
OUTPUT VOLTAGE HIGH
vs
vs
SUPPLY VOLTAGE
SUPPLY VOLTAGE
4
3.75
3.5
4
3.75
3.5
T
A
= 85°C
T = 25°C
A
100 µA
100 µA
6 mA
12 mA
6 mA
12 mA
3.25
3.25
24 mA
24 mA
3
3
2.75
2.75
2.5
2.25
2
2.5
2.25
2
1.75
1.5
1.75
1.5
4.5
4.75
5
5.25
5.5
5.75
4.5
4.75
5
5.25
5.5
5.75
V
CC
– Supply Voltage – V
V
CC
– Supply Voltage – V
OUTPUT VOLTAGE HIGH
vs
SUPPLY VOLTAGE
4
3.75
3.5
T
A
= 0°C
100 µA
3.25
6 mA
12 mA
3
24 mA
2.75
2.5
2.25
2
1.75
1.5
4.5
4.75
5
5.25
5.5
5.75
V
CC
– Supply Voltage – V
Figure 2. V
Values
OH
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
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Copyright 1998, Texas Instruments Incorporated
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