OPA392_V01 [TI]
OPAx392 Precision, Low-Offset-Voltage, Low-Noise, Low-Input-Bias-Current, Rail-to-Rail I/O, e-trim⢠Operational Amplifiers;
| 型号： | OPA392_V01 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | OPAx392 Precision, Low-Offset-Voltage, Low-Noise, Low-Input-Bias-Current, Rail-to-Rail I/O, e-trim⢠Operational Amplifiers |
| 文件： | 总30页 (文件大小：2045K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
OPA392
SBOS926A – JANUARY 2021 – REVISED AUGUST 2021
OPAx392 Precision, Low-Offset-Voltage, Low-Noise, Low-Input-Bias-Current,
Rail-to-Rail I/O, e-trim™ Operational Amplifiers
1 Features
3 Description
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Low offset voltage: ±10 µV (maximum)
Low-drift: ±0.18 µV/°C
Low input bias current: 10 fA
Low noise: 4.4 nV/√Hz at 10 kHz
Low 1/f noise: 2 µVPP (0.1 Hz to 10 Hz)
Low supply voltage operation: 1.7 V to 5.5 V
Low quiescent current: 1.22 mA
Fast settling: 0.75 µs (1 V to 0.1%)
Fast slew rate: 4.5 V/µs
High output current: +65/–55-mA short circuit
Gain bandwidth: 13 MHz
Rail-to-rail input and output
Specified temperature range: –40°C to +125°C
EMI and RFI filtered inputs
The OPAx392 family of operational amplifiers
(OPA392, OPA2392, and OPA4392) features ultra-low
offset, offset drift, and input bias current with rail-to-rail
input and output operation. In addition to precision
dc accuracy, the ac performance is optimized for
low noise and fast-settling transient response. These
features make the OPAx392 an excellent choice
for driving high-precision analog-to-digital converters
(ADCs) or buffering the output of high-resolution,
digital-to-analog converters (DACs).
The OPAx392 feature TI's e-trim™ operational
amplifier technology to achieve ultra-low offset
voltage and offset voltage drift without any input
chopping or auto-zero techniques. This technique
enables ultra-low input bias current for sensor inputs
or photodiode current-to-voltage measurements,
creating high-performance transimpedance stages for
optical modules or medical instrumentation.
2 Applications
•
•
•
•
•
•
Multiparameter patient monitor
Electrocardiogram (ECG)
Chemistry/gas analyzer
Optical module
Analog input module
Process analytics (pH, gas, concentration, force
and humidity)
Gas detector
Analog security camera
Merchant DC/DC
Pulse oximeter
Inter-DC interconnect (long-haul, submarine)
Data acquisition (DAQ)
Device Information
PART NUMBER
PACKAGE(1)
BODY SIZE (NOM)
1.00 mm x 0.8 mm
2.00 mm x 1.25 mm
2.90 mm x 1.60 mm
1.20 mm x 1.20 mm
3.00 mm x 3.00 mm
4.90 mm x 3.90 mm
5.00 mm x 4.40 mm
3.00 mm x 3.00 mm
DSBGA (6)(3)
OPA392
SC-70 (5) (3)
•
•
•
•
•
•
SOT-23 (5)
DSBGA (9)(3)
VSSOP (8)(3)
SOIC (8)(3)
OPA2392(2)
OPA4392(2)
TSSOP (14)(3)
QFN (16)(3)
Precision Current
+3.3 V
Shunt Monitor
(1) For all available packages, see the package option
addendum at the end of the data sheet.
(2) Device is preview.
+
VIN
OPA392
ADC
œ
(3) Package is preview.
+3.3 V
Precision Current
Source
œ
OPA392
+
DAC
Optical Power
Monitor
œ
OPA392
+
ADC
OPAx392 Input Offset Voltage Distribution
OPAx392 Applications in Optical Modules
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
OPA392
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SBOS926A – JANUARY 2021 – REVISED AUGUST 2021
Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 6
6.1 Absolute Maximum Ratings ....................................... 6
6.2 ESD Ratings .............................................................. 6
6.3 Recommended Operating Conditions ........................6
6.4 Thermal Information ...................................................6
6.5 Electrical Characteristics ............................................7
6.6 Typical Characteristics................................................9
7 Detailed Description......................................................15
7.1 Overview...................................................................15
7.2 Functional Block Diagram.........................................15
7.3 Feature Description...................................................16
7.4 Device Functional Modes..........................................16
8 Application and Implementation..................................17
8.1 Application Information............................................. 17
8.2 Typical Application.................................................... 17
9 Power Supply Recommendations................................20
10 Layout...........................................................................20
10.1 Layout Guidelines................................................... 20
10.2 Layout Example...................................................... 20
11 Device and Documentation Support..........................21
11.1 Device Support........................................................21
11.2 Documentation Support.......................................... 21
11.3 Receiving Notification of Documentation Updates..21
11.4 Support Resources................................................. 21
11.5 Trademarks............................................................. 21
11.6 Electrostatic Discharge Caution..............................21
11.7 Glossary..................................................................21
12 Mechanical, Packaging, and Orderable
Information.................................................................... 22
4 Revision History
Changes from Revision * (January 2021) to Revision A (August 2021)
Changed OPA392 device in DBV (SOT-23-5) package from advanced information (preview) to production
data (active)........................................................................................................................................................1
Page
•
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5 Pin Configuration and Functions
+IN
Vœ
1
2
3
5
V+
OUT
Vœ
1
2
3
5
V+
+
œ
œIN
4
OUT
+IN
4
œIN
Not to scale
Not to scale
Figure 5-1. DCK Package (5-Pin SOT, Preview), Top Figure 5-2. DBV Package (5-Pin SOT-23), Top View
View
1
2
A
B
C
+IN
V–
–IN
EN
OUT
V+
Not to scale
Figure 5-3. YCJ Package (6-Pin DSBGA, Preview), Top View
Table 5-1. Pin Functions: OPA392
PIN
NO.
I/O
DESCRIPTION
NAME
–IN
DBV (SOT-23)
DCK (SC-70)
YCJ (DSBGA)
4
3
3
1
B1
A1
B2
C1
A2
C2
I
I
Inverting input
+IN
EN
OUT
V–
Noninverting input
—
1
—
4
I
Enable pin. High = amplifier enabled.
Output
O
—
—
2
2
Negative (lowest) power supply
Positive (highest) power supply
V+
5
5
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1
2
3
OUT A
œIN A
+IN A
Vœ
1
2
3
4
8
7
6
5
V+
OUT B
œIN B
+IN B
A
B
C
+IN B
V–
+IN A
–IN B
EN
V+
–IN A
Not to scale
Figure 5-4. OPA2392 D (8-Pin SOIC, Preview) and
DGK (8-Pin MSOP, Preview) Packages, Top View
OUT B
OUT A
Not to scale
Figure 5-5. OPA2392 YBJ (9-Pin DSBGA, Preview)
Package, Top View
Table 5-2. Pin Functions: OPA2392
PIN
NO.
I/O
DESCRIPTION
NAME
D (SOIC),
DGK (VSSOP)
YBJ (DSBGA)
–IN A
2
6
B3
B1
A3
A1
B2
C3
C1
A2
C2
I
I
Inverting input, channel A
Inverting input, channel B
Noninverting input, channel A
Noninverting input, channel B
Enable pin. High = both amplifiers enabled.
Output, channel A
–IN B
+IN A
+IN B
EN
3
I
5
I
—
1
I
OUT A
OUT B
V–
O
O
—
—
7
Output, channel B
4
Negative (lowest) power supply
Positive (highest) power supply
V+
8
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OUT A
œIN A
+IN A
V+
1
2
3
4
5
6
7
14
13
12
11
10
9
OUT D
œIN D
+IN D
Vœ
+IN A
V+
1
2
3
4
12
11
10
9
+IN D
V–
Thermal Pad
+IN B
œIN B
OUT B
+IN C
œIN C
OUT C
+IN B
–IN B
+IN C
–IN C
8
Not to scale
Figure 5-6. OPA4392 PW (14-Pin TSSOP, Preview)
Package, Top View
Not to scale
Figure 5-7. OPA4392 RTE (16-Pin QFN, Preview)
Package, Top View
Table 5-3. Pin Functions: OPA4392
PIN
NO.
I/O
DESCRIPTION
NAME
PW (TSSOP)
RTE (QFN)
–IN A
2
6
16
I
I
Inverting input, channel A
–IN B
4
Inverting input, channel B
–IN C
–IN D
+IN A
+IN B
+IN C
+IN D
EN AB
EN CD
OUT A
OUT B
OUT C
OUT D
Thermal Pad
V–
9
9
I
Inverting input, channel C
13
3
13
I
Inverting input, channel D
1
I
Noninverting input, channel A
Noninverting input, channel B
Noninverting input, channel C
Noninverting input, channel D
Enable pin for A and B amplifiers. High = amplifiers A and B are enabled.
Enable pin for C and D amplifiers. High = amplifiers C and D are enabled.
Output, channel A
5
3
I
10
12
—
—
1
10
I
12
I
6
I
7
I
15
O
O
O
O
—
—
—
7
5
Output, channel B
8
8
Output, channel C
14
—
11
4
14
Output, channel D
Thermal Pad
Connect thermal pad to V–
11
2
Negative (lowest) power supply
Positive (highest) power supply
V+
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
UNIT
Single-supply
6
VS
Supply voltage, VS = (V+) – (V–)
Input voltage, all pins
V
Dual-supply
Common-mode
Differential
±3
(V+) + 0.5
(V+) – (V–) + 0.2
±10
(V–) – 0.5
V
Input current, all pins
Output short circuit(2)
Operating temperature
Junction temperature
Storage temperature
mA
Continuous
–55
Continuous
150
TA
°C
°C
°C
TJ
–55
150
Tstg
–65
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) Short-circuit to ground, one amplifier per package.
6.2 ESD Ratings
VALUE
2000
500
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
1.7
NOM
MAX
5.5
UNIT
V
Single-supply
VS
TA
Supply voltage
Dual-supply
±0.85
–40
±2.75
+125
Specified temperature
Specified temperature
°C
6.4 Thermal Information
OPA392
THERMAL METRIC(1)
DBV (SOT-23)
5 PINS
187.1
UNIT
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
107.4
57.5
ΨJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
33.5
ΨJB
57.1
RθJC(bot)
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics
at TA = 25°C, VS = 1.7 V to 5.5 V (single-supply) or VS = ±0.85 V to ±2.75 V (dual-supply), RL = 10 kΩ connected to VS / 2,
VCM = VS / 2, and VOUT = VS / 2 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OFFSET VOLTAGE
±1
±2
±10
±30
VS = 5.0 V
VCM = (V+) – 200 mV
TA = –40°C to +125°C
VCM = (V–), TA = –40°C to 125°C
TA = 0°C to 85°C
VOS
Input offset voltage
μV
±100
±125
±0.16
±0.18
TA = –40°C to +125°C
±0.6
±0.9
dVOS/dT
PSRR
Input offset voltage drift
VS = 5.0 V
μV/°C
μV/V
VCM = 5.0 V,
TA = –40°C to +125°C
±30
±80
Power supply rejection
ratio
VCM = (V–)
TA = –40°C to +125°C
INPUT BIAS CURRENT
±0.01
±0.01
±0.8
±5
IB
Input bias current
TA = –40°C to +85°C
TA = –40°C to +125°C
pA
pA
±30
±0.8
±5
IOS
Input offset current
Input voltage noise
TA = –40°C°C to +85°C
TA = –40°C to +125°C
±30
NOISE
2.0
3.2
42
f = 0.1 Hz to 10 Hz
f = 10 Hz
μVPP
VCM = (V+) – 0.3
VCM = (V+) – 0.3
VCM = (V+) – 0.3
VCM = (V+) – 0.3
80
6.5
10.4
4.4
5.8
70
eN
Input voltage noise density f = 1 kHz
f = 10 kHz
nV/√Hz
iN
Input current noise
f = 1 kHz
fA/√Hz
V
INPUT VOLTAGE
Common-mode voltage
range
VCM
(V–)
75
(V+)
120
113
97
(V–) < VCM < (V+) – 1.5 V
TA = –40°C to +125°C
VS = 5.5 V
Common-mode rejection
ratio
CMRR
dB
66
88
(V–) < VCM < (V+),
TA = –40°C to +125°C
111
INPUT CAPACITANCE
ZID
Differential
1013 || 2.8
1013 || 3.5
Ω || pF
Ω || pF
ZICM
Common-mode
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6.5 Electrical Characteristics (continued)
at TA = 25°C, VS = 1.7 V to 5.5 V (single-supply) or VS = ±0.85 V to ±2.75 V (dual-supply), RL = 10 kΩ connected to VS / 2,
VCM = VS / 2, and VOUT = VS / 2 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OPEN-LOOP GAIN
(V–) + 50 mV < VOUT
(V+) – 50 mV, RL = 10 kΩ
<
115
110
132
128
(V–) + 100 mV < VO
<
VS = 5.5
(V+) – 100 mV, RL = 2 kΩ
(V–) + 100 mV < VOUT
<
(V+) – 100 mV, RL = 2 kΩ,
TA = –40°C to +125°C
100
106
106
(V–) + 50 mV < VOUT
<
AOL
Open-loop voltage gain
dB
(V+) – 50 mV, RL = 10 kΩ,
VCM = (V+) – 1.15 V
124
124
(V–) + 100 mV < VOUT
<
(V+) – 100 mV, RL = 2 kΩ,
VCM = (V+) – 1.15 V
VS = 1.7
(V–) + 100 mV < VOUT
<
(V+) – 100 mV, RL = 2 kΩ,
VCM = (V+) – 1.15 V,
100
TA = –40°C to +125°C
FREQUENCY RESPONSE
GBW
Gain-bandwidth product
AV = 1000 V/V
13
4.5
MHz
V/μs
V/μs
°
falling
rising
SR
Slew rate
4-V step, gain = +1
3.5
Phase margin
Settling time
CL = 100 pF
45
To 0.1%, 2-V step, gain = +1
To 0.01%, 2-V step, gain = +1
VIN × gain > VS
0.75
1
tS
μs
Overload recovery time
0.45
–112
0.00025
μs
dB
%
Total harmonic distortion + VOUT = 1 VRMS, gain = +1, f = 1 kHz, RL = 10 kΩ,
noise
THD+N
VCM = (V–) + 1.5 V
OUTPUT
RL = 10 kΩ
RL = 2 kΩ
RL = 10 kΩ
RL = 2 kΩ
20
30
20
35
VS = 1.7 V
VS = 5.5 V
Voltage output swing from
both rails
mV
Sinking, VS = 5.5 V
Sourcing, VS = 5.5 V
–55
65
ISC
Short-circuit current
mA
Ω
Open-loop output
impedance
RO
f = 1 MHz
120
POWER SUPPLY
IO = 0 mA
1.22
1.4
1.5
Quiescent current per
amplifier
IQ
mA
IO = 0 mA, TA = –40°C to +125°C
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6.6 Typical Characteristics
at TA = 25°C, VS = 5.5 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
VS = 5.0 V
VS = 5.0 V, VCM = 4.8 V
Figure 6-1. Offset Voltage Distribution
Figure 6-2. Offset Voltage Distribution
30
25
20
15
10
5
0
1
1.04 1.08 1.12 1.16 1.2 1.24 1.28 1.32 1.36 1.4
Quiescent Current (mA)
C004
VS = 5.0 V
Figure 6-4. Quiescent Current Distribution
Figure 6-3. Offset Voltage Distribution
30
25
20
15
10
5
0
0.9
0.95
1
1.05
1.1
1.15
1.2
1.25
1.3
Quiescent Current (mA)
C002
VS = 1.7 V
Figure 6-5. Quiescent Current Distribution
Figure 6-6. Open-Loop Gain and Phase vs Frequency
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6.6 Typical Characteristics (continued)
at TA = 25°C, VS = 5.5 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
VS = 1.7 V
Figure 6-8. Input Bias Current vs Common-Mode Voltage
Figure 6-7. Closed-Loop Gain and Phase vs Frequency
VS = 3.3 V
Figure 6-9. Input Bias Current vs Common-Mode Voltage
Figure 6-10. Input Bias Current vs Temperature
Figure 6-12. Output Voltage Swing vs Output Current (Sinking)
Figure 6-11. Output Voltage Swing vs Output Current (Sourcing)
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6.6 Typical Characteristics (continued)
at TA = 25°C, VS = 5.5 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
VS = ±0.85 V
VS = ±0.85 V
Figure 6-14. Output Voltage Swing vs Output Current (Sinking)
Figure 6-13. Output Voltage Swing vs Output Current (Sourcing)
5 Units
Figure 6-16. CMRR vs Temperature
Figure 6-15. CMRR and PSRR vs Frequency
5 Units
Figure 6-17. PSRR vs Temperature
Figure 6-18. Voltage Noise vs Frequency
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6.6 Typical Characteristics (continued)
at TA = 25°C, VS = 5.5 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
f = 1 kHz
VOUT = 1 VRMS
Figure 6-20. THD+N vs Output Amplitude
Figure 6-19. THD+N Ratio vs Frequency
5 Units
Figure 6-22. Quiescent Current vs Supply Voltage
Figure 6-21. 0.1-Hz to 10-Hz Noise
5 Units
5 Units
Figure 6-24. Open-Loop Gain vs Temperature
Figure 6-23. Quiescent Current vs Temperature
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6.6 Typical Characteristics (continued)
at TA = 25°C, VS = 5.5 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
G = –1
Figure 6-25. Open-Loop Output Impedance vs Frequency
Figure 6-26. Small-Signal Overshoot vs Capacitive Load
(10‑mV Step)
G = 1
Figure 6-28. No Phase Reversal
Figure 6-27. Small-Signal Overshoot vs Capacitive Load
(10‑mV Step)
Figure 6-29. Positive Overload Recovery
Figure 6-30. Negative Overload Recovery
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6.6 Typical Characteristics (continued)
at TA = 25°C, VS = 5.5 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
G = 1
G = –1
Figure 6-31. Small-Signal Step Response (10-mV Step)
Figure 6-32. Small-Signal Step Response (10-mV Step)
G = 1
G = –1
Figure 6-33. Large-Signal Step Response (4-V Step)
Figure 6-34. Large-Signal Step Response (4-V Step)
PRF = –10 dBm
Figure 6-35. Settling Time
Figure 6-36. EMIRR vs Frequency
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7 Detailed Description
7.1 Overview
The OPAx392 is a family of low offset, low-noise e-trim operational amplifiers (op amps) that uses a proprietary
offset trim technique. These op amps offer ultra-low input offset voltage and drift and achieve excellent input and
output dynamic linearity. The OPAx392 operate from 1.7 V to 5.5 V, are unity-gain stable, and are designed for a
wide range of general-purpose and precision applications.
The amplifiers feature state-of-the-art CMOS technology and advanced design features that help achieve
extremely low input bias current, wide input and output voltage ranges, high loop gain, and low, flat output
impedance in small package options. The OPAx392 strengths also include 13-MHz bandwidth, 4.4-nV/√Hz noise
spectral density, and low 1/f noise. These features make the OPAx392 optimal for interfacing with sensors,
photodiodes, and high-performance analog-to-digital converters (ADCs).
7.2 Functional Block Diagram
V+
Reference
Current
œIN
+IN
VBIAS1
Class AB
Control
OUT
Circuitry
VBIAS2
Þ
V
(Ground)
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7.3 Feature Description
7.3.1 Low Operating Voltage
The OPAx392 family can be used with single or dual supplies from an operating range of VS = 1.7 V (±0.85 V) up
to 5.5 V (±2.75 V). The offset voltage is trimmed at 5.0 V, however, the device maintains ultra-low offset voltages
down to VS = 1.7 V.
Key parameters that vary over the supply voltage or temperature range are shown in Section 6.6.
7.3.2 Low Input Bias Current
The typical input bias current of the OPAx392 is extremely low (typically 10 fA). Input bias current is dominated
by leakage current from the ESD protection diodes, which is proportional to the area of the diode. The OPAx392
is able to achieve ultra-low input bias current as a result of modern process technology and advanced ESD
protection design that minimizes the area of the diode.
In overdriven conditions, the bias current can increase significantly. The most common cause of an overdriven
condition occurs when the operational amplifier is outside of the linear range of operation. When the output of
the operational amplifier is driven to one of the supply rails, the feedback loop requirements cannot be satisfied
and a differential input voltage develops across the input pins. This differential input voltage results in the
forward-biasing of the ESD cells. The equivalent circuit is shown in Figure 7-1.
V+
10 ꢀ
+IN
œ
CORE
10 ꢀ
œIN
+
Vœ
Figure 7-1. Equivalent Input Circuit
7.4 Device Functional Modes
The OPAx392 family is operational when the power-supply voltage is greater than 1.7 V (±0.85 V). For devices
that use the EN function (see Section 5), the devices are disabled when the EN pin is low. In this state,
quiescient current is significantly reduced, and the output is high impedance. The maximum specified power-
supply voltage for the OPAx392 is 5.5 V (±2.75 V).
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8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information
The OPAx392 is a unity-gain stable, precision operational amplifier family free from unexpected output and
phase reversal. The use of proprietary e-trim operational amplifier technology gives the benefit of low input
offset voltage over time and temperature, along with ultra-low input bias current. The OPAx392 are optimized
for full rail-to-rail input, allowing for low-voltage, single-supply operation or split-supply use. These miniature,
high-precision, low-noise amplifiers offer high-impedance inputs that have a common-mode range to the supply
rail, with low offset across the supply range, and a rail-to-rail output that swings within 5 mV of the supplies
under normal test conditions. The OPAx392 precision amplifiers are designed for upstream analog signal chain
applications in low or high gains, as well as downstream signal chain functions such as DAC buffering.
8.2 Typical Application
This single-supply, low-side, bidirectional current-sensing design example detects load currents from –1 A to
+1 A. The single-ended output spans from 110 mV to 3.19 V. This design uses the OPA392 because of the low
offset voltage and rail-to-rail input and output. One of the amplifiers is configured as a difference amplifier and
the other amplifier provides the reference voltage.
Figure 8-1 shows the schematic.
VCC
VREF
VCC
R5
+
U1B
ILOAD
R6
R2
+
R1
+
VBUS
+
œ
VSHUNT
RSHUNT
VOUT
U1A
VCC
R4
R3
œ
RL
Figure 8-1. Bidirectional Current-Sensing Schematic
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8.2.1 Design Requirements
This solution has the following requirements:
•
•
•
Supply voltage: 3.3 V
Input: –1 A to +1 A
Output: 1.65 V ±1.54 V (110 mV to 3.19 V)
8.2.2 Detailed Design Procedure
The load current, ILOAD, flows through the shunt resistor, RSHUNT, to develop the shunt voltage, VSHUNT. The
shunt voltage is then amplified by the difference amplifier consisting of U1A and R1 through R4. The gain of the
difference amplifier is set by the ratio of R4 to R3. To minimize errors, set R2 = R4 and R1 = R3. The reference
voltage, VREF, is supplied by buffering a resistor divider using U1B. The transfer function is given by Equation 1.
VOUT = VSHUNT ´ GainDiff_Amp + VREF
(1)
where
VSHUNT = ILOAD ´ RSHUNT
•
R4
GainDiff_Amp
=
R3
•
R6
R5 + R6
VREF = VCC
´
•
There are two types of errors in this design: offset and gain. Gain errors are introduced by the tolerance of the
shunt resistor and the ratios of R4 to R3 and, similarly, R2 to R1. Offset errors are introduced by the voltage
divider (R5 and R6) and how closely the ratio of R4 / R3 matches R2 / R1. The latter value affects the CMRR of
the difference amplifier, ultimately translating to an offset error.
The value of VSHUNT is the ground potential for the system load because VSHUNT is a low-side measurement.
Therefore, a maximum value must be placed on VSHUNT. In this design, the maximum value for VSHUNT is set
to 100 mV. Equation 2 calculates the maximum value of the shunt resistor given a maximum shunt voltage of
100 mV and maximum load current of 1 A.
VSHUNT(Max)
100 mV
= 100 mW
RSHUNT(Max)
=
=
ILOAD(Max)
1 A
(2)
The tolerance of RSHUNT is directly proportional to cost. For this design, a shunt resistor with a tolerance of 0.5%
is selected. If greater accuracy is required, select a 0.1% resistor or better.
The load current is bidirectional; therefore, the shunt voltage range is –100 mV to +100 mV. This voltage is
divided down by R1 and R2 before reaching the operational amplifier, U1A. Make sure that the voltage present
at the noninverting node of U1A is within the common-mode range of the device. Therefore, use an operational
amplifier, such as the OPA392, that has a common-mode range that extends below the negative supply voltage.
Finally, to minimize offset error, the OPA392 has a typical offset voltage of merely ±0.25 µV (±5 µV maximum).
Given a symmetric load current of –1 A to +1 A, the voltage divider resistors (R5 and R6) must be equal. To
be consistent with the shunt resistor, a tolerance of 0.5% is selected. To minimize power consumption, 10‑kΩ
resistors are used.
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To set the gain of the difference amplifier, the common-mode range and output swing of the OPA392 must be
considered. Equation 3 and Equation 4 depict the typical common-mode range and maximum output swing,
respectively, of the OPA392 given a 3.3-V supply.
–100 mV < VCM < 3.4 V
100 mV < VOUT < 3.2 V
(3)
(4)
The gain of the difference amplifier can now be calculated as shown in Equation 5:
V
OUT_Max - VOUT_Min
3.2 V - 100 mV
100 mW ´ [1 A - (- 1A)]
V
V
= 15.5
=
GainDiff_Amp
=
R
SHUNT ´ (IMAX - IMIN
)
(5)
The resistor value selected for R1 and R3 is 1 kΩ. 15.4 kΩ is selected for R2 and R4 because this number is the
nearest standard value. Therefore, the ideal gain of the difference amplifier is 15.4 V/V.
The gain error of the circuit primarily depends on R1 through R4. As a result of this dependence, 0.1% resistors
are selected. This configuration reduces the likelihood that the design requires a two-point calibration. A simple
one-point calibration, if desired, removes the offset errors introduced by the 0.5% resistors.
8.2.3 Application Curve
3.30
1.65
0
-1.0
-0.5
0
0.5
1.0
Input Current (A)
Figure 8-2. Bidirectional Current-Sensing Circuit Performance: Output Voltage vs Input Current
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9 Power Supply Recommendations
The OPAx392 are specified for operation from 1.7 V to 5.5 V (±0.85 V to ±2.75 V).
CAUTION
Exceeding supply voltages listed in the Absolute Maximum Ratings table can permanently damage
the device.
10 Layout
10.1 Layout Guidelines
Pay attention to good layout practice. Keep traces short, and when possible, use a printed-circuit board
(PCB) ground plane with surface-mount components placed as close to the device pins as possible. Place
a 0.1-µF capacitor closely across the supply pins. These guidelines must be applied throughout the analog
circuit to improve performance and provide benefits such as reducing the electromagnetic interference (EMI)
susceptibility.
For lowest offset voltage and precision performance, circuit layout and mechanical conditions must be optimized.
Avoid temperature gradients that create thermoelectric (Seebeck) effects in the thermocouple junctions formed
from connecting dissimilar conductors. These thermally-generated potentials can be made to cancel by making
sure these potentials are equal on both input terminals. Other layout and design considerations include:
•
•
•
•
Use low thermoelectric-coefficient conditions (avoid dissimilar metals).
Use guard traces to minimize leakage current when ultra-low bias current is required.
Thermally isolate components from power supplies or other heat sources.
Shield operational amplifier and input circuitry from air currents, such as cooling fans.
Following these guidelines reduces the likelihood of junctions being at different temperatures, which can cause
thermoelectric voltage drift of 0.1 µV/°C or higher, depending on materials used.
10.2 Layout Example
VIN
+
VOUT
RG
RF
Figure 10-1. OPA392 Layout Schematic
VS
Minimize
parasitic
inductance by
CBYPASS
VOUT
placing bypass
capacitor close
to V+.
OUT
V+
Vœ
+IN œIN
RG
Keep high
impedance
input signal
away from
noisy traces.
VIN
RF
Route trace under package for output to
feedback resistor connection.
Figure 10-2. OPA392 Layout Example
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
11.1.1.1 TINA-TI™ Simulation Software (Free Download)
TINA-TI™ simulation software is a simple, powerful, and easy-to-use circuit simulation program based on a
SPICE engine. TINA-TI simulation software is a free, fully-functional version of the TINA™ software, preloaded
with a library of macromodels, in addition to a range of both passive and active models. TINA-TI simulation
software provides all the conventional dc, transient, and frequency domain analysis of SPICE, as well as
additional design capabilities.
Available as a free download from the Analog eLab Design Center, TINA-TI simulation software offers extensive
post-processing capability that allows users to format results in a variety of ways. Virtual instruments offer
the ability to select input waveforms and probe circuit nodes, voltages, and waveforms, creating a dynamic
quick-start tool.
Note
These files require that either the TINA software (from DesignSoft™) or TINA-TI software be installed.
Download the free TINA-TI software from the TINA-TI™ folder.
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation see the following:
•
Circuit Board Layout Techniques
11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
11.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.5 Trademarks
e-trim™, TINA-TI™, and TI E2E™ are trademarks of Texas Instruments.
TINA™ and DesignSoft™ are trademarks of DesignSoft, Inc.
All trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.7 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
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12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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12-Aug-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
OPA392DBVR
OPA392DBVT
ACTIVE
ACTIVE
SOT-23
SOT-23
DBV
DBV
5
5
3000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
23GT
23GT
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
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12-Aug-2021
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
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11-Aug-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
OPA392DBVR
OPA392DBVT
SOT-23
SOT-23
DBV
DBV
5
5
3000
250
178.0
178.0
9.0
9.0
3.3
3.3
3.2
3.2
1.4
1.4
4.0
4.0
8.0
8.0
Q3
Q3
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Aug-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
OPA392DBVR
OPA392DBVT
SOT-23
SOT-23
DBV
DBV
5
5
3000
250
180.0
180.0
180.0
180.0
18.0
18.0
Pack Materials-Page 2
PACKAGE OUTLINE
DBV0005A
SOT-23 - 1.45 mm max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
0.1 C
1.75
1.45
1.45
0.90
B
A
PIN 1
INDEX AREA
1
2
5
2X 0.95
1.9
3.05
2.75
1.9
4
3
0.5
5X
0.3
0.15
0.00
(1.1)
TYP
0.2
C A B
0.25
GAGE PLANE
0.22
0.08
TYP
8
0
TYP
0.6
0.3
TYP
SEATING PLANE
4214839/F 06/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.25 mm per side.
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EXAMPLE BOARD LAYOUT
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X (0.95)
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214839/F 06/2021
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X(0.95)
4
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214839/F 06/2021
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
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