OPA3S328RGRR_技术文档

OPA3S328

SBOS937A – OCTOBER 2020 – REVISED SEPTEMBER 2021

OPA3S328 40-MHz, Dual, Precision, Low-Noise, Low-Input-Bias-Current

CMOS Operational Amplifier With Integrated Switches

1 Features

3 Description

•

Precision operational amplifier with integrated

switches for transimpedance applications

Wide bandwidth: 40 MHz

Low offset voltage: 60 µV (max)

Very low offset drift: 1 µV/°C (max)

Low input bias current: 0.2 pA

Rail-to-rail input and output

The OPA3S328 is

a

precision, low-voltage,

CMOS operational amplifier (op amp) with

integrated switches that are optimized for flexible

transimpedance applications. Low input bias current

and low input capacitance allows for high-frequency

transimpedance gains at low photocurrent operation

(< 1 nA). The integrated switches, low offset, and

rail-to-rail output performance of the OPA3S328

enable high accuracy across multiple decades of

current values. Small packages, along with integrated

switches, allow for selectable transimpedance

gains and help reduce size for space-constrained

applications.

•

Zero-crossover input stage

Low voltage noise: 6.1 nV/√Hz at 10 kHz

Low current noise: 0.125 pA/√Hz at 10 kHz

Low leakage switches: 10 pA

Slew rate: 30 V/µs

Quiescent current: 3.8 mA per channel

Current in shutdown mode: 30 µA

Output impedance in shutdown mode: 100 GΩ

Single-supply voltage range: 2.2 V to 5.5 V

Unity-gain stable

Small packages:

– 20-lead, 3.5-mm x 3.5-mm VQFN

– 2.0-mm x 2.0-mm DSBGA

The OPA3S328 features zero-crossover input

technology, giving the flexibility for the input common-

mode range to span the full supply range without

offset deviations. The device provides enable-disable

capability to allow for portable, handheld applications

in test and measurement. When disabled, the

OPA3S328 output impedance is typically 100 GΩ,

allowing for wired-OR applications using multiple

transimpedance channels.

2 Applications

•

Optical transport inter-dc interconnect

Optical module

Optical network terminal unit (ONT)

Small cell base station

Digital multimeter (DMM)

Data acquisition (DAQ)

Device Information

PART NUMBER

PACKAGE⁽¹⁾

BODY SIZE (NOM)

3.50 mm × 3.50 mm

2.00 mm × 2.00 mm

VQFN (20)

DSBGA (24)⁽²⁾

OPA3S328

(1) For all available packages, see the package option

addendum at the end of the data sheet.

(2) DSBGA package is preview.

V+

OUTA

INSA

50

25

0

OUTSA1

OUTSA2

–

–INA

+INA

+

OPA3S328

OUTSA3

(YBJ Package Only)

SELA1

SELA0

Switch Control

GND

SELB1

SELB0

-25

OUTSB1

OUTSB2

OUTSB3

–

+

–INB

+INB

-50

-3

-2

-1

0

1

2

3

Common-mode Voltage (V)

V–

OUTB

INSB

Input Offset Voltage vs Input Common-Mode

Voltage

Functional Block Diagram

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

OPA3S328

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SBOS937A – OCTOBER 2020 – REVISED SEPTEMBER 2021

Table of Contents

1 Features............................................................................1

2 Applications.....................................................................1

3 Description.......................................................................1

4 Revision History.............................................................. 2

5 Pin Configuration and Functions...................................3

6 Specifications.................................................................. 5

6.1 Absolute Maximum Ratings ....................................... 5

6.2 ESD Ratings .............................................................. 5

6.3 Recommended Operating Conditions ........................5

6.4 Thermal Information ...................................................5

6.5 Electrical Characteristics ............................................6

6.6 Timing Diagram...........................................................8

6.7 Typical Characteristics................................................9

7 Parameter Measurement Information..........................17

7.1 Switch Characterization Configurations....................17

8 Detailed Description......................................................18

8.1 Overview...................................................................18

8.2 Functional Block Diagram.........................................18

8.3 Feature Description...................................................18

8.4 Device Functional Modes..........................................20

9 Application and Implementation..................................21

9.1 Application Information............................................. 21

9.2 Typical Application.................................................... 24

10 Power Supply Recommendations..............................25

11 Layout...........................................................................26

11.1 Layout Guidelines................................................... 26

11.2 Layout Example...................................................... 26

12 Device and Documentation Support..........................27

12.1 Device Support....................................................... 27

12.2 Documentation Support.......................................... 28

12.3 Receiving Notification of Documentation Updates..28

12.4 Support Resources................................................. 28

12.5 Trademarks.............................................................28

12.6 Electrostatic Discharge Caution..............................28

12.7 Glossary..................................................................28

13 Mechanical, Packaging, and Orderable

Information.................................................................... 28

4 Revision History

Changes from Revision * (October 2020) to Revision A (September 2021)

Changed OPA3S328 device in RGR (VQFN-20) package from advanced information (preview) to production

data (active)........................................................................................................................................................1

Page

•

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5 Pin Configuration and Functions

1

2

3

4

5

A

B

C

D

E

OUTA

+INA

SELA1

V+

SELA1

SELA0

GND

1

2

3

4

5

15

14

13

12

11

OUTSA2

OUTSA1

OUTSB1

OUTSB2

OUTSB3

OUTSA2,

SELA0

INSA

OUTSB1

INSB

OUTSA3

DNC

Thermal Pad

OUTSA1

OUTSB2

–INB

GND

SELB0

SELB1

OUTSB3

+INB

DNC

SELB0

OUTB

SELB1

V–

Not to scale

Figure 5-1. OPA3S328 RGR (20-Pin VQFN)

Package, Top View

Figure 5-2. OPA3S328 YBJ (24-Pin DSBGA

Preview) Package, Top View

Table 5-1. Pin Functions

NO.

I/O

DESCRIPTION

NAME

DNC

RGR

—

3

YBJ

B4, C4, D4

C5

—

Do not connect

GND

—

Digital ground pin

–INA

18

8

A1

I

Negative (inverting) input for amplifier A

Negative (inverting) input for amplifier B

Positive (noninverting) input for amplifier A

Positive (noninverting) input for amplifier B

–INB

E1

+INA

17

9

A3

+INB

E3

INSA

16

10

19

7

B2

I/O Switch A1, A2, A3 input

I/O Switch B1, B2, B3 input

INSB

D2

OUTA

A2

O

Output of amplifier A

Output of amplifier B

OUTB

OUTSA1

OUTSA2

OUTSA3

OUTSB1

OUTSB2

OUTSB3

SELA0

SELA1

SELB0

SELB1

V–

E2

14

15

—

13

12

11

2

C1

I/O Switch A1 output

I/O Switch A2 output

I/O Switch A3 output

I/O Switch B1 output

I/O Switch B2 output

I/O Switch B3 output

B1

B3

C2

D1

D3

B1

I

Input select for switch matrix A

1

A4

Input select for switch matrix A

Input select for switch matrix B

Negative (lowest) power supply

Positive (highest) power supply

Exposed thermal pad. Connect to V–

4

D5

I

5

E4

I

6

E5

—

V+

20

A5

Thermal Pad

—

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Table 5-2. Select Pin Decoder

SWITCH CONFIGURATION

SWITCH SWITCH SWITCH SWITCH SWITCH SWITCH

A1 A2 B1 B2 B3

A3⁽¹⁾

STATUS STATUS STATUS1 STATUS STATUS STATUS

SELA1

SELA0

SELB1

SELB0

SHUTDOWN STATUS

LOW

HIGH

LOW

HIGH

LOW

—

Amplifier A enabled

CLOSED

OPEN

CLOSED

OPEN

—

OPEN

CLOSED

In special mode, the SELB0 and SELB1 decoding scheme

shown here is ignored, and instead, Table 5-3 applies.

HIGH

—

LOW

HIGH

LOW

HIGH

LOW

HIGH

Amplifier B enabled

—

CLOSED

OPEN

CLOSED

OPEN

CLOSED

OPEN

(1) Switch A3 is available in the YBJ (VQFN-20) package option only.

Table 5-3. Select Pin Decoder in Special Mode: SELA0 = SELA1 = HIGH

SWITCH CONFIGURATION

SWITCH SWITCH SWITCH SWITCH SWITCH SWITCH

A1 A2 B1 B2 B3

A3⁽¹⁾

STATUS STATUS STATUS1 STATUS STATUS STATUS

SELA1

SELA0

SELB1

SELB0

SHUTDOWN STATUS

Amplifier A in power down

and amplifier B enabled

HIGH

LOW

HIGH

LOW

HIGH

LOW

HIGH

OPEN

Amplifier A enabled and

amplifier B in power down

Both Amplifier A and

amplifier B enabled

Both Amplifier A and

amplifier B in power down

(1) Switch A3 is available in the YBJ (VQFN-20) package option only.

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6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) ⁽¹⁾

MIN

–0.3

MAX

6

UNIT

V

V_S

Supply voltage, V_S= (V+) – (V–)

Input voltage, all pins

(V–) – 0.3

–10

(V+) + 0.3

+10

V

Input current (INA+, INA–, INB+, INB–, INSA/B, OUTSA/B/1/2/3)

Output short-circuit⁽²⁾

mA

Continuous Continuous

T_A

Operating temperature

–55

–65

150

°C

T_stg

Storage temperature

(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply

functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions.

If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully

functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.

(2) Short-circuit to ground, one amplifier per package.

6.2 ESD Ratings

VALUE

2000

500

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

Charged-device model (CDM), per ANSI/ESDA/JEDEC JS-002⁽²⁾

V_(ESD)

Electrostatic discharge

V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

2.2

NOM

MAX

5.5

UNIT

V

Single-supply

Dual-supply

Supply

voltage

V_S

±1.1

1.8

±2.75

5.5

V

V_D

T_A

Digital supply voltage, V_D= (V+) – (GND)

Specified temperature

V

–40

+125

°C

6.4 Thermal Information

OPA3S328

RGR (VQFN)

20 PINS

43.7

THERMAL METRIC⁽¹⁾

UNIT

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

R_θJC(top)

R_θJB

41.7

19.5

Ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

0.8

Ψ_JB

19.5

R_θJC(bot)

5.3

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

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6.5 Electrical Characteristics

at T_A= 25°C, V_S= ±1.1 V to ±2.75 V (V_S= 2.2 V to 5.5 V ), R_L= 10 kΩ connected to V_S/ 2, V_CM= V_S/ 2, and V_OUT= V_S/ 2,

all voltages referred to V– (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

OFFSET VOLTAGE

10

±60

±90

±175

±1

V_OS

Input offset voltage

T_A= 0°C to 85°C

μV

T_A= –40°C to +125°C

dV_OS/dT

PSRR

Input offset voltage drift

±0.15

±1

μV/°C

μV/V

±10

Input offset voltage versus

power supply

V_S= ±1.1 V to ±2.75 V

T_A= –40°C to +125°C

±15

140

75

f = dc

Channel separation

dB

f = 100 kHz

INPUT BIAS CURRENT

±0.2

±10

I_B

Amplifier input bias current T_A= 0°C to 85°C

T_A= –40°C to +125°C

pA

±100

±20

Amplifier input offset

T_A= 0°C to 85°C

current

I_OS

±20

T_A= –40°C to +125°C

±200

NOISE

Input voltage noise

f = 0.1 Hz to 10 Hz

f = 100 Hz

3

25

μV_PP

e_N

Input voltage noise density f = 1 kHz

f = 10 kHz

9.8

nV/√Hz

pA/√Hz

6.1

i_N

Input current noise

f = 10 kHz

0.125

INPUT VOLTAGE

Common-mode voltage

range

V_CM

(V–) – 0.1

(V+) + 0.1

V

106

96

120

110

Common-mode rejection

ratio

(V–) – 0.1 V < V_CM

(V+) + 0.1 V

<

CMRR

dB

T_A= –40°C to +125°C

INPUT CAPACITANCE

Z_ID

Differential

1 || 4

1 || 2

TΩ || pF

Z_ICM

Common-mode

OPEN-LOOP GAIN

(V–) + 100 mV < V_O

(V+) – 100 mV,

R_L= 10 kΩ

<

108

96

132

130

T_A= –40°C to +125°C

A_OL

Open-loop voltage gain

dB

106

90

123

120

(V–) + 100 mV < V_O

(V+) – 100 mV, R_L= 2 kΩ

FREQUENCY RESPONSE

GBW

SR

Gain-bandwidth product

40

±30

0.3

MHz

V/μs

Slew rate

4-V step, G = +1

To 0.1%, 4-V step , G = +1

To 0.01%, 4-V step , G = +1

V_IN× G > V_S

t_S

Settling time

μs

0.42

0.5

Overload recovery time

Total harmonic distortion +

noise

THD+N

f_CP

V_O= 1 V_RMS, G = +1, f = 1 kHz, R_L= 10 kΩ

0.00017%

27

Charge pump frequency

MHz

6

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6.5 Electrical Characteristics (continued)

at T_A= 25°C, V_S= ±1.1 V to ±2.75 V (V_S= 2.2 V to 5.5 V ), R_L= 10 kΩ connected to V_S/ 2, V_CM= V_S/ 2, and V_OUT= V_S/ 2,

all voltages referred to V– (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

OUTPUT

R_L= 10 kΩ

5

15

5

V_S= 2.2 V

V_S= 5.5 V

R_L= 2 kΩ

R_L= 10 kΩ

R_L= 2 kΩ

Voltage output swing from

both rails

mV

15

Sinking, V_S= 5.5 V

Sourcing, V_S= 5.5 V

–68

63

I_SC

Short-circuit current

mA

Ω

Open-loop output

impedance

R_O

f = 10 kHz

55

OUTPUT DISABLE

Quiescent current in power

down

I_QPD

Total quiescent current, both amplifiers A and B disabled

30

50

µA

t_PDOFF

t_PD

Output enable time

Output disable time

10

3

µs

Output impedance in

power down

Z_PD

100 || 16

GΩ || pF

SELECT INPUTS

V_IH

V_IL

High level input voltage

GND = 0 V

1.5

0

V+

0.3

V

Low level input voltage

GND voltage input range

(V–)

(V+) – 1.8

V

R_PD

Input pulldown resistance SELA/B/0/1 pins

10

MΩ

SWITCHES

Switching time off to on

(open to close)

R_{L_SW}= 300 Ω, C_L= 35 pF, INSA/B = 5 V,

OUTSA/B/1/2/3 = 0 V, V_S= 5 V

t_ON

1.3

2

µs

Switching time on to off

(close to open)

R_{L_SW}= 300 Ω, C_L= 35 pF, INSA/B = 5 V,

OUTSA/B/1/2/3 = 0 V, V_S= 5 V

t_OFF

Switch open, INSA/B = 5 V, OUTSA/B/1/2/3 = 0 V

30

10

150

260

90

Switch input leakage

current (INSA/B)

Switch open,

I_{L_INS}

pA

INSA/B = 1.5 V,

OUTSA/B/1/2/3 = 4.5 V

T_A= 0°C to 85°C

25

T_A= –40°C to +125°C

82

11

Switch output leakage

current

(OUTSA/B/1/2/3)

Switch open,

INSA/B = 1.5 V,

OUTSA/B/1/2/3 = 4.5 V

I_{L_OUTS}

T_A= 0°C to 85°C

100

190

5

120

250

20

pA

T_A= –40°C to +125°C

Switch closed,

INSA/B =

OUTSA/B/1/2/3 = 5 V

I_{L_ON}

Channel on leakage

T_A= 0°C to 85°C

140

155

T_A= –40°C to +125°C

C_IN

Switch input capacitance

Switch open, INSA/B = 2.5 V

3

0.7

6

pF

C_OUT

Switch output capacitance Switch open, OUTSA/B/1/2/3 = 2.5 V

Switch total capacitance

Switch closed, INSA/B = OUTSA/B/1/2/3 = 2.5 V

84

125

Switch closed,

R_ON

Switch on resistance

V+ = 5 V,

T_A= 0°C to 85°C

88

Ω

INSA/B = 2.5 V

T_A= –40°C to +125°C

102

Switch closed,

INSA/B = 4 V,

V+ = 5 V

Switch on resistance

match between channels

ΔR_ON

0.2

27

2

Ω

Switch on resistance

flatness (vs input signal

range)

Switch closed,

INSA/B= 0 V to V+,

V+ = 5 V

40

T_A= –40°C to +125°C

100

Switch charge injection

Switch off isolation

C_{L_SW}= 1 nF

6

pC

dB

R_{L_SW}= 50 Ω, C_{L_SW}= 5 pF, f = 1 MHz

84

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6.5 Electrical Characteristics (continued)

at T_A= 25°C, V_S= ±1.1 V to ±2.75 V (V_S= 2.2 V to 5.5 V ), R_L= 10 kΩ connected to V_S/ 2, V_CM= V_S/ 2, and V_OUT= V_S/ 2,

all voltages referred to V– (unless otherwise noted)

PARAMETER

TEST CONDITIONS

R_{L_SW}= 50 Ω, C_{L_SW}= 5 pF, f = 1 MHz

R_{L_SW}= 50 Ω, C_{L_SW}= 5 pF

MIN

TYP

MAX

UNIT

Switch channel-to-channel

crosstalk

76

dB

Switch −3 dB bandwidth

350

MHz

POWER SUPPLY

3.8

4.5

5.0

Quiescent current per

amplifier

I_Q

I_O= 0 mA

mA

T_A= –40°C to +125°C

6.6 Timing Diagram

SELA0

SELA1

SWITCH A1

STATUS

CLOSED

OPEN

CLOSED

t_OFF

t_ON

SWITCH A2

STATUS

CLOSED

t_ON

OPEN

t_OFF

AMP A/B

POWER

DOWN

POWER DOWN

OFF (AMPS ENABLED)

t_PDOFF

t_PD

NOTE: SELA0 and SELA1 are shown. Timing for SELB0 and SELB1 to SWITCH B1, B2 and B3 transitions match SELA0 and SELA1

timing.

Figure 6-1. Select Pin Timing Diagram

8

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6.7 Typical Characteristics

at T_A= 25°C, V_S= 5.5 V, V_CM= V_OUT= mid-supply, C_L= 20 pF, and R_L= 10 kΩ (unless otherwise noted)

20

15

10

5

15

12

9

6

3

0

-30 -25 -20 -15 -10 -5

0

5

10 15 20 25 30

-30 -25 -20 -15 -10 -5

0

5

10 15 20 25 30

Input Offset Voltage (V)

V_S= 2.2 V

Figure 6-2. Offset Voltage Production Distribution

25

Figure 6-3. Offset Voltage Production Distribution

20

15

10

5

15

10

5

0

-1.5

-1

-0.5

0

0.5

1

1.5

-1.5

-1

-0.5

0

0.5

1

1.5

Offset Voltage Drift (µV/°C)

V_S= 2.2 V

Figure 6-4. Offset Voltage Drift Distribution

Figure 6-5. Offset Voltage Drift Distribution

50

25

0

50

25

0

-25

-50

-1.25 -1 -0.75 -0.5 -0.25

0

0.25 0.5 0.75

1

1.25

-3

-2

-1

0

1

2

3

Common-mode Voltage (V)

V_S= 2.2 V

Figure 6-6. Offset Voltage vs Common-Mode Voltage

Figure 6-7. Offset Voltage vs Common-Mode Voltage

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6.7 Typical Characteristics (continued)

at T_A= 25°C, V_S= 5.5 V, V_CM= V_OUT= mid-supply, C_L= 20 pF, and R_L= 10 kΩ (unless otherwise noted)

160

140

120

100

80

200

180

160

140

120

100

80

160

140

120

100

80

0.01

0.1

1

Gain

Phase

60

40

10

20

60

0

40

V_S= 2.2 V

V_S= 5.5 V

-20

100m

20

100

125

1

10

100

1k

10k 100k 1M 10M

-50

-25

0

25

50

75

100

Frequency (Hz)

Temperature (°C)

Figure 6-8. Open-Loop Gain/Phase vs Frequency

4.5

Figure 6-9. Open-Loop Gain vs Temperature

0.5

I_B−

I_B+

I_OS

0.4

0.3

0.2

0.1

0

4.25

4

3.75

3.5

-0.1

-0.2

-0.3

-0.4

-0.5

V_S= 2.2 V

V_S= 5.5 V

3.25

-50

-25

0

25

50

75

100

125

-3 -2.5 -2 -1.5 -1 -0.5

0

0.5

1

1.5

2

2.5

3

Temperature (°C)

Common-Mode Voltage (V)

Figure 6-10. Quiescent Current vs Supply Voltage

200

Figure 6-11. Input Bias Current vs Common-Mode Voltage

140

I_B−

I_B+

I_OS

PSRR−

PSRR+

CMRR

100

50

120

20

10

5

100

80

60

40

20

0

2

1

0.5

0.2

0.1

0.05

-55

-30

-5

20

45

70

95

120

145

10m 100m

1

10 100 1k 10k 100k 1M 10M

Frequency (Hz)

Temperature (C)

Figure 6-12. Input Bias Current vs Temperature

Figure 6-13. CMRR and PSRR vs Frequency

10

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6.7 Typical Characteristics (continued)

at T_A= 25°C, V_S= 5.5 V, V_CM= V_OUT= mid-supply, C_L= 20 pF, and R_L= 10 kΩ (unless otherwise noted)

10

5

160

140

120

100

0.01

0.1

1

0

-5

V_S= 2.2 V

V_S= 5.5 V

10

125

-10

-50

-25

0

25

50

75

100

-25

0

25

50

75

100

125

Temperature (°C)

Figure 6-15. CMRR vs Temperature

Figure 6-14. PSRR vs Temperature

1000

500

300

200

100

50

30

20

10

5

3

2

1

100m

1

10

100

1k

10k 100k 1M 10M 100M

Frequency (Hz)

Time (1 s/div)

Figure 6-16. Input Voltage Noise Spectral Density vs Frequency

Figure 6-17. 0.1-Hz to 10-Hz Input Voltage Noise

60

50

40

30

20

10

0

8

V_S= 5.5 V

V_S= 2.2 V

7

6

5

4

3

2

1

0

-10

G = −1

-20

G = +1

G = +10

-30

G = +100

-40

1

10

100

1k

10k

100k

1M

10M

100

1k

10k

100k

Frequency (Hz)

1M

10M

100M

Frequency (Hz)

Figure 6-19. Maximum Output Voltage vs Frequency

Figure 6-18. Closed-Loop Gain vs Frequency

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6.7 Typical Characteristics (continued)

at T_A= 25°C, V_S= 5.5 V, V_CM= V_OUT= mid-supply, C_L= 20 pF, and R_L= 10 kΩ (unless otherwise noted)

1.2

0.9

0.6

0.3

0

-0.3

-0.6

-0.9

-1.2

−40C

25C

−40C

25C

85C

125C

0

10

20

30

40

50

60

70

0

10

20

30

40

50

60

70

Output Current (mA)

V_V+= 1.1 V, V_V–= –1.1 V, current source load

Figure 6-21. Output Voltage Swing vs Output Current

Figure 6-20. Output Voltage Swing vs Output Current

2.75

-1.5

−40C

25C

2.5

2.25

2

85C

-1.75

125C

-2

1.75

-2.25

-2.5

1.5

−40C

25C

85C

125C

1.25

1

-2.75

0

10 20 30 40 50 60 70 80 90 100 110 120

Output Current (mA)

0

10

20

30

40

50

60

70

80

90 100

Output Current (mA)

V_V+= 2.75 V, V_V–= –2.75 V, current source load

Figure 6-23. Output Voltage Swing vs Output Current

Figure 6-22. Output Voltage Swing vs Output Current

10000

7000

5000

3000

2000

1000

700

500

300

200

100

70

50

30

1

10

100

1k

10k

100k

1M

10M

Frequency (Hz)

V_V+= 5.5 V, V_V–= 0 V, voltage source load

Figure 6-25. Open-Loop Output Impedance vs Frequency

Figure 6-24. Output Voltage Swing vs Output Current

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6.7 Typical Characteristics (continued)

at T_A= 25°C, V_S= 5.5 V, V_CM= V_OUT= mid-supply, C_L= 20 pF, and R_L= 10 kΩ (unless otherwise noted)

140

120

100

80

140

120

100

80

R_L= 10 k

R_L= 2 k

−40C

0C

25C

85C

125C

60

40

20

0

0.001

0.002

0.005

0.01

0.02 0.03 0.050.07 0.1

0.001

0.002

0.005

0.01

0.02 0.03 0.050.07 0.1

Supply Voltage − Output Voltage (V)

R_L= 2 kΩ

Figure 6-26. Open-Loop Gain vs Output to Supply Voltage Delta Figure 6-27. Open-Loop Gain vs Output to Supply Voltage Delta

30

25

20

15

10

5

70

65

60

55

50

45

40

35

30

25

20

15

10

R_ISO= 0 

R_ISO= 25 

R_ISO= 50 

R_ISO= 0 

R_ISO= 25 

R_ISO= 50 

0

10

20 30 40 50 70 100

200 300 500 7001000

10

20 30 40 50 70 100

200 300 500 7001000

Capacitance (pF)

G = –1

Figure 6-28. Small-Signal Overshoot vs Load Capacitance

Capacitance (pF)

G = +1

Figure 6-29. Small-Signal Overshoot vs Load Capacitance

0.1

-60

0.002

G = −1, R_L= 10k

G = −1, R_L= 2k 

G = −1, R_L= 600 

G = +1, R_L= 10k 

G = +1, R_L= 2k 

G = +1, R_L= 600 

0.05

0.02

0.01

0.001

-100

-80

0.005

0.0007

0.002

0.001

0.0005

0.0004

-100

-120

-140

0.0005

0.0003

G = −1, R_L= 10k

G = −1, R_L= 2k

G = −1, R_L= 600

G = +1, R_L= 10k

G = +1, R_L= 2k

G = +1, R_L= 600

0.0002

0.0001

5E-5

0.0002

2E-5

1E-5

0.0001

-120

20k

20

200

2k

100m

1

Frequency (Hz)

Output Amplitude (V_RMS

)

V_OUT= 1 V_RMS

f = 1 kHz

Figure 6-30. THD+N vs Amplitude

Figure 6-31. THD+N vs Frequency

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6.7 Typical Characteristics (continued)

at T_A= 25°C, V_S= 5.5 V, V_CM= V_OUT= mid-supply, C_L= 20 pF, and R_L= 10 kΩ (unless otherwise noted)

V_IN

V_OUT

Time (200 ns/div)

G = –1

G = +1

Figure 6-32. Small-Signal Step Response

Figure 6-33. Small-Signal Step Response

V_IN

V_OUT

Time (200 ns/div)

G = –1

Time (200 ns/div)

G = +1

Figure 6-34. Large-Signal Step Response

Figure 6-35. Large-Signal Step Response

300

250

200

150

100

50

60

50

40

30

20

10

0

I_OUT(off)

I_IN(off)

I_INOUT(on)

0

-50

-25

0

25

50

75

100

125

150

-10

-5

0

5

10

15

20

25

30

35

40

Temperature (C)

Switch Leakage (pA)

I_{L_INS}, T_A= –40° C

G = –1

Figure 6-36. Switch Leakage Current vs Temperature

Figure 6-37. Switch Input Leakage Current Histogram

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6.7 Typical Characteristics (continued)

at T_A= 25°C, V_S= 5.5 V, V_CM= V_OUT= mid-supply, C_L= 20 pF, and R_L= 10 kΩ (unless otherwise noted)

50

40

30

20

10

0

20

15

10

5

0

-10

-5

0

5

10

15

20

25

30

-50 -40 -30 -20 -10

0

10

20

30

40

50

Switch Leakage (pA)

I_{L_INS}, T_A= 25° C

Switch Leakage (pA)

I_{L_INS}, T_A= 125° C

Figure 6-38. Switch Input Leakage Current Histogram

Figure 6-39. Switch Input Leakage Current Histogram

30

40

35

30

25

20

15

10

5

25

20

15

10

5

0

-10

-8

-6

-4

-2

0

2

4

6

8

10

-5

-4

-3

-2

-1

Switch Leakage (pA)

I_{L_OUTS}, T_A= –40° C

0

1

2

3

4

5

Switch Leakage (pA)

I_{L_OUTS}, T_A= 25° C

Figure 6-41. Switch Output Leakage Current Histogram

Figure 6-40. Switch Output Leakage Current Histogram

30

135

−40°C

25°C

85°C

125

115

105

95

25

20

15

10

5

125°C

85

75

65

55

0

45

-10

10

30

50

70

90

110

130

150

-3 -2.5 -2 -1.5 -1 -0.5

0

0.5

1

1.5

2

2.5

3

Switch Leakage (pA)

I_{L_OUTS}, T_A= 125° C

Switch Common-Mode Voltage (V)

Figure 6-42. Switch Output Leakage Current Histogram

Figure 6-43. Switch On-Resistance vs Common-Mode Voltage

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6.7 Typical Characteristics (continued)

at T_A= 25°C, V_S= 5.5 V, V_CM= V_OUT= mid-supply, C_L= 20 pF, and R_L= 10 kΩ (unless otherwise noted)

550

500

450

400

350

300

250

200

150

100

50

0

-20

V_S= 5.5 V

V_S= 3.3 V

V_S= 2.2 V

-40

-60

-80

-100

-120

10k

100k

1M

10M

-3 -2.5 -2 -1.5 -1 -0.5

0

0.5

1

1.5

2

2.5

3

Frequency (Hz)

Switch Common-Mode Voltage (V)

Figure 6-45. Switch Crosstalk vs Frequency

Figure 6-44. Switch On-Resistance vs Common-Mode Voltage

3

2

10

9

V_S= 5.5 V

V_S= 2.2 V

8

1

7

0

6

5

-1

-2

-3

-4

-5

-6

4

3

2

1

0

-1

-2

100k

1M

10M

100M

-3 -2.4 -1.8 -1.2 -0.6

0

0.6 1.2 1.8 2.4

3

Frequency (Hz)

Switch Common-Mode Voltage (V)

Figure 6-46. Switch Attenuation vs Frequency

Figure 6-47. Switch Charge Injection vs Common-Mode Voltage

V_SELXX

V_OUT

V_SELXX

V_OUT

Time (1 µs/div)

Figure 6-48. Switch Turn-on

Figure 6-49. Switch Turn-off

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7 Parameter Measurement Information

7.1 Switch Characterization Configurations

+

V_INS= 5.0 V, 1.5 V

–

I_{L_INS}

OUTA

INSA

V+

I_{L_OUTS}

OUTSA1

–

–INA

+INA

OUTSA2

OUTSA3

GND

+

I_{L_OUTS}

*

OPA3S328

SELA1

SELA0

Switch Control

SELB1

SELB0

I_{L_OUTS}

OUTSB1

OUTSB2

–

+

–INB

+INB

OUTSB3

+

V–

V_OUTS= 0 V, 3.5 V

INSB

OUTB

–

*OUTSA3 is available only in

the YBJ package

I_{L_INS}

+

–

V_INS= 5.0 V, 1.5 V

(V+) = 5.5 V, (V–) = 0 V

Figure 7-1. Switch Leakage Current, Open

+

V_INS= 5.0 V

–

I_{L_ON}

OUTA

INSA

V+

OUTSA1

OUTSA2

–

–INA

+INA

+

OPA3S328

*

OUTSA3

GND

SELA1

SELA0

Switch Control

SELB1

SELB0

OUTSB1

OUTSB2

OUTSB3

–

+

–INB

+INB

V–

INSB

OUTB

*OUTSA3 is available only in

the YBJ package

I_{L_ON}

+

–

V_INS= 5.0 V

(V+) = 5.5 V, (V–) = 0 V

Figure 7-2. Switch Leakage Current, Closed

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8 Detailed Description

8.1 Overview

The OPA3S328 features two high-speed, precision amplifiers combined with programmable switches that are

designed to offer a compact sensor or optical interface for high resolution analog-to-digital converters (ADCs).

Low output impedance with flat frequency characteristics and zero-crossover distortion circuitry enable high

linearity over the full input common-mode range, achieving true rail-to-rail input from a 2.2-V to 5.5-V single

supply. Integrated switches allow for multiple gain settings on a single amplifier stage without the need for an

additional multiplexer device.

In addition to transimpedance applications, the OPA3S328 is flexible with many different application uses for a

variety of equipment, such as optical modules, battery testers, medical instrumentation. This device can be used

to replace larger transimpedance amplifiers, log amplifiers, programmable gain amplifiers, or programmable

active filters.

8.2 Functional Block Diagram

V+

OUTA

INSA

OUTSA1

OUTSA2

–

–INA

+INA

+

OPA3S328

OUTSA3

(YBJ Package Only)

SELA1

SELA0

Switch Control

GND

SELB1

SELB0

OUTSB1

OUTSB2

OUTSB3

–

+

–INB

+INB

V–

OUTB

INSB

8.3 Feature Description

8.3.1 Low Operating Voltage

The OPA3S328 amplifiers and switches operate on a single-supply voltage (2.2 V to 5.5 V), or a dual-supply

voltage (±1.1 V to ±2.75 V), making these devices highly versatile, and easy to use with low supply rails. Use

local bypass ceramic capacitors (typically, 0.001 µF to 0.1 µF) to ground on the power-supply pins, as well as a

bypass capacitor connected between the positive and negative supply pins for dual-supply operation.

The digital input pins for switch and shutdown control (SELA0, SELA1, SELB0, SELB1) are referenced to the

V+ supply for the positive rail, and to the digital ground (GND pin) for the negative rail. The GND pin can be

forced to any voltage greater than V– and less than V+. However, the voltage between GND and V+ must be

greater than the minimum requirement for the digital circuit block operation; see Section 8.4. For single-supply

use cases, connect GND to V–.

The OPA3S328 amplifiers are fully specified from 2.2 V to 5.5 V and over the temperature range of –40°C to

+125°C.

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8.3.2 Input and ESD Protection

The OPA3S328 incorporates internal electrostatic discharge (ESD) protection circuits on all pins. In the case

of input and output pins, this protection primarily consists of current-steering diodes connected between the

input and power-supply pins. These ESD protection diodes also provide in-circuit input overdrive protection,

provided that the current is limited to 10 mA. Many input signals are inherently current-limited to less than 10

mA; therefore, a limiting resistor is not required. Figure 8-1 shows how a series input resistor (R_S) may be added

to the driven input to limit the input current. The added resistor contributes thermal noise at the amplifier input;

therefore, keep this value to a minimum in noise-sensitive applications.

V+

œ

V_OUT

Amp

R_S

V_IN

+

I_OVERLOAD

10 mA, Max

Figure 8-1. Input Current Protection

8.3.3 Programmable Switches

The OPA3S328 features integrated switches that can be used in many different configurations. Two sets of

switches each have a single input (INSA and INSB) that multiplexes to two or three different outputs (OUTSA1,

2, and 3 and OUTSB1, 2, and 3). The QFN package has both a 1-to-2 switch matrix and a 1-to-3 switch

matrix. The DSBGA package has two 1-to-3 switch matrices. The switches feature make-before-break switching,

meaning that when programmed to a different switch connection, the previous switch does not change to high-

impedance state until the new switch is closed, with a typical 2-µs delay when both switches are closed. This

feature keeps the amplifier from operating in an open-loop state when the switches are used in a switched-gain

transimpedance configuration.

8.3.4 Rail-to-Rail Input

The OPA3S328 features true rail-to-rail input operation, with supply voltages as low as ±1.1 V (2.2 V). The

design of the OPA3S328 amplifiers include an internal charge-pump that powers the amplifier input stage

with an internal supply rail at approximately 1.6 V above the external supply (V_S+). This internal supply rail

allows the single differential input pair to operate and remain very linear over a very-wide input common-mode

range. A unique zero-crossover input topology eliminates the input offset transition region typical of many

rail-to-rail, complementary-input-stage, operational amplifiers. This topology allows the OPA3S328 to provide

superior common-mode performance (CMRR > 120 dB, typical) over the entire common-mode input range,

which extends 100 mV beyond both power-supply rails. When driving analog-to-digital converters (ADCs), the

highly linear V_CMrange of the OPA3S328 provides maximum linearity and lowest distortion.

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8.3.5 Phase Reversal

The OPA3S328 op amps are designed to be immune to phase reversal when the input pins exceed the supply

voltages, and thus provide further in-system stability and predictability. Figure 8-2 shows the input voltage

exceeding the supply voltage without any phase reversal.

V_IN

V_OUT

Time (100 µs/div)

Figure 8-2. No Phase Reversal

8.4 Device Functional Modes

The OPA3S328 is specified to operate when power-supply voltages are between 2.2 V to 5.5 V (single-ended).

Each amplifier can also be placed in power-down mode, as described in the in the following subsection.

8.4.1 Power-Down Mode

The OPA3S328 amplifiers can be placed into a power-down state independently. When in this power-down state,

the output of the amplifier is high-impedance (> 1 GΩ) and the amplifier consumes 30 µA of quiescent current.

Power down is controlled through digital logic pins SELA0, SELA1, SELB0 and SELB1, which require a minimum

1.8 V between V+ and GND to provide functionality. For guidance on programming the device for power down,

see the logic table in Table 5-3.

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9 Application and Implementation

Note

Information in the following applications sections is not part of the TI component specification,

and TI does not warrant its accuracy or completeness. TI’s customers are responsible for

determining suitability of components for their purposes, as well as validating and testing their design

implementation to confirm system functionality.

9.1 Application Information

The OPA3S328 offers a unique combination of two outstanding dc and ac performance amplifiers, along

with integrated low-leakage switches. This combination of devices can be configured in a variety of ways in

many different circuit blocks, such as switched-gain transimpedance amplifiers, switched-gain voltage amplifiers,

programmable frequency active filters, and flexible analog-to-digital converter front ends.

9.1.1 Capacitive Load and Stability

The OPA3S328 is designed to be used in high-speed applications for TIA and ADC input-driving amplifiers. As

with all op amps, there may be specific instances where the OPA3S328 can become unstable. The particular op

amp circuit configuration, layout, gain, and output loading are some of the factors to consider when establishing

whether an amplifier is stable in operation. An op amp in the unity-gain (1-V/V) buffer configuration and driving

a capacitive load exhibits a greater tendency to become unstable than an amplifier operated at a higher noise

gain, as seen in Figure 6-29. The capacitive load, in conjunction with the op amp output resistance, creates a

pole within the feedback loop that degrades the phase margin. The degradation of the phase margin increases

as the capacitive loading increases. When operating in the unity-gain configuration, the OPA3S328 remains

stable with a pure capacitive load up to 100 pF.

One technique to increase the capacitive load drive capability of an amplifier operating in a unity-gain

configuration is to insert a small resistor (R_S), typically 10 Ω to 50 Ω, in series with the output, as shown in

Figure 9-1. This resistor significantly reduces the overshoot and ringing associated with large capacitive loads.

–

R_S

V_OUT

+

V_IN

R_L

C_L

GND

Figure 9-1. Improving Capacitive Load Drive

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9.1.2 EMI Susceptibility and Input Filtering

Operational amplifiers vary in susceptibility to electromagnetic interference (EMI). If conducted EMI enters the

operational amplifier, the dc offset observed at the amplifier output may shift from the nominal value while EMI

is present. This shift is a result of signal rectification associated with the internal semiconductor junctions. While

all operational amplifier pin functions can be affected by EMI, the input pins are likely to be the most susceptible.

The OPA3S328 operational amplifiers incorporate an internal input low-pass filter that reduces the amplifiers

response to EMI. Both common-mode and differential-mode filtering are provided by the input filter. The amplifier

EMIRR response can be seen in Figure 9-2.

120

110

100

90

80

70

60

50

40

30

20

10M

100M

Frequency (Hz)

1G

Figure 9-2. OPA3S328 EMIRR Response

9.1.3 Transimpedance Amplifier

Wide gain bandwidth, low-input bias current, low input voltage, and current noise make the OPA3S328 an

excellent wideband photodiode transimpedance amplifier. Low-voltage noise is important because photodiode

capacitance causes the effective noise gain of the circuit to increase at high frequency.

The key elements to a transimpedance design, as shown in Figure 9-3, are the:

•

expected diode capacitance (C_D), which should include the parasitic input common-mode voltage and

differential-mode input capacitance

•

desired transimpedance gain (R_F)

gain-bandwidth (GBW) for the OPA3S328 (40 MHz).

With these three variables set, the feedback capacitor value (C_F) can be set to control the frequency response.

C_Fincludes the stray capacitance of R_F, which is 0.2 pF for a typical surface-mount resistor.

C_F

R_F

10 MΩ

V+

ꢀ

œ

C_D

V_OUT

Amp

+

Vœ

NOTE: C_Fis optional to prevent gain peaking, and includes the stray capacitance of R_F.

Figure 9-3. Dual-Supply Transimpedance Amplifier

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For optimal frequency response, set the feedback pole as shown in Equation 1:

1

GBW

=

2pR_FC_F

4pR_FC_D

(1)

(2)

Bandwidth is calculated by Equation 2:

GBW

f

=

(Hz)

-3dB

2pR_FC_D

For single-supply applications, the +IN input can be biased with a positive dc voltage to allow the output to reach

true zero when the photodiode is not exposed to any light, and respond without the added delay that results from

coming out of the negative rail. This configuration is shown in Figure 9-4. This bias voltage also appears across

the photodiode, providing a reverse bias for faster operation.

C_F

R_F

10 MΩ

V+

ꢀ

œ

V_OUT

Amp

V_BIAS

+

NOTE: C_Fis optional to prevent gain peaking, and includes the stray capacitance of R_F.

Figure 9-4. Single-Supply Transimpedance Amplifier

For additional information, see the Compensate Transimpedance Amplifiers Intuitively application report, and

the Build a Programmable Gain Transimpedance Amplifier Using the OPA3S328 application report, available for

download at www.ti.com.

9.1.3.1 Optimizing the Transimpedance Circuit

To achieve the best performance, select components according to the following guidelines:

1. For lowest noise, select R_Fto create the total required gain. Using a lower value for R_Fand adding gain

after the transimpedance amplifier generally produces poorer noise performance. The noise produced by R_F

increases with the square-root of R_F, whereas the signal increases linearly. Therefore, signal-to-noise ratio

improves when all the required gain is placed in the transimpedance stage.

2. Minimize photodiode capacitance and stray capacitance at the summing junction (inverting input). This

capacitance causes the voltage noise of the op amp to be amplified (increasing amplification at high

frequency). Using a low-noise voltage source to reverse-bias a photodiode can significantly reduce

capacitance. Smaller photodiodes have lower capacitance. Use optics to concentrate light on a small

photodiode.

3. Noise increases with increased bandwidth. Limit the circuit bandwidth to only that required. Use a capacitor

across the R_Fto limit bandwidth, even if not required for stability.

4. Circuit board leakage can degrade the performance of an otherwise well-designed amplifier. Clean the circuit

board carefully. A circuit-board guard trace that encircles the summing junction and is driven at the same

voltage helps to control leakage.

For additional information, see the Noise Analysis of FET Transimpedance Amplifiers application report and the

Noise Analysis for High-Speed Op Amps application report, available for download at www.ti.com.

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9.2 Typical Application

R_FA1

20 k

R_FA2

200 k

C_FA1

22 pF

R_S1

49.9

C_FA2

22 pF

C_S1

1 nF

V+

OUTA

INSA

OUTSA1

OUTSA2

–

–INA

+INA

V_BIAS

+

OPA3S328

SELA1

SELA0

GND

Switch Control

ADS7066

SELB1

SELB0

V_BIASCAL

–

+

OUTSB1

OUTSB2

–INB

+INB

V_BIAS

OUTSB3

R_S2

V–

OUTB

INSB

49.9

GND

R_FB2

20 k

C_S2

1 nF

GND

R_FB1

200 k

C_FB2

22 pF

C_FB1

22 pF

Figure 9-5. Dual Transimpedance Front End With Gain Switching

9.2.1 Design Requirements

•

Gain = 0.02 V/µA and 0.2 V/µA

Low-pass cutoff frequency = 36 kHz

1% accuracy from 10 nA to 100 µA

24

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9.2.2 Detailed Design Procedure

•

Select transimpedance gains to align the measurement current range within the range of the ADC. For

the ADS7066, the input range is programmed to 5 V. Using this configuration, the peak current range is

calculated by dividing the input range by the feedback resistor, R_FB, which yields 25 μA for a 200-kΩ resistor

and 250 μA for a 20-kΩ feedback resistor.

•

The current measurement LSB size is 5 V / (R_F× 65536). The result yields 381 pA resolution for a 200-kΩ

feedback resistor, and 3.81 nA resolution for a 20-kΩ resistor.

A dc voltage is used on the noninverting terminal of the amplifier for two important reasons. The first

reason is to reverse-bias the photodiode, which helps reduce photodiode capacitance and makes sure the

photodiode does not operate in a forward-bias state. The second reason is to keep the output voltage of

the amplifier from coming too close to the negative supply (V–) voltage when the input current is zero. If the

output voltage comes within approximately 40 mV (assuming a 10-kΩ load), the amplifier enters a saturation

state, which results in loss of open-loop gain and slow transient response in order to exit the state (overload

recovery). Typically 100 mV is enough to make sure that the amplifier does not saturate.

A feedback capacitor can be used to help the stability of the circuit. Typically, if the feedback capacitor has a

higher capacitance than the total input capacitance, advanced compensation schemes are not necessary to

maintain stability of the amplifier along with the capacitance of the photodiode. This configuration can limit the

usable bandwidth of the circuit; see Section 9.1.3.1 for further details.

•

9.2.3 Application Curve

140

130

120

110

100

90

R_F= 20 kW

R_F= 200 kW

80

70

60

50

40

10

100

1k

10k 100k

Frequency (Hz)

1M

10M

100M

C002

Figure 9-6. OPA3S328 Transimpedance Gain

10 Power Supply Recommendations

The OPA3S328 is specified for operation from 2.2 V to 5.5 V (±1.1 V to ±2.75 V), and many specifications apply

from –40°C to +125°C.

CAUTION

Supply voltages larger than 6 V can permanently damage the device; see Section 6.1.

Place 0.1-µF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or

high-impedance power supplies. For more detailed information on bypass capacitor placement, see Section 11.

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11 Layout

11.1 Layout Guidelines

The OPA3S328 contains two wideband amplifiers and an integrated charge pump. To realize the full operational

performance of the device and remove the noise from the charge pump circuit, good high-frequency PCB layout

practices must be employed. The bypass capacitors must be connected between each supply pin and ground as

close to the device as possible. Additionally, in dual-supply systems, there must be a ceramic bypass capacitor

between the supply pins. Use bypass capacitor traces designed for minimum inductance.

11.2 Layout Example

Current Input

Connect a ceramic bypass capacitor

as close as possible to minimize high

Voltage

frequency supply noise.

Output

Via

OUTS

A2

Via

SELA1

SELA0

GND

OUTS

A1

Connect a ceramic

bypass capacitor

Exposed Thermal

Pad on Underside

between V+ and Vœ on

the top layer. Minimize

inductance between the

pins and capacitor with

wide traces.

OUTS

B1

Connected to V-

OUTS

B2

Via

SELB0

SELB1

OUTS

B3

Via

Voltage

Output

Connect a ceramic bypass capacitor as

close as possible to minimize high

frequency supply noise.

Current Input

Figure 11-1. Layout Example

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12 Device and Documentation Support

12.1 Device Support

12.1.1 Development Support

12.1.1.1 TINA-TI™ Simulation Software (Free Download)

TINA^™is a simple, powerful, and easy-to-use circuit simulation program based on a SPICE engine. TINA-TI^™

simulation software is a free, fully-functional version of the TINA software, preloaded with a library of macro

models in addition to a range of both passive and active models. TINA-TI software provides all the conventional

dc, transient, and frequency domain analysis of SPICE, as well as additional design capabilities.

Available as a free download from the Analog eLab Design Center, TINA-TI software offers extensive post-

processing capability that allows users to format results in a variety of ways. Virtual instruments offer the ability

to select input waveforms and probe circuit nodes, voltages, and waveforms, creating a dynamic quick-start tool.

Note

These files require that either the TINA software (from DesignSoft^™) or TINA-TI software be installed.

Download the free TINA-TI software from the TINA-TI folder.

12.1.1.2 TI Precision Designs

TI Precision Designs are analog solutions created by TI’s precision analog applications experts and offer the

theory of operation, component selection, simulation, complete PCB schematic and layout, bill of materials,

and measured performance of many useful circuits. TI Precision Designs are available online at http://

www.ti.com/ww/en/analog/precision-designs/.

12.1.1.3 WEBENCH^®Filter Designer

WEBENCH^®Filter Designer is a simple, powerful, and easy-to-use active filter design program. The

WEBENCH^®Filter Designer lets you create optimized filter designs using a selection of TI operational amplifiers

and passive components from TI's vendor partners.

Available as a web-based tool from the WEBENCH^®Design Center, WEBENCH^®Filter Designer allows you to

design, optimize, and simulate complete multistage active filter solutions within minutes.

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12.2 Documentation Support

12.2.1 Related Documentation

The following documents are relevant to using the OPA3S328, and recommended for reference. All are available

for download at www.ti.com (unless otherwise noted):

•

Texas Instruments, PM2.5/PM10 Particle Sensor Analog Front-End for Air Quality Monitoring Design

Texas Instruments, QFN/SON PCB Attachment

Texas Instruments, Quad Flatpack No-Lead Logic Packages

Texas Instruments, Compensate Transimpedance Amplifiers Intuitively

Texas Instruments, Noise Analysis of FET Transimpedance Amplifiers

Texas Instruments, Noise Analysis for High-Speed Op Amps

Texas Instruments, Build a Programmable Gain Transimpedance Amplifier Using the OPA3S328

12.3 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on

Subscribe to updates to register and receive a weekly digest of any product information that has changed. For

change details, review the revision history included in any revised document.

12.4 Support Resources

TI E2E^™support forums are an engineer's go-to source for fast, verified answers and design help — straight

from the experts. Search existing answers or ask your own question to get the quick design help you need.

Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do

not necessarily reflect TI's views; see TI's Terms of Use.

12.5 Trademarks

TINA^™and DesignSoft^™are trademarks of DesignSoft, Inc.

TINA-TI^™and TI E2E^™are trademarks of Texas Instruments.

WEBENCH^®is a registered trademark of Texas Instruments.

All trademarks are the property of their respective owners.

12.6 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

12.7 Glossary

TI Glossary

This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

28

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PACKAGE MATERIALS INFORMATION

www.ti.com

1-Oct-2021

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

OPA3S328RGRR

OPA3S328RGRT

VQFN

RGR

20

3000

250

330.0

180.0

12.4

3.75

1.15

8.0

12.0

Q2

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

1-Oct-2021

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

OPA3S328RGRR

OPA3S328RGRT

VQFN

RGR

20

3000

250

367.0

210.0

367.0

185.0

35.0

Pack Materials-Page 2

IMPORTANT NOTICE AND DISCLAIMER

TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE

DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”

AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY

IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD

PARTY INTELLECTUAL PROPERTY RIGHTS.

These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable

standards, and any other safety, security, regulatory or other requirements.

These resources are subject to change without notice. TI grants you permission to use these resources only for development of an

application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license

is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you

will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these

resources.

TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with

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TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	OPA3S328RGRR
厂家：	TEXAS INSTRUMENTS
描述：	OPA3S328 40-MHz, Dual, Precision, Low-Noise, Low-Input-Bias-Current CMOS Operational Amplifier With Integrated Switches
文件：	总36页 (文件大小：2256K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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