OPA3S2859-EP [TI]
增强型产品双通道 900MHz、2.2nV/√Hz 可编程增益跨阻放大器;
| 型号： | OPA3S2859-EP |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 增强型产品双通道 900MHz、2.2nV/√Hz 可编程增益跨阻放大器 放大器 |
| 文件： | 总28页 (文件大小：1949K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
OPA3S2859-EP
ZHCSMS7B –APRIL 2021 –REVISED DECEMBER 2021
OPA3S2859-EP 增强型产品双通道900MHz、2.2nV/√Hz 可编程增益跨阻放大器
1 特性
3 说明
• 增益带宽积：900MHz
• 内部可编程增益开关
• 高阻抗FET 输入
• 输入电压噪声：2.2nV/√Hz
• 压摆率：350V/μs
OPA3S2859-EP 是一款具有CMOS 输入的宽带低噪声
可编程增益放大器，适用于宽带跨阻和电压放大器应
用。当将该器件配置为跨阻放大器 (TIA) 时，0.9GHz
增益带宽积 (GBWP) 能够在低电容光电二极管(PD) 应
用中实现高闭环带宽。
• 电源电压范围：3.3V 至5.25V
• 静态电流：22mA/通道
• 断电模式IQ：75μA
• 温度范围：-55°C 至125°C
• 支持国防、航天和医疗应用
– 受控基线
三个内部开关反馈路径以及一个可选的并行非开关反馈
路径最多允许四个可选增益配置。与使用分立式外部开
关的系统相比，内部开关将更大程度降低寄生影响，从
而提高性能。每个开关针对 < 1kΩ 到 > 100kΩ 的反
馈电阻值进行了优化，适用于宽动态范围的应用。使用
两线制并行接口控制两个通道的选定开关路径。对于所
选的每个通道，也可以通过施加锁存引脚来使增益路径
保持恒定，这随后会禁用所选通道的开关控制，并防止
通道更改增益。
– 一个组装和测试基地
– 一个制造基地
– 延长了产品生命周期
– 延长了产品变更通知
– 产品可追溯性
器件信息(1)
封装尺寸（标称值）
器件型号
封装
WQFN (24)
2 应用
OPA3S2859-EP
4.00mm × 4.00mm
• 可切换的跨阻放大器
• 智能弹药
• 激光测距
• 光时域反射计(OTDR)
• 硅光电倍增器(SiPM) 缓冲放大器
• 光电倍增管后置放大器
• 高速可编程增益放大器
(1) 如需了解所有可用封装，请参阅数据表末尾的封装选项附录。
.
.
.
6
3
0
Þ VBIAS
-3
-6
VS-
VS+
VS+
PD
INA+
-9
0,1
SEL1
0,0
œ
RF = 1 kW
1,0
-12
+
RF = 10 kW
LTCH_A
RF = 100 kW
-15
1M
10M
Frequency (Hz)
100M
1G
LTCH_B
+
OPA3
1,0
œ
0,0
SEL0
VS+
VS-
跨阻带宽与频率间的关系
0,1
INB+
Þ VBIAS
方框图
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SBOSA61
OPA3S2859-EP
ZHCSMS7B –APRIL 2021 –REVISED DECEMBER 2021
www.ti.com.cn
Table of Contents
8.4 Device Functional Modes..........................................18
9 Application and Implementation..................................20
9.1 Application Information............................................. 20
9.2 Typical Application.................................................... 20
10 Power Supply Recommendations..............................22
11 Layout...........................................................................22
11.1 Layout Guidelines................................................... 22
11.2 Layout Examples.....................................................22
12 Device and Documentation Support..........................25
12.1 Device Support....................................................... 25
12.2 Documentation Support.......................................... 25
12.3 接收文档更新通知................................................... 25
12.4 支持资源..................................................................25
12.5 Trademarks.............................................................25
12.6 Electrostatic Discharge Caution..............................25
12.7 术语表..................................................................... 25
13 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revison History............................................................... 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 5
6.1 Absolute Maximum Ratings........................................ 5
6.2 ESD Ratings............................................................... 5
6.3 Recommended Operating Conditions.........................5
6.4 Thermal Information....................................................5
6.5 Electrical Characteristics.............................................6
6.6 Switching Characteristics............................................8
6.7 Typical Characteristics..............................................10
7 Parameter Measurement Information..........................16
8 Detailed Description......................................................17
8.1 Overview...................................................................17
8.2 Functional Block Diagram.........................................17
8.3 Feature Description...................................................18
Information.................................................................... 25
4 Revison History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision A (April 2021) to Revision B (December 2021)
Page
• 将数据表的状态从预告信息更改为量产数据..................................................................................................... 1
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5 Pin Configuration and Functions
22
20
19
23
21
24
VS-
INA+
SEL1
1
2
3
4
18
17
VS+
LTCH_A
LTCH_B
16
15
VS+
PD
Thermal
Pad
SEL0
INB+
5
6
VS+
VS-
14
13
图5-1. RTW Package
24-Pin WQFN With Exposed Thermal Pad
Top View
表5-1. Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
23
8
COM_A
COM_B
I
I
Photodiode input –Channel A
Photodiode input –Channel B
Feedback connection to Channel A –TIA Gain Resistor (Low gain, optimized for gain in < 10 kΩ
FB_A0
FB_A1
20
21
I
I
range)
Feedback connection to Channel A –TIA Gain Resistor
(Mid gain, optimized for gain in 10 kΩ –100 kΩ range)
Feedback connection to Channel A –TIA Gain Resistor (High gain, optimized for gain in > 100 kΩ
FB_A2
FB_B0
22
11
I
I
range)
Feedback connection to Channel B –TIA Gain Resistor (Low gain, optimized for gain in < 10 kΩ
range)
Feedback connection to Channel B –TIA Gain Resistor
(Mid gain, optimized for gain in 10 kΩ –100 kΩ range)
FB_B1
FB_B2
10
9
I
I
Feedback connection to Channel B –TIA Gain Resistor (High gain, optimized for gain in > 100 kΩ
range)
INA-
INA+
INB-
INB+
24
1
I
I
I
I
Negative (inverting) input for amplifier A
Positive (noninverting) input for amplifier A
Negative (inverting) input for amplifier B
Positive (noninverting) input for amplifier B
7
6
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表5-1. Pin Functions (continued)
PIN
I/O
DESCRIPTION
NAME
NO.
Latch control input for Channel A. LTCH_A = logic high (default) = transparent mode, gain setting
changes based on SEL0 and SEL1 pins are reflected at the output.
LTCH_A = logic low = latch mode = changing SEL0 and SEL1 pins does not affect the gain
configuration of amplifier.
LTCH_A
3
I
Latch control input for Channel B. LTCH_B = logic high (default) = transparent mode, gain setting
changes based on SEL0 and SEL1 pins are reflected at the output.
LTCH_B = logic low = latch mode = changing SEL0 and SEL1 pins does not affect the gain
configuration of amplifier.
LTCH_B
4
I
PD
15
I
I
Power down pin. PD = logic high (default) = normal operation, PD = logic low = power down mode.
TIA gain selection. SEL0 = logic high (default). See 表5-2 for details.
TIA gain selection. SEL1 = logic high (default). See 表5-2 for details.
Output of amplifier A
SEL0
SEL1
VOUT_A
VOUT_B
VS-
5
2
I
19
O
O
I
12
Output of amplifier B
13, 18
14, 16, 17
Negative (lowest) power supply
VS+
I
Positive (highest) power supply
Connect the thermal pad to the most negative power supply (pin 13 and 18) of the device under test
(DUT).
Thermal pad
—
表5-2. Select Pin Decoder
SEL1
LOW
LOW
SEL0
HIGH
LOW
Gain
Low Gain, optimized for gain in < 10 kΩ range
Mid Gain, optimized for gain in 10 kΩ –100 kΩ
range
HIGH
LOW
High Gain, optimized for gain in > 100 kΩ range
HIGH (Default)
HIGH (Default)
External Gain. All internal switches open
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
(VS–) –0.5
(VS–) –0.5
MAX
UNIT
V
VS
Total supply voltage (VS+ - VS-)
Input voltage
5.5
VIN+, VIN-
VID
(VS+) + 0.5
V
Differential input voltage
Output voltage
1
(VS+) + 0.5
±4
V
VOUT
IIN
IOUT
TJ
V
Continuous input current
Continuous output current(2)
Junction temperature
Operating free-air temperature
Storage temperature
mA
mA
°C
°C
°C
25
150
TA
125
–55
–65
Tstg
150
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute maximum ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
briefly operating outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not
sustain damage, but it may not be fully functional. Operating the device in this manner may affect device reliability, functionality,
performance, and shorten the device lifetime.
(2) Long-term continuous output current for electromigration limits
6.2 ESD Ratings
VALUE
±1500
±1000
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1)
Electrostatic
discharge
V(ESD)
V
Charged device model (CDM), per JEDEC specification JEDEC JS-002, all pins(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
3.3
NOM
MAX
5.25
125
UNIT
V
VS
TA
Total supply voltage (VS+ - VS-)
Ambient temperature
5
°C
–55
6.4 Thermal Information
OPA3S2859-EP
RTW
THERMAL METRIC(1)
UNIT
24 PINS
54.1
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
55.6
30.6
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
2.5
ΨJT
30.6
ΨJB
RθJC(bot)
13.9
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics
VS+ = 5 V, VS- = 0 V, RL = 200 Ω, output load is referenced to midsupply, input common-mode biased at midsupply, and TA
≈+25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
AC PERFORMANCE
130
40
MHz
MHz
MHz
MHz
V/µs
VOUT = 100 mVPP, Gain = 1 kΩ, CIN= 4 pF
VOUT = 100 mVPP, Gain = 10 kΩ, CIN = 4 pF
VOUT = 100 mVPP, Gain = 100kΩ, Cin = 4 pF
Small-signal transimpedance
bandwidth(1)
SSBW
GBWP
14
Gain-bandwidth product
Slew rate (10% - 90%)
900
350
2.2
VOUT = 2-V step
f = 1 MHz
en
Input-referred voltage noise
Closed-loop output impedance
nV/√Hz
Ω
ZOUT
f = 1 MHz
0.02
DC PERFORMANCE
AOL
AOL
VOS
Open-loop voltage gain
f = DC
70
64
76
dB
dB
Open-loop voltage gain
Input offset voltage
TA = -55°C to +125°C
TA = -55°C to +125°C
±0.9
8
mV
–8
ΔVOS
ΔT
/
Input offset voltage drift
TA = -55°C to +125°C
µV/°C
–2
IBN, IBI
IBOS
Input bias current(2)
Input offset current(2)
50
50
pA
pA
–50
-50
VCM = ±0.5 V (from midsupply),
TA = -55°C to +125°C
CMRR
Common-mode rejection ratio
67
78
dB
INPUTS
CIN+
Non-inverting input capacitance
Inverting input capacitance (3)
Common-mode input range (high)
1.4
3
pF
pF
V
CIN-
VIH
CMRR > 62 dB , TA = -55°C to +125°C
3.4
1.7
3.6
CMRR > 62 dB , VS+ = 3.3 V,
TA = -55°C to +125°C
VIH
VIL
VIL
Common-mode input range (high)
Common-mode input range (low)
Common-mode input range (low)
1.9
0
V
V
V
CMRR > 62 dB , TA = -55°C to +125°C
0.4
0.4
CMRR > 62 dB , VS+ = 3.3 V,
TA = -55°C to +125°C
0
OUTPUTS
VOH
Output voltage (high)
TA = -55°C to +125°C
3.95
2.3
4.1
2.4
1.1
1
V
V
VOH
Output voltage (high)
VS+ = 3.3 V, TA = -55°C to +125°C
TA = -55°C to +125°C
VOL
Output voltage(low)
1.2
V
VOL
Output voltage(low)
VS+ = 3.3 V, TA = -55°C to +125°C
RL = 10 Ω, AOL > 52 dB
1.15
V
IO_LIN
Linear output drive (source and sink)
65
58
74
mA
RL = 10 Ω, AOL > 52 dB, TA = -55°C to
+125°C
IO_LIN
Linear output drive (source and sink)
mA
CHANNEL-TO-CHANNEL MATCHING
Crosstalk (output-referred)
Offset voltage mismatch
-70
dB
mV
pA
f = 1 MHz, Gain = 100 kΩ, VOUT = 100 mVPP
TA = -55°C to +125°C
-10
-20
10
20
Offset current mismatch
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6.5 Electrical Characteristics (continued)
VS+ = 5 V, VS- = 0 V, RL = 200 Ω, output load is referenced to midsupply, input common-mode biased at midsupply, and TA
≈+25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER SUPPLY
VS+ = 5 V
44
51
39
85
72
53
63
47
mA
mA
mA
dB
IQ
Quiescent current (both channels)
VS+ = 5 V, TA = +125°C
VS+ = 5 V, TA = -55°C
TA = -55°C to +125°C
TA = -55°C to +125°C
PSRR+ Power Supply Rejection Ratio
PSRR- Power Supply Rejection Ratio
POWER DOWN
72
66
dB
Voltage referenced to VS+, amplifier OFF
below this voltage, TA = -55°C to +125°C
Disable voltage threshold
VS+ - 1.5 VS+ - 1.3
VS+ - 1.2 VS+ - 0.8
V
V
Voltage referenced to VS+, amplifier ON
above this voltage, TA = -55°C to +125°C
Enable voltage threshold
Power-down quiescent current
Power-down quiescent current
PD bias current
75
6
140
170
µA
µA
µA
µA
µA
TA = -55°C to +125°C
VPD = VS- or VS+
PD bias current
VPD = VS- or VS+ , TA = -55°C to +125°C
VPD at switching threshold
22
PD bias current
160
VPD at switching threshold,
TA = -55°C to +125°C
PD bias current
405
µA
Turnon time delay
Turnoff time delay
Time to VOUT = 90% of final value
Time to VOUT = 10% of final value
90
ns
ns
330
(1) CIN = Photodiode capacitance + PCB capacitance. Photodiode capacitance is 3.3 pF and estimated PCB capacitance is 0.7 pF.
(2) Leakage currents from switches are not included in this measurement.
(3) CIN- refers to the capacitance at the inverting input of the amplifier. CIN- = CIN-(CM) + CDIFF + Switch capacitance on the amplifier
inverting pin (ON capacitance of the closed switch + OFF capacitance for open switches).
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6.6 Switching Characteristics
VS+ = 5 V, VS- = 0 V, input common-mode biased at midsupply, RF0 = 1 kΩ, RF1 = 10 kΩ, RF2 = 100 kΩ, RL = 200 Ω, output
load is referenced to midsupply, and TA ≈+25°C (unless otherwise noted), see figure 7-1 for schematic configuration. (1) (2)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
GAIN SWITCHES
SW0 OFF to SW1 ON
160
230
80
SW0 OFF to SW2 ON
SW1 OFF to SW0 ON
SW1 OFF to SW2 ON
SW2 OFF to SW0 ON
SW2 OFF to SW1 ON
SWCOM0 ON; SWCOM1 and SWCOM2 OFF
SWCOM1 ON; SWCOM0 and SWCOM2 OFF
SWCOM2 ON; SWCOM0 and SWCOM1 OFF
SWCOM0 , SWCOM1 and SWCOM2 OFF
SW0 ON
Switch transition-time (5)
COM capacitance (3) (6)
FB capacitance (5) (7)
ns
230
80
110
1.3
1.2
1.2
1.2
1.9
1.6
1.5
1.4
1.2
1.1
80
CCOM0
CCOM1
CCOM2
CCOM_OPEN
CFB0
pF
CFB1
SW1 ON
CFB2
SW2 ON
CFB0_OPEN
CFB1_OPEN
CFB2_OPEN
RON_COM0
RON_FB0
RON_COM1
RON_FB1
RON_COM2
RON_FB2
SW0 OFF
SW1 OFF
SW2 OFF
38
125
37
On resistance (8) (9)
Ω
375
35
SWCOM0 for Channel A and B
SWFB0 for Channel A and B
SWCOM1 for Channel A and B
SWFB1 for Channel A and B
SWCOM2 for Channel A and B
SWFB2 for Channel A and B
0.15
0.4
0.45
0.07
3
On resistance channel-to-channel
matching (3) (4)
Ω
0.12
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6.6 Switching Characteristics (continued)
VS+ = 5 V, VS- = 0 V, input common-mode biased at midsupply, RF0 = 1 kΩ, RF1 = 10 kΩ, RF2 = 100 kΩ, RL = 200 Ω, output
load is referenced to midsupply, and TA ≈+25°C (unless otherwise noted), see figure 7-1 for schematic configuration. (1) (2)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
LOGIC PIN FUNCTION (LATCH, SEL)
Logic low below the threshold voltage,
TA = -55°C to +125°C
Logic low threshold
Logic high threshold
VS+ - 1.5 VS+ - 1.3
V
V
Logic high above the threshold voltage,
TA = -55°C to +125°C
VS+ - 1.2 VS+ - 0.8
Bias current
Bias current
Bias current
VPIN = VS- or VS+
6
µA
µA
µA
VPIN = VS- or VS+ , TA = -55°C to +125°C
VPIN at switching threshold
22
160
VPIN at switching threshold,
TA = -55°C to +125°C
Bias current
405
µA
Setup time
Hold time
100
100
ns
ns
(1) All the specifications apply for both Channels A and B, unless otherwise noted.
(2) When switching from one gain condition to another, the new gain switches are closed before opening the previous gain switches
(make-before-break).
(3) SWCOM0, SWCOM1, SWCOM2 refer to switch on the common-mode side (COM) for the different gain options.
(4) SWFB0, SWFB1, SWFB2 refer to switch on the feedback side (FB) for the different gain options.
(5) SW0, SW1, SW2 refers to the two switches needed for a given gain condition. For example, SW0 refers to SWCOM0 and SWFB0
.
(6) CCOM0, CCOM1, CCOM2 is the capacitance at the COM pin for different gain options. It is equal to ON capacitance of closed switch +
OFF capacitance of open switches.
(7) CFB0, CFB1, CFB2 is the capacitance at the FBX pin. It is equal to ON capacitance of the gain option selected (SWCOM0 + SWFB0
capacitance).
(8) RON_COM0, RON_COM1, RON_COM2, refer to ON resistance for the COM side switch.
(9) RON_FB0, RON_FB1, RON_FB2, refer to ON resistance for the FB side switch.
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6.7 Typical Characteristics
VS+ = +2.5 V, VS-= -2.5 V, RL = 200 Ω, CIN = 4 pF, output load is referenced to mid-supply, input common-mode biased at
mid-supply, and TA ≈+25°C (unless otherwise noted)
3
6
3
0
0
-3
-3
-6
-6
-9
-9
RL = 50
RL = 100
RL = 200
RL = 400
RF = 1 kW
RF = 10 kW
RF = 100 kW
-12
-15
-12
-15
1M
10M
Frequency (Hz)
100M
1G
1M
10M
Frequency (Hz)
100M
D001
VOUT = 100 mVPP, RF = 1 kΩ
VOUT = 100 mVPP
图6-2. Small-Signal Frequency Response vs Output Load
图6-1. Small-Signal Frequency Response vs Gain
6
6
3
3
RF = 1 k
0
0
-3
-3
-6
RF = 100 k
-6
-9
125 C
-9
85 C
25 C
-45 C
-55 C
RF = 1 k
RF = 10 k
-12
-15
-12
RF = 10 k
RF = 100 k
-15
1M
10M
100M
1G
1M
10M
100M
1G
Frequency (Hz)
Frequency (Hz)
VOUT = 100 mVPP
VOUT = 2 VPP
图6-3. Small-Singal Frequency Response vs Ambient
图6-4. Large-Signal Frequency Response vs Gain
Temperature
.
VOUT = 100 mVPP
图6-6. Closed-Loop Output Impedance vs Frequency
图6-5. Open-Loop Magnitude and Phase vs Frequency
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6.7 Typical Characteristics (continued)
VS+ = +2.5 V, VS-= -2.5 V, RL = 200 Ω, CIN = 4 pF, output load is referenced to mid-supply, input common-mode biased at
mid-supply, and TA ≈+25°C (unless otherwise noted)
0
-20
100
10
1
RF = 1 k
RF = 10 k
RF = 100 k
-40
-60
-80
-100
-120
100k
1M
10M
100M
1k
10k
100k
Frequency (Hz)
1M
10M
100M
Frequency (Hz)
VOUT = 2 VPP
.
图6-7. Large-Signal Crosstalk vs Gain
图6-8. Voltage Noise Density vs Frequency
1000
100
60
40
20
0
125 C
Input
RF = 10 k
85 C
RF = 1 k
RF = 10 k
RF = 100 k
25 C
-45 C
RF = 100 k
-55 C
RF = 1 k
-20
-40
-60
10
3
10k
100k
1M
10M
100M
Time (100 ns/div)
Frequency (Hz)
VOUT = 100 mVPP
.
图6-10. Small-Signal Transient Response
图6-9. Voltage Noise Density vs Ambient Temperature
1.5
4
3
Input
Ideal Output
RF = 1 k
RF = 10 k
1.25
RF = 1 k
1
RF = 10 k
RF = 100 k
0.75
0.5
2
1
0.25
0
0
-0.25
-0.5
-0.75
-1
-1
-2
-3
-4
-1.25
-1.5
Time (100 ns/div)
VOUT = 2 VPP
Time (100 ns/div)
2X Output Overdrive
图6-11. Large-Signal Transient Response
图6-12. Output Overload Reponse − Low Gain Settings
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6.7 Typical Characteristics (continued)
VS+ = +2.5 V, VS-= -2.5 V, RL = 200 Ω, CIN = 4 pF, output load is referenced to mid-supply, input common-mode biased at
mid-supply, and TA ≈+25°C (unless otherwise noted)
4
3
3.5
3
2.5
2
1.5
1
0.5
0
Ideal Output
RF = 100 k
2
1
0
-0.5
-1
-1.5
-2
-2.5
-3
-3.5
-1
-2
-3
-4
Power Down (PD)
Output: RF= 1 k
Output: RF= 10 k
Output: RF= 100 k
Time (50 ns/div)
.
Time (1 s/div)
2X Output Overdrive
图6-14. Turn-On Transient Response
图6-13. Output Overload Reponse − High Gain Setting
3.5
100
80
60
40
20
0
PSRR+
PSRR−
Power Down (PD)
Output: RF= 1 k
Output: RF= 10 k
Output: RF= 100 k
3
2.5
2
1.5
1
0.5
0
-0.5
-1
-1.5
-2
-2.5
-3
-20
1k
-3.5
10k
100k
1M
10M
100M
1G
Time (50 ns/div)
.
Frequency (Hz)
.
图6-15. Turn-Off Transient Response
图6-16. Power Supply Rejection Ratio vs Frequency
55
47.5
45
50
45
40
35
42.5
40
Unit 1
Unit 2
Unit 3
Unit 1
Unit 2
Unit 3
37.5
3
3.25 3.5 3.75
4
4.25 4.5 4.75
5
5.25
-60 -40 -20
0
20 40 60 80 100 120 140 160
Ambient Temperature (C)
Total Supply Voltage (V)
3 Typical Units
3 Typical Units
图6-17. Quiescent Current (Both Channels) vs Supply Voltage
图6-18. Quiescent Current (Both Channels) vs Ambient
Temperature
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6.7 Typical Characteristics (continued)
VS+ = +2.5 V, VS-= -2.5 V, RL = 200 Ω, CIN = 4 pF, output load is referenced to mid-supply, input common-mode biased at
mid-supply, and TA ≈+25°C (unless otherwise noted)
110
105
100
95
5
4
Unit 1
Unit 2
Unit 3
3
2
90
1
85
80
0
75
-1
-2
-3
-4
-5
70
65
Unit 1
Unit 2
Unit 3
60
55
50
-60 -40 -20
0
20 40 60 80 100 120 140 160
3
3.25 3.5 3.75
4
4.25 4.5 4.75
5
5.25
Temperature (C)
Total Supply Voltage (V)
3 Typical Units
3 Typical Units
图6-19. Quiescent Current (Amplifiers Disabled) vs Ambient
图6-20. Offset Voltage vs Supply Voltage
Temperature
5
4
5
4
Unit 1
Unit 2
Unit 3
3
3
2
2
1
1
0
0
-1
-2
-1
-2
-3
-4
-5
-3
Unit 1
Unit 2
Unit 3
-4
-5
-40 -20
0
20
40
60
80 100 120 140 160
-2.5 -2 -1.5 -1 -0.5
0
0.5
1
1.5
2
2.5
Temperature (C)
Common-Mode Voltage (V)
3 Typical Units
3 Typical Units
图6-21. Offset Voltage vs Ambient Temperature
图6-22. Offset Voltage vs Input Common-Mode Voltage
5
4
5
TA = 125 C
TA = 25 C
TA = -55 C
Unit 1
Unit 2
4
Unit 3
3
3
2
2
1
1
0
0
-1
-2
-3
-4
-5
-1
-2
-3
-4
-5
-2.5 -2 -1.5 -1 -0.5
0
0.5
1
1.5
2
2.5
-2.5 -2 -1.5 -1 -0.5
0
0.5
1
1.5
2
2.5
Common-Mode Voltage (V)
Output Voltage (V)
.
3 Typical Units
图6-23. Offset Voltage vs Input Common-Mode Voltage vs
图6-24. Offset Voltage vs Output Swing
Ambient Temperature
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6.7 Typical Characteristics (continued)
VS+ = +2.5 V, VS-= -2.5 V, RL = 200 Ω, CIN = 4 pF, output load is referenced to mid-supply, input common-mode biased at
mid-supply, and TA ≈+25°C (unless otherwise noted)
5
TA = 125 C
4
TA = 25 C
TA = -55 C
1n
100p
10p
3
2
1
0
-1
-2
-3
-4
-5
1p
Unit 1
Unit 2
Unit 3
0.1p
-40 -20
0
20
40
60
80 100 120 140 160
-2.5 -2 -1.5 -1 -0.5
0
0.5
1
1.5
2
2.5
Temperature (C)
Output Voltage (V)
3 Typical Units
.
图6-26. Input Bias Current vs Ambient Temperature
图6-25. Offset Voltage vs Output Swing vs Ambient
Temperature
20
0
Unit 1
Unit 2
Unit 3
10
TA = 125 C
TA = 25 C
TA = -55 C
-0.25
-0.5
-0.75
-1
15
5
0
-1.25
-1.5
-1.75
-2
-5
-10
-15
-20
-120
-100
-80
-60
-40
-20
0
-2.5
-2
-1.5
-1
-0.5
0
0.5
1
1.5
Output Current (mA)
Common Mode Voltage (V)
.
3 Typical Units
图6-28. Output Swing vs Sinking Current
图6-27. Input Bias Current vs Input Common-Mode Voltage
2
1000
750
500
250
0
TA = 125 C
TA = 25 C
TA = -55 C
1.75
1.5
1.25
1
0.75
0.5
0.25
0
39
40
41
42
43
44
45
46
0
10 20 30 40 50 60 70 80 90 100 110 120
Output Current (mA)
Quiescent Current (mA)
.
µ = 42.2 mA, σ= 0.251 mA
图6-30. Quiescent Current (Both Channels) Distribution
图6-29. Output Swing vs Sourcing Current
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6.7 Typical Characteristics (continued)
VS+ = +2.5 V, VS-= -2.5 V, RL = 200 Ω, CIN = 4 pF, output load is referenced to mid-supply, input common-mode biased at
mid-supply, and TA ≈+25°C (unless otherwise noted)
1000
750
500
250
0
1000
750
500
250
0
-8 -7 -6 -5 -4 -3 -2 -1
0
1
2
3
4
5
6
7
8
-8 -7 -6 -5 -4 -3 -2 -1
0
1
2
3
4
5
6
7
8
Offset Voltage (mV)
Offset Voltage (mV)
µ = 0.450 mV, σ= 0.845 mV
图6-31. Offset Voltage Distribution − Channel A
600
µ = 0.606 mV, σ= 0.754 mV
图6-32. Offset Voltage Distribution − Channel B
600
500
400
300
200
100
0
500
400
300
200
100
0
-1
-0.25
0.5
1.25
2
2.75
-1
-0.25
0.5
1.25
2
2.75
Input Bias Current (pA)
Input Bias Current (pA)
µ = 0.896 pA, σ= 0.383 pA
µ = 0.825 pA, σ= 0.386 pA
图6-33. Input Bias Current Distribution − Channel A
图6-34. Input Bias Current Distribution − Channel B
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7 Parameter Measurement Information
The test setup configuration for OPA3S2859-EP is shown below.
RFB
IN–
FBx
CIN-0/1/2
RON_FB0/1/2
SWFB0/1/2
SWCOM0/1/2
RON_COM0/1/2
COMx
–
+
VOUT
CCOM0/1/2/OPEN
CFB0/1/2/OPEN
CIN+
IN+
图7-1. Switching Characteristics Configuration
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8 Detailed Description
8.1 Overview
The OPA3S2859-EP features dual channel, high-speed, low noise, wide gain bandwidth amplifier with
programmable gain switches to offer a compact, easy-to-use device for wideband transimpedance applications,
high-speed data acquisition systems, and applications with weak signal inputs that require low-noise and high-
gain front ends. Integrated switches allow for multiple gain settings on a single amplifier stage without the need
for an additional multiplexer, therefore minimizing board parasitics.
The OPA3S2859-EP is offered in a 4-mm × 4-mm, 24-pin WQFN package that features multiple feedback (FB)
pins for different gain options to make simple feedback network connection between the amplifier output and
inverting input. The three internally switched feedback paths along with an additional parallel non-switched
feedback path allows for up to four selectable gain configurations.
8.2 Functional Block Diagram
SWCOM2
SWFB2
RON_COM2
RON_FB2
CCOM2
CFB2
SWCOM1
SWFB1
RON_COM1
RON_FB1
CCOM1
CFB1
SWCOM0
SWFB0
RON_COM0
RON_FB0
COM_A
CCOM0
CFB0
CIN-
–
+
VOUT_A
INA+
LATCH_A
SEL0
CIN+
5.03 pF
SEL1
5.03 pF
CIN+
LATCH_B
INB+
+
–
VOUT_B
SWCOM0
SWFB0
RON_COM0
RON_FB0
CIN-
COM_B
CCOM0
CCOM1
CCOM2
CFB0
SWCOM1
SWFB1
RON_COM1
RON_FB1
CFB1
SWCOM2
SWFB2
RON_COM2
RON_FB2
CFB2
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8.3 Feature Description
8.3.1 Programmable Gain
The OPA3S2859-EP features integrated switches that can be used for implementing different gain
configurations. The closed-loop bandwidth and noise of a TIA are affected by the transimpedance gain and
photodiode capacitance. The OPA3S2859-EP has a higher bandwidth in its low-gain configuration for a given
value of photodiode capacitance compared to the high-gain configuration. Increasing the gain of the TIA stage
by a factor of X increases the output signal by a factor X, but the noise contribution from the resistor only
increases by √X. The input-referred noise density of the low-gain configuration is therefore higher than the
input-referred noise density of the high-gain configuration.
OPA3S2859-EP provides control for switching among three independently-configured external feedback
networks using FB_x0, FB_x1, FB_x2 pins, and allows for up to four selectable gain configurations with an
additional parallel non-switched feedback path. The internal switches minimize parasitic contributions to increase
performance compared to external methods. Each switch is optimized for increasing feedback resistor values
ranging from < 1 kΩto > 100 kΩfor wide dynamic range applications. The selected switch path is controlled for
both channels using a 2-wire parallel interface (SEL0 and SEL1).
In many systems it is typical that gain will switch sequentially (also known as adjacent gain switching). For
example, the gain will switch low to medium to high or high to medium to low. When switching between adjacent
gains, the switches feature make-before-break switching, when programmed to a different switch connection, the
previous switch does not change to high impedance state until the new switch is closed, with a typical 80 ns to
230 ns delay when both switches are closed. This feature helps the amplifier from not operating in an open-loop
state when the switches are used in a switched-gain transimpedance configuration.
8.3.2 Slew Rate
The OPA3S2859-EP features a high slew rate of 350 V/µs. The slew rate is a critical parameter in high-speed
pulse applications such as optical time-domain reflectometry (OTDR). The high slew rate implies that the device
accurately reproduces a 2-V, sub 100-ns pulse edge, as seen in 图 6-11. The wide bandwidth and slew rate of
the device make it an excellent amplifier for high-speed signal-chain front ends.
8.3.3 Input and ESD Protection
The OPA3S2859-EP is fabricated on a low-voltage, high-speed, BiCMOS process. The internal, junction
breakdown voltages are low for these small geometry devices, and as a result, all device pins are protected with
internal ESD protection diodes to the power supplies. There are two antiparallel diodes between the inputs of the
amplifier that clamp the inputs during an overrange or fault condition.
8.4 Device Functional Modes
8.4.1 Split-Supply and Single-Supply Operation
The OPA3S2859-EP can be configured with single-sided supplies or split-supplies without degrading
performance. In either case, the thermal pad should be tied to the same voltage as VS-.
8.4.2 Power-Down Mode
The OPA3S2859-EP features a power-down mode to conserve power. Connecting the PD pin low disables the
amplifier thereby reducing the quiescent current and places the output in a high-impedance state.
PD pin has an internal pull up resistor, if the pin is left floating then the device defaults to an ON state. The PD
disable and enable threshold voltages are with reference to the positive supply, as shown in the Electrical
Characteristics section. If the amplifier is configured with the positive supply at 5 V and the negative supply at
ground, then the disable and enable threshold voltages are 3.5 V and 4.2 V, respectively. If the amplifier is
configured with ±2.5 V supplies, then the threshold voltages are at 1 V and 1.7 V.
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8.4.3 Gain Select Mode (SEL)
The OPA3S2859-EP features two pins SEL0 and SEL1 to choose between three different internal switch
networks and an external option. The SELx disable and enable threshold voltages are with reference to the
positive supply as shown in the Switching Characteristics table. Note: while the SELx logic will select the same
switch configuration for channel A and B, the external components (feedback network) of channels A and B do
not have to be exactly the same.
When switching between different gain settings (feedback networks), the device has a transition time of only 80
ns to 230 ns (typical) as shown in the Switching Characteristics table. In many systems, it is typical that gain will
be stepped sequentially (for example, low to medium to high or high to medium to low). The SELx logic
assignment ensures that switching gains up or down involve only one input-pin transition, reducing the
probability of unintended false codes during logic settling, as shown in 表5-2.
8.4.4 Latch Mode
OPA3S2859-EP features LTCH_A and LTCH_B pins which independently latch the gain configuration for
Channel A and Channel B, respectively. If the latch control inputs are connected to logic high or floating, then the
chosen feedback selection (through the SEL0 and SEL1 pins) applies to A and B analog channels immediately,
this is also called transparent mode. If the latch control inputs are logic low, then changing the feedback
selection (through the SEL0 and SEL1 pins) does not affect the gain configuration of the respective amplifier
channel. 图8-1 shows minimum timing requirements that should be met when using LTCH_x pins to latch gain
configuration.
By using the latch control input for each channel, the feedback selection can be controlled separately from the
common SEL1 and SEL0 pins, see an example below. The latch control inputs can also provide benefits in some
cases where channel A and B need to have the same configuration. For example, in transparent mode, when
switching between different gain settings any timing skew from SEL1 and SEL0 may result in unintended switch
logic configurations for a short-duration resulting in transient output glitch. These intermediate glitch states can
be minimized by holding the LTCH_x pin low until the new selection value at SEL pins has settled.
This feature is also useful in larger systems with multiple OPA3S2859-EP devices, the gain path can be set
using common SEL0 and SEL1 signals for all the devices and latch pins can be used to control the gain
independently for each amplifier channel.
Example configuration, to update the gain settings for Channel A only, follow these steps:
1. Set LTCH_B to logic low (latch mode), this way changes made on Channel A do not affect Channel B gain
configuration.
2. If LTCH_A is high (transparent mode), use SEL0 and SEL1 pins to select the feedback network of interest. If
LTCH_A is low, toggle it to logic high and use SEL0 and SEL1 pins to select the feedback network of interest.
3. To hold the selected gain, set LTCH_A to logic low. Ensure minimum setup time requirements (100 ns) are
met between SELx selection to LTCH_A going low. Also, ensure that during the hold time (100 ns), no changes
should be made on SELx pins. The minimum timing is based on internal device configuration, if needed,
additional time must be added due to board layout parasitics and signal delays.
4. Gain setting for channel A is now latched and any changes on SELx pins will not change the gain
configuration for channel A.
Hold time
SELx
LTCH_x
Setup time
图8-1. Timing Diagram
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9 Application and Implementation
备注
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
9.1 Application Information
The OPA3S2859-EP offers a unique combination of dual channel, wide bandwidth low noise amplifiers with
integrated programmable gain switches. This combination makes this amplifier an excellent choice for
photodiode transimpedance amplifier applications with variable gain needs.
9.2 Typical Application
图 9-1 shows the circuit used to measure transimpedance bandwidth of the OPA3S2859-EP with different
feedback network setting options. This configuration imitates the impedance of the photodiode on the input of
the TIA.
100 k
0.7 pF
10 k
1.5 pF
1 k
2.5 V
0,1
0,0
RIN
COM
pin
169
–
+
1,0
VOUT
+
–
–
2.5 V
图9-1. OPA3S2859-EP Test Circuit
9.2.1 Design Requirements
The objective is to design a variable gain, low noise, wideband optical front-end transimpedance amplifier. The
design requirements are:
• Amplifier supply voltage: ± 2.5 V
• Transimpedance gain: 1 kΩ, 10 kΩ, 100 kΩ
• Photodiode capacitance: CAPD = 3.3 pF (additional estimated PCB capacitance = 0.7 pF)
• Target bandwidth: 130 MHz, 40 MHz, 14 MHz
9.2.2 Detailed Design Procedure
The OPA3S2859-EP meets the growing demand for wideband, low-noise photodiode amplifiers. The closed-loop
bandwidth of a transimpedance amplifier is a function of the following:
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1. The total input capacitance (CIN). This total includes the photodiode capacitance, the input capacitance of
the amplifier (common-mode and differential capacitance) and any stray capacitance from the PCB.
2. The op amp gain bandwidth product (GBWP).
3. The transimpedance gain (RF).
图 9-1 shows the OPA3S2859-EP configured as programmable gain TIA using different feedback paths through
the switch network. The feedback resistance (RF) and the input capacitance (CIN) form a zero in the noise gain
that results in instability if left unchecked. To counteract the effect of the zero, a pole is inserted into the noise
gain transfer function by adding the feedback capacitor (CF). The Transimpedance Considerations for High-
Speed Amplifiers Application Report discusses theories and equations that show how to compensate a
transimpedance amplifier for a particular transimpedance gain and input capacitance. The bandwidth and
compensation equations from the application report are available in an Excel® calculator. What You Need To
Know About Transimpedance Amplifiers –Part 1 provides a link to the calculator.
The equations and calculators in the referenced application report and blog posts are used to model the
bandwidth (f–3dB) and noise performance of the OPA3S2859-EP configured as a TIA. For this setup, to emulate
an ideal current source, choose RIN value to be 1 to 10x greater than RF such that the low frequency noise gain
closer to 1 V/V to 2 V/V (RF = 1 kΩ, 10 kΩ, 100 kΩ, RIN = 10 kΩ, 100 kΩ, 100 kΩ; respectively). The resultant
performance is shown in 图 9-2. To maximize bandwidth, make sure to reduce any stray parasitic capacitance
from the PCB. Increasing RF results in lower bandwidth. To maximize the signal-to-noise ratio (SNR) in an
optical front-end system, maximize the gain in the TIA stage.
9.2.3 Application Curves
6
3
0
-3
-6
-9
RF = 1 kW
-12
RF = 10 kW
RF = 100 kW
-15
1M
10M
Frequency (Hz)
100M
1G
OPA3
图9-2. Bandwidth vs Frequency
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10 Power Supply Recommendations
The OPA3S2859-EP operates on supplies from 3.3 V to 5.25 V. The device operates on single-sided supplies,
split and balanced bipolar supplies, and unbalanced bipolar supplies. Because the OPA3S2859-EP does not
feature rail-to-rail inputs or outputs, the input common-mode and output swing ranges are limited at 3.3-V
supplies.
11 Layout
11.1 Layout Guidelines
Achieving optimum performance with a high-frequency amplifier, such as the OPA3S2859-EP, requires careful
attention to board layout parasitics and external component types. Recommendations that optimize performance
include the following:
• Reduce capacitive coupling between feedback traces. Trace-to-trace capacitance between the three
feedback connection traces can cause the traces to couple together at high frequency and effect the gain of
the device. Particularly for high gain feedback configurations, capacitive coupling to feedback paths with
lower gain can significantly reduce the bandwidth if not properly isolated. For example, in a circuit
configuration with 100k, 10k, and 1k feedback elements, the 100k gain path can see over 66% reduction in
bandwidth when using an non-optimized feedback layout. To properly isolate the feedback traces it is
important to space the traces out and pour ground plane between the traces to isolate their capcitance;
additional trace length, however, does add further inductance and capacitance to the traces which can also
effect performance. Therefore, it is important to balance the feedback area and trace length to best minimize
the major parasitic effect. A good starting point is to use a design similar to the evaluation module with a
feedback area of approximately 6 mm × 6 mm. This can then be adjusted depending on circuit limitations and
needs.
• Minimize parasitic capacitance from the signal I/O pins to ac ground. Parasitic capacitance on the
output pins can cause instability where as parasitic capacitance on the input pin reduces the amplifier
bandwidth. To reduce unwanted capacitance, cut out the power and ground traces under the signal input
pins, output pins, and exterior feedback trace when possible. A small value isolation resistor between the
DUT output and feedback network can also help reduce the parasitic loading caused by the feedback trace
on the output. Otherwise, ground and power planes must be unbroken elsewhere on the board.
• Minimize the distance from the power-supply pins to the high-frequency bypass capacitors. Use high-
quality, 100-pF to 0.1-µF, C0G and NPO-type decoupling capacitors with voltage ratings at least three times
greater than the amplifiers maximum power supplies. Place the smallest value capacitors on the same side
as the DUT. If space constraints force the larger value bypass capacitors to be placed on the opposite side of
the PCB, use multiple vias on the supply and ground side of the capacitors. This configuration makes sure
that there is a low-impedance path to the amplifiers power-supply pins across the amplifiers gain bandwidth
specification. Avoid narrow power and ground traces to minimize inductance between the pins and the
decoupling capacitors. Larger (2.2-µF to 6.8-µF) decoupling capacitors that are effective at lower frequency
must be used on the supply pins. Place these decoupling capacitors further from the device. Share the
decoupling capacitors among several devices in the same area of the printed circuit board (PCB).
11.2 Layout Examples
图 11-1 shows a typical layout around the OPA3S2859-EP based on the evaluation module. The smallest
decoupling capacitors were placed as close as possible to the DUT with wide metal area to minimize inductance.
Special attention was placed on the feedback network layout to optimize the design for a typical application
using 1 kΩ, 10 kΩ, and 100 kΩ feedback resistors. Please see 图 11-2 for more details. The black colored areas
under the input and feedback traces show the voids cut in the ground plane underneath the traces to minimize
capacitance to ground as much as possible.
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Ground plane
removed under input,
output, and feedback
traces
INA+
SEL1
VS-
VS+
VS+
PD
Decoupling
capacitors placed
close to DUT
LTCH_A
LTCH_B
SEL0
VS+
VS-
INB+
Ground isolated
feedback traces
图11-1. General Layout Example
图 11-2 shows an example of a feedback network from the evaluation module optimized to reduce the capacitive
coupling between the feedback and output traces. Ground plane is poured between each of the feedback traces
and component footprints as much as possible for the best isolation. A small isoation resistor (RISO) in
connected between the output and feedback trace to help isolate the trace capacitance from being directly
connected to the DUT output. Additionally, the ground plane is removed from under the feedback trace to further
reduce the parasitic capacitance to ground created by the additional trace length required for the feedback
network.
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ROUT
Small resistor to
RF2
CF2
isolate
feedback trace
from output
RF0
CF0
Ground pour to
minimize
feedback trace
coupling
图11-2. Feedback Network Layout Recommendations
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12 Device and Documentation Support
12.1 Device Support
12.1.1 Development Support
• Texas Instruments, Optical Front-End System Reference Design design guide
• Texas Instruments, LIDAR-Pulsed Time-of-Flight Reference Design Using High-Speed Data Converters
design guide
• Texas Instruments, LIDAR Pulsed Time of Flight Reference Design design guide
12.2 Documentation Support
12.2.1 Related Documentation
See the following for related documentation:
• Texas Instruments, OPA3S2859-EP Evaluation Module user's guide
• Texas Instruments, Transimpedance Considerations for High-Speed Amplifiers application report
• Texas Instruments, What You Need To Know About Transimpedance Amplifiers –Part 1 blog
• Texas Instruments, What You Need To Know About Transimpedance Amplifiers –Part 2 blog
• Texas Instruments, Training Video: How to Design Transimpedance Amplifier Circuits
• Texas Instruments, Training Video: High-Speed Transimpedance Amplifier Design Flow
• Texas Instruments, Training Video: How to Convert a TINA-TI Model into a Generic SPICE Model
12.3 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
12.4 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
12.5 Trademarks
TI E2E™ is a trademark of Texas Instruments.
Excel® is a registered trademark of Microsoft Corporation.
所有商标均为其各自所有者的财产。
12.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.7 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
OPA3S2859MRTWREP
XOPA3S2859MRTWREP
ACTIVE
ACTIVE
WQFN
WQFN
RTW
RTW
24
24
3000 RoHS & Green
3000 TBD
NIPDAU
Level-2-260C-1 YEAR
Call TI
-55 to 125
-55 to 125
3S2859
Call TI
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
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28-Dec-2021
Addendum-Page 2
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