OMAP3503 [TI]
Applications Processor; 应用处理器型号: | OMAP3503 |
厂家: | TEXAS INSTRUMENTS |
描述: | Applications Processor |
文件: | 总227页 (文件大小:2954K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
OMAP3515/03 Applications Processor
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1 OMAP3515/03 Applications Processor
1.1 Features
•
External Memory Interfaces:
•
OMAP3515/03 Applications Processor:
–
SDRAM Controller (SDRC)
–
–
OMAP™ 3 Architecture
MPU Subsystem
•
•
•
16, 32-bit Memory Controller With
2G-Byte Total Address Space
Interfaces to Low-Power Double Data
Rate (LPDDR) SDRAM
SDRAM Memory Scheduler (SMS) and
Rotation Engine
•
•
600-MHz ARM Cortex™-A8 Core
NEON™ SIMD Coprocessor
–
2D/3D Graphics Accelerator (OMAP3515
Device Only)
•
Tile Based Architecture Delivering 10
MPoly/sec
–
General Purpose Memory Controller
(GPMC)
•
Universal Scalable Shader Engine:
Multi-threaded Engine Incorporating
Pixel and Vertex Shader Functionality
•
•
•
16-bit Wide Multiplexed Address/Data
Bus
Up to 8 Chip Select Pins With 129M-Byte
Address Space per Chip Select Pin
Glueless Interface to NOR Flash, NAND
Flash (With ECC Hamming Code
•
Industry Standard API Support:
OpenGLES 1.1 and 2.0, OpenVG1.0 and
Direct3D Mobile
•
•
Fine Grained Task Switching, Load
Balancing, and Power Management
Programmable High Quality Image
Anti-Aliasing
Calculation), SRAM and Pseudo-SRAM
•
•
Flexible Asynchronous Protocol Control
for Interface to Custom Logic (FPGA,
CPLD, ASICs, etc.)
Nonmultiplexed Address/Data Mode
(Limited 2K-Byte Address Space)
–
Fully Software-Compatible With ARM9™
•
ARM Cortex™-A8 Core
–
–
ARMv7 Architecture
•
•
System Direct Memory Access (sDMA)
Controller (32 Logical Channels With
Configurable Priority)
•
•
•
Trust Zone®
Thumb®-2
MMU Enhancements
Camera Image Signal Processing (ISP)
In-Order, Dual-Issue, Superscalar
Microprocessor Core
NEON™ Multimedia Architecture
Over 2x Performance of ARMv6 SIMD
Supports Both Integer and Floating Point
SIMD
Jazelle® RCT Execution Environment
Architecture
Dynamic Branch Prediction with Branch
Target Address Cache, Global History
Buffer, and 8-Entry Return Stack
–
–
–
–
CCD and CMOS Imager Interface
Memory Data Input
RAW Data Interface
BT.601/BT.656 Digital YCbCr 4:2:2
(8-/16-Bit) Interface
A-Law Compression and Decompression
Preview Engine for Real-Time Image
Processing
Glueless Interface to Common Video
Decoders
Histogram Module/Auto-Exposure,
Auto-White Balance, and Auto-Focus
Engine
–
–
–
–
–
–
–
–
–
–
Embedded Trace Macrocell (ETM) Support
for Non-Invasive Debug
•
•
ARM Cortex™-A8 Memory Architecture:
–
Resize Engine
–
–
–
16K-Byte Instruction Cache (4-Way
Set-Associative)
16K-Byte Data Cache (4-Way
Set-Associative)
•
•
Resize Images From 1/4x to 4x
Separate Horizontal/Vertical Control
•
Display Subsystem
Parallel Digital Output
–
256K-Byte L2 Cache
•
•
Up to 24-Bit RGB
HD Maximum Resolution
Endianess: ARM Big Endian
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this document.
is a trademark of ~ Texas Instruments.
All other trademarks are the property of their respective owners.
PRODUCT PREVIEW information concerns products in the
formative or design phase of development. Characteristic data and
other specifications are design goals. Texas Instruments reserves
the right to change or discontinue these products without notice.
Copyright © 2008, Texas Instruments Incorporated
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SPRS505–FEBRUARY 2008
•
•
Supports Up to 2 LCD Panels
Support for Remote Frame Buffer
Interface (RFBI) LCD Panels
Association [IrDA] and Consumer Infrared
[CIR] Modes)
Three Master/Slave High-Speed
–
Inter-Integrated Circuit (I2C) Controllers
–
2 10-Bit Digital-to-Analog Converters
(DACs) Supporting:
•
•
Removable Media Interfaces:
•
•
Composite NTSC/PAL Video
Luma/Chroma Separate Video (S-Video)
–
Three Multimedia Card (MMC)/ Secure
Digital (SD) With Secure Data I/O (SDIO)
–
–
–
–
Rotation 90-, 180-, and 270-degrees
Resize Images From 1/4x to 8x
Color Space Converter
Comprehensive Power, Reset, and Clock
Management
–
–
SmartReflex™ Technology
Dynamic Voltage and Frequency Scaling
(DVFS)
8-bit Alpha Blending
•
Serial Communication
•
Test Interfaces
–
5 Multichannel Buffered Serial Ports
(McBSPs)
–
IEEE-1149.1 (JTAG) Boundary-Scan
Compatible
•
•
•
512 Byte Transmit/Receive Buffer
(McBSP1/3/4/5)
5K-Byte Transmit/Receive Buffer
(McBSP2)
SIDETONE Core Support (McBSP2 and 3
Only) For Filter, Gain, and Mix
Operations
–
–
Embedded Trace Macro Interface (ETM)
Serial Data Transport Interface (SDTI)
•
•
•
•
12 32-bit General Purpose Timers
2 32-bit Watchdog Timers
1 32-bit 32-kHz Sync Timer
Up to 188 General-Purpose I/O (GPIO) Pins
(Multiplexed With Other Device Functions)
•
•
Direct Interface to I2S and PCM Device
and TDM Buses
128 Channel Transmit/Receive Mode
•
•
65-nm CMOS Technology
–
–
–
Four Master/Slave Multichannel Serial Port
Interface (McSPI) Ports
High-Speed/Full-Speed/Low-Speed USB
OTG Controller (12-/8-Pin ULPI Interface)
High-Speed/Full-Speed/Low-Speed
Multiport USB Host Controller
Package-On-Package (POP) Implementation
for Memory Stacking (CBB Package Only)
•
Packages:
–
515-pin PBGA Package (CBB Suffix), .5mm
Ball Pitch (Top), .4mm Ball Pitch (Bottom)
–
423-pin PBGA Package (CUS Suffix), .65mm
Ball Pitch
•
12-/8-Pin ULPI Interface or 6-/4-/3-Pin
Serial Interface
•
•
3.3-V and 1.8-V I/O, 0.8-V to 1.8-V Adaptive
Core Voltage
•
Supports Transceiverless Link Logic
(TLL)
Applications:
–
–
One HDQ/1-Wire Interface
Three UARTs (One with Infrared Data
–
TBD
2
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1.2 Description
OMAP3515 and OMAP3503 high-performance, applications processors are based on the enhanced
OMAP™ 3 architecture.
The OMAP™ 3 architecture is designed to provide best-in-class video, image, and graphics processing
sufficient to support the following:
•
•
•
•
•
Streaming video
2D/3D mobile gaming
Video conferencing
High-resolution still image
Video capture in 2.5G wireless terminals, 3G wireless terminals, and rich multimedia-featured
handsets, and high-performance personal digital assistants (PDAs).
The device supports high-level operating systems (OSs), such as:
•
•
•
•
Windows CE
Symbian OS
Linux
Palm OS
This OMAP device includes state-of-the-art power-management techniques required for high-performance
mobile products.
The following subsystems are part of the device:
•
•
Microprocessor unit (MPU) subsystem based on the ARM Cortex™-A8 microprocessor
SGX530 subsystem for 2D and 3D graphics acceleration to support display and gaming effects
(3515only)
•
•
Camera image signal processor (ISP) that supports multiple formats and interfacing options connected
to a wide variety of image sensors
Display subsystem with a wide variety of features for multiple concurrent image manipulation, and a
programmable interface supporting a wide variety of displays. The display subsystem also supports
NTSC/PAL video out.
•
Level 3 (L3) and level 4 (L4) interconnects that provide high-bandwidth data transfers for multiple
initiators to the internal and external memory controllers and to on-chip peripherals
The device also offers:
•
A comprehensive power and clock-management scheme that enables high-performance, low-power
operation, and ultralow-power standby features. The device also supports SmartReflex™ adaptative
voltage control. This power management technique for automatic control of the operating voltage of a
module reduces the active power consumption.
•
Memory stacking feature using the package-on-package (POP) implementation (CBB package only)
OMAP3515/03 devices are available in a 515-pin PBGA package (CBB suffix) and a 423-pin PBGA
package (CUS suffix). Some features of the CBB package are not available in the CUS package.
Table 1-1 lists the differences between the CBB and CUS packages.
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Table 1-1. Differences Between CBB and CUS Packages
Feature
Pin Assignments
CBB Package
CUS Package
Pin assignments are different from the CUS
package. For CUS package pin assignments, see
Table 2-2, Ball Characteristics (CUS Package).
For CBB package pin assignments, see Table 2-1,
Ball Characteristics (CBB Package).
Package-On-Package (POP)
Interface
POP interface supported.
Eight chip select pins available.
Four wait pins available.
POP interface not available.
Chip select pins gpmc_ncs1 and gpmc_ncs2 are
not available.
GPMC
Wait pins gpmc_wait1 and gpmc_wait2 are not
available.
The following signals are available on two pins
(double muxed): uart2_cts (AF6/AB26), uart2_rts
(AE6/AB25), uart2_tx (AF5/AA25), and uart2_rx
(AE5/AD25).
The following signals are available on one pin
only: uart2_cts (V6), uart2_rts (V5), uart2_tx
(W4), and uart2_rx (V4).
UART2
The following signals are available on three pins
(triple muxed): mcbsp3_dx (AF6/AB26/V21),
mcbsp3_dr (AE6/AB25/U21), mcbsp3_clkx
The following signals are available on two pins
only (double muxed): mcbsp3_dx (V6/W18),
mcbsp3_dr (V5/Y18), mcbsp3_clkx (W4/V18),
McBSP3
GP Timer
McBSP4
(AF5/AA25/W21), and mcbsp3_fsx (AE5/AD25/K26). and mcbsp3_fsx (V4/AA19).
The following signals are available on three pins
(triple muxed): gpt8_pwm_evt (N8/AD25/V3),
gpt9_pwm_evt (T8/AB26/Y2), gpt10_pwm_evt
(R8/AB25/Y3), and gpt11_pwm_evt (P8/AA25/Y4).
The following signals are available on two pins
only (double muxed): gpt8_pwm_evt (G4/M4),
gpt9_pwm_evt (F4/N4), gpt10_pwm_evt (G5/N3),
and gpt11_pwm_evt (F3/M5).
The following signals are available on two pins
(double muxed): mcbsp4_clkx (T8/AE1), mcbsp4_dr
(R8/AD1), mcbsp4_dx (P8/AD2), and mcbsp4_fsx
(N8/AC1).
The following signals are available on one pin
only: mcbsp4_clkx (F4), mcbsp4_dr (G5),
mcbsp4_dx (F3), and mcbsp4_fsx (G4).
HSUSB3_TLL
MM_FSUSB3
Supported.
Supported.
Not Supported.
Not Supported.
Chip select pins mcspi1_cs1 and mcspi1_cs2 are
not available.
McSPI1
Four chip select pins are available.
The following signals are available on two pins
(double muxed): mmc3_cmd (AC3/AE10) and
mmc3_clk (AB1/AF10).
The following signals are available on one pin
only: mmc3_cmd (AD3) and mmc3_clk (AC1).
MMC3
A maximum of 170 GPIO pins are supported.
The following GPIO pins are not available:
gpio_112, gpio_113, gpio_114, gpio_115,
gpio_52, gpio_53, gpio_63, gpio_64, gpio_144,
gpio_145, gpio_146, gpio_147, gpio_152,
gpio_153, gpio_154, gpio_155, gpio_175, and
gpio_176.
GPIO
PLL
A maximum of 188 GPIO pins are supported.
The adpllv2d_dithering_en2 pin is supported.
Pin muxing restricts the total number of GPIO
pins available at one time. For more details, see
Table 2-4, Multiplexing Characteristics (CUS
Pkg.).
The adpllv2d_dithering_en2 pin is not supported.
This OMAP3515/03 Applications Processor data manual presents the electrical and mechanical
specifications for the OMAP3515/03 Applications Processor. It consists of the following sections:
•
A description of the OMAP3515/03 terminals: assignment, electrical characteristics, multiplexing, and
functional description (Section 2)
•
A presentation of the electrical characteristics requirements: power domains, operating conditions,
power consumption, and dc characteristics (Section 3)
•
•
•
•
The clock specifications: input and output clocks, DPLL and DLL (Section 4)
The video DAC specification (Section 5)
The timing requirements and switching characteristics (ac timings) of the interfaces (Section 6)
A description of thermal characteristics, device nomenclature, and mechanical data about the available
packaging (Section 7)
4
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1.3 Functional Block Diagram
Figure 1-1 shows the functional block diagram of the OMAP3515/03 Applications Processor.
Dual-
Camera
(serial and
Parallel)
OMAP Applications Processor
CVBS
or
S-Video
LCD Panel
MPU
Subsystem
Amp
TV
ARM Cortex-
Serial Parallel
Camera
ISP
Image
Capture
Hardware
Image
Pipeline
and
Preview
A8TM Core
TrustZone
16K/16K L1$
HS USB
Host
(with
USB
TTL)
HS
Dual Output 3-Layer
Display Processor
(1xGraphics, 2xVideo)
Temporal Dithering
SDTV®QCIF Support
2D/3D
Graphics
Accelerator
(3515 Only)
32
Channel
System
DMA
USB
OTG
L2$
256K
64
Async
64
64
64
32
32
32 32
32
64
32
L3 Interconnect Network-Hierarchial, Performance, and Power Driven
32 64 32 32
SMS:
32
64K
32
L4 Interconnect
112K
SDRAM
Memory
Scheduler/
Rotation
On-Chip
RAM
2KB
Public/
62KB
Secure
On-Chip
ROM
80KB
Secure/
32KB
BOOT
GPMC:
General
Purpose
Memory
Controller
NAND/
System
Controls
PRCM
Peripherals:
3xUART, 3xHigh-Speed I2C,
5xMcBSP
(2x with Sidetone/Audio Buffer)
4xMcSPI, 6xGPIO,
3xHigh-Speed MMC/SDIO,
HDQ/1 Wire,
2xSmartReflexTM
Control
Module
NOR
Flash,
SRAM
SDRC:
SDRAM
Memory
Controller
2xMailboxes
12xGPTimers, 2xWDT,
32K Sync Timer
External
Peripherals
Interfaces
Emulation
Debug: SDTI, ETM, JTAG,
External and
Stacked Memories
CoresightTM DAP
Figure 1-1. OMAP3515/03 Functional Block Diagram
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Contents
1
2
OMAP3515/03 Applications Processor.............. 1
5
VIDEO DAC SPECIFICATIONS ..................... 122
1.1 Features .............................................. 1
1.2 Description............................................ 3
1.3 Functional Block Diagram ............................ 5
TERMINAL DESCRIPTION.............................. 7
2.1 Terminal Assignment ................................. 7
2.2 Ball Characteristics.................................. 10
2.3 Multiplexing Characteristics ......................... 57
2.4 Signal Description ................................... 72
ELECTRICAL CHARACTERISTICS.................. 96
3.1 Power Domains ..................................... 96
3.2 Absolute Maximum Ratings ......................... 98
3.3 Recommended Operating Conditions ............. 100
3.4 DC Electrical Characteristics....................... 101
3.5 Core Voltage Decoupling .......................... 103
3.6 Power-up and Power-down ........................ 105
CLOCK SPECIFICATIONS........................... 108
4.1 Input Clock Specifications ......................... 109
4.2 Output Clock Specifications........................ 114
4.3 DPLL and DLL Specifications...................... 116
5.1 Interface Description ............................... 122
5.2
Electrical Specifications Over Recommended
Operating Conditions .............................. 124
5.3
Analog Supply (vdda_dac) Noise Requirements .. 126
5.4 External Component Value Choice ................ 127
TIMING REQUIREMENTS AND SWITCHING
6
CHARACTERISTICS.................................. 128
6.1 Timing Test Conditions ............................ 128
6.2 Interface Clock Specifications ..................... 128
6.3 Timing Parameters................................. 129
6.4 External Memory Interfaces........................ 130
6.5 Video Interfaces.................................... 152
6.6 Serial Communications Interfaces ................. 169
6.7 Removable Media Interfaces ...................... 201
6.8 Test Interfaces ..................................... 216
PACKAGE CHARACTERISTICS.................... 222
7.1 Package Thermal Resistance...................... 222
7.2 Device Support..................................... 222
3
4
7
6
Contents
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2 TERMINAL DESCRIPTION
2.1 Terminal Assignment
Figure 2-1, Figure 2-2, and Figure 2-3 show the ball locations for the 515- and 423- ball plastic ball grid
array (PBGA) packages. Table 2-1 through Table 2-24 indicate the signal names and ball grid numbers for
both packages.
Note: There are no balls present on the top of the 423-ball PBGA package.
AH
AG
AF
AE
AD
AC
AB
AA
Y
W
V
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
1
3
5
7
9
11
13
17
19
21
23
25
27
15
2
4
6
8
10
12
14
16
18
20
22
24
26
28
030-001
Figure 2-1. OMAP3515/03 Applications Processor CBB S-PBGA-N515 Package (Bottom View)
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AC
AB
AA
Y
W
V
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
1
5
7
9
11
13
15
17
19
21
23
3
2
4
6
8
10
12
14
16
18
20
22
030-002
Balls A1, A2, A22, A23, AB1, AB2, AB22, AB23, AC1, AC2, AC22, AC23, B1, B2, B22, and B23 are unused.
Figure 2-2. OMAP3515/03 Applications Processor CBB S-PBGA-N515 Package (Top View)
8
TERMINAL DESCRIPTION
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AD
AC
AB
AA
Y
W
V
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
Figure 2-3. OMAP3515/03 Applications Processor CUS-PBGA-N423 Package (Bottom View)
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2.2 Ball Characteristics
Table 2-1 and Table 2-2 describe the terminal characteristics and the signals multiplexed on each pin for
the CBB and CUS package, respectively. The following list describes the table column headers:
1. BALL BOTTOM: Ball number(s) on the bottom side associated with each signal(s) on the bottom.
2. BALL TOP: Ball number(s) on the top side associated with each signal(s) on the top.
3. PIN NAME: Names of signals multiplexed on each ball (also notice that the name of the pin is the
signal name in mode 0).
Note: Table 2-1 and Table 2-2 do not take into account subsystem pin multiplexing options.
Subsystem pin multiplexing options are described in Section 2.4, Signal Descriptions.
4. MODE: Multiplexing mode number.
a. Mode 0 is the primary mode; this means that when mode 0 is set, the function mapped on the pin
corresponds to the name of the pin. There is always a function mapped on the primary mode.
Notice that primary mode is not necessarily the default mode.
Note: The default mode is the mode which is automatically configured on release of the internal
GLOBAL_PWRON reset; also see the RESET REL. MODE column.
b. Modes 1 to 7 are possible modes for alternate functions. On each pin, some modes are effectively
used for alternate functions, while some modes are not used and do not correspond to a functional
configuration.
5. TYPE: Signal direction
–
–
–
–
–
–
I = Input
O = Output
I/O = Input/Output
D = Open drain
DS = Differential
A = Analog
Note: In the safe_mode, the buffer is configured in high-impedance.
6. BALL RESET STATE: The state of the terminal at reset (power up).
–
0: The buffer drives VOL (pulldown/pullup resistor not activated)
0(PD): The buffer drives VOL with an active pulldown resistor.
1: The buffer drives VOH (pulldown/pullup resistor not activated)
1(PU): The buffer drives VOH with an active pullup resistor.
Z: High-impedance
–
–
–
–
L: High-impedance with an active pulldown resistor
H : High-impedance with an active pullup resistor
7. BALL RESET REL. STATE: The state of the terminal at reset release.
–
0: The buffer drives VOL (pulldown/pullup resistor not activated)
0(PD): The buffer drives VOL with an active pulldown resistor.
1: The buffer drives VOH (pulldown/pullup resistor not activated)
1(PU): The buffer drives VOH with an active pullup resistor.
Z: High-impedance
–
–
–
–
L: High-impedance with an active pulldown resistor
H : High-impedance with an active pullup resistor
8. RESET REL. MODE: This mode is automatically configured on release of the internal
GLOBAL_PWRON reset.
9. POWER: The voltage supply that powers the terminal’s I/O buffers.
10. HYS: Indicates if the input buffer is with hysteresis.
11. BUFFER STRENGTH: Drive strength of the associated output buffer.
12. PULL U/D - TYPE: Denotes the presence of an internal pullup or pulldown resistor. Pullup and
pulldown resistors can be enabled or disabled via software.
10
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Note: The pullup/pulldown drive strength is equal to 100 µA except for CBB balls P27, P26, R27, and
R25 and CUB balls N22, N21, N20, and P24, which the pulldown drive strength is equal to 1.8 kΩ.
13. IO CELL: IO cell information.
Note: Configuring two pins to the same input signal is not supported as it can yield unexpected results.
This can be easily prevented with the proper software configuration.
Table 2-1. Ball Characteristics (CBB Pkg.)(1)
BALL
BALL
PIN
MODE TYPE BALL
BALL RESET POWER [9] HYS
BUFFER
PULL
IO
BOTTOM TOP
NAME [3]
[4]
[5]
RESET RESET
REL.
MODE
[8]
[10] STRENGTH
(mA) [11]
U/D CELL [13]
TYPE
[12]
[1]
[2]
STATE
[6]
REL.
STATE
[7]
D6
C6
J2
J1
sdrc_d0
sdrc_d1
sdrc_d2
sdrc_d3
sdrc_d4
sdrc_d5
sdrc_d6
sdrc_d7
sdrc_d8
sdrc_d9
sdrc_d10
sdrc_d11
sdrc_d12
sdrc_d13
sdrc_d14
sdrc_d15
sdrc_d16
sdrc_d17
sdrc_d18
sdrc_d19
sdrc_d20
sdrc_d21
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
VDDS_ MEM Yes
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
PU/
PD
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
VDDS_ MEM Yes
VDDS_ MEM Yes
VDDS_ MEM Yes
VDDS_ MEM Yes
VDDS_ MEM Yes
VDDS_ MEM Yes
VDDS_ MEM Yes
VDDS_ MEM Yes
VDDS_ MEM Yes
VDDS_ MEM Yes
VDDS_ MEM Yes
VDDS_ MEM Yes
VDDS_ MEM Yes
VDDS_ MEM Yes
VDDS_ MEM Yes
VDDS_ MEM Yes
VDDS_ MEM Yes
VDDS_ MEM Yes
VDDS_ MEM Yes
VDDS_ MEM Yes
VDDS_ MEM Yes
PU/
PD
B6
G2
G1
F2
PU/
PD
C8
PU/
PD
C9
PU/
PD
A7
F1
PU/
PD
B9
D2
PU/
PD
A9
D1
PU/
PD
C14
B14
C15
B16
D17
C17
B17
D18
D11
B10
C11
D12
C12
A11
B13
A13
B14
A14
B16
A16
B19
A19
B3
PU/
PD
PU/
PD
PU/
PD
PU/
PD
PU/
PD
PU/
PD
PU/
PD
PU/
PD
PU/
PD
A3
PU/
PD
B5
PU/
PD
A5
PU/
PD
B8
PU/
PD
A8
PU/
PD
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TERMINAL DESCRIPTION
11
OMAP3515/03 Applications Processor
www.ti.com
SPRS505–FEBRUARY 2008
Table 2-1. Ball Characteristics (CBB Pkg.)(1) (continued)
BALL
BOTTOM TOP
BALL
PIN
NAME [3]
MODE TYPE BALL
BALL RESET POWER [9] HYS
BUFFER
PULL
IO
U/D CELL [13]
TYPE
[4]
[5]
RESET RESET
REL.
MODE
[8]
[10] STRENGTH
(mA) [11]
[1]
[2]
STATE
[6]
REL.
STATE
[7]
[12]
B13
D14
C18
A19
B19
B20
D20
A21
B21
C21
B9
sdrc_d22
sdrc_d23
sdrc_d24
sdrc_d25
sdrc_d26
sdrc_d27
sdrc_d28
sdrc_d29
sdrc_d30
sdrc_d31
0
0
0
0
0
0
0
0
0
0
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
L
L
L
L
L
L
L
L
L
L
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
0
0
0
0
0
0
0
0
0
0
VDDS_ MEM Yes
4
4
4
4
4
4
4
4
4
4
PU/
PD
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
A9
VDDS_ MEM Yes
VDDS_ MEM Yes
VDDS_ MEM Yes
VDDS_ MEM Yes
VDDS_ MEM Yes
VDDS_ MEM Yes
VDDS_ MEM Yes
VDDS_ MEM Yes
VDDS_ MEM Yes
PU/
PD
B21
A21
D22
D23
E22
E23
G22
G23
PU/
PD
PU/
PD
PU/
PD
PU/
PD
PU/
PD
PU/
PD
PU/
PD
PU/
PD
H9
H10
A4
AB21
AC21
N22
N23
P22
P23
R22
R23
T22
sdrc_ba0
sdrc_ba1
sdrc_a0
sdrc_a1
sdrc_a2
sdrc_a3
sdrc_a4
sdrc_a5
sdrc_a6
sdrc_a7
sdrc_a8
sdrc_a9
sdrc_a10
sdrc_a11
sdrc_a12
sdrc_a13
sdrc_a14
sdrc_ncs0
sdrc_ncs1
sdrc_clk
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
IO
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
L
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
VDDS_ MEM No
VDDS_ MEM No
VDDS_ MEM No
VDDS_ MEM No
VDDS_ MEM No
VDDS_ MEM No
VDDS_ MEM No
VDDS_ MEM No
VDDS_ MEM No
VDDS_ MEM No
VDDS_ MEM No
VDDS_ MEM No
VDDS_ MEM No
VDDS_ MEM No
VDDS_ MEM No
VDDS_ MEM No
VDDS_ MEM No
VDDS_ MEM No
VDDS_ MEM No
VDDS_ MEM Yes
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
B4
B3
C5
C4
D5
C3
C2
C1
D4
D3
D2
D1
E2
T23
U22
U23
V22
V23
W22
W23
Y22
M22
M23
A11
E1
H11
H12
A13
PU/
PD
A14
H16
B11
J22
sdrc_nclk
sdrc_cke0
safe_mode
sdrc_cke1
safe_mode
sdrc_nras
sdrc_ncas
0
0
7
0
7
0
0
O
O
1
1
1
0
7
VDDS_ MEM No
VDDS_ MEM Yes
4
4
NA
LVCMOS
LVCMOS
H
PU/
PD
H17
J23
O
H
1
7
VDDS_ MEM Yes
4
PU/
PD
LVCMOS
H14
H13
L23
L22
O
O
1
1
1
1
0
0
VDDS_ MEM No
VDDS_ MEM No
4
4
NA
NA
LVCMOS
LVCMOS
12
TERMINAL DESCRIPTION
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OMAP3515/03 Applications Processor
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SPRS505–FEBRUARY 2008
Table 2-1. Ball Characteristics (CBB Pkg.)(1) (continued)
BALL
BALL
PIN
MODE TYPE BALL
BALL RESET POWER [9] HYS
BUFFER
PULL
IO
BOTTOM TOP
NAME [3]
[4]
[5]
RESET RESET
REL.
MODE
[8]
[10] STRENGTH
(mA) [11]
U/D CELL [13]
TYPE
[12]
[1]
[2]
STATE
[6]
REL.
STATE
[7]
H15
B7
K23
C1
sdrc_nwe
sdrc_dm0
sdrc_dm1
sdrc_dm2
sdrc_dm3
sdrc_dqs0
0
0
0
0
0
0
O
O
O
O
O
IO
1
0
0
0
0
L
1
0
0
0
0
Z
0
0
0
0
0
0
VDDS_ MEM No
4
4
4
4
4
4
NA
NA
NA
NA
NA
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
VDDS_ MEM No
VDDS_ MEM No
VDDS_ MEM No
VDDS_ MEM No
VDDS_ MEM Yes
A16
B11
C20
A6
A17
A6
A20
C2
PU/
PD
A17
A10
A20
N4
B17
B6
sdrc_dqs1
sdrc_dqs2
sdrc_dqs3
0
0
0
IO
IO
IO
L
L
L
L
Z
Z
Z
L
0
0
0
7
VDDS_ MEM Yes
VDDS_ MEM Yes
VDDS_ MEM Yes
VDDS_ MEM Yes
4
4
4
4
PU/
PD
LVCMOS
LVCMOS
LVCMOS
LVCMOS
PU/
PD
B20
AC15
PU/
PD
gpmc_a1
gpio_34
0
4
7
0
4
7
0
4
7
0
4
7
0
4
7
0
4
7
0
4
7
0
4
7
0
1
O
PU/
PD
IO
safe_mode
gpmc_a2
gpio_35
M4
L4
AB15
AC16
AB16
AC17
AB17
AC18
AB18
AC19
O
L
L
L
L
7
7
7
7
7
7
7
7
VDDS_ MEM Yes
VDDS_ MEM Yes
VDDS_ MEM Yes
VDDS_ MEM Yes
VDDS_ MEM Yes
VDDS_ MEM Yes
VDDS_ MEM Yes
VDDS_ MEM Yes
4
4
4
4
4
4
4
4
PU/
PD
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
IO
safe_mode
gpmc_a3
gpio_36
O
PU/
PD
IO
safe_mode
gpmc_a4
gpio_37
K4
T3
R3
N3
M3
L3
O
L
L
PU/
PD
IO
safe_mode
gpmc_a5
gpio_38
O
L
L
PU/
PD
IO
safe_mode
gpmc_a6
gpio_39
O
H
H
H
H
H
H
H
H
PU/
PD
IO
safe_mode
gpmc_a7
gpio_40
O
PU/
PD
IO
safe_mode
gpmc_a8
gpio_41
O
PU/
PD
IO
safe_mode
gpmc_a9
O
I
PU/
PD
sys_
ndmareq2
gpio_42
4
7
0
1
IO
safe_mode
K3
AB19 gpmc_a10
O
I
H
H
7
VDDS_ MEM Yes
4
PU/
PD
LVCMOS
sys_
ndmareq3
gpio_43
4
IO
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TERMINAL DESCRIPTION
13
OMAP3515/03 Applications Processor
www.ti.com
SPRS505–FEBRUARY 2008
Table 2-1. Ball Characteristics (CBB Pkg.)(1) (continued)
BALL
BOTTOM TOP
BALL
PIN
NAME [3]
MODE TYPE BALL
BALL RESET POWER [9] HYS
BUFFER
PULL
IO
U/D CELL [13]
TYPE
[4]
[5]
RESET RESET
REL.
MODE
[8]
[10] STRENGTH
(mA) [11]
[1]
[2]
STATE
[6]
REL.
STATE
[7]
[12]
safe_mode
gpmc_d0
7
0
K1
L1
M2
M1
N2
N1
R2
R1
T2
IO
IO
IO
IO
IO
IO
IO
IO
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
0
0
0
0
0
0
0
0
0
VDDS_ MEM Yes
4
4
4
4
4
4
4
4
4
PU/
PD
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
gpmc_d1
gpmc_d2
gpmc_d3
gpmc_d4
gpmc_d5
gpmc_d6
gpmc_d7
0
0
0
0
0
0
0
VDDS_ MEM Yes
VDDS_ MEM Yes
VDDS_ MEM Yes
VDDS_ MEM Yes
VDDS_ MEM Yes
VDDS_ MEM Yes
VDDS_ MEM Yes
VDDS_ MEM Yes
PU/
PD
L2
PU/
PD
P2
T1
V1
V2
W2
H2
PU/
PD
PU/
PD
PU/
PD
PU/
PD
T1
PU/
PD
AB3
gpmc_d8
gpio_44
0
4
7
0
4
7
0
4
7
0
4
7
0
4
7
0
4
7
0
4
7
0
4
7
0
0
4
7
0
4
IO
IO
PU/
PD
safe_mode
gpmc_d9
gpio_45
K2
P1
R1
R2
T2
AC3
AB4
AC4
AB6
AC6
AB7
AC7
IO
IO
H
H
H
H
H
H
H
H
H
H
H
H
H
H
0
0
0
0
0
0
0
VDDS_ MEM Yes
VDDS_ MEM Yes
VDDS_ MEM Yes
VDDS_ MEM Yes
VDDS_ MEM Yes
VDDS_ MEM Yes
VDDS_ MEM Yes
4
4
4
4
4
4
4
PU/
PD
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
safe_mode
gpmc_d10
gpio_46
IO
IO
PU/
PD
safe_mode
gpmc_d11
gpio_47
IO
IO
PU/
PD
safe_mode
gpmc_d12
gpio_48
IO
IO
PU/
PD
safe_mode
gpmc_d13
gpio_49
IO
IO
PU/
PD
safe_mode
gpmc_d14
gpio_50
W1
Y1
IO
IO
PU/
PD
safe_mode
gpmc_d15
gpio_51
IO
IO
PU/
PD
safe_mode
gpmc_ncs0
gpmc_ncs1
gpio_52
G4
H3
Y2
Y1
O
O
1
1
1
0
0
VDDS_ MEM No
VDDS_ MEM Yes
4
4
NA
LVCMOS
LVCMOS
H
PU/
PD
IO
safe_mode
gpmc_ncs2
gpio_53
V8
NA
O
H
H
7
VDDS_ MEM Yes
4
PU/
PD
LVCMOS
IO
14
TERMINAL DESCRIPTION
Submit Documentation Feedback
OMAP3515/03 Applications Processor
www.ti.com
SPRS505–FEBRUARY 2008
Table 2-1. Ball Characteristics (CBB Pkg.)(1) (continued)
BALL
BALL
PIN
MODE TYPE BALL
BALL RESET POWER [9] HYS
BUFFER
PULL
IO
BOTTOM TOP
NAME [3]
[4]
[5]
RESET RESET
REL.
MODE
[8]
[10] STRENGTH
(mA) [11]
U/D CELL [13]
TYPE
[12]
[1]
[2]
STATE
[6]
REL.
STATE
[7]
safe_mode
gpmc_ncs3
7
0
1
U8
NA
O
I
H
H
H
H
7
7
VDDS_ MEM Yes
4
4
PU/
PD
LVCMOS
LVCMOS
sys_
ndmareq0
gpio_54
4
7
0
1
IO
safe_mode
gpmc_ncs4
T8
NA
O
I
VDDS_ MEM Yes
PU/
PD
sys_
ndmareq1
mcbsp4_
clkx
2
3
IO
IO
IO
gpt9_pwm_
evt
gpio_55
4
7
0
1
safe_mode
gpmc_ncs5
R8
P8
N8
NA
NA
NA
O
I
H
H
H
H
H
H
7
7
7
VDDS_ MEM Yes
VDDS_ MEM Yes
VDDS_ MEM Yes
4
4
4
PU/
PD
LVCMOS
LVCMOS
LVCMOS
sys_
ndmareq2
mcbsp4_dr
2
3
I
gpt10_pwm
_evt
IO
gpio_56
4
7
0
1
IO
safe_mode
gpmc_ncs6
O
I
PU/
PD
sys_
ndmareq3
mcbsp4_dx
2
3
IO
IO
gpt11_pwm
_evt
gpio_57
4
7
0
1
2
3
IO
safe_mode
gpmc_ncs7
gpmc_io_dir
mcbsp4_fsx
O
O
PU/
PD
IO
IO
gpt8_pwm_
evt
gpio_58
safe_mode
gpmc_clk
gpio_59
4
7
0
4
7
0
IO
T4
F3
W2
W1
O
L
0
0
0
0
0
VDDS_ MEM Yes
VDDS_ MEM No
4
4
PU/
PD
LVCMOS
LVCMOS
IO
safe_mode
gpmc_nadv
_ale
O
NA
G2
F4
G3
V2
V1
gpmc_noe
gpmc_nwe
0
0
0
O
O
O
1
1
L
1
1
0
0
0
0
VDDS_ MEM No
VDDS_ MEM No
VDDS_ MEM Yes
4
4
4
NA
NA
LVCMOS
LVCMOS
LVCMOS
AC12 gpmc_nbe0
_cle
PU/
PD
gpio_60
4
IO
Submit Documentation Feedback
TERMINAL DESCRIPTION
15
OMAP3515/03 Applications Processor
www.ti.com
SPRS505–FEBRUARY 2008
Table 2-1. Ball Characteristics (CBB Pkg.)(1) (continued)
BALL
BOTTOM TOP
BALL
PIN
NAME [3]
MODE TYPE BALL
BALL RESET POWER [9] HYS
BUFFER
PULL
IO
U/D CELL [13]
TYPE
[4]
[5]
RESET RESET
REL.
MODE
[8]
[10] STRENGTH
(mA) [11]
[1]
[2]
STATE
[6]
REL.
STATE
[7]
[12]
safe_mode
gpmc_nbe1
gpio_61
7
0
4
7
0
4
7
0
U3
H1
NA
O
L
L
L
0
7
0
VDDS_ MEM Yes
4
4
PU/
PD
LVCMOS
LVCMOS
IO
safe_mode
AB10 gpmc_nwp
gpio_62
O
VDDS_ MEM Yes
PU/
PD
IO
safe_mode
M8
L8
AB12 gpmc_wait0
I
H
H
H
H
0
7
VDDS_ MEM Yes
VDDS_ MEM Yes
NA
4
PU/
PD
LVCMOS
LVCMOS
AC10 gpmc_wait1
gpio_63
0
4
7
0
4
7
0
1
I
PU/
PD
IO
safe_mode
K8
J8
NA
NA
gpmc_wait2
gpio_64
I
H
H
H
H
7
7
VDDS_ MEM Yes
VDDS_ MEM Yes
4
4
PU/
PD
LVCMOS
LVCMOS
IO
safe_mode
gpmc_wait3
I
I
PU/
PD
sys_
ndmareq1
gpio_65
safe_mode
dss_pclk
4
7
0
4
7
0
4
7
0
4
7
0
4
7
0
IO
D28
D26
NA
NA
NA
NA
NA
O
H
H
H
L
H
H
H
L
7
7
7
7
7
VDDS
VDDS
VDDS
VDDS
VDDS
Yes
Yes
Yes
Yes
No
4
4
4
8
4
PU/
PD
LVCMOS
LVCMOS
LVCMOS
LVCMOS
gpio_66
IO
safe_mode
dss_hsync
gpio_67
O
PU/
PD
IO
safe_mode
dss_vsync
gpio_68
D27
O
PU/
PD
IO
safe_mode
dss_acbias
gpio_69
E27
O
PU/
PD
IO
safe_mode
dss_data0
AG22
IO
L
L
PU/
PD
LVDS/
CMOS
uart1_cts
gpio_70
2
4
7
0
I
IO
safe_mode
dss_data1
AH22
AG23
NA
NA
IO
L
L
L
L
7
7
VDDS
VDDS
No
No
4
4
PU/
PD
LVDS/
CMOS
uart1_rts
gpio_71
2
4
7
0
O
IO
safe_mode
dss_data2
IO
IO
PU/
PD
LVDS/
CMOS
gpio_72
4
7
safe_mode
16
TERMINAL DESCRIPTION
Submit Documentation Feedback
OMAP3515/03 Applications Processor
www.ti.com
SPRS505–FEBRUARY 2008
Table 2-1. Ball Characteristics (CBB Pkg.)(1) (continued)
BALL
BALL
PIN
MODE TYPE BALL
BALL RESET POWER [9] HYS
BUFFER
PULL
IO
BOTTOM TOP
NAME [3]
[4]
[5]
RESET RESET
REL.
MODE
[8]
[10] STRENGTH
(mA) [11]
U/D CELL [13]
TYPE
[12]
[1]
[2]
STATE
[6]
REL.
STATE
[7]
AH23
NA
dss_data3
0
IO
IO
L
L
L
7
VDDS
VDDS
No
No
4
4
PU/
PD
LVDS/
CMOS
gpio_73
safe_mode
dss_data4
4
7
0
AG24
AH24
NA
NA
IO
I
L
7
PU/
PD
LVDS/
CMOS
uart3_rx_
irrx
2
gpio_74
safe_mode
dss_data5
4
7
0
IO
IO
O
L
L
7
VDDS
No
4
PU/
PD
LVDS/
CMOS
uart3_tx_
irtx
2
gpio_75
safe_mode
dss_data6
uart1_tx
4
7
0
2
4
7
0
2
4
7
0
4
7
0
4
7
0
IO
E26
F28
NA
NA
IO
O
L
L
L
L
7
7
VDDS
VDDS
Yes
Yes
8
8
PU/
PD
LVCMOS
LVCMOS
gpio_76
IO
safe_mode
dss_data7
uart1_rx
IO
I
PU/
PD
gpio_77
IO
safe_mode
dss_data8
gpio_78
F27
G26
NA
NA
NA
IO
IO
L
L
L
L
L
L
7
7
7
VDDS
VDDS
VDDS
Yes
Yes
NA
8
8
4
PU/
PD
LVCMOS
LVCMOS
safe_mode
dss_data9
gpio_79
IO
IO
PU/
PD
safe_mode
dss_data10
AD28
IO
IO
PU/
PD
LVDS/
CMOS
gpio_80
4
7
0
safe_mode
dss_data11
AD27
AB28
AB27
NA
NA
NA
IO
IO
L
L
L
L
L
L
7
7
7
VDDS
VDDS
VDDS
NA
NA
NA
4
4
4
PU/
PD
LVDS/
CMOS
gpio_81
4
7
0
safe_mode
dss_data12
IO
IO
PU/
PD
LVDS/
CMOS
gpio_82
4
7
0
safe_mode
dss_data13
IO
IO
PU/
PD
LVDS/
CMOS
gpio_83
4
7
safe_mode
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TERMINAL DESCRIPTION
17
OMAP3515/03 Applications Processor
www.ti.com
SPRS505–FEBRUARY 2008
Table 2-1. Ball Characteristics (CBB Pkg.)(1) (continued)
BALL
BOTTOM TOP
BALL
PIN
NAME [3]
MODE TYPE BALL
BALL RESET POWER [9] HYS
BUFFER
PULL
IO
U/D CELL [13]
TYPE
[4]
[5]
RESET RESET
REL.
MODE
[8]
[10] STRENGTH
(mA) [11]
[1]
[2]
STATE
[6]
REL.
STATE
[7]
[12]
AA28
NA
dss_data14
0
IO
IO
L
L
L
7
VDDS
VDDS
NA
NA
4
4
PU/
PD
LVDS/
CMOS
gpio_84
4
7
0
safe_mode
dss_data15
AA27
NA
IO
IO
L
7
PU/
PD
LVDS/
CMOS
gpio_85
safe_mode
dss_data16
gpio_86
4
7
0
4
7
0
4
7
0
G25
H27
H26
NA
NA
NA
IO
IO
L
L
L
L
L
L
7
7
7
VDDS
VDDS
VDDS
Yes
Yes
Yes
8
8
8
PU/
PD
LVCMOS
LVCMOS
LVCMOS
safe_mode
dss_data17
gpio_87
IO
IO
PU/
PD
safe_mode
dss_data18
IO
PU/
PD
mcspi3_clk
dss_data0
gpio_88
2
3
4
7
0
IO
IO
IO
safe_mode
dss_data19
H25
NA
IO
IO
L
L
7
VDDS
Yes
8
PU/
PD
LVCMOS
LVCMOS
LVCMOS
mcspi3_
simo
2
dss_data1
gpio_89
3
4
7
0
IO
IO
safe_mode
dss_data20
E28
NA
O
H
H
7
VDDS
Yes
4
PU/
PD
mcspi3_
somi
2
IO
dss_data2
gpio_90
3
4
7
0
IO
IO
safe_mode
dss_data21
J26
NA
NA
O
L
L
L
L
7
7
VDDS
VDDS
Yes
8
4
PU/
PD
mcspi3_cs0
dss_data3
gpio_91
2
3
4
7
0
IO
IO
IO
safe_mode
dss_data22
AC27
O
NA
PU/
PD
LVDS/
CMOS
mcspi3_cs1
dss_data4
gpio_92
2
3
4
7
O
IO
IO
safe_mode
18
TERMINAL DESCRIPTION
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OMAP3515/03 Applications Processor
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SPRS505–FEBRUARY 2008
Table 2-1. Ball Characteristics (CBB Pkg.)(1) (continued)
BALL
BALL
PIN
MODE TYPE BALL
BALL RESET POWER [9] HYS
BUFFER
PULL
IO
BOTTOM TOP
NAME [3]
[4]
[5]
RESET RESET
REL.
MODE
[8]
[10] STRENGTH
(mA) [11]
U/D CELL [13]
TYPE
[12]
[1]
[2]
STATE
[6]
REL.
STATE
[7]
AC28
NA
dss_data23
0
O
L
L
7
VDDS
NA
4
PU/
PD
LVDS/
CMOS
dss_data5
gpio_93
3
4
7
0
IO
IO
safe_mode
tv_out2
W28
Y28
Y27
W27
W26
A24
NA
NA
NA
NA
NA
NA
O
O
O
O
I
Z
Z
Z
Z
Z
L
0
0
0
0
0
0
0
7
VDDADAC
VDDADAC
VDDADAC
VDDADAC
VDDADAC
VDDS
8
8
NA
NA
NA
NA
NA
10-bit
DAC
tv_out1
tv_vfb1
tv_vfb2
tv_vref
cam_hs
0
0
0
0
0
10-bit
DAC
NA
NA
NA
L
10-bit
DAC
10-bit
DAC
10-bit
DAC
IO
IO
Yes
4
PU/
PD
LVCMOS
gpio_94
safe_mode
cam_vs
4
7
0
4
7
0
4
7
0
4
7
0
2
A23
C25
C27
C23
NA
NA
NA
NA
IO
IO
L
L
L
L
L
L
L
L
7
7
7
7
VDDS
VDDS
VDDS
VDDS
Yes
Yes
Yes
Yes
4
4
4
4
PU/
PD
LVCMOS
LVCMOS
LVCMOS
LVCMOS
gpio_95
safe_mode
cam_ xclka
gpio_96
O
PU/
PD
IO
safe_mode
cam_pclk
gpio_97
I
PU/
PD
IO
safe_mode
cam_fld
IO
IO
PU/
PD
cam_global
_reset
gpio_98
safe_mode
cam_d0
4
7
0
IO
AG17
AH17
B24
NA
NA
NA
NA
I
I
L
L
L
L
L
L
L
L
7
7
7
7
VDDS
VDDS
VDDS
VDDS
Yes
Yes
Yes
Yes
4
4
4
4
PD
PD
LVDS/
CMOS
gpio_99
safe_mode
cam_d1
4
7
0
I
I
LVDS/
CMOS
gpio_100
safe_mode
cam_d2
4
7
0
I
PU/
PD
LVCMOS
LVCMOS
gpio_101
safe_mode
cam_d3
4
7
0
IO
C24
I
PU/
PD
gpio_102
4
IO
Submit Documentation Feedback
TERMINAL DESCRIPTION
19
OMAP3515/03 Applications Processor
www.ti.com
SPRS505–FEBRUARY 2008
Table 2-1. Ball Characteristics (CBB Pkg.)(1) (continued)
BALL
BOTTOM TOP
BALL
PIN
NAME [3]
MODE TYPE BALL
BALL RESET POWER [9] HYS
BUFFER
PULL
IO
U/D CELL [13]
TYPE
[4]
[5]
RESET RESET
REL.
MODE
[8]
[10] STRENGTH
(mA) [11]
[1]
[2]
STATE
[6]
REL.
STATE
[7]
[12]
safe_mode
cam_d4
7
0
D24
NA
I
L
L
L
7
7
VDDS
VDDS
Yes
Yes
4
4
PU/
PD
LVCMOS
LVCMOS
gpio_103
safe_mode
cam_d5
4
7
0
IO
A25
NA
I
L
PU/
PD
gpio_104
safe_mode
cam_d6
4
7
0
4
7
0
4
7
0
4
7
0
4
7
0
IO
K28
L28
K27
L27
B25
NA
NA
NA
NA
NA
I
L
L
L
L
L
L
L
L
L
L
7
7
7
7
7
VDDS
VDDS
VDDS
VDDS
VDDS
NA
NA
NA
NA
Yes
4
4
4
4
4
PD
PD
PD
PD
LVDS/
CMOS
gpio_105
safe_mode
cam_d7
IO
I
LVDS/
CMOS
gpio_106
safe_mode
cam_d8
IO
I
LVDS/
CMOS
gpio_107
safe_mode
cam_d9
IO
I
LVDS/
CMOS
gpio_108
safe_mode
cam_d10
IO
I
PU/
PD
LVCMOS
gpio_109
safe_mode
cam_d11
4
7
0
4
7
0
4
7
0
2
IO
C26
B26
B23
NA
NA
NA
I
L
L
L
L
L
L
7
7
7
VDDS
VDDS
VDDS
Yes
Yes
Yes
4
4
4
PU/
PD
LVCMOS
LVCMOS
LVCMOS
gpio_110
IO
safe_mode
cam_ xclkb
gpio_111
O
PU/
PD
IO
safe_mode
cam_wen
I
PU/
PD
cam_
O
shutter
gpio_167
4
7
0
IO
safe_mode
D25
NA
cam_
O
L
L
7
VDDS
Yes
4
PU/
PD
LVCMOS
strobe
gpio_126
safe_mode
gpio_112
4
7
4
IO
AG19
AH19
NA
NA
I
I
L
L
L
L
7
7
VDDS
VDDS
Yes
Yes
4
4
PD
PD
LVDS/
CMOS
safe_mode
gpio_113
7
4
LVDS/
CMOS
safe_mode
7
20
TERMINAL DESCRIPTION
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OMAP3515/03 Applications Processor
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SPRS505–FEBRUARY 2008
Table 2-1. Ball Characteristics (CBB Pkg.)(1) (continued)
BALL
BALL
PIN
MODE TYPE BALL
BALL RESET POWER [9] HYS
BUFFER
PULL
IO
BOTTOM TOP
NAME [3]
[4]
[5]
RESET RESET
REL.
MODE
[8]
[10] STRENGTH
(mA) [11]
U/D CELL [13]
TYPE
[12]
[1]
[2]
STATE
[6]
REL.
STATE
[7]
AG18
NA
gpio_114
4
I
I
L
L
L
L
L
7
7
7
VDDS
VDDS
VDDS
Yes
Yes
Yes
4
4
PD
PD
LVDS/
CMOS
safe_mode
gpio_115
7
4
AH18
P21
NA
NA
LVDS/
CMOS
safe_mode
mcbsp2_fsx
gpio_116
7
0
4
7
0
IO
IO
PGM
4(2)
PU/
PD
LVCMOS
LVCMOS
safe_mode
N21
NA
mcbsp2_
clkx
IO
IO
PGM
L
7
VDDS
Yes
4(2)
PU/
PD
gpio_117
safe_mode
mcbsp2_dr
gpio_118
safe_mode
mcbsp2_dx
gpio_119
safe_mode
mmc1_clk
ms_clk
4
7
0
4
7
0
4
7
0
1
4
7
0
1
4
7
0
1
4
7
0
1
4
7
0
1
4
7
0
1
4
7
0
4
R21
M21
N28
NA
NA
NA
I
PGM
PGM
L
L
L
L
7
7
7
VDDS
VDDS
Yes
Yes
Yes
4(2)
4(2)
8
PU/
PD
LVCMOS
LVCMOS
LVCMOS
IO
IO
IO
PU/
PD
O
O
MMC1_
VDDS
PU/
PD
gpio_120
safe_mode
mmc1_cmd
ms_bs
IO
M27
N27
N26
N25
P28
P27
NA
NA
NA
NA
NA
NA
IO
O
L
L
L
L
L
L
L
L
L
L
L
L
7
7
7
7
7
7
MMC1_
VDDS
Yes
Yes
Yes
Yes
Yes
No
8
8
8
8
8
8
PU/
PD
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
gpio_121
safe_mode
mmc1_dat0
ms_dat0
IO
IO
IO
IO
MMC1_
VDDS
PU/
PD
gpio_122
safe_mode
mmc1_dat1
ms_dat1
IO
IO
IO
MMC1_
VDDS
PU/
PD
gpio_123
safe_mode
mmc1_dat2
ms_dat2
IO
IO
IO
MMC1_
VDDS
PU/
PD
gpio_124
safe_mode
mmc1_dat3
ms_dat3
IO
IO
IO
MMC1_
VDDS
PU/
PD
gpio_125
safe_mode
mmc1_dat4
gpio_126
IO
IO
VDDS
PD
Submit Documentation Feedback
TERMINAL DESCRIPTION
21
OMAP3515/03 Applications Processor
www.ti.com
SPRS505–FEBRUARY 2008
Table 2-1. Ball Characteristics (CBB Pkg.)(1) (continued)
BALL
BOTTOM TOP
BALL
PIN
NAME [3]
MODE TYPE BALL
BALL RESET POWER [9] HYS
BUFFER
PULL
IO
U/D CELL [13]
TYPE
[4]
[5]
RESET RESET
REL.
MODE
[8]
[10] STRENGTH
(mA) [11]
[1]
[2]
STATE
[6]
REL.
STATE
[7]
[12]
safe_mode
mmc1_dat5
gpio_127
7
0
4
7
0
4
7
0
4
7
0
1
4
7
0
1
P26
R27
R25
AE2
NA
NA
NA
NA
IO
IO
L
L
L
L
L
L
L
L
7
7
7
7
VDDS
VDDS
VDDS
VDDS
No
No
8
8
8
4
PD
PD
PD
LVCMOS
LVCMOS
LVCMOS
LVCMOS
safe_mode
mmc1_dat6
gpio_128
IO
IO
safe_mode
mmc1_dat7
gpio_129
IO
IO
No
safe_mode
mmc2_clk
mcspi3_clk
gpio_130
O
Yes
PU/
PD
IO
IO
safe_mode
mmc2_ cmd
AG5
AH5
NA
NA
IO
IO
H
H
H
H
7
7
VDDS
VDDS
Yes
Yes
4
4
PU/
PD
LVCMOS
LVCMOS
mcspi3_
simo
gpio_131
4
7
0
IO
safe_mode
mmc2_
dat0
IO
IO
IO
PU/
PD
mcspi3_
somi
1
gpio_132
4
7
0
safe_mode
AH4
AG4
NA
NA
mmc2_
dat1
IO
IO
H
H
H
H
7
7
VDDS
VDDS
Yes
Yes
4
4
PU/
PD
LVCMOS
LVCMOS
gpio_133
4
7
0
safe_mode
mmc2_
dat2
IO
PU/
PD
mcspi3_cs1
gpio_134
1
4
7
0
O
IO
safe_mode
AF4
AE4
NA
NA
mmc2_
dat3
IO
H
L
H
L
7
7
VDDS
VDDS
Yes
Yes
4
4
PU/
PD
LVCMOS
LVCMOS
mcspi3_cs0
gpio_135
1
4
7
0
IO
IO
safe_mode
mmc2_
dat4
IO
O
PU/
PD
mmc2_dir_
dat0
1
mmc3_dat0
gpio_136
3
4
7
IO
IO
safe_mode
22
TERMINAL DESCRIPTION
Submit Documentation Feedback
OMAP3515/03 Applications Processor
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SPRS505–FEBRUARY 2008
Table 2-1. Ball Characteristics (CBB Pkg.)(1) (continued)
BALL
BALL
PIN
MODE TYPE BALL
BALL RESET POWER [9] HYS
BUFFER
PULL
IO
BOTTOM TOP
NAME [3]
[4]
[5]
RESET RESET
REL.
MODE
[8]
[10] STRENGTH
(mA) [11]
U/D CELL [13]
TYPE
[12]
[1]
[2]
STATE
[6]
REL.
STATE
[7]
AH3
NA
mmc2_
dat5
0
1
2
IO
O
L
L
7
VDDS
Yes
4
PU/
PD
LVCMOS
mmc2_dir_
dat1
cam_global
_reset
IO
mmc3_dat1
gpio_137
3
4
5
IO
IO
IO
hsusb3_tll_
stp
mm3_rxdp
safe_mode
6
7
0
IO
AF3
NA
mmc2_
dat6
IO
O
L
L
7
VDDS
Yes
4
PU/
PD
LVCMOS
mmc2_dir_
cmd
1
2
cam_
O
shutter
mmc3_dat2
gpio_138
3
4
5
IO
IO
IO
hsusb3_tll_
dir
safe_mode
7
0
AE3
NA
mmc2_
dat7
IO
I
L
L
7
VDDS
Yes
4
PU/
PD
LVCMOS
mmc2_
clkin
1
mmc3_dat3
gpio_139
3
4
5
IO
IO
IO
hsusb3_tll_
nxt
mm3_rxdm
safe_mode
mcbsp3_dx
uart2_cts
6
7
0
1
4
5
IO
AF6
AE6
NA
NA
IO
I
L
L
L
L
7
7
VDDS
VDDS
Yes
Yes
4
4
PU/
PD
LVCMOS
LVCMOS
gpio_140
IO
IO
hsusb3_tll_
data4
safe_mode
mcbsp3_dr
uart2_rts
7
0
1
4
5
I
PU/
PD
O
gpio_141
IO
IO
hsusb3_tll_
data5
safe_mode
7
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TERMINAL DESCRIPTION
23
OMAP3515/03 Applications Processor
www.ti.com
SPRS505–FEBRUARY 2008
Table 2-1. Ball Characteristics (CBB Pkg.)(1) (continued)
BALL
BOTTOM TOP
BALL
PIN
NAME [3]
MODE TYPE BALL
BALL RESET POWER [9] HYS
BUFFER
PULL
IO
U/D CELL [13]
TYPE
[4]
[5]
RESET RESET
REL.
MODE
[8]
[10] STRENGTH
(mA) [11]
[1]
[2]
STATE
[6]
REL.
STATE
[7]
[12]
AF5
NA
mcbsp3_
clkx
0
IO
L
L
7
VDDS
Yes
4
PU/
PD
LVCMOS
uart2_tx
1
4
5
O
gpio_142
IO
IO
hsusb3_tll_
data6
safe_mode
mcbsp3_fsx
uart2_rx
7
0
1
4
5
AE5
AB26
AB25
AA25
NA
NA
NA
NA
IO
I
L
H
H
H
L
H
H
H
7
7
7
7
VDDS
VDDS
VDDS
VDDS
Yes
Yes
Yes
Yes
4
4
4
4
PU/
PD
LVCMOS
LVCMOS
LVCMOS
LVCMOS
gpio_143
IO
IO
hsusb3_tll_
data7
safe_mode
uart2_cts
7
0
1
2
I
PU/
PD
mcbsp3_dx
IO
IO
gpt9_pwm_
evt
gpio_144
safe_mode
uart2_rts
4
7
0
1
2
IO
O
I
PU/
PD
mcbsp3_dr
gpt10_pwm
_evt
IO
gpio_145
safe_mode
uart2_tx
4
7
0
1
IO
O
PU/
PD
mcbsp3_
clkx
IO
gpt11_pwm
_evt
2
IO
IO
gpio_146
safe_mode
uart2_rx
4
7
0
1
2
AD25
NA
I
H
H
7
VDDS
Yes
4
PU/
PD
LVCMOS
mcbsp3_fsx
IO
IO
gpt8_pwm_
evt
gpio_147
safe_mode
uart1_tx
4
7
0
IO
AA8
AA9
NA
NA
O
L
L
L
L
7
7
VDDS
VDDS
Yes
Yes
4
4
PU/
PD
LVCMOS
LVCMOS
gpio_148
safe_mode
uart1_rts
4
7
0
IO
O
PU/
PD
gpio_149
4
7
IO
safe_mode
24
TERMINAL DESCRIPTION
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OMAP3515/03 Applications Processor
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SPRS505–FEBRUARY 2008
Table 2-1. Ball Characteristics (CBB Pkg.)(1) (continued)
BALL
BALL
PIN
MODE TYPE BALL
BALL RESET POWER [9] HYS
BUFFER
PULL
IO
BOTTOM TOP
NAME [3]
[4]
[5]
RESET RESET
REL.
MODE
[8]
[10] STRENGTH
(mA) [11]
U/D CELL [13]
TYPE
[12]
[1]
[2]
STATE
[6]
REL.
STATE
[7]
W8
NA
uart1_cts
gpio_150
0
4
5
I
L
L
L
L
7
7
VDDS
VDDS
Yes
Yes
4
4
PU/
PD
LVCMOS
LVCMOS
IO
O
hsusb3_tll_
clk
safe_mode
uart1_rx
7
0
2
Y8
NA
NA
I
PU/
PD
mcbsp1_
clkr
IO
mcspi4_clk
gpio_151
3
4
7
0
IO
IO
safe_mode
AE1
mcbsp4_
clkx
IO
L
L
L
L
L
L
L
L
7
7
7
7
VDDS
VDDS
VDDS
VDDS
Yes
Yes
Yes
Yes
4
4
4
4
PU/
PD
LVCMOS
LVCMOS
LVCMOS
LVCMOS
gpio_152
4
5
IO
IO
hsusb3_tll_
data1
mm3_txse0
safe_mode
mcbsp4_dr
6
7
0
IO
I
AD1
AD2
AC1
NA
NA
NA
PU/
PD
gpio_153
4
5
IO
IO
hsusb3_tll_
data0
mm3_rxrcv
safe_mode
mcbsp4_dx
6
7
0
IO
IO
PU/
PD
gpio_154
4
5
IO
IO
hsusb3_tll_
data2
mm3_txdat
safe_mode
mcbsp4_fsx
6
7
0
IO
IO
PU/
PD
gpio_155
4
5
IO
IO
hsusb3_tll_
data3
mm3_txen_
n
6
IO
IO
safe_mode
7
0
Y21
NA
mcbsp1_
clkr
L
L
7
VDDS
Yes
4
PU/
PD
LVCMOS
mcspi4_clk
gpio_156
1
4
7
IO
IO
safe_mode
Submit Documentation Feedback
TERMINAL DESCRIPTION
25
OMAP3515/03 Applications Processor
www.ti.com
SPRS505–FEBRUARY 2008
Table 2-1. Ball Characteristics (CBB Pkg.)(1) (continued)
BALL
BOTTOM TOP
BALL
PIN
NAME [3]
MODE TYPE BALL
BALL RESET POWER [9] HYS
BUFFER
PULL
IO
U/D CELL [13]
TYPE
[4]
[5]
RESET RESET
REL.
MODE
[8]
[10] STRENGTH
(mA) [11]
[1]
[2]
STATE
[6]
REL.
STATE
[7]
[12]
AA21
NA
mcbsp1_fsr
0
1
IO
I
L
L
7
VDDS
Yes
4
PU/
PD
LVCMOS
adpllv2d_dit
hering_en1
cam_global
_reset
2
IO
IO
gpio_157
safe_mode
mcbsp1_dx
4
7
0
1
V21
U21
T21
NA
NA
NA
IO
IO
L
L
L
L
L
L
7
7
7
VDDS
VDDS
VDDS
Yes
Yes
Yes
4
4
4
PU/
PD
LVCMOS
LVCMOS
LVCMOS
mcspi4_
simo
mcbsp3_dx
gpio_158
2
4
7
0
1
IO
IO
safe_mode
mcbsp1_dr
I
PU/
PD
mcspi4_
somi
IO
mcbsp3_dr
gpio_159
2
4
7
0
2
O
IO
safe_mode
mcbsp_clks
I
PU/
PD
cam_
O
shutter
gpio_160
uart1_cts
4
5
7
0
1
2
4
7
0
IO
I
safe_mode
mcbsp1_fsx
mcspi4_cs0
mcbsp3_fsx
gpio_161
K26
NA
NA
IO
IO
IO
IO
L
L
L
L
7
7
VDDS
VDDS
Yes
Yes
4
4
PU/
PD
LVCMOS
LVCMOS
safe_mode
W21
mcbsp1_
clkx
IO
IO
IO
PU/
PD
mcbsp3_
clkx
2
gpio_162
4
7
0
safe_mode
H18
H19
H20
NA
NA
NA
uart3_cts_
rctx
IO
IO
H
H
H
H
H
H
7
7
7
VDDS
VDDS
VDDS
Yes
Yes
Yes
4
4
4
PU/
PD
LVCMOS
LVCMOS
LVCMOS
gpio_163
4
7
0
safe_mode
uart3_rts_
sd
O
PU/
PD
gpio_164
4
7
0
IO
safe_mode
uart3_rx_
irrx
I
PU/
PD
gpio_165
4
IO
26
TERMINAL DESCRIPTION
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OMAP3515/03 Applications Processor
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SPRS505–FEBRUARY 2008
Table 2-1. Ball Characteristics (CBB Pkg.)(1) (continued)
BALL
BALL
PIN
MODE TYPE BALL
BALL RESET POWER [9] HYS
BUFFER
PULL
IO
BOTTOM TOP
NAME [3]
[4]
[5]
RESET RESET
REL.
MODE
[8]
[10] STRENGTH
(mA) [11]
U/D CELL [13]
TYPE
[12]
[1]
[2]
STATE
[6]
REL.
STATE
[7]
safe_mode
7
0
H21
NA
uart3_tx_
irtx
O
H
H
7
VDDS
Yes
4
PU/
PD
LVCMOS
gpio_166
safe_mode
hsusb0_clk
gpio_120
4
7
0
4
7
0
4
7
0
4
7
0
4
7
0
IO
T28
T25
R28
T26
T27
NA
NA
NA
NA
NA
I
L
H
L
L
L
L
H
L
L
L
7
7
7
7
7
VDDS
VDDS
VDDS
VDDS
VDDS
Yes
Yes
Yes
Yes
Yes
4
4
4
4
4
PU/
PD
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
IO
safe_mode
hsusb0_stp
gpio_121
O
PU/
PD
IO
safe_mode
hsusb0_dir
gpio_122
I
PU/
PD
IO
safe_mode
hsusb0_nxt
gpio_124
I
PU/
PD
IO
safe_mode
hsusb0_
data0
IO
O
PU/
PD
uart3_tx_
irtx
2
gpio_125
4
7
0
IO
safe_mode
U28
U27
U26
NA
NA
NA
hsusb0_
data1
IO
I
L
L
L
L
L
L
7
7
7
VDDS
VDDS
VDDS
Yes
Yes
Yes
4
4
4
PU/
PD
LVCMOS
LVCMOS
LVCMOS
uart3_rx_
irrx
2
gpio_130
4
7
0
IO
safe_mode
hsusb0_
data2
IO
O
PU/
PD
uart3_rts_
sd
2
gpio_131
4
7
0
IO
safe_mode
hsusb0_
data3
IO
IO
IO
PU/
PD
uart3_cts_
rctx
2
gpio_169
4
7
0
safe_mode
U25
V28
NA
NA
hsusb0_
data4
IO
IO
L
L
L
L
7
7
VDDS
VDDS
Yes
Yes
4
4
PU/
PD
LVCMOS
LVCMOS
gpio_188
4
7
0
safe_mode
hsusb0_
data5
IO
IO
PU/
PD
gpio_189
4
Submit Documentation Feedback
TERMINAL DESCRIPTION
27
OMAP3515/03 Applications Processor
www.ti.com
SPRS505–FEBRUARY 2008
Table 2-1. Ball Characteristics (CBB Pkg.)(1) (continued)
BALL
BOTTOM TOP
BALL
PIN
NAME [3]
MODE TYPE BALL
BALL RESET POWER [9] HYS
BUFFER
PULL
IO
U/D CELL [13]
TYPE
[4]
[5]
RESET RESET
REL.
MODE
[8]
[10] STRENGTH
(mA) [11]
[1]
[2]
STATE
[6]
REL.
STATE
[7]
[12]
safe_mode
7
0
V27
NA
hsusb0_
data6
IO
IO
L
L
L
7
7
VDDS
VDDS
Yes
Yes
4
4
PU/
PD
LVCMOS
LVCMOS
gpio_190
4
7
0
safe_mode
V26
NA
hsusb0_
data7
IO
IO
L
PU/
PD
gpio_191
safe_mode
i2c1_scl
4
7
0
K21
J21
NA
NA
NA
IOD
IOD
H
H
H
H
H
H
0
0
7
VDDS
VDDS
VDDS
Yes
Yes
Yes
4
4
4
PU/
PD
Open
Drain
i2c1_sda
0
PU/
PD
Open
Drain
AF15
i2c2_scl
gpio_168
safe_mode
i2c2_sda
gpio_183
safe_mode
i2c3_scl
0
4
7
0
4
7
0
4
7
0
4
7
0
1
IOD
IO
PU/
PD
Open
Drain
AE15
AF14
AG14
AD26
NA
NA
NA
NA
IOD
IO
H
H
H
H
H
H
H
H
7
7
7
0
VDDS
VDDS
VDDS
VDDS
Yes
Yes
Yes
Yes
4
4
4
4
PU/
PD
Open
Drain
IOD
IO
PU/
PD
Open
Drain
gpio_184
safe_mode
i2c3_sda
gpio_185
safe_mode
i2c4_scl
IOD
IO
PU/
PD
Open
Drain
IOD
O
PU/
PD
Open
Drain
sys_
nvmode1
safe_mode
i2c4_sda
7
0
1
AE26
J25
NA
NA
IOD
O
H
H
H
H
0
7
VDDS
VDDS
Yes
Yes
4
4
PU/
PD
Open
Drain
sys_
nvmode2
safe_mode
hdq_sio
7
0
1
2
3
4
7
0
1
4
7
IOD
I
PU/
PD
LVCMOS
sys_altclk
i2c2_sccbe
i2c3_sccbe
gpio_170
O
O
IO
safe_mode
mcspi1_clk
mmc2_dat4
gpio_171
AB3
NA
IO
IO
IO
PGM
L
7
VDDS
Yes
4(2)
PU/
PD
LVCMOS
safe_mode
28
TERMINAL DESCRIPTION
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OMAP3515/03 Applications Processor
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SPRS505–FEBRUARY 2008
Table 2-1. Ball Characteristics (CBB Pkg.)(1) (continued)
BALL
BALL
PIN
MODE TYPE BALL
BALL RESET POWER [9] HYS
BUFFER
PULL
IO
BOTTOM TOP
NAME [3]
[4]
[5]
RESET RESET
REL.
MODE
[8]
[10] STRENGTH
(mA) [11]
U/D CELL [13]
TYPE
[12]
[1]
[2]
STATE
[6]
REL.
STATE
[7]
AB4
NA
mcspi1_
simo
0
IO
PGM
PGM
L
L
7
7
VDDS
VDDS
Yes
Yes
4(2)
PU/
PD
LVCMOS
LVCMOS
mmc2_dat5
gpio_172
1
4
7
0
IO
IO
safe_mode
AA4
NA
mcspi1_
somi
IO
4(2)
PU/
PD
mmc2_dat6
gpio_173
1
4
7
0
1
4
7
0
1
IO
IO
safe_mode
mcspi1_cs0
mmc2_dat7
gpio_174
AC2
AC3
NA
NA
IO
IO
IO
PGM
PGM
H
H
7
7
VDDS
VDDS
Yes
Yes
4(2)
PU/
PD
LVCMOS
LVCMOS
safe_mode
mcspi1_cs1
O
I
4(2)
PU/
PD
adpllv2d_dit
hering_en2
mmc3_cmd
gpio_175
3
4
7
0
3
4
7
0
2
IO
IO
safe_mode
mcspi1_cs2
mmc3_clk
gpio_176
AB1
AB2
NA
NA
O
O
PGM
H
H
7
7
VDDS
VDDS
Yes
Yes
4(2)
PU/
PD
LVCMOS
LVCMOS
IO
safe_mode
mcspi1_cs3
O
H
4
PU/
PD
hsusb2_tll_
data2
IO
hsusb2_
data2
3
IO
gpio_177
mm2_txdat
safe_mode
mcspi2_clk
4
5
7
0
2
IO
IO
AA3
NA
IO
IO
L
L
7
VDDS
Yes
4
PU/
PD
LVCMOS
hsusb2_tll_
data7
hsusb2_
data7
3
O
gpio_178
4
7
0
IO
safe_mode
Y2
NA
mcspi2_
simo
IO
IO
IO
I
L
L
7
VDDS
Yes
4
PU/
PD
LVCMOS
gpt9_pwm_
evt
1
2
3
4
hsusb2_tll_
data4
hsusb2_
data4
gpio_179
IO
Submit Documentation Feedback
TERMINAL DESCRIPTION
29
OMAP3515/03 Applications Processor
www.ti.com
SPRS505–FEBRUARY 2008
Table 2-1. Ball Characteristics (CBB Pkg.)(1) (continued)
BALL
BOTTOM TOP
BALL
PIN
NAME [3]
MODE TYPE BALL
BALL RESET POWER [9] HYS
BUFFER
PULL
IO
U/D CELL [13]
TYPE
[4]
[5]
RESET RESET
REL.
MODE
[8]
[10] STRENGTH
(mA) [11]
[1]
[2]
STATE
[6]
REL.
STATE
[7]
[12]
safe_mode
7
0
Y3
NA
mcspi2_
somi
IO
IO
IO
O
L
L
7
VDDS
Yes
4
PU/
PD
LVCMOS
gpt10_pwm
_evt
1
2
3
hsusb2_tll_
data5
hsusb2_
data5
gpio_180
safe_mode
mcspi2_cs0
4
7
0
1
IO
Y4
NA
IO
IO
H
H
7
VDDS
Yes
4
PU/
PD
LVCMOS
gpt11_pwm
_evt
hsusb2_tll_
data6
2
3
IO
O
hsusb2_
data6
gpio_181
safe_mode
mcspi2_cs1
4
7
0
1
IO
V3
NA
O
L
L
7
VDDS
Yes
4
PU/
PD
LVCMOS
gpt8_pwm_
evt
IO
hsusb2_tll_
data3
2
3
IO
IO
hsusb2_
data3
gpio_182
4
5
IO
IO
mm2_txen_
n
safe_mode
sys_32k
7
0
0
0
0
4
7
0
4
7
0
AE25
AE17
AF17
AF25
NA
NA
NA
NA
I
Z
Z
Z
0
I
I
NA
NA
NA
0
VDDS
VDDS
VDDS
VDDS
Yes
Yes
Yes
Yes
NA
4
NA
NA
NA
LVCMOS
LVCMOS
LVCMOS
LVCMOS
sys_xtalin
sys_xtalout
sys_clkreq
gpio_1
I
O
IO
IO
O
1
PU/
PD
safe_mode
sys_nirq
AF26
NA
I
H
H
7
VDDS
Yes
4
PU/
PD
LVCMOS
gpio_0
IO
safe_mode
AH25
AF24
NA
NA
sys_
nrespwron
I
Z
0
I
NA
0
VDDS
VDDS
Yes
Yes
NA
4
NA
LVCMOS
LVCMOS
sys_
nreswarm
0
IOD
IO
1 (PU)
PU/
PD
gpio_30
safe_mode
sys_boot0
gpio_2
4
7
0
4
AH26
NA
I
Z
Z
0
VDDS
Yes
4
PU/
PD
LVCMOS
IO
30
TERMINAL DESCRIPTION
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OMAP3515/03 Applications Processor
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SPRS505–FEBRUARY 2008
Table 2-1. Ball Characteristics (CBB Pkg.)(1) (continued)
BALL
BALL
PIN
MODE TYPE BALL
BALL RESET POWER [9] HYS
BUFFER
PULL
IO
BOTTOM TOP
NAME [3]
[4]
[5]
RESET RESET
REL.
MODE
[8]
[10] STRENGTH
(mA) [11]
U/D CELL [13]
TYPE
[12]
[1]
[2]
STATE
[6]
REL.
STATE
[7]
safe_mode
sys_boot1
gpio_3
7
0
4
7
0
4
7
0
4
7
0
1
AG26
AE14
AF18
AF19
NA
NA
NA
NA
I
Z
Z
Z
Z
Z
Z
Z
Z
0
0
0
0
VDDS
VDDS
VDDS
VDDS
Yes
Yes
Yes
Yes
4
4
4
4
PU/
PD
LVCMOS
LVCMOS
LVCMOS
LVCMOS
IO
safe_mode
sys_boot2
gpio_4
I
PU/
PD
IO
safe_mode
sys_boot3
gpio_5
I
PU/
PD
IO
safe_mode
sys_boot4
I
PU/
PD
mmc2_dir_
dat2
O
gpio_6
4
7
0
1
IO
safe_mode
sys_boot5
AE21
NA
I
Z
Z
0
VDDS
Yes
4
PU/
PD
LVCMOS
mmc2_dir_
dat3
O
gpio_7
safe_mode
sys_boot6
gpio_8
4
7
0
4
7
0
IO
AF21
AF22
NA
NA
I
Z
0
Z
L
0
7
VDDS
VDDS
Yes
Yes
4
4
PU/
PD
LVCMOS
LVCMOS
IO
safe_mode
sys_off_
mode
O
PU/
PD
gpio_9
4
7
0
4
7
0
4
7
0
IO
safe_mode
sys_clkout1
gpio_10
AG25
AE22
NA
NA
O
L
L
L
L
7
7
VDDS
VDDS
Yes
Yes
4
4
PU/
PD
LVCMOS
LVCMOS
IO
safe_mode
sys_clkout2
gpio_186
O
PU/
PD
IO
safe_mode
B1
NA
NA
NA
NA
NA
NA
NA
sys_
ipmcsws
AI
AO
I
Z
0
AI
AO
L
NA
NA
0
VDDS
VDDS
VDDS
VDDS
VDDS
VDDS
VDDS
NA
No
NA
NA
NA
NA
4
NA
NA
Analog
A1
sys_
opmcsws
0
0
0
0
0
0
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
AA17
AA13
AA12
AA18
AA20
jtag_ntrst
jtag_tck
jtag_rtck
L
Yes
Yes
Yes
Yes
Yes
PU/
PD
I
L
L
0
PU/
PD
O
IO
I
L
0
0
PU/
PD
jtag_tms_tm
sc
H
H
H
0
4
PU/
PD
jtag_tdi
H
0
NA
PU/
PD
Submit Documentation Feedback
TERMINAL DESCRIPTION
31
OMAP3515/03 Applications Processor
www.ti.com
SPRS505–FEBRUARY 2008
Table 2-1. Ball Characteristics (CBB Pkg.)(1) (continued)
BALL
BOTTOM TOP
BALL
PIN
NAME [3]
MODE TYPE BALL
BALL RESET POWER [9] HYS
BUFFER
PULL
IO
U/D CELL [13]
TYPE
[4]
[5]
RESET RESET
REL.
MODE
[8]
[10] STRENGTH
(mA) [11]
[1]
[2]
STATE
[6]
REL.
STATE
[7]
[12]
AA19
AA11
NA
NA
jtag_tdo
0
O
L
Z
0
0
VDDS
VDDS
Yes
Yes
4
4
PU/
PD
LVCMOS
LVCMOS
jtag_emu0
gpio_11
0
4
7
0
4
7
0
1
IO
IO
H
H
PU/
PD
safe_mode
jtag_emu1
gpio_31
AA10
AF10
NA
NA
IO
IO
H
H
H
H
0
4
VDDS
VDDS
Yes
Yes
4
4
PU/
PD
LVCMOS
LVCMOS
safe_mode
etk_clk
O
PU/
PD
mcbsp5_
clkx
IO
mmc3_clk
hsusb1_stp
gpio_12
2
3
4
5
6
O
O
IO
IO
I
mm1_rxdp
hsusb1_tll_
stp
AE10
AF11
NA
NA
etk_ctl
0
2
3
4
6
O
IO
O
H
H
H
H
4
4
VDDS
VDDS
Yes
Yes
4
4
PU/
PD
LVCMOS
LVCMOS
mmc3_cmd
hsusb1_clk
gpio_13
IO
O
hsusb1_tll_
clk
etk_d0
0
1
O
PU/
PD
mcspi3_
simo
IO
mmc3_dat4
2
3
IO
IO
hsusb1_
data0
gpio_14
4
5
6
IO
IO
IO
mm1_rxrcv
hsusb1_tll_
data0
AG12
NA
etk_d1
0
1
O
H
H
4
VDDS
Yes
4
PU/
PD
LVCMOS
mcspi3_
somi
IO
hsusb1_
data1
3
IO
gpio_15
4
5
6
IO
IO
IO
mm1_txse0
hsusb1_tll_
data1
32
TERMINAL DESCRIPTION
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OMAP3515/03 Applications Processor
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SPRS505–FEBRUARY 2008
Table 2-1. Ball Characteristics (CBB Pkg.)(1) (continued)
BALL
BALL
PIN
MODE TYPE BALL
BALL RESET POWER [9] HYS
BUFFER
PULL
IO
BOTTOM TOP
NAME [3]
[4]
[5]
RESET RESET
REL.
MODE
[8]
[10] STRENGTH
(mA) [11]
U/D CELL [13]
TYPE
[12]
[1]
[2]
STATE
[6]
REL.
STATE
[7]
AH12
NA
etk_d2
0
1
3
O
H
H
L
L
L
L
H
H
L
L
L
L
4
4
4
4
4
4
VDDS
VDDS
VDDS
VDDS
VDDS
VDDS
Yes
Yes
Yes
Yes
Yes
Yes
4
4
4
4
4
4
PU/
PD
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
mcspi3_cs0
IO
IO
hsusb1_
data2
gpio_16
4
5
6
IO
IO
IO
mm1_txdat
hsusb1_tll_
data2
AE13
AE11
AH9
NA
NA
NA
NA
NA
etk_d3
0
1
2
3
O
PU/
PD
mcspi3_clk
mmc3_dat3
IO
IO
IO
hsusb1_
data7
gpio_17
4
6
IO
IO
hsusb1_tll_
data7
etk_d4
0
1
2
3
O
I
PU/
PD
mcbsp5_dr
mmc3_dat0
IO
IO
hsusb1_
data4
gpio_18
4
6
IO
IO
hsusb1_tll_
data4
etk_d5
0
1
2
3
O
PU/
PD
mcbsp5_fsx
mmc3_dat1
IO
IO
IO
hsusb1_
data5
gpio_19
4
6
IO
IO
hsusb1_tll_
data5
AF13
etk_d6
0
1
2
3
O
PU/
PD
mcbsp5_dx
mmc3_dat2
IO
IO
IO
hsusb1_
data6
gpio_20
4
6
IO
IO
hsusb1_tll_
data6
AH14
etk_d7
0
1
2
3
O
O
PU/
PD
mcspi3_cs1
mmc3_dat7
IO
IO
hsusb1_
data3
gpio_21
4
5
IO
IO
mm1_txen_
n
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TERMINAL DESCRIPTION
33
OMAP3515/03 Applications Processor
www.ti.com
SPRS505–FEBRUARY 2008
Table 2-1. Ball Characteristics (CBB Pkg.)(1) (continued)
BALL
BOTTOM TOP
BALL
PIN
NAME [3]
MODE TYPE BALL
BALL RESET POWER [9] HYS
BUFFER
PULL
IO
U/D CELL [13]
TYPE
[4]
[5]
RESET RESET
REL.
MODE
[8]
[10] STRENGTH
(mA) [11]
[1]
[2]
STATE
[6]
REL.
STATE
[7]
[12]
hsusb1_tll_
data3
6
IO
AF9
NA
etk_d8
0
1
O
O
L
L
4
VDDS
Yes
4
PU/
PD
LVCMOS
sys_drm_
msecure
mmc3_dat6
hsusb1_dir
gpio_22
2
3
4
6
IO
I
IO
O
hsusb1_tll_
dir
AG9
NA
etk_d9
0
1
O
O
L
L
4
VDDS
Yes
4
PU/
PD
LVCMOS
sys_secure
_indicator
mmc3_dat5
hsusb1_nxt
gpio_23
2
3
4
5
6
IO
I
IO
IO
O
mm1_rxdm
hsusb1_tll_
nxt
AE7
AF7
NA
NA
etk_d10
uart1_rx
0
2
3
4
6
O
I
L
L
L
L
4
4
VDDS
VDDS
Yes
Yes
4
4
PU/
PD
LVCMOS
LVCMOS
hsusb2_clk
gpio_24
O
IO
O
hsusb2_tll_
clk
etk_d11
hsusb2_stp
gpio_25
0
3
4
5
6
O
O
IO
IO
I
PU/
PD
mm2_rxdp
hsusb2_tll_
stp
AG7
AH7
NA
NA
etk_d12
hsusb2_dir
gpio_26
0
3
4
6
O
I
L
L
L
L
4
4
VDDS
VDDS
Yes
Yes
4
4
PU/
PD
LVCMOS
LVCMOS
IO
O
hsusb2_tll_
dir
etk_d13
hsusb2_nxt
gpio_27
0
3
4
5
6
O
I
PU/
PD
IO
IO
O
mm2_rxdm
hsusb2_tll_
nxt
34
TERMINAL DESCRIPTION
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OMAP3515/03 Applications Processor
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SPRS505–FEBRUARY 2008
Table 2-1. Ball Characteristics (CBB Pkg.)(1) (continued)
BALL
BALL
PIN
MODE TYPE BALL
BALL RESET POWER [9] HYS
BUFFER
PULL
IO
BOTTOM TOP
NAME [3]
[4]
[5]
RESET RESET
REL.
MODE
[8]
[10] STRENGTH
(mA) [11]
U/D CELL [13]
TYPE
[12]
[1]
[2]
STATE
[6]
REL.
STATE
[7]
AG8
NA
etk_d14
0
3
O
L
L
4
VDDS
Yes
4
PU/
PD
LVCMOS
hsusb2_
data0
IO
gpio_28
4
5
6
IO
IO
IO
mm2_rxrcv
hsusb2_tll_
data0
AH8
NA
etk_d15
0
3
O
L
L
4
VDDS
Yes
4
PU/
PD
LVCMOS
hsusb2_
data1
IO
gpio_29
4
5
6
IO
IO
IO
mm2_txse0
hsusb2_tll_
data1
(1) NA in this table stands for Not Applicable.
(2) The buffer strength of this IO cell is programmable (2, 4, 6, or 8 mA) according to the selected mode; the default value is described in
the above table.
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TERMINAL DESCRIPTION
35
OMAP3515/03 Applications Processor
www.ti.com
SPRS505–FEBRUARY 2008
Table 2-2. Ball Characteristics (CUS Pkg.)(1)
BALL
BOTTOM
[1]
PIN
NAME [3]
MODE TYPE
BALL
RESET RESET
STATE
[6]
BALL RESET
POWER [9]
HYS
[10]
BUFFER
STRENGTH
(mA) [11]
PULL
U/D
TYPE
[12]
IO
[4]
[5]
REL.
MODE
[8]
CELL [13]
REL.
STATE
[7]
D7
C5
sdrc_d0
sdrc_d1
sdrc_d2
sdrc_d3
sdrc_d4
sdrc_d5
sdrc_d6
sdrc_d7
sdrc_d8
sdrc_d9
sdrc_d10
sdrc_d11
sdrc_d12
sdrc_d13
sdrc_d14
sdrc_d15
sdrc_d16
sdrc_d17
sdrc_d18
sdrc_d19
sdrc_d20
sdrc_d21
sdrc_d22
sdrc_d23
sdrc_d24
sdrc_d25
sdrc_d26
sdrc_d27
sdrc_d28
sdrc_d29
sdrc_d30
sdrc_d31
sdrc_ba0
sdrc_ba1
sdrc_a0
sdrc_a1
sdrc_a2
sdrc_a3
sdrc_a4
sdrc_a5
sdrc_a6
sdrc_a7
sdrc_a8
sdrc_a9
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
O
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
0
0
0
0
0
0
0
0
0
0
0
0
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
VDDS_ MEM
VDDS_ MEM
VDDS_ MEM
VDDS_ MEM
VDDS_ MEM
VDDS_ MEM
VDDS_ MEM
VDDS_ MEM
VDDS_ MEM
VDDS_ MEM
VDDS_ MEM
VDDS_ MEM
VDDS_ MEM
VDDS_ MEM
VDDS_ MEM
VDDS_ MEM
VDDS_ MEM
VDDS_ MEM
VDDS_ MEM
VDDS_ MEM
VDDS_ MEM
VDDS_ MEM
VDDS_ MEM
VDDS_ MEM
VDDS_ MEM
VDDS_ MEM
VDDS_ MEM
VDDS_ MEM
VDDS_ MEM
VDDS_ MEM
VDDS_ MEM
VDDS_ MEM
VDDS_ MEM
VDDS_ MEM
VDDS_ MEM
VDDS_ MEM
VDDS_ MEM
VDDS_ MEM
VDDS_ MEM
VDDS_ MEM
VDDS_ MEM
VDDS_ MEM
VDDS_ MEM
VDDS_ MEM
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
PU/ PD
PU/ PD
PU/ PD
PU/ PD
PU/ PD
PU/ PD
PU/ PD
PU/ PD
PU/ PD
PU/ PD
PU/ PD
PU/ PD
PU/ PD
PU/ PD
PU/ PD
PU/ PD
PU/ PD
PU/ PD
PU/ PD
PU/ PD
PU/ PD
PU/ PD
PU/ PD
PU/ PD
PU/ PD
PU/ PD
PU/ PD
PU/ PD
PU/ PD
PU/ PD
PU/ PD
PU/ PD
NA
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
C6
B5
D9
D10
C7
B7
B11
C12
B12
D13
C13
B14
A14
B15
C9
E12
B8
B9
C10
B10
D12
E13
E15
D15
C15
B16
C16
D16
B17
B18
C18
D18
A4
O
No
NA
O
No
NA
B4
O
No
NA
D6
O
No
NA
B3
O
No
NA
B2
O
No
NA
C3
O
No
NA
E3
O
No
NA
F6
O
No
NA
E10
E9
O
No
NA
O
No
NA
36
TERMINAL DESCRIPTION
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OMAP3515/03 Applications Processor
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SPRS505–FEBRUARY 2008
Table 2-2. Ball Characteristics (CUS Pkg.)(1) (continued)
BALL
BOTTOM
[1]
PIN
NAME [3]
MODE TYPE
BALL
RESET RESET
STATE
[6]
BALL RESET
POWER [9]
HYS
[10]
BUFFER
STRENGTH
(mA) [11]
PULL
U/D
TYPE
[12]
IO
[4]
[5]
REL.
MODE
[8]
CELL [13]
REL.
STATE
[7]
E7
G6
sdrc_a10
sdrc_a11
sdrc_a12
sdrc_a13
sdrc_a14
sdrc_ncs0
sdrc_ncs1
sdrc_clk
0
0
0
0
0
0
0
0
0
0
7
0
7
0
0
0
0
0
0
0
0
0
0
0
0
4
7
0
4
7
0
4
7
0
4
7
0
4
7
0
4
7
0
4
O
O
O
O
O
O
O
IO
O
O
0
0
0
0
0
1
1
L
1
H
0
0
0
0
0
1
1
0
1
1
0
0
0
0
0
0
0
0
0
7
VDDS_ MEM
VDDS_ MEM
VDDS_ MEM
VDDS_ MEM
VDDS_ MEM
VDDS_ MEM
VDDS_ MEM
VDDS_ MEM
VDDS_ MEM
VDDS_ MEM
No
No
No
No
No
No
No
Yes
No
Yes
4
4
4
4
4
4
4
4
4
4
NA
NA
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
G7
NA
F7
NA
F9
NA
A19
B19
A10
A11
B20
NA
NA
PU/ PD
NA
sdrc_nclk
sdrc_cke0
safe_mode
sdrc_cke1
safe_mode
sdrc_nras
sdrc_ncas
sdrc_nwe
sdrc_dm0
sdrc_dm1
sdrc_dm2
sdrc_dm3
sdrc_dqs0
sdrc_dqs1
sdrc_dqs2
sdrc_dqs3
gpmc_a1
gpio_34
PU/ PD
C20
O
H
1
7
VDDS_ MEM
Yes
4
PU/ PD
LVCMOS
D19
C19
A20
B6
O
O
1
1
1
0
0
0
0
L
L
L
L
L
1
1
1
0
0
0
0
Z
Z
Z
Z
L
0
0
0
0
0
0
0
0
0
0
0
7
VDDS_ MEM
VDDS_ MEM
VDDS_ MEM
VDDS_ MEM
VDDS_ MEM
VDDS_ MEM
VDDS_ MEM
VDDS_ MEM
VDDS_ MEM
VDDS_ MEM
VDDS_ MEM
VDDS_ MEM
No
No
4
4
4
4
4
4
4
4
4
4
4
4
NA
NA
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
O
No
NA
O
No
NA
B13
A7
O
No
NA
O
No
NA
A16
A5
O
No
NA
IO
IO
IO
IO
O
Yes
Yes
Yes
Yes
Yes
PU/ PD
PU/ PD
PU/ PD
PU/ PD
PU/ PD
A13
A8
A17
K4
IO
safe_mode
gpmc_a2
gpio_35
K3
K2
J4
J3
J2
J1
O
L
L
L
L
7
7
7
7
7
7
VDDS_ MEM
VDDS_ MEM
VDDS_ MEM
VDDS_ MEM
VDDS_ MEM
VDDS_ MEM
Yes
Yes
Yes
Yes
Yes
Yes
4
4
4
4
4
4
PU/ PD
PU/ PD
PU/ PD
PU/ PD
PU/ PD
PU/ PD
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
IO
safe_mode
gpmc_a3
gpio_36
O
IO
safe_mode
gpmc_a4
gpio_37
O
L
L
IO
safe_mode
gpmc_a5
gpio_38
O
L
L
IO
safe_mode
gpmc_a6
gpio_39
O
H
H
H
H
IO
safe_mode
gpmc_a7
gpio_40
O
IO
Submit Documentation Feedback
TERMINAL DESCRIPTION
37
OMAP3515/03 Applications Processor
www.ti.com
SPRS505–FEBRUARY 2008
Table 2-2. Ball Characteristics (CUS Pkg.)(1) (continued)
BALL
BOTTOM
[1]
PIN
NAME [3]
MODE TYPE
BALL
RESET RESET
STATE
[6]
BALL RESET
POWER [9]
HYS
[10]
BUFFER
STRENGTH
(mA) [11]
PULL
U/D
TYPE
[12]
IO
[4]
[5]
REL.
MODE
[8]
CELL [13]
REL.
STATE
[7]
safe_mode
gpmc_a8
gpio_41
7
0
4
7
0
1
H1
H2
O
H
H
H
H
7
7
VDDS_ MEM
VDDS_ MEM
Yes
Yes
4
4
PU/ PD
PU/ PD
LVCMOS
LVCMOS
IO
safe_mode
gpmc_a9
O
I
sys_
ndmareq2
gpio_42
safe_mode
gpmc_a10
4
7
0
1
IO
G2
O
I
H
H
7
VDDS_ MEM
Yes
4
PU/ PD
LVCMOS
sys_
ndmareq3
gpio_43
safe_mode
gpmc_d0
gpmc_d1
gpmc_d2
gpmc_d3
gpmc_d4
gpmc_d5
gpmc_d6
gpmc_d7
gpmc_d8
gpio_44
4
7
0
0
0
0
0
0
0
0
0
4
7
0
4
7
0
4
7
0
4
7
0
4
7
0
4
7
0
4
7
0
4
IO
L2
M1
M2
N2
M3
P1
P2
R1
R2
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
0
0
0
0
0
0
0
0
0
VDDS_ MEM
VDDS_ MEM
VDDS_ MEM
VDDS_ MEM
VDDS_ MEM
VDDS_ MEM
VDDS_ MEM
VDDS_ MEM
VDDS_ MEM
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
4
4
4
4
4
4
4
4
4
PU/ PD
PU/ PD
PU/ PD
PU/ PD
PU/ PD
PU/ PD
PU/ PD
PU/ PD
PU/ PD
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
safe_mode
gpmc_d9
gpio_45
T2
U1
R3
T3
U2
V1
V2
IO
IO
H
H
H
H
H
H
H
H
H
H
H
H
H
H
0
0
0
0
0
0
0
VDDS_ MEM
VDDS_ MEM
VDDS_ MEM
VDDS_ MEM
VDDS_ MEM
VDDS_ MEM
VDDS_ MEM
Yes
Yes
Yes
Yes
Yes
Yes
Yes
4
4
4
4
4
4
4
PU/ PD
PU/ PD
PU/ PD
PU/ PD
PU/ PD
PU/ PD
PU/ PD
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
safe_mode
gpmc_d10
gpio_46
IO
IO
safe_mode
gpmc_d11
gpio_47
IO
IO
safe_mode
gpmc_d12
gpio_48
IO
IO
safe_mode
gpmc_d13
gpio_49
IO
IO
safe_mode
gpmc_d14
gpio_50
IO
IO
safe_mode
gpmc_d15
gpio_51
IO
IO
38
TERMINAL DESCRIPTION
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OMAP3515/03 Applications Processor
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SPRS505–FEBRUARY 2008
Table 2-2. Ball Characteristics (CUS Pkg.)(1) (continued)
BALL
BOTTOM
[1]
PIN
NAME [3]
MODE TYPE
BALL
RESET RESET
STATE
[6]
BALL RESET
POWER [9]
HYS
[10]
BUFFER
STRENGTH
(mA) [11]
PULL
U/D
TYPE
[12]
IO
[4]
[5]
REL.
MODE
[8]
CELL [13]
REL.
STATE
[7]
safe_mode
gpmc_ncs0
gpmc_ncs3
7
0
0
1
E2
D2
O
O
I
1
1
0
7
VDDS_ MEM
VDDS_ MEM
No
4
4
NA
LVCMOS
LVCMOS
H
H
Yes
PU/ PD
sys_
ndmareq0
gpio_54
4
7
0
1
IO
safe_mode
gpmc_ncs4
F4
O
I
H
H
7
VDDS_ MEM
Yes
4
PU/ PD
LVCMOS
sys_
ndmareq1
mcbsp4_
clkx
2
3
IO
IO
IO
gpt9_pwm_
evt
gpio_55
4
7
0
1
safe_mode
gpmc_ncs5
G5
F3
G4
O
I
H
H
H
H
H
H
7
7
7
VDDS_ MEM
VDDS_ MEM
VDDS_ MEM
Yes
Yes
Yes
4
4
4
PU/ PD
PU/ PD
PU/ PD
LVCMOS
LVCMOS
LVCMOS
sys_
ndmareq2
mcbsp4_dr
2
3
I
gpt10_pwm
_evt
IO
gpio_56
4
7
0
1
IO
safe_mode
gpmc_ncs6
O
I
sys_
ndmareq3
mcbsp4_dx
2
3
IO
IO
gpt11_pwm
_evt
gpio_57
4
7
0
1
2
3
IO
safe_mode
gpmc_ncs7
gpmc_io_dir
mcbsp4_fsx
O
O
IO
IO
gpt8_pwm_
evt
gpio_58
safe_mode
gpmc_clk
gpio_59
4
7
0
4
7
0
IO
W2
F1
O
L
0
0
0
0
0
VDDS_ MEM
VDDS_ MEM
Yes
No
4
4
PU/ PD
NA
LVCMOS
LVCMOS
IO
safe_mode
gpmc_nadv
_ale
O
F2
gpmc_noe
gpmc_nwe
0
0
O
O
1
1
1
1
0
0
VDDS_ MEM
VDDS_ MEM
No
No
4
4
NA
NA
LVCMOS
LVCMOS
G3
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TERMINAL DESCRIPTION
39
OMAP3515/03 Applications Processor
www.ti.com
SPRS505–FEBRUARY 2008
Table 2-2. Ball Characteristics (CUS Pkg.)(1) (continued)
BALL
BOTTOM
[1]
PIN
NAME [3]
MODE TYPE
BALL
RESET RESET
STATE
[6]
BALL RESET
POWER [9]
HYS
[10]
BUFFER
STRENGTH
(mA) [11]
PULL
U/D
TYPE
[12]
IO
[4]
[5]
REL.
MODE
[8]
CELL [13]
REL.
STATE
[7]
K5
gpmc_nbe0
_cle
0
O
L
0
0
VDDS_ MEM
Yes
4
PU/ PD
LVCMOS
gpio_60
safe_mode
gpmc_nbe1
gpio_61
4
7
0
4
7
0
4
7
0
0
1
IO
L1
E1
O
L
L
L
0
7
0
VDDS_ MEM
VDDS_ MEM
Yes
Yes
4
4
PU/ PD
PU/ PD
LVCMOS
LVCMOS
IO
safe_mode
gpmc_nwp
gpio_62
O
IO
safe_mode
gpmc_wait0
gpmc_wait3
C1
C2
I
I
I
H
H
H
H
0
7
VDDS_ MEM
VDDS_ MEM
Yes
Yes
NA
4
PU/ PD
PU/ PD
LVCMOS
LVCMOS
sys_
ndmareq1
gpio_65
safe_mode
dss_pclk
4
7
0
4
7
0
4
7
0
4
7
0
4
7
0
IO
G22
E22
O
H
H
H
L
H
H
H
L
7
7
7
7
7
VDDS
VDDS
VDDS
VDDS
VDDS
Yes
Yes
Yes
Yes
No
4
4
4
8
4
PU/ PD
PU/ PD
PU/ PD
PU/ PD
PU/ PD
LVCMOS
LVCMOS
LVCMOS
LVCMOS
gpio_66
IO
safe_mode
dss_hsync
gpio_67
O
IO
safe_mode
dss_vsync
gpio_68
F22
O
IO
safe_mode
dss_acbias
gpio_69
J21
O
IO
safe_mode
dss_data0
AC19
IO
L
L
LVDS/
CMOS
uart1_cts
gpio_70
2
4
7
0
I
IO
safe_mode
dss_data1
AB19
IO
L
L
7
VDDS
No
4
PU/ PD
LVDS/
CMOS
uart1_rts
gpio_71
2
4
7
0
O
IO
safe_mode
dss_data2
AD20
AC20
IO
IO
L
L
L
L
7
7
VDDS
VDDS
No
No
4
4
PU/ PD
PU/ PD
LVDS/
CMOS
gpio_72
safe_mode
dss_data3
4
7
0
IO
IO
LVDS/
CMOS
gpio_73
4
7
safe_mode
40
TERMINAL DESCRIPTION
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OMAP3515/03 Applications Processor
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SPRS505–FEBRUARY 2008
Table 2-2. Ball Characteristics (CUS Pkg.)(1) (continued)
BALL
BOTTOM
[1]
PIN
NAME [3]
MODE TYPE
BALL
RESET RESET
STATE
[6]
BALL RESET
POWER [9]
HYS
[10]
BUFFER
STRENGTH
(mA) [11]
PULL
U/D
TYPE
[12]
IO
[4]
[5]
REL.
MODE
[8]
CELL [13]
REL.
STATE
[7]
AD21
AC21
dss_data4
0
2
IO
I
L
L
7
7
VDDS
No
No
4
4
PU/ PD
PU/ PD
LVDS/
CMOS
uart3_rx_
irrx
gpio_74
safe_mode
dss_data5
4
7
0
IO
IO
O
L
L
VDDS
LVDS/
CMOS
uart3_tx_
irtx
2
gpio_75
safe_mode
dss_data6
uart1_tx
4
7
0
2
4
7
0
2
4
7
0
4
7
0
4
7
0
IO
D24
E23
IO
O
L
L
L
L
7
7
VDDS
VDDS
Yes
Yes
8
8
PU/ PD
PU/ PD
LVCMOS
LVCMOS
gpio_76
IO
safe_mode
dss_data7
uart1_rx
IO
I
gpio_77
IO
safe_mode
dss_data8
gpio_78
E24
F23
IO
IO
L
L
L
L
L
L
7
7
7
VDDS
VDDS
VDDS
Yes
Yes
NA
8
8
4
PU/ PD
PU/ PD
PU/ PD
LVCMOS
LVCMOS
safe_mode
dss_data9
gpio_79
IO
IO
safe_mode
dss_data10
AC22
IO
IO
LVDS/
CMOS
gpio_80
4
7
0
safe_mode
dss_data11
AC23
AB22
Y22
IO
IO
L
L
L
L
L
L
L
L
7
7
7
7
VDDS
VDDS
VDDS
VDDS
NA
NA
NA
NA
4
4
4
4
PU/ PD
PU/ PD
PU/ PD
PU/ PD
LVDS/
CMOS
gpio_81
4
7
0
safe_mode
dss_data12
IO
IO
LVDS/
CMOS
gpio_82
4
7
0
safe_mode
dss_data13
IO
IO
LVDS/
CMOS
gpio_83
4
7
0
safe_mode
dss_data14
W22
IO
IO
LVDS/
CMOS
gpio_84
4
7
safe_mode
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TERMINAL DESCRIPTION
41
OMAP3515/03 Applications Processor
www.ti.com
SPRS505–FEBRUARY 2008
Table 2-2. Ball Characteristics (CUS Pkg.)(1) (continued)
BALL
BOTTOM
[1]
PIN
NAME [3]
MODE TYPE
BALL
RESET RESET
STATE
[6]
BALL RESET
POWER [9]
HYS
[10]
BUFFER
STRENGTH
(mA) [11]
PULL
U/D
TYPE
[12]
IO
[4]
[5]
REL.
MODE
[8]
CELL [13]
REL.
STATE
[7]
V22
dss_data15
0
IO
IO
L
L
7
VDDS
NA
4
PU/ PD
LVDS/
CMOS
gpio_85
safe_mode
dss_data16
gpio_86
4
7
0
4
7
0
4
7
0
2
3
4
7
0
2
J22
G23
G24
IO
IO
L
L
L
L
L
L
7
7
7
VDDS
VDDS
VDDS
Yes
Yes
Yes
8
8
8
PU/ PD
PU/ PD
PU/ PD
LVCMOS
LVCMOS
LVCMOS
safe_mode
dss_data17
gpio_87
IO
IO
safe_mode
dss_data18
mcspi3_clk
dss_data0
gpio_88
IO
IO
IO
IO
safe_mode
dss_data19
H23
D23
IO
IO
L
L
7
7
VDDS
VDDS
Yes
Yes
8
4
PU/ PD
LVCMOS
LVCMOS
LVCMOS
mcspi3_
simo
dss_data1
gpio_89
3
4
7
0
2
IO
IO
safe_mode
dss_data20
O
H
H
PU/ PD
mcspi3_
somi
IO
dss_data2
gpio_90
3
4
7
0
2
3
4
7
0
IO
IO
safe_mode
dss_data21
mcspi3_cs0
dss_data3
gpio_91
K22
V21
O
L
L
L
L
7
7
VDDS
VDDS
Yes
NA
8
4
PU/ PD
PU/ PD
IO
IO
IO
safe_mode
dss_data22
O
LVDS/
CMOS
mcspi3_cs1
dss_data4
gpio_92
2
3
4
7
0
O
IO
IO
safe_mode
dss_data23
W21
O
L
L
7
VDDS
NA
4
PU/ PD
LVDS/
CMOS
dss_data5
gpio_93
safe_mode
tv_out2
3
4
7
0
0
0
IO
IO
AA23
AB24
AB23
O
O
O
Z
Z
Z
0
0
0
0
0
VDDADAC
VDDADAC
VDDADAC
8
8
NA
NA
NA
10-bit DAC
10-bit DAC
10-bit DAC
tv_out1
tv_vfb1
NA
42
TERMINAL DESCRIPTION
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OMAP3515/03 Applications Processor
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SPRS505–FEBRUARY 2008
Table 2-2. Ball Characteristics (CUS Pkg.)(1) (continued)
BALL
BOTTOM
[1]
PIN
NAME [3]
MODE TYPE
BALL
RESET RESET
STATE
[6]
BALL RESET
POWER [9]
HYS
[10]
BUFFER
STRENGTH
(mA) [11]
PULL
U/D
TYPE
[12]
IO
[4]
[5]
REL.
MODE
[8]
CELL [13]
REL.
STATE
[7]
Y23
Y24
A22
tv_vfb2
tv_vref
0
0
0
4
7
0
4
7
0
4
7
0
4
7
0
2
O
I
Z
Z
L
NA
NA
L
0
0
7
VDDADAC
VDDADAC
VDDS
NA
NA
10-bit DAC
10-bit DAC
LVCMOS
cam_hs
IO
IO
Yes
Yes
Yes
Yes
Yes
4
4
4
4
4
PU/ PD
gpio_94
safe_mode
cam_vs
E18
B22
J19
H24
IO
IO
L
L
L
L
L
L
L
L
7
7
7
7
VDDS
VDDS
VDDS
VDDS
PU/ PD
PU/ PD
PU/ PD
PU/ PD
LVCMOS
LVCMOS
LVCMOS
LVCMOS
gpio_95
safe_mode
cam_ xclka
gpio_96
O
IO
safe_mode
cam_pclk
gpio_97
I
IO
safe_mode
cam_fld
IO
IO
cam_global
_reset
gpio_98
safe_mode
cam_d0
4
7
0
IO
AB18
AC18
I
I
L
L
L
L
7
7
VDDS
VDDS
Yes
Yes
4
4
PD
PD
LVDS/
CMOS
gpio_99
safe_mode
cam_d1
4
7
0
I
I
LVDS/
CMOS
gpio_100
safe_mode
cam_d2
4
7
0
4
7
0
4
7
0
4
7
0
4
7
0
4
7
0
4
7
G19
F19
G20
B21
L24
K24
I
L
L
L
L
L
L
L
L
L
L
L
L
7
7
7
7
7
7
VDDS
VDDS
VDDS
VDDS
VDDS
VDDS
Yes
Yes
Yes
Yes
NA
4
4
4
4
4
4
PU/ PD
PU/ PD
PU/ PD
PU/ PD
PD
LVCMOS
LVCMOS
LVCMOS
LVCMOS
gpio_101
safe_mode
cam_d3
IO
I
gpio_102
safe_mode
cam_d4
IO
I
gpio_103
safe_mode
cam_d5
IO
I
gpio_104
safe_mode
cam_d6
IO
I
LVDS/
CMOS
gpio_105
safe_mode
cam_d7
IO
I
NA
PD
LVDS/
CMOS
gpio_106
safe_mode
IO
Submit Documentation Feedback
TERMINAL DESCRIPTION
43
OMAP3515/03 Applications Processor
www.ti.com
SPRS505–FEBRUARY 2008
Table 2-2. Ball Characteristics (CUS Pkg.)(1) (continued)
BALL
BOTTOM
[1]
PIN
NAME [3]
MODE TYPE
BALL
RESET RESET
STATE
[6]
BALL RESET
POWER [9]
HYS
[10]
BUFFER
STRENGTH
(mA) [11]
PULL
U/D
TYPE
[12]
IO
[4]
[5]
REL.
MODE
[8]
CELL [13]
REL.
STATE
[7]
J23
K23
F21
G21
C22
F18
cam_d8
gpio_107
safe_mode
cam_d9
0
4
7
0
4
7
0
4
7
0
4
7
0
4
7
0
2
I
L
L
L
L
L
L
L
L
L
L
L
L
7
7
7
7
7
7
VDDS
VDDS
VDDS
VDDS
VDDS
VDDS
NA
NA
4
4
4
4
4
4
PD
LVDS/
CMOS
IO
I
PD
LVDS/
CMOS
gpio_108
safe_mode
cam_d10
gpio_109
safe_mode
cam_d11
gpio_110
safe_mode
cam_ xclkb
gpio_111
safe_mode
cam_wen
IO
I
Yes
Yes
Yes
Yes
PU/ PD
PU/ PD
PU/ PD
PU/ PD
LVCMOS
LVCMOS
LVCMOS
LVCMOS
IO
I
IO
O
IO
I
cam_
O
shutter
gpio_167
safe_mode
cam_ strobe
gpio_126
4
7
0
4
7
0
4
7
0
IO
J20
V20
T21
O
L
L
L
L
7
7
7
VDDS
VDDS
VDDS
Yes
Yes
Yes
4
PU/ PD
PU/ PD
PU/ PD
LVCMOS
LVCMOS
LVCMOS
IO
safe_mode
mcbsp2_fsx
gpio_116
IO
IO
PGM
PGM
4(2)
safe_mode
mcbsp2_
clkx
IO
IO
4(2)
gpio_117
safe_mode
mcbsp2_dr
gpio_118
safe_mode
mcbsp2_dx
gpio_119
safe_mode
mmc1_clk
ms_clk
4
7
0
4
7
0
4
7
0
1
4
7
0
1
4
7
V19
R20
M23
I
PGM
PGM
L
L
L
L
7
7
7
VDDS
VDDS
Yes
Yes
4(2)
4(2)
8
PU/ PD
PU/ PD
PU/ PD
LVCMOS
LVCMOS
LVCMOS
IO
IO
IO
O
O
MMC1_ VDDS Yes
MMC1_ VDDS Yes
gpio_120
safe_mode
mmc1_cmd
ms_bs
IO
L23
IO
O
L
L
7
8
PU/ PD
LVCMOS
gpio_121
safe_mode
IO
44
TERMINAL DESCRIPTION
Submit Documentation Feedback
OMAP3515/03 Applications Processor
www.ti.com
SPRS505–FEBRUARY 2008
Table 2-2. Ball Characteristics (CUS Pkg.)(1) (continued)
BALL
BOTTOM
[1]
PIN
NAME [3]
MODE TYPE
BALL
RESET RESET
STATE
[6]
BALL RESET
POWER [9]
HYS
[10]
BUFFER
STRENGTH
(mA) [11]
PULL
U/D
TYPE
[12]
IO
[4]
[5]
REL.
MODE
[8]
CELL [13]
REL.
STATE
[7]
M22
M21
M20
N23
mmc1_dat0
ms_dat0
0
1
4
7
0
1
4
7
0
1
4
7
0
1
4
7
0
4
7
0
4
7
0
4
7
0
4
7
0
1
4
7
0
1
IO
IO
IO
L
L
L
L
L
L
L
L
7
7
7
7
MMC1_ VDDS Yes
MMC1_ VDDS Yes
MMC1_ VDDS Yes
MMC1_ VDDS Yes
8
8
8
8
PU/ PD
PU/ PD
PU/ PD
PU/ PD
LVCMOS
LVCMOS
LVCMOS
LVCMOS
gpio_122
safe_mode
mmc1_dat1
ms_dat1
IO
IO
IO
gpio_123
safe_mode
mmc1_dat2
ms_dat2
IO
IO
IO
gpio_124
safe_mode
mmc1_dat3
ms_dat3
IO
IO
IO
gpio_125
safe_mode
mmc1_dat4
gpio_126
N22
N21
N20
P24
Y1
IO
IO
L
L
L
L
L
L
L
L
L
L
7
7
7
7
7
VDDS
VDDS
VDDS
VDDS
VDDS
No
No
8
8
8
8
4
PD
PD
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
safe_mode
mmc1_dat5
gpio_127
IO
IO
safe_mode
mmc1_dat6
gpio_128
IO
IO
No
PD
safe_mode
mmc1_dat7
gpio_129
IO
IO
No
PD
safe_mode
mmc2_clk
mcspi3_clk
gpio_130
O
Yes
PU/ PD
IO
IO
safe_mode
mmc2_ cmd
AB5
AB3
Y3
IO
IO
H
H
H
H
H
H
7
7
7
VDDS
VDDS
VDDS
Yes
Yes
Yes
4
4
4
PU/ PD
PU/ PD
PU/ PD
LVCMOS
LVCMOS
LVCMOS
mcspi3_
simo
gpio_131
safe_mode
mmc2_ dat0
4
7
0
1
IO
IO
IO
mcspi3_
somi
gpio_132
safe_mode
mmc2_ dat1
gpio_133
4
7
0
4
7
IO
IO
IO
safe_mode
Submit Documentation Feedback
TERMINAL DESCRIPTION
45
OMAP3515/03 Applications Processor
www.ti.com
SPRS505–FEBRUARY 2008
Table 2-2. Ball Characteristics (CUS Pkg.)(1) (continued)
BALL
BOTTOM
[1]
PIN
NAME [3]
MODE TYPE
BALL
RESET RESET
STATE
[6]
BALL RESET
POWER [9]
HYS
[10]
BUFFER
STRENGTH
(mA) [11]
PULL
U/D
TYPE
[12]
IO
[4]
[5]
REL.
MODE
[8]
CELL [13]
REL.
STATE
[7]
W3
V3
mmc2_ dat2
mcspi3_cs1
gpio_134
0
1
4
7
0
1
4
7
0
1
IO
O
H
H
L
H
H
L
7
7
7
VDDS
Yes
Yes
Yes
4
4
4
PU/ PD
PU/ PD
PU/ PD
LVCMOS
LVCMOS
LVCMOS
IO
safe_mode
mmc2_ dat3
mcspi3_cs0
gpio_135
IO
IO
IO
VDDS
VDDS
safe_mode
mmc2_ dat4
AB2
IO
O
mmc2_dir_d
at0
mmc3_dat0
gpio_136
3
4
7
0
1
IO
IO
safe_mode
mmc2_ dat5
AA2
IO
O
L
L
L
L
L
L
7
7
7
VDDS
VDDS
VDDS
Yes
Yes
Yes
4
4
4
PU/ PD
PU/ PD
PU/ PD
LVCMOS
LVCMOS
LVCMOS
mmc2_dir_d
at1
cam_global
_reset
2
IO
mmc3_dat1
gpio_137
3
4
7
0
1
IO
IO
safe_mode
mmc2_ dat6
Y2
IO
O
mmc2_dir_
cmd
cam_
shutter
2
O
mmc3_dat2
gpio_138
3
4
7
0
1
3
4
7
0
1
4
7
0
1
4
7
IO
IO
safe_mode
mmc2_ dat7
mmc2_ clkin
mmc3_dat3
gpio_139
AA1
IO
I
IO
IO
safe_mode
mcbsp3_dx
uart2_cts
V6
V5
IO
I
L
L
L
L
7
7
VDDS
VDDS
Yes
Yes
4
4
PU/ PD
PU/ PD
LVCMOS
LVCMOS
gpio_140
IO
safe_mode
mcbsp3_dr
uart2_rts
I
O
IO
gpio_141
safe_mode
46
TERMINAL DESCRIPTION
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OMAP3515/03 Applications Processor
www.ti.com
SPRS505–FEBRUARY 2008
Table 2-2. Ball Characteristics (CUS Pkg.)(1) (continued)
BALL
BOTTOM
[1]
PIN
NAME [3]
MODE TYPE
BALL
RESET RESET
STATE
[6]
BALL RESET
POWER [9]
HYS
[10]
BUFFER
STRENGTH
(mA) [11]
PULL
U/D
TYPE
[12]
IO
[4]
[5]
REL.
MODE
[8]
CELL [13]
REL.
STATE
[7]
W4
V4
mcbsp3_
clkx
0
IO
L
L
L
L
7
7
VDDS
Yes
Yes
4
4
PU/ PD
LVCMOS
LVCMOS
uart2_tx
gpio_142
safe_mode
mcbsp3_fsx
uart2_rx
1
4
7
0
1
4
7
0
4
7
0
4
7
0
4
7
0
2
O
IO
IO
I
VDDS
PU/ PD
gpio_143
safe_mode
uart1_tx
IO
W7
W6
AC2
V7
O
L
L
L
L
L
L
L
L
7
7
7
7
VDDS
VDDS
VDDS
VDDS
Yes
Yes
Yes
Yes
4
4
4
4
PU/ PD
PU/ PD
PU/ PD
PU/ PD
LVCMOS
LVCMOS
LVCMOS
LVCMOS
gpio_148
safe_mode
uart1_rts
IO
O
gpio_149
safe_mode
uart1_cts
gpio_150
safe_mode
uart1_rx
IO
I
IO
I
mcbsp1_
clkr
IO
mcspi4_clk
gpio_151
3
4
7
0
IO
IO
safe_mode
W19
mcbsp1_
clkr
IO
L
L
L
L
7
7
VDDS
VDDS
Yes
Yes
4
4
PU/ PD
PU/ PD
LVCMOS
LVCMOS
mcspi4_clk
gpio_156
1
4
7
0
1
IO
IO
safe_mode
mcbsp1_fsr
AB20
IO
I
adpllv2d_dit
hering_en1
cam_global
_reset
2
IO
IO
gpio_157
safe_mode
mcbsp1_dx
4
7
0
1
W18
IO
IO
L
L
L
L
7
7
VDDS
VDDS
Yes
Yes
4
4
PU/ PD
LVCMOS
LVCMOS
mcspi4_
simo
mcbsp3_dx
gpio_158
2
4
7
0
1
IO
IO
safe_mode
mcbsp1_dr
Y18
I
PU/ PD
mcspi4_
somi
IO
mcbsp3_dr
2
O
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TERMINAL DESCRIPTION
47
OMAP3515/03 Applications Processor
www.ti.com
SPRS505–FEBRUARY 2008
Table 2-2. Ball Characteristics (CUS Pkg.)(1) (continued)
BALL
BOTTOM
[1]
PIN
NAME [3]
MODE TYPE
BALL
RESET RESET
STATE
[6]
BALL RESET
POWER [9]
HYS
[10]
BUFFER
STRENGTH
(mA) [11]
PULL
U/D
TYPE
[12]
IO
[4]
[5]
REL.
MODE
[8]
CELL [13]
REL.
STATE
[7]
gpio_159
safe_mode
mcbsp_clks
4
7
0
2
IO
AA18
I
L
L
7
VDDS
Yes
4
PU/ PD
LVCMOS
cam_
O
shutter
gpio_160
uart1_cts
4
5
7
0
1
2
4
7
0
IO
I
safe_mode
mcbsp1_fsx
mcspi4_cs0
mcbsp3_fsx
gpio_161
AA19
V18
IO
IO
IO
IO
L
L
L
L
7
7
VDDS
VDDS
Yes
Yes
4
4
PU/ PD
PU/ PD
LVCMOS
LVCMOS
safe_mode
mcbsp1_
clkx
IO
IO
IO
mcbsp3_
clkx
2
gpio_162
4
7
0
safe_mode
A23
B23
B24
C23
uart3_cts_
rctx
IO
IO
H
H
H
H
H
H
H
H
7
7
7
7
VDDS
VDDS
VDDS
VDDS
Yes
Yes
Yes
Yes
4
4
4
4
PU/ PD
PU/ PD
PU/ PD
PU/ PD
LVCMOS
LVCMOS
LVCMOS
LVCMOS
gpio_163
4
7
0
safe_mode
uart3_rts_
sd
O
gpio_164
4
7
0
IO
safe_mode
uart3_rx_
irrx
I
gpio_165
4
7
0
IO
safe_mode
uart3_tx_
irtx
O
gpio_166
safe_mode
hsusb0_clk
gpio_120
4
7
0
4
7
0
4
7
0
4
7
0
4
IO
R21
R23
P23
R22
I
L
H
L
L
H
L
7
7
7
7
VDDS
VDDS
VDDS
VDDS
Yes
Yes
Yes
Yes
4
4
4
4
PU/ PD
PU/ PD
PU/ PD
PU/ PD
LVCMOS
LVCMOS
LVCMOS
LVCMOS
IO
safe_mode
hsusb0_stp
gpio_121
O
IO
safe_mode
hsusb0_dir
gpio_122
I
IO
safe_mode
hsusb0_nxt
gpio_124
I
L
L
IO
48
TERMINAL DESCRIPTION
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OMAP3515/03 Applications Processor
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SPRS505–FEBRUARY 2008
Table 2-2. Ball Characteristics (CUS Pkg.)(1) (continued)
BALL
BOTTOM
[1]
PIN
NAME [3]
MODE TYPE
BALL
RESET RESET
STATE
[6]
BALL RESET
POWER [9]
HYS
[10]
BUFFER
STRENGTH
(mA) [11]
PULL
U/D
TYPE
[12]
IO
[4]
[5]
REL.
MODE
[8]
CELL [13]
REL.
STATE
[7]
safe_mode
7
0
T24
T23
U24
U23
hsusb0_
data0
IO
O
L
L
L
L
L
L
L
L
7
7
7
7
VDDS
Yes
Yes
Yes
Yes
4
4
4
4
PU/ PD
PU/ PD
PU/ PD
PU/ PD
LVCMOS
LVCMOS
LVCMOS
LVCMOS
uart3_tx_
irtx
2
gpio_125
4
7
0
IO
safe_mode
hsusb0_
data1
IO
I
VDDS
VDDS
VDDS
uart3_rx_
irrx
2
gpio_130
4
7
0
IO
safe_mode
hsusb0_
data2
IO
O
uart3_rts_
sd
2
gpio_131
4
7
0
IO
safe_mode
hsusb0_
data3
IO
IO
IO
uart3_cts_
rctx
2
gpio_169
4
7
0
safe_mode
W24
V23
W23
T22
hsusb0_
data4
IO
IO
L
L
L
L
L
L
L
L
7
7
7
7
VDDS
VDDS
VDDS
VDDS
Yes
Yes
Yes
Yes
4
4
4
4
PU/ PD
PU/ PD
PU/ PD
PU/ PD
LVCMOS
LVCMOS
LVCMOS
LVCMOS
gpio_188
4
7
0
safe_mode
hsusb0_
data5
IO
IO
gpio_189
4
7
0
safe_mode
hsusb0_
data6
IO
IO
gpio_190
4
7
0
safe_mode
hsusb0_
data7
IO
IO
gpio_191
safe_mode
i2c1_scl
4
7
0
0
0
4
7
0
4
K20
K21
IOD
IOD
IOD
IO
H
H
H
H
H
H
0
0
7
VDDS
VDDS
VDDS
Yes
Yes
Yes
4
4
4
PU/ PD Open Drain
PU/ PD Open Drain
PU/ PD Open Drain
i2c1_sda
i2c2_scl
AC15
gpio_168
safe_mode
i2c2_sda
gpio_183
AC14
IOD
IO
H
H
7
VDDS
Yes
4
PU/ PD Open Drain
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TERMINAL DESCRIPTION
49
OMAP3515/03 Applications Processor
www.ti.com
SPRS505–FEBRUARY 2008
Table 2-2. Ball Characteristics (CUS Pkg.)(1) (continued)
BALL
BOTTOM
[1]
PIN
NAME [3]
MODE TYPE
BALL
RESET RESET
STATE
[6]
BALL RESET
POWER [9]
HYS
[10]
BUFFER
STRENGTH
(mA) [11]
PULL
U/D
TYPE
[12]
IO
[4]
[5]
REL.
MODE
[8]
CELL [13]
REL.
STATE
[7]
safe_mode
i2c3_scl
7
0
4
7
0
4
7
0
1
AC13
AC12
Y16
IOD
IO
H
H
H
H
H
H
7
7
0
VDDS
VDDS
VDDS
Yes
Yes
Yes
4
4
4
PU/ PD Open Drain
PU/ PD Open Drain
PU/ PD Open Drain
gpio_184
safe_mode
i2c3_sda
gpio_185
safe_mode
i2c4_scl
IOD
IO
IOD
O
sys_
nvmode1
safe_mode
i2c4_sda
7
0
1
Y15
A24
IOD
O
H
H
H
H
0
7
VDDS
VDDS
Yes
Yes
4
4
PU/ PD Open Drain
sys_
nvmode2
safe_mode
hdq_sio
7
0
1
2
3
4
7
0
1
4
7
0
IOD
I
PU/ PD
LVCMOS
sys_altclk
i2c2_sccbe
i2c3_sccbe
gpio_170
O
O
IO
safe_mode
mcspi1_clk
mmc2_dat4
gpio_171
T5
R4
IO
IO
IO
PGM
PGM
L
L
7
7
VDDS
VDDS
Yes
Yes
4(2)
PU/ PD
PU/ PD
LVCMOS
LVCMOS
safe_mode
mcspi1_
simo
IO
4(2)
mmc2_dat5
gpio_172
1
4
7
0
IO
IO
safe_mode
T4
mcspi1_
somi
IO
PGM
L
7
VDDS
Yes
4(2)
PU/ PD
LVCMOS
mmc2_dat6
gpio_173
1
4
7
0
1
4
7
0
2
IO
IO
safe_mode
mcspi1_cs0
mmc2_dat7
gpio_174
T6
R5
IO
IO
IO
PGM
H
H
7
7
VDDS
VDDS
Yes
Yes
4(2)
PU/ PD
PU/ PD
LVCMOS
LVCMOS
safe_mode
mcspi1_cs3
O
H
4
hsusb2_tll_
data2
IO
hsusb2_
data2
3
IO
gpio_177
4
5
IO
IO
mm2_txdat
50
TERMINAL DESCRIPTION
Submit Documentation Feedback
OMAP3515/03 Applications Processor
www.ti.com
SPRS505–FEBRUARY 2008
Table 2-2. Ball Characteristics (CUS Pkg.)(1) (continued)
BALL
BOTTOM
[1]
PIN
NAME [3]
MODE TYPE
BALL
RESET RESET
STATE
[6]
BALL RESET
POWER [9]
HYS
[10]
BUFFER
STRENGTH
(mA) [11]
PULL
U/D
TYPE
[12]
IO
[4]
[5]
REL.
MODE
[8]
CELL [13]
REL.
STATE
[7]
safe_mode
mcspi2_clk
7
0
2
N5
IO
IO
L
L
7
VDDS
Yes
4
PU/ PD
LVCMOS
hsusb2_tll_
data7
hsusb2_
data7
3
O
gpio_178
4
7
0
IO
safe_mode
N4
mcspi2_
simo
IO
IO
IO
I
L
L
7
VDDS
Yes
4
PU/ PD
LVCMOS
gpt9_pwm_
evt
1
2
3
hsusb2_tll_
data4
hsusb2_
data4
gpio_179
4
7
0
IO
safe_mode
N3
mcspi2_
somi
IO
IO
IO
O
L
L
7
VDDS
Yes
4
PU/ PD
LVCMOS
gpt10_pwm
_evt
1
2
3
hsusb2_tll_
data5
hsusb2_
data5
gpio_180
safe_mode
mcspi2_cs0
4
7
0
1
IO
M5
IO
IO
H
H
7
VDDS
Yes
4
PU/ PD
LVCMOS
gpt11_pwm
_evt
hsusb2_tll_
data6
2
3
IO
O
hsusb2_
data6
gpio_181
safe_mode
mcspi2_cs1
4
7
0
1
IO
M4
O
L
L
7
VDDS
Yes
4
PU/ PD
LVCMOS
gpt8_pwm_
evt
IO
hsusb2_tll_
data3
2
3
IO
IO
hsusb2_
data3
gpio_182
4
5
IO
IO
mm2_txen_
n
safe_mode
sys_32k
7
0
0
AA16
AD15
I
I
Z
Z
I
I
NA
NA
VDDS
VDDS
Yes
Yes
NA
NA
NA
LVCMOS
LVCMOS
sys_xtalin
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TERMINAL DESCRIPTION
51
OMAP3515/03 Applications Processor
www.ti.com
SPRS505–FEBRUARY 2008
Table 2-2. Ball Characteristics (CUS Pkg.)(1) (continued)
BALL
BOTTOM
[1]
PIN
NAME [3]
MODE TYPE
BALL
RESET RESET
STATE
[6]
BALL RESET
POWER [9]
HYS
[10]
BUFFER
STRENGTH
(mA) [11]
PULL
U/D
TYPE
[12]
IO
[4]
[5]
REL.
MODE
[8]
CELL [13]
REL.
STATE
[7]
AD14
Y13
sys_xtalout
sys_clkreq
gpio_1
0
0
4
7
0
4
7
0
O
Z
0
O
1
NA
0
VDDS
VDDS
Yes
Yes
NA
LVCMOS
LVCMOS
IO
IO
4
4
PU/ PD
safe_mode
sys_nirq
W16
I
H
H
7
VDDS
Yes
PU/ PD
LVCMOS
gpio_0
IO
safe_mode
AA10
Y10
sys_
nrespwron
I
Z
0
I
NA
0
VDDS
VDDS
Yes
Yes
NA
4
NA
LVCMOS
LVCMOS
sys_
nreswarm
0
IOD
IO
1 (PU)
PU/ PD
gpio_30
safe_mode
sys_boot0
gpio_2
4
7
0
4
7
0
4
7
0
4
7
0
4
7
0
1
AB12
AC16
AD17
AD18
AC17
I
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
0
0
0
0
0
VDDS
VDDS
VDDS
VDDS
VDDS
Yes
Yes
Yes
Yes
Yes
4
4
4
4
4
PU/ PD
PU/ PD
PU/ PD
PU/ PD
PU/ PD
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
IO
safe_mode
sys_boot1
gpio_3
I
IO
safe_mode
sys_boot2
gpio_4
I
IO
safe_mode
sys_boot3
gpio_5
I
IO
safe_mode
sys_boot4
I
mmc2_dir_d
at2
O
gpio_6
4
7
0
1
IO
safe_mode
sys_boot5
AB16
I
Z
Z
0
VDDS
Yes
4
PU/ PD
LVCMOS
mmc2_dir_d
at3
O
gpio_7
safe_mode
sys_boot6
gpio_8
4
7
0
4
7
0
IO
AA15
AD23
I
Z
0
Z
L
0
7
VDDS
VDDS
Yes
Yes
4
4
PU/ PD
PU/ PD
LVCMOS
LVCMOS
IO
safe_mode
sys_off_
mode
O
gpio_9
4
7
0
4
7
IO
safe_mode
sys_clkout1
gpio_10
Y7
O
L
L
7
VDDS
Yes
4
PU/ PD
LVCMOS
IO
safe_mode
52
TERMINAL DESCRIPTION
Submit Documentation Feedback
OMAP3515/03 Applications Processor
www.ti.com
SPRS505–FEBRUARY 2008
Table 2-2. Ball Characteristics (CUS Pkg.)(1) (continued)
BALL
BOTTOM
[1]
PIN
NAME [3]
MODE TYPE
BALL
RESET RESET
STATE
[6]
BALL RESET
POWER [9]
HYS
[10]
BUFFER
STRENGTH
(mA) [11]
PULL
U/D
TYPE
[12]
IO
[4]
[5]
REL.
MODE
[8]
CELL [13]
REL.
STATE
[7]
AA6
sys_clkout2
gpio_186
0
4
7
0
O
L
L
7
VDDS
Yes
4
PU/ PD
LVCMOS
IO
safe_mode
A1
A2
sys_
ipmcsws
AI
Z
0
AI
NA
NA
VDDS
VDDS
NA
No
NA
NA
NA
NA
Analog
sys_
0
AO
AO
LVCMOS
opmcsws
AB7
AB6
AA7
AA9
jtag_ntrst
jtag_tck
jtag_rtck
0
0
0
0
I
I
L
L
L
L
0
0
0
0
VDDS
VDDS
VDDS
VDDS
Yes
Yes
Yes
Yes
NA
NA
4
PU/ PD
PU/ PD
PU/ PD
PU/ PD
LVCMOS
LVCMOS
LVCMOS
LVCMOS
O
IO
L
0
jtag_tms_tm
sc
H
H
4
AB10
AB9
jtag_tdi
jtag_tdo
0
0
0
4
7
0
4
7
0
1
I
H
L
H
Z
0
0
0
VDDS
VDDS
VDDS
Yes
Yes
Yes
NA
4
PU/ PD
PU/ PD
PU/ PD
LVCMOS
LVCMOS
LVCMOS
O
AC24
jtag_emu0
gpio_11
IO
IO
H
H
4
safe_mode
jtag_emu1
gpio_31
AD24
AC1
IO
IO
H
H
H
H
0
4
VDDS
VDDS
Yes
Yes
4
4
PU/ PD
PU/ PD
LVCMOS
LVCMOS
safe_mode
etk_clk
O
mcbsp5_
clkx
IO
mmc3_clk
hsusb1_stp
gpio_12
2
3
4
5
6
O
O
IO
IO
I
mm1_rxdp
hsusb1_tll_s
tp
AD3
AD6
etk_ctl
0
2
3
4
6
O
IO
O
H
H
H
H
4
4
VDDS
VDDS
Yes
Yes
4
4
PU/ PD
LVCMOS
LVCMOS
mmc3_cmd
hsusb1_clk
gpio_13
IO
O
hsusb1_tll_c
lk
etk_d0
0
1
O
PU/ PD
mcspi3_
simo
IO
mmc3_dat4
2
3
IO
IO
hsusb1_
data0
gpio_14
4
5
6
IO
IO
IO
mm1_rxrcv
hsusb1_tll_
data0
Submit Documentation Feedback
TERMINAL DESCRIPTION
53
OMAP3515/03 Applications Processor
www.ti.com
SPRS505–FEBRUARY 2008
Table 2-2. Ball Characteristics (CUS Pkg.)(1) (continued)
BALL
BOTTOM
[1]
PIN
NAME [3]
MODE TYPE
BALL
RESET RESET
STATE
[6]
BALL RESET
POWER [9]
HYS
[10]
BUFFER
STRENGTH
(mA) [11]
PULL
U/D
TYPE
[12]
IO
[4]
[5]
REL.
MODE
[8]
CELL [13]
REL.
STATE
[7]
AC6
etk_d1
0
1
O
H
H
4
VDDS
Yes
4
PU/ PD
LVCMOS
mcspi3_
somi
IO
hsusb1_
data1
3
IO
gpio_15
4
5
6
IO
IO
IO
mm1_txse0
hsusb1_tll_
data1
AC7
AD8
AC5
AD2
AC8
etk_d2
0
1
3
O
H
H
L
H
H
L
4
4
4
4
4
VDDS
VDDS
VDDS
VDDS
VDDS
Yes
Yes
Yes
Yes
Yes
4
4
4
4
4
PU/ PD
PU/ PD
PU/ PD
PU/ PD
PU/ PD
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
mcspi3_cs0
IO
IO
hsusb1_
data2
gpio_16
4
5
6
IO
IO
IO
mm1_txdat
hsusb1_tll_
data2
etk_d3
0
1
2
3
O
mcspi3_clk
mmc3_dat3
IO
IO
IO
hsusb1_
data7
gpio_17
4
6
IO
IO
hsusb1_tll_
data7
etk_d4
0
1
2
3
O
I
mcbsp5_dr
mmc3_dat0
IO
IO
hsusb1_
data4
gpio_18
4
6
IO
IO
hsusb1_tll_
data4
etk_d5
0
1
2
3
O
L
L
mcbsp5_fsx
mmc3_dat1
IO
IO
IO
hsusb1_
data5
gpio_19
4
6
IO
IO
hsusb1_tll_
data5
etk_d6
0
1
2
3
O
L
L
mcbsp5_dx
mmc3_dat2
IO
IO
IO
hsusb1_
data6
gpio_20
4
IO
54
TERMINAL DESCRIPTION
Submit Documentation Feedback
OMAP3515/03 Applications Processor
www.ti.com
SPRS505–FEBRUARY 2008
Table 2-2. Ball Characteristics (CUS Pkg.)(1) (continued)
BALL
BOTTOM
[1]
PIN
NAME [3]
MODE TYPE
BALL
RESET RESET
STATE
[6]
BALL RESET
POWER [9]
HYS
[10]
BUFFER
STRENGTH
(mA) [11]
PULL
U/D
TYPE
[12]
IO
[4]
[5]
REL.
MODE
[8]
CELL [13]
REL.
STATE
[7]
hsusb1_tll_
data6
6
IO
AD9
etk_d7
0
1
2
3
O
O
L
L
4
VDDS
Yes
4
PU/ PD
LVCMOS
mcspi3_cs1
mmc3_dat7
IO
IO
hsusb1_
data3
gpio_21
4
5
IO
IO
mm1_txen_
n
hsusb1_tll_
data3
6
IO
AC4
etk_d8
0
1
O
O
L
L
4
VDDS
Yes
4
PU/ PD
LVCMOS
sys_drm_
msecure
mmc3_dat6
hsusb1_dir
gpio_22
2
3
4
6
IO
I
IO
O
hsusb1_tll_
dir
AD5
etk_d9
0
1
O
O
L
L
4
VDDS
Yes
4
PU/ PD
LVCMOS
sys_secure_
indicator
mmc3_dat5
hsusb1_nxt
gpio_23
2
3
4
5
6
IO
I
IO
IO
O
mm1_rxdm
hsusb1_tll_
nxt
AC3
AC9
etk_d10
uart1_rx
0
2
3
4
6
O
I
L
L
L
L
L
L
4
4
4
VDDS
VDDS
VDDS
Yes
Yes
Yes
4
4
4
PU/ PD
PU/ PD
PU/ PD
LVCMOS
LVCMOS
LVCMOS
hsusb2_clk
gpio_24
O
IO
O
hsusb2_tll_c
lk
etk_d11
hsusb2_stp
gpio_25
0
3
4
5
6
O
O
IO
IO
I
mm2_rxdp
hsusb2_tll_s
tp
AC10
etk_d12
hsusb2_dir
gpio_26
0
3
4
6
O
I
IO
O
hsusb2_tll_
dir
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SPRS505–FEBRUARY 2008
Table 2-2. Ball Characteristics (CUS Pkg.)(1) (continued)
BALL
BOTTOM
[1]
PIN
NAME [3]
MODE TYPE
BALL
RESET RESET
STATE
[6]
BALL RESET
POWER [9]
HYS
[10]
BUFFER
STRENGTH
(mA) [11]
PULL
U/D
TYPE
[12]
IO
[4]
[5]
REL.
MODE
[8]
CELL [13]
REL.
STATE
[7]
AD11
AC11
etk_d13
hsusb2_nxt
gpio_27
0
3
4
5
6
O
I
L
L
L
4
4
VDDS
Yes
Yes
4
4
PU/ PD
LVCMOS
LVCMOS
IO
IO
O
mm2_rxdm
hsusb2_tll_
nxt
etk_d14
0
3
O
L
VDDS
PU/ PD
hsusb2_
data0
IO
gpio_28
4
5
6
IO
IO
IO
mm2_rxrcv
hsusb2_tll_
data0
AD12
etk_d15
0
3
O
L
L
4
VDDS
Yes
4
PU/ PD
LVCMOS
hsusb2_
data1
IO
gpio_29
4
5
6
IO
IO
IO
mm2_txse0
hsusb2_tll_
data1
(1) NA in this table stands for Not Applicable.
(2) The buffer strength of this IO cell is programmable (2, 4, 6, or 8 mA) according to the selected mode; the default value is described in
the above table.
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2.3 Multiplexing Characteristics
Table 2-3 and Table 2-4 provide a description of the OMAP3515/03 multiplexing on the CBB and CUS
packages, respectively.
Note: Table 2-3 and Table 2-4 do not take into account subsystem pin multiplexing options. Subsystem
pin multiplexing options are described in Section 2.4, Signal Description.
Table 2-3. Multiplexing Characteristics (CBB Pkg.)(1)
Ball
Bottom
Ball
Top
Mode 0
Mode 1
Mode 2
Mode 3
Mode 4
Mode 5
Mode 6
Mode 7
D6
C6
J2
J1
sdrc_d0
sdrc_d1
sdrc_d2
sdrc_d3
sdrc_d4
sdrc_d5
sdrc_d6
sdrc_d7
sdrc_d8
sdrc_d9
sdrc_d10
sdrc_d11
sdrc_d12
sdrc_d13
sdrc_d14
sdrc_d15
sdrc_d16
sdrc_d17
sdrc_d18
sdrc_d19
sdrc_d20
sdrc_d21
sdrc_d22
sdrc_d23
sdrc_d24
sdrc_d25
sdrc_d26
sdrc_d27
sdrc_d28
sdrc_d29
sdrc_d30
sdrc_d31
sdrc_ba0
sdrc_ba1
sdrc_a0
sdrc_a1
sdrc_a2
sdrc_a3
sdrc_a4
sdrc_a5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
B6
G2
C8
G1
C9
F2
A7
F1
B9
D2
A9
D1
C14
B14
C15
B16
D17
C17
B17
D18
D11
B10
C11
D12
C12
A11
B13
D14
C18
A19
B19
B20
D20
A21
B21
C21
H9
B13
A13
B14
A14
B16
A16
B19
A19
B3
A3
B5
A5
B8
A8
B9
A9
B21
A21
D22
D23
E22
E23
G22
G23
AB21
AC21
N22
N 23
P22
P23
R22
R23
H10
A4
B4
B3
C5
C4
D5
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SPRS505–FEBRUARY 2008
Table 2-3. Multiplexing Characteristics (CBB Pkg.)(1) (continued)
Ball
Bottom
Ball
Top
Mode 0
Mode 1
Mode 2
Mode 3
Mode 4
Mode 5
Mode 6
Mode 7
C3
C2
T22
T23
sdrc_a6
sdrc_a7
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
C1
U22
U23
V22
V23
W22
W23
Y22
M22
M23
A11
B11
J22
sdrc_a8
-
-
D4
sdrc_a9
-
-
D3
sdrc_a10
sdrc_a11
sdrc_a12
sdrc_a13
sdrc_a14
sdrc_ncs0
sdrc_ncs1
sdrc_clk
-
-
D2
-
-
D1
-
-
E2
-
-
E1
-
-
H11
H12
A13
A14
H16
H17
H14
H13
H15
B7
-
-
-
-
-
-
sdrc_nclk
sdrc_cke0
sdrc_cke1
sdrc_nras
sdrc_ncas
sdrc_nwe
sdrc_dm0
sdrc_dm1
sdrc_dm2
sdrc_dm3
sdrc_dqs0
sdrc_dqs1
sdrc_dqs2
sdrc_dqs3
gpmc_a1
gpmc_a2
gpmc_a3
gpmc_a4
gpmc_a5
gpmc_a6
gpmc_a7
gpmc_a8
gpmc_a9
-
-
-
safe_mode
J23
-
safe_mode
L23
-
-
L22
-
-
K23
C1
-
-
-
-
A16
B11
C20
A6
A17
A6
-
-
-
-
A20
C2
-
-
-
-
A17
A10
A20
N4
B17
B6
-
-
-
-
B20
AC15
AB15
AC16
AB16
AC17
AB17
AC18
AB18
AC19
-
-
gpio_34
gpio_35
gpio_36
gpio_37
gpio_38
gpio_39
gpio_40
gpio_41
gpio_42
safe_mode
safe_mode
safe_mode
safe_mode
safe_mode
safe_mode
safe_mode
safe_mode
safe_mode
M4
L4
K4
T3
R3
N3
M3
L3
sys_
ndmareq2
K3
AB19
gpmc_a10
sys_
-
-
gpio_43
-
-
safe_mode
ndmareq3
K1
L1
M2
M1
N2
gpmc_d0
gpmc_d1
gpmc_d2
gpmc_d3
gpmc_d4
gpmc_d5
gpmc_d6
gpmc_d7
gpmc_d8
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
L2
-
-
P2
T1
V1
V2
W2
H2
N 1
R2
-
-
-
-
R1
-
-
T2
-
-
T1
-
-
AB3
gpio_44
safe_mode
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SPRS505–FEBRUARY 2008
Table 2-3. Multiplexing Characteristics (CBB Pkg.)(1) (continued)
Ball
Bottom
Ball
Top
Mode 0
Mode 1
Mode 2
Mode 3
Mode 4
Mode 5
Mode 6
Mode 7
K2
AC3
AB4
AC4
AB6
AC6
AB7
AC7
Y2
gpmc_d9
gpmc_d10
gpmc_d11
gpmc_d12
gpmc_d13
gpmc_d14
gpmc_d15
gpmc_ncs0
gpmc_ncs1
gpmc_ncs2
gpmc_ncs3
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
gpio_45
gpio_46
gpio_47
gpio_48
gpio_49
gpio_50
gpio_51
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
safe_mode
safe_mode
safe_mode
safe_mode
safe_mode
safe_mode
safe_mode
-
P1
R1
R2
T2
W1
Y1
G4
H3
Y1
gpio_52
gpio_53
gpio_54
safe_mode
safe_mode
safe_mode
V8
NA
U8
NA
sys_
ndmareq0
T8
R8
P8
N8
NA
NA
NA
NA
gpmc_ncs4
gpmc_ncs5
gpmc_ncs6
sys_
ndmareq1
mcbsp4_clkx gpt9_pwm_
evt
gpio_55
gpio_56
gpio_57
gpio_58
-
-
-
-
-
-
-
-
safe_mode
safe_mode
safe_mode
safe_mode
sys_
ndmareq2
mcbsp4_dr gpt10_pwm_
evt
sys_
ndmareq3
mcbsp4_dx gpt11_pwm_
evt
gpmc_ncs7 gpmc_io_dir mcbsp4_fsx gpt8_pwm_
evt
T4
F3
W2
W1
gpmc_clk
-
-
-
-
-
-
gpio_59
-
-
-
-
-
safe_mode
-
gpmc_nadv_
ale
G2
F4
G3
V2
V1
gpmc_noe
gpmc_nwe
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
AC12 gpmc_nbe0_
cle
gpio_60
safe_mode
U3
H1
M8
L8
NA
AB10
AB12
AC10
NA
gpmc_nbe1
gpmc_nwp
gpmc_wait0
gpmc_wait1
gpmc_wait2
gpmc_wait3
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
gpio_61
gpio_62
-
-
-
-
-
-
-
-
-
-
-
-
-
safe_mode
safe_mode
-
gpio_63
gpio_64
gpio_65
safe_mode
safe_mode
safe_mode
K8
J8
NA
sys_
ndmareq1
D28
D26
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
dss_pclk
dss_hsync
dss_vsync
dss_acbias
dss_data0
dss_data1
dss_data2
dss_data3
dss_data4
dss_data5
dss_data6
dss_data7
dss_data8
dss_data9
dss_data10
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
gpio_66
gpio_67
gpio_68
gpio_69
gpio_70
gpio_71
gpio_72
gpio_73
gpio_74
gpio_75
gpio_76
gpio_77
gpio_78
gpio_79
gpio_80
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
safe_mode
safe_mode
safe_mode
safe_mode
safe_mode
safe_mode
safe_mode
safe_mode
safe_mode
safe_mode
safe_mode
safe_mode
safe_mode
safe_mode
safe_mode
-
D27
-
E27
-
AG22
AH22
AG23
AH23
AG24
AH24
E26
uart1_cts
uart1_rts
-
-
uart3_rx_irrx
uart3_tx_irtx
uart1_tx
F28
uart1_rx
F27
-
-
-
G26
AD28
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OMAP3515/03 Applications Processor
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SPRS505–FEBRUARY 2008
Table 2-3. Multiplexing Characteristics (CBB Pkg.)(1) (continued)
Ball
Bottom
Ball
Top
Mode 0
Mode 1
Mode 2
Mode 3
Mode 4
Mode 5
Mode 6
Mode 7
AD27
AB28
AB27
AA28
AA27
G25
H27
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
dss_data11
dss_data12
dss_data13
dss_data14
dss_data15
dss_data16
dss_data17
dss_data18
dss_data19
dss_data20
dss_data21
dss_data22
dss_data23
tv_out2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
gpio_81
gpio_82
gpio_83
gpio_84
gpio_85
gpio_86
gpio_87
gpio_88
gpio_89
gpio_90
gpio_91
gpio_92
gpio_93
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
safe_mode
safe_mode
safe_mode
safe_mode
safe_mode
safe_mode
safe_mode
safe_mode
safe_mode
safe_mode
safe_mode
safe_mode
safe_mode
-
-
-
-
-
-
-
-
-
-
-
-
-
H26
mcspi3_clk
dss_data0
H25
mcspi3_simo
dss_data1
E28
mcspi3_somi
dss_data2
J26
mcspi3_cs0
dss_data3
AC27
AC28
W28
Y28
mcspi3_cs1
dss_data4
-
-
-
-
-
-
-
-
-
-
dss_data5
-
-
-
-
-
-
-
-
-
-
tv_out1
-
-
Y27
tv_vfb1
-
-
W27
W26
A24
tv_vfb2
-
-
tv_vref
-
-
cam_hs
gpio_94
gpio_95
gpio_96
gpio_97
gpio_98
safe_mode
safe_mode
safe_mode
safe_mode
safe_mode
A23
cam_vs
C25
cam_xclka
cam_pclk
cam_fld
C27
C23
cam_global_
reset
AG17
AH17
B24
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
cam_d0
cam_d1
cam_d2
cam_d3
cam_d4
cam_d5
cam_d6
cam_d7
cam_d8
cam_d9
cam_d10
cam_d11
cam_xclkb
cam_wen
cam_strobe
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
gpio_99
gpio_100
gpio_101
gpio_102
gpio_103
gpio_104
gpio_105
gpio_106
gpio_107
gpio_108
gpio_109
gpio_110
gpio_111
gpio_167
gpio_126
gpio_112
gpio_113
gpio_114
gpio_115
gpio_116
gpio_117
gpio_118
gpio_119
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
safe_mode
safe_mode
safe_mode
safe_mode
safe_mode
safe_mode
safe_mode
safe_mode
safe_mode
safe_mode
safe_mode
safe_mode
safe_mode
safe_mode
safe_mode
safe_mode
safe_mode
safe_mode
safe_mode
safe_mode
safe_mode
safe_mode
safe_mode
-
-
C24
D24
A25
-
-
-
K28
-
L28
-
K27
-
L27
-
B25
-
C26
B26
-
-
B23
cam_shutter
D25
AG19
AH19
AG18
AH18
P21
-
-
-
-
-
-
-
-
-
-
-
-
mcbsp2_fsx
mcbsp2_clkx
mcbsp2_dr
mcbsp2_dx
N21
R21
M21
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SPRS505–FEBRUARY 2008
Table 2-3. Multiplexing Characteristics (CBB Pkg.)(1) (continued)
Ball
Ball
Top
Mode 0
Mode 1
Mode 2
Mode 3
Mode 4
Mode 5
Mode 6
Mode 7
Bottom
N28
M27
N27
N26
N25
P28
N A
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
mmc1_clk
mmc1_cmd
mmc1_dat0
mmc1_dat1
mmc1_dat2
mmc1_dat3
mmc1_dat4
mmc1_dat5
mmc1_dat6
mmc1_dat7
mmc2_clk
ms_clk
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
gpio_120
gpio_121
gpio_122
gpio_123
gpio_124
gpio_125
gpio_126
gpio_127
gpio_128
gpio_129
gpio_130
gpio_131
gpio_132
gpio_133
gpio_134
gpio_135
gpio_136
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
safe_mode
safe_mode
safe_mode
safe_mode
safe_mode
safe_mode
safe_mode
safe_mode
safe_mode
safe_mode
safe_mode
safe_mode
safe_mode
safe_mode
safe_mode
safe_mode
safe_mode
ms_bs
-
ms_dat0
-
ms_dat1
-
ms_dat2
-
ms_dat3
-
P27
-
-
P26
-
-
R27
R25
AE2
AG5
AH5
AH4
AG4
AF4
AE4
-
-
-
-
mcspi3_clk
-
mmc2_cmd mcspi3_simo
mmc2_dat0 mcspi3_somi
-
-
mmc2_dat1
-
-
mmc2_dat2 mcspi3_cs1
mmc2_dat3 mcspi3_cs0
-
-
mmc2_dat4
mmc2_dat5
mmc2_dat6
mmc2_dir_
dat0
mmc3_dat0
AH3
AF3
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
mmc2_dir_ cam_global_ mmc3_dat1
gpio_137
gpio_138
gpio_139
gpio_140
gpio_141
gpio_142
gpio_143
gpio_144
gpio_145
gpio_146
gpio_147
hsusb3_tll_
stp
mm3_rxdp
safe_mode
safe_mode
safe_mode
safe_mode
safe_mode
safe_mode
safe_mode
safe_mode
safe_mode
safe_mode
safe_mode
dat1
reset
mmc2_dir_
cmd
cam_shutter mmc3_dat2
hsusb3_tll_
dir
-
AE3
mmc2_dat7 mmc2_clkin
-
-
-
-
-
mmc3_dat3
hsusb3_tll_
nxt
mm3_rxdm
AF6
mcbsp3_dx
mcbsp3_dr
mcbsp3_clkx
mcbsp3_fsx
uart2_cts
uart2_cts
uart2_rts
uart2_tx
-
-
-
-
-
-
-
-
hsusb3_tll_
data4
-
-
-
-
-
-
-
-
AE6
hsusb3_tll_
data5
AF5
hsusb3_tll_
data6
AE5
uart2_rx
hsusb3_tll_
data7
AB26
AB25
AA25
AD25
mcbsp3_dx
gpt9_pwm_
evt
-
-
-
-
uart2_rts
mcbsp3_dr gpt10_pwm_
evt
uart2_tx
mcbsp3_clkx gpt11_pwm_
evt
uart2_rx
mcbsp3_fsx gpt8_pwm_
evt
AA8
AA9
W8
NA
NA
NA
uart1_tx
uart1_rts
uart1_cts
-
-
-
-
-
-
-
-
-
gpio_148
gpio_149
gpio_150
-
-
-
-
-
safe_mode
safe_mode
safe_mode
hsusb3_tll_
clk
Y8
NA
NA
uart1_rx
-
-
mcbsp1_clkr mcspi4_clk
gpio_151
gpio_152
-
-
safe_mode
safe_mode
AE1
mcbsp4_clkx
-
-
-
-
-
-
hsusb3_tll_
data1
mm3_txse0
AD1
AD2
NA
NA
mcbsp4_dr
mcbsp4_dx
-
-
gpio_153
gpio_154
hsusb3_tll_
data0
mm3_rxrcv
mm3_txdat
safe_mode
safe_mode
hsusb3_tll_
data2
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61
OMAP3515/03 Applications Processor
www.ti.com
SPRS505–FEBRUARY 2008
Table 2-3. Multiplexing Characteristics (CBB Pkg.)(1) (continued)
Ball
Bottom
Ball
Top
Mode 0
Mode 1
Mode 2
Mode 3
Mode 4
Mode 5
Mode 6
Mode 7
AC1
NA
mcbsp4_fsx
-
-
-
-
gpio_155
hsusb3_tll_ mm3_txen_n safe_mode
data3
Y21
NA
NA
mcbsp1_clkr mcspi4_clk
-
-
gpio_156
gpio_157
-
-
-
-
safe_mode
safe_mode
AA21
mcbsp1_fsr
adpllv2d_
dithering_en
1
cam_global_
reset
V21
U21
T21
K26
W21
H18
NA
NA
NA
NA
NA
NA
mcbsp1_dx mcspi4_simo mcbsp3_dx
mcbsp1_dr mcspi4_somi mcbsp3_dr
-
-
-
-
-
-
gpio_158
gpio_159
gpio_160
gpio_161
gpio_162
gpio_163
-
-
-
-
-
-
-
safe_mode
safe_mode
safe_mode
safe_mode
safe_mode
safe_mode
-
mcbsp_clks
-
cam_shutter
uart1_cts
mcbsp1_fsx mcspi4_cs0 mcbsp3_fsx
-
-
-
mcbsp1_clkx
-
-
mcbsp3_clkx
-
uart3_cts_rct
x
H19
H20
H21
T28
T25
R28
T26
T27
NA
N A
NA
NA
NA
NA
NA
NA
uart3_rts_sd
uart3_rx_irrx
uart3_tx_irtx
hsusb0_clk
hsusb0_stp
hsusb0_dir
hsusb0_nxt
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
gpio_164
gpio_165
gpio_166
gpio_120
gpio_121
gpio_122
gpio_124
gpio_125
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
safe_mode
safe_mode
safe_mode
safe_mode
safe_mode
safe_mode
safe_mode
safe_mode
-
-
-
-
-
-
hsusb0_
data0
uart3_tx_irtx
U28
U27
U26
U25
V28
V27
V26
NA
NA
NA
NA
NA
NA
NA
hsusb0_
data1
-
-
-
-
-
-
-
uart3_rx_irrx
uart3_rts_sd
-
-
-
-
-
-
-
gpio_130
gpio_131
gpio_169
gpio_188
gpio_189
gpio_190
gpio_191
-
-
-
-
-
-
-
-
-
-
-
-
-
-
safe_mode
safe_mode
safe_mode
safe_mode
safe_mode
safe_mode
safe_mode
hsusb0_
data2
hsusb0_
data3
uart3_cts_
rctx
hsusb0_
data4
-
-
-
-
hsusb0_
data5
hsusb0_
data6
hsusb0_
data7
K21
J21
NA
NA
NA
NA
NA
NA
NA
i2c1_scl
i2c1_sda
i2c2_scl
i2c2_sda
i2c3_scl
i2c3_sda
i2c4_scl
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
AF15
AE15
AF14
AG14
AD26
gpio_168
gpio_183
gpio_184
gpio_185
-
safe_mode
safe_mode
safe_mode
safe_mode
safe_mode
sys_
nvmode1
AE26
NA
i2c4_sda
sys_
-
-
-
-
-
safe_mode
nvmode2
J25
AB3
AB4
AA4
AC2
NA
NA
NA
NA
NA
hdq_sio
sys_altclk
i2c2_sccbe
i2c3_sccbe
gpio_170
gpio_171
gpio_172
gpio_173
gpio_174
-
-
-
-
-
-
-
-
-
-
safe_mode
safe_mode
safe_mode
safe_mode
safe_mode
mcspi1_clk
mmc2_dat4
-
-
-
-
-
-
-
-
mcspi1_simo mmc2_dat5
mcspi1_somi mmc2_dat6
mcspi1_cs0 mmc2_dat7
62
TERMINAL DESCRIPTION
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OMAP3515/03 Applications Processor
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SPRS505–FEBRUARY 2008
Table 2-3. Multiplexing Characteristics (CBB Pkg.)(1) (continued)
Ball
Bottom
Ball
Top
Mode 0
Mode 1
Mode 2
Mode 3
Mode 4
Mode 5
Mode 6
Mode 7
AC3
NA
mcspi1_cs1
adpllv2d_
dithering_en
2
-
mmc3_cmd
gpio_175
-
-
safe_mode
AB1
AB2
NA
NA
mcspi1_cs2
mcspi1_cs3
-
-
-
mmc3_clk
gpio_176
gpio_177
-
-
-
safe_mode
safe_mode
hsusb2_tll_
data2
hsusb2_
data2
mm2_txdat
AA3
Y2
NA
NA
NA
NA
NA
mcspi2_clk
-
hsusb2_tll_
data7
hsusb2_
data7
gpio_178
gpio_179
gpio_180
gpio_181
gpio_182
-
-
-
-
-
-
safe_mode
safe_mode
safe_mode
safe_mode
safe_mode
mcspi2_simo gpt9_pwm_
evt
hsusb2_tll_
data4
hsusb2_
data4
-
Y3
mcspi2_somi gpt10_pwm_ hsusb2_tll_
evt data5
hsusb2_
data5
-
Y4
mcspi2_cs0 gpt11_pwm_ hsusb2_tll_
hsusb2_
data6
-
evt
data6
V3
mcspi2_cs1
gpt8_pwm_
evt
hsusb2_tll_
data3
hsusb2_
data3
mm2_txen_n
AE25
AE17
AF17
AF25
AF26
AH25
NA
NA
NA
NA
NA
NA
sys_32k
sys_xtalin
sys_xtalout
sys_clkreq
sys_nirq
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
gpio_1
gpio_0
-
safe_mode
safe_mode
-
sys_nrespwr
on
AF24
NA
sys_nreswar
m
-
-
-
gpio_30
-
-
safe_mode
AH26
AG26
AE14
AF18
AF19
NA
NA
NA
NA
NA
sys_boot0
sys_boot1
sys_boot2
sys_boot3
sys_boot4
-
-
-
-
-
-
-
-
-
-
-
-
-
-
gpio_2
gpio_3
gpio_4
gpio_5
gpio_6
-
-
-
-
-
-
-
-
-
-
safe_mode
safe_mode
safe_mode
safe_mode
safe_mode
mmc2_dir_
dat2
AE21
NA
sys_boot5
sys_boot6
mmc2_dir_
dat3
-
-
gpio_7
-
-
safe_mode
AF21
AF22
N A
NA
-
-
-
-
-
-
gpio_8
gpio_9
-
-
-
-
safe_mode
safe_mode
sys_off_
mode
AG25
AE22
B1
NA
NA
NA
NA
sys_clkout1
sys_clkout2
sys_ipmcsws
-
-
-
-
-
-
-
-
-
-
-
-
gpio_10
-
-
-
-
-
-
-
-
safe_mode
gpio_186
safe_mode
-
-
-
-
A1
sys_
opmcsws
AA17
AA13
AA12
AA18
NA
NA
NA
NA
jtag_ntrst
jtag_tck
jtag_rtck
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
jtag_tms_
tmsc
AA20
AA19
AA11
AA10
NA
NA
NA
NA
jtag_tdi
jtag_tdo
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
jtag_emu0
jtag_emu1
gpio_11
gpio_31
safe_mode
safe_mode
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63
OMAP3515/03 Applications Processor
www.ti.com
SPRS505–FEBRUARY 2008
Table 2-3. Multiplexing Characteristics (CBB Pkg.)(1) (continued)
Ball
Bottom
Ball
Top
Mode 0
etk_clk
etk_ctl
Mode 1
Mode 2
mmc3_clk
mmc3_cmd
Mode 3
Mode 4
gpio_12
gpio_13
gpio_14
gpio_15
gpio_16
gpio_17
gpio_18
gpio_19
gpio_20
gpio_21
gpio_22
gpio_23
gpio_24
gpio_25
gpio_26
gpio_27
gpio_28
gpio_29
Mode 5
Mode 6
Mode 7
AF10
AE10
AF11
AG12
AH12
AE13
AE11
AH9
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
mcbsp5_clkx
-
hsusb1_stp
hsusb1_clk
mm1_rxdp
hsusb1_tll_
stp
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
hsusb1_tll_
clk
etk_d0
etk_d1
etk_d2
etk_d3
etk_d4
etk_d5
etk_d6
etk_d7
etk_d8
etk_d9
etk_d10
etk_d11
etk_d12
etk_d13
etk_d14
etk_d15
mcspi3_simo mmc3_dat4
hsusb1_
data0
mm1_rxrcv
hsusb1_tll_
data0
mcspi3_somi
mcspi3_cs0
mcspi3_clk
mcbsp5_dr
-
hsusb1_
data1
mm1_txse0
hsusb1_tll_
data1
-
hsusb1_
data2
mm1_txdat
hsusb1_tll_
data2
mmc3_dat3
mmc3_dat0
hsusb1_
data7
-
-
-
-
hsusb1_tll_
data7
hsusb1_
data4
hsusb1_tll_
data4
mcbsp5_fsx mmc3_dat1
mcbsp5_dx mmc3_dat2
mcspi3_cs1 mmc3_dat7
hsusb1_
data5
hsusb1_tll_
data5
AF13
AH14
AF9
hsusb1_
data6
hsusb1_tll_
data6
hsusb1_
data3
mm1_txen_n hsusb1_tll_
data3
sys_drm_
msecure
mmc3_dat6
hsusb1_dir
hsusb1_nxt
hsusb2_clk
hsusb2_stp
hsusb2_dir
hsusb2_nxt
-
hsusb1_tll_
dir
AG9
AE7
sys_secure_ mmc3_dat5
indicator
mm1_rxdm
-
hsusb1_tll_
nxt
-
-
-
-
-
-
uart1_rx
hsusb2_tll_
clk
AF7
-
-
-
-
-
mm2_rxdp
-
hsusb2_tll_
stp
AG7
AH7
hsusb2_tll_
dir
mm2_rxdm
mm2_rxrcv
mm2_txse0
hsusb2_tll_
nxt
AG8
AH8
hsusb2_
data0
hsusb2_tll_
data0
hsusb2_
data1
hsusb2_tll_
data1
(1) NA in table stands for Not Applicable.
64
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SPRS505–FEBRUARY 2008
Table 2-4. Multiplexing Characteristics (CUS Pkg.)(1)
Ball
Mode 0
Mode 1
Mode 2
Mode 3
Mode 4
Mode 5
Mode 6
Mode 7
Bottom
D7
sdrc_d0
sdrc_d1
sdrc_d2
sdrc_d3
sdrc_d4
sdrc_d5
sdrc_d6
sdrc_d7
sdrc_d8
sdrc_d9
sdrc_d10
sdrc_d11
sdrc_d12
sdrc_d13
sdrc_d14
sdrc_d15
sdrc_d16
sdrc_d17
sdrc_d18
sdrc_d19
sdrc_d20
sdrc_d21
sdrc_d22
sdrc_d23
sdrc_d24
sdrc_d25
sdrc_d26
sdrc_d27
sdrc_d28
sdrc_d29
sdrc_d30
sdrc_d31
sdrc_ba0
sdrc_ba1
sdrc_a0
sdrc_a1
sdrc_a2
sdrc_a3
sdrc_a4
sdrc_a5
sdrc_a6
sdrc_a7
sdrc_a8
sdrc_a9
sdrc_a10
sdrc_a11
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
C5
C6
B5
D9
D10
C7
B7
B11
C12
B12
D13
C13
B14
A14
B15
C9
E12
B8
B9
C10
B10
D12
E13
E15
D15
C15
B16
C16
D16
B17
B18
C18
D18
A4
B4
D6
B3
B2
C3
E3
F6
E10
E9
E7
G6
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OMAP3515/03 Applications Processor
www.ti.com
SPRS505–FEBRUARY 2008
Table 2-4. Multiplexing Characteristics (CUS Pkg.)(1) (continued)
Ball
Mode 0
Mode 1
Mode 2
Mode 3
Mode 4
Mode 5
Mode 6
Mode 7
Bottom
G7
F7
sdrc_a12
sdrc_a13
sdrc_a14
sdrc_ncs0
sdrc_ncs1
sdrc_clk
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
F9
-
-
A19
B19
A10
A11
B20
C20
D19
C19
A20
B6
-
-
-
-
-
-
sdrc_nclk
sdrc_cke0
sdrc_cke1
sdrc_nras
sdrc_ncas
sdrc_nwe
sdrc_dm0
sdrc_dm1
sdrc_dm2
sdrc_dm3
sdrc_dqs0
sdrc_dqs1
sdrc_dqs2
sdrc_dqs3
gpmc_a1
gpmc_a2
gpmc_a3
gpmc_a4
gpmc_a5
gpmc_a6
gpmc_a7
gpmc_a8
gpmc_a9
-
-
-
safe_mode
-
safe_mode
-
-
-
-
-
-
-
-
B13
A7
-
-
-
-
A16
A5
-
-
-
-
A13
A8
-
-
-
-
A17
K4
-
-
gpio_34
gpio_35
gpio_36
gpio_37
gpio_38
gpio_39
gpio_40
gpio_41
gpio_42
safe_mode
safe_mode
safe_mode
safe_mode
safe_mode
safe_mode
safe_mode
safe_mode
safe_mode
K3
K2
J4
J3
J2
J1
H1
H2
sys_
ndmareq2
G2
gpmc_a10
sys_
-
-
gpio_43
-
-
safe_mode
ndmareq3
L2
M1
M2
N2
M3
P1
P2
R1
R2
T2
U1
R3
T3
U2
V1
gpmc_d0
gpmc_d1
gpmc_d2
gpmc_d3
gpmc_d4
gpmc_d5
gpmc_d6
gpmc_d7
gpmc_d8
gpmc_d9
gpmc_d10
gpmc_d11
gpmc_d12
gpmc_d13
gpmc_d14
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
gpio_44
gpio_45
gpio_46
gpio_47
gpio_48
gpio_49
gpio_50
safe_mode
safe_mode
safe_mode
safe_mode
safe_mode
safe_mode
safe_mode
66
TERMINAL DESCRIPTION
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OMAP3515/03 Applications Processor
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SPRS505–FEBRUARY 2008
Table 2-4. Multiplexing Characteristics (CUS Pkg.)(1) (continued)
Ball
Mode 0
Mode 1
Mode 2
Mode 3
Mode 4
Mode 5
Mode 6
Mode 7
Bottom
V2
gpmc_d15
gpmc_ncs0
gpmc_ncs3
-
-
-
-
-
-
-
-
gpio_51
-
-
-
-
-
-
-
safe_mode
-
E2
D2
sys_
gpio_54
safe_mode
ndmareq0
F4
G5
F3
G4
gpmc_ncs4
gpmc_ncs5
gpmc_ncs6
gpmc_ncs7
gpmc_clk
sys_
ndmareq1
mcbsp4_clkx
mcbsp4_dr
mcbsp4_dx
mcbsp4_fsx
gpt9_pwm_
evt
gpio_55
gpio_56
gpio_57
gpio_58
-
-
-
-
-
-
-
-
safe_mode
safe_mode
safe_mode
safe_mode
sys_
ndmareq2
gpt10_pwm_
evt
sys_
ndmareq3
gpt11_pwm_
evt
gpmc_io_dir
gpt8_pwm_
evt
W2
F1
-
-
-
-
-
-
gpio_59
-
-
-
-
-
safe_mode
-
gpmc_nadv_a
le
F2
G3
K5
gpmc_noe
gpmc_nwe
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
gpmc_nbe0_c
le
gpio_60
safe_mode
L1
E1
C1
C2
gpmc_nbe1
gpmc_nwp
gpmc_wait0
gpmc_wait3
-
-
-
-
-
-
-
-
-
-
-
gpio_61
gpio_62
-
-
-
-
-
-
-
-
-
safe_mode
safe_mode
-
sys_
gpio_65
safe_mode
ndmareq1
G22
E22
dss_pclk
dss_hsync
dss_vsync
dss_acbias
dss_data0
dss_data1
dss_data2
dss_data3
dss_data4
dss_data5
dss_data6
dss_data7
dss_data8
dss_data9
dss_data10
dss_data11
dss_data12
dss_data13
dss_data14
dss_data15
dss_data16
dss_data17
dss_data18
dss_data19
dss_data20
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
gpio_66
gpio_67
gpio_68
gpio_69
gpio_70
gpio_71
gpio_72
gpio_73
gpio_74
gpio_75
gpio_76
gpio_77
gpio_78
gpio_79
gpio_80
gpio_81
gpio_82
gpio_83
gpio_84
gpio_85
gpio_86
gpio_87
gpio_88
gpio_89
gpio_90
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
safe_mode
safe_mode
safe_mode
safe_mode
safe_mode
safe_mode
safe_mode
safe_mode
safe_mode
safe_mode
safe_mode
safe_mode
safe_mode
safe_mode
safe_mode
safe_mode
safe_mode
safe_mode
safe_mode
safe_mode
safe_mode
safe_mode
safe_mode
safe_mode
safe_mode
-
-
F22
-
-
J21
-
-
AC19
AB19
AD20
AC20
AD21
AC21
D24
uart1_cts
-
uart1_rts
-
-
-
-
-
uart3_rx_irrx
-
uart3_tx_irtx
-
uart1_tx
-
E23
uart1_rx
-
E24
-
-
F23
-
-
AC22
AC23
AB22
Y22
-
-
-
-
-
-
-
-
W22
V22
-
-
-
-
J22
-
-
G23
G24
H23
-
-
mcspi3_clk
mcspi3_simo
mcspi3_somi
dss_data0
dss_data1
dss_data2
D23
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TERMINAL DESCRIPTION
67
OMAP3515/03 Applications Processor
www.ti.com
SPRS505–FEBRUARY 2008
Table 2-4. Multiplexing Characteristics (CUS Pkg.)(1) (continued)
Ball
Mode 0
Mode 1
Mode 2
Mode 3
Mode 4
Mode 5
Mode 6
Mode 7
Bottom
K22
V21
dss_data21
dss_data22
dss_data23
tv_out2
-
-
-
-
-
-
-
-
-
-
-
-
-
mcspi3_cs0
dss_data3
gpio_91
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
safe_mode
mcspi3_cs1
dss_data4
gpio_92
safe_mode
W21
AA23
AB24
AB23
Y23
-
-
-
-
-
-
-
-
-
-
dss_data5
gpio_93
safe_mode
-
-
-
-
-
-
-
-
-
-
-
-
tv_out1
-
-
tv_vfb1
-
-
tv_vfb2
-
-
Y24
tv_vref
-
-
A22
cam_hs
gpio_94
gpio_95
gpio_96
gpio_97
gpio_98
safe_mode
safe_mode
safe_mode
safe_mode
safe_mode
E18
cam_vs
B22
cam_xclka
cam_pclk
cam_fld
J19
H24
cam_global_r
eset
AB18
AC18
G19
F19
G20
B21
L24
K24
J23
cam_d0
cam_d1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
gpio_99
gpio_100
gpio_101
gpio_102
gpio_103
gpio_104
gpio_105
gpio_106
gpio_107
gpio_108
gpio_109
gpio_110
gpio_111
gpio_167
gpio_126
gpio_116
gpio_117
gpio_118
gpio_119
gpio_120
gpio_121
gpio_122
gpio_123
gpio_124
gpio_125
gpio_126
gpio_127
gpio_128
gpio_129
gpio_130
gpio_131
gpio_132
gpio_133
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
safe_mode
safe_mode
safe_mode
safe_mode
safe_mode
safe_mode
safe_mode
safe_mode
safe_mode
safe_mode
safe_mode
safe_mode
safe_mode
safe_mode
safe_mode
safe_mode
safe_mode
safe_mode
safe_mode
safe_mode
safe_mode
safe_mode
safe_mode
safe_mode
safe_mode
safe_mode
safe_mode
safe_mode
safe_mode
safe_mode
safe_mode
safe_mode
safe_mode
-
-
cam_d2
-
-
cam_d3
-
-
cam_d4
-
-
cam_d5
-
-
cam_d6
-
-
cam_d7
-
-
cam_d8
-
-
K23
F21
G21
C22
F18
J20
cam_d9
-
-
cam_d10
-
-
cam_d11
-
-
cam_xclkb
cam_wen
cam_strobe
mcbsp2_fsx
mcbsp2_clkx
mcbsp2_dr
mcbsp2_dx
mmc1_clk
mmc1_cmd
mmc1_dat0
mmc1_dat1
mmc1_dat2
mmc1_dat3
mmc1_dat4
mmc1_dat5
mmc1_dat6
mmc1_dat7
mmc2_clk
mmc2_cmd
mmc2_dat0
mmc2_dat1
-
-
-
cam_shutter
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
V20
T21
V19
R20
M23
L23
M22
M21
M20
N23
N22
N21
N20
P24
Y1
-
-
-
-
ms_clk
ms_bs
ms_dat0
ms_dat1
ms_dat2
ms_dat3
-
-
-
-
mcspi3_clk
mcspi3_simo
mcspi3_somi
-
AB5
AB3
Y3
68
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OMAP3515/03 Applications Processor
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SPRS505–FEBRUARY 2008
Table 2-4. Multiplexing Characteristics (CUS Pkg.)(1) (continued)
Ball
Mode 0
Mode 1
Mode 2
Mode 3
Mode 4
Mode 5
Mode 6
Mode 7
Bottom
W3
mmc2_dat2
mmc2_dat3
mmc2_dat4
mcspi3_cs1
mcspi3_cs0
-
-
-
-
gpio_134
gpio_135
gpio_136
-
-
-
-
-
-
safe_mode
safe_mode
safe_mode
V3
-
AB2
mmc2_dir_
dat0
mmc3_dat0
AA2
Y2
mmc2_dat5
mmc2_dat6
mmc2_dir_
dat1
cam_global_r
eset
mmc3_dat1
mmc3_dat2
gpio_137
gpio_138
-
-
-
-
safe_mode
safe_mode
mmc2_dir_
cmd
cam_shutter
AA1
V6
mmc2_dat7
mcbsp3_dx
mcbsp3_dr
mcbsp3_clkx
mcbsp3_fsx
uart1_tx
mmc2_clkin
-
mmc3_dat3
gpio_139
gpio_140
gpio_141
gpio_142
gpio_143
gpio_148
gpio_149
gpio_150
gpio_151
gpio_156
gpio_157
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
safe_mode
safe_mode
safe_mode
safe_mode
safe_mode
safe_mode
safe_mode
safe_mode
safe_mode
safe_mode
safe_mode
uart2_cts
-
-
V5
uart2_rts
-
-
W4
V4
uart2_tx
-
-
uart2_rx
-
-
W7
W6
AC2
V7
-
-
-
uart1_rts
-
-
-
uart1_cts
-
-
-
uart1_rx
-
mcbsp1_clkr
-
mcspi4_clk
W19
AB20
mcbsp1_clkr
mcbsp1_fsr
mcspi4_clk
-
-
adpllv2d_
dithering_en1
cam_global_r
eset
W18
Y18
AA18
AA19
V18
A23
B23
B24
C23
R21
R23
P23
R22
T24
mcbsp1_dx
mcbsp1_dr
mcbsp_clks
mcbsp1_fsx
mcbsp1_clkx
uart3_cts_rctx
uart3_rts_sd
uart3_rx_irrx
uart3_tx_irtx
hsusb0_clk
hsusb0_stp
hsusb0_dir
mcspi4_simo
mcbsp3_dx
-
-
-
-
-
-
-
-
-
-
-
-
-
-
gpio_158
gpio_159
gpio_160
gpio_161
gpio_162
gpio_163
gpio_164
gpio_165
gpio_166
gpio_120
gpio_121
gpio_122
gpio_124
gpio_125
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
safe_mode
safe_mode
safe_mode
safe_mode
safe_mode
safe_mode
safe_mode
safe_mode
safe_mode
safe_mode
safe_mode
safe_mode
safe_mode
safe_mode
mcspi4_somi
mcbsp3_dr
-
-
cam_shutter
uart1_cts
mcspi4_cs0
mcbsp3_fsx
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
mcbsp3_clkx
-
-
-
-
-
-
-
hsusb0_nxt
-
hsusb0_
data0
uart3_tx_irtx
T23
U24
U23
W24
V23
W23
T22
K20
hsusb0_
data1
-
-
-
-
-
-
-
-
uart3_rx_irrx
uart3_rts_sd
-
-
-
-
-
-
-
-
gpio_130
gpio_131
gpio_169
gpio_188
gpio_189
gpio_190
gpio_191
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
safe_mode
safe_mode
safe_mode
safe_mode
safe_mode
safe_mode
safe_mode
-
hsusb0_
data2
hsusb0_
data3
uart3_cts_
rctx
hsusb0_
data4
-
-
-
-
-
hsusb0_
data5
hsusb0_
data6
hsusb0_
data7
i2c1_scl
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TERMINAL DESCRIPTION
69
OMAP3515/03 Applications Processor
www.ti.com
SPRS505–FEBRUARY 2008
Table 2-4. Multiplexing Characteristics (CUS Pkg.)(1) (continued)
Ball
Mode 0
Mode 1
Mode 2
Mode 3
Mode 4
Mode 5
Mode 6
Mode 7
Bottom
K21
AC15
AC14
AC13
AC12
Y16
i2c1_sda
i2c2_scl
i2c2_sda
i2c3_scl
i2c3_sda
i2c4_scl
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
gpio_168
gpio_183
gpio_184
gpio_185
-
safe_mode
safe_mode
safe_mode
safe_mode
safe_mode
sys_
nvmode1
Y15
i2c4_sda
sys_
-
-
-
-
-
safe_mode
nvmode2
A24
T5
hdq_sio
sys_altclk
mmc2_dat4
mmc2_dat5
mmc2_dat6
mmc2_dat7
-
i2c2_sccbe
i2c3_sccbe
gpio_170
gpio_171
gpio_172
gpio_173
gpio_174
gpio_177
-
-
-
-
-
-
-
safe_mode
safe_mode
safe_mode
safe_mode
safe_mode
safe_mode
mcspi1_clk
mcspi1_simo
mcspi1_somi
mcspi1_cs0
mcspi1_cs3
-
-
-
-
-
-
-
-
-
R4
T4
-
-
T6
-
R5
hsusb2_tll_
data2
hsusb2_
data2
mm2_txdat
N5
N4
N3
M5
M4
mcspi2_clk
-
hsusb2_tll_
data7
hsusb2_
data7
gpio_178
gpio_179
gpio_180
gpio_181
gpio_182
-
-
-
-
-
-
safe_mode
safe_mode
safe_mode
safe_mode
safe_mode
mcspi2_simo
gpt9_pwm_
evt
hsusb2_tll_
data4
hsusb2_
data4
-
mcspi2_somi gpt10_pwm_
evt
hsusb2_tll_
data5
hsusb2_
data5
-
mcspi2_cs0
gpt11_pwm_
evt
hsusb2_tll_
data6
hsusb2_
data6
-
mcspi2_cs1
gpt8_pwm_
evt
hsusb2_tll_
data3
hsusb2_
data3
mm2_txen_n
AA16
AD15
AD14
Y13
sys_32k
sys_xtalin
sys_xtalout
sys_clkreq
sys_nirq
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
gpio_1
gpio_0
-
safe_mode
safe_mode
-
W16
AA10
sys_nrespwro
n
Y10
sys_nreswar
m
-
-
-
gpio_30
-
-
safe_mode
AB12
AC16
AD17
AD18
AC17
sys_boot0
sys_boot1
sys_boot2
sys_boot3
sys_boot4
-
-
-
-
-
-
-
-
-
-
-
-
-
-
gpio_2
gpio_3
gpio_4
gpio_5
gpio_6
-
-
-
-
-
-
-
-
-
-
safe_mode
safe_mode
safe_mode
safe_mode
safe_mode
mmc2_dir_
dat2
AB16
sys_boot5
sys_boot6
mmc2_dir_
dat3
-
-
gpio_7
-
-
safe_mode
AA15
AD23
-
-
-
-
-
-
gpio_8
gpio_9
-
-
-
-
safe_mode
safe_mode
sys_off_
mode
Y7
AA6
A1
sys_clkout1
sys_clkout2
sys_ipmcsws
-
-
-
-
-
-
-
-
-
-
-
-
gpio_10
-
-
-
-
-
-
-
-
safe_mode
gpio_186
safe_mode
-
-
-
-
A2
sys_
opmcsws
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Table 2-4. Multiplexing Characteristics (CUS Pkg.)(1) (continued)
Ball
Mode 0
Mode 1
Mode 2
Mode 3
Mode 4
Mode 5
Mode 6
Mode 7
Bottom
AB7
jtag_ntrst
jtag_tck
jtag_rtck
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
AB6
AA7
AA9
jtag_tms_
tmsc
AB10
AB9
jtag_tdi
jtag_tdo
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
AC24
AD24
AC1
jtag_emu0
jtag_emu1
etk_clk
-
-
-
gpio_11
gpio_31
gpio_12
-
safe_mode
safe_mode
-
-
-
-
-
mcbsp5_clkx
mmc3_clk
hsusb1_stp
mm1_rxdp
hsusb1_tll_
stp
AD3
AD6
AC6
AC7
AD8
AC5
AD2
AC8
AD9
AC4
AD5
AC3
AC9
AC10
AD11
AC11
AD12
etk_ctl
etk_d0
etk_d1
etk_d2
etk_d3
etk_d4
etk_d5
etk_d6
etk_d7
etk_d8
etk_d9
etk_d10
etk_d11
etk_d12
etk_d13
etk_d14
etk_d15
-
mmc3_cmd
hsusb1_clk
gpio_13
gpio_14
gpio_15
gpio_16
gpio_17
gpio_18
gpio_19
gpio_20
gpio_21
gpio_22
gpio_23
gpio_24
gpio_25
gpio_26
gpio_27
gpio_28
gpio_29
-
hsusb1_tll_
clk
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
mcspi3_simo
mcspi3_somi
mcspi3_cs0
mcspi3_clk
mcbsp5_dr
mcbsp5_fsx
mcbsp5_dx
mcspi3_cs1
mmc3_dat4
hsusb1_
data0
mm1_rxrcv
hsusb1_tll_
data0
-
hsusb1_
data1
mm1_txse0
hsusb1_tll_
data1
-
hsusb1_
data2
mm1_txdat
hsusb1_tll_
data2
mmc3_dat3
hsusb1_
data7
-
hsusb1_tll_
data7
mmc3_dat0
hsusb1_
data4
-
hsusb1_tll_
data4
mmc3_dat1
hsusb1_
data5
-
hsusb1_tll_
data5
mmc3_dat2
hsusb1_
data6
-
hsusb1_tll_
data6
mmc3_dat7
hsusb1_
data3
mm1_txen_n
-
hsusb1_tll_
data3
sys_drm_
msecure
mmc3_dat6
hsusb1_dir
hsusb1_nxt
hsusb2_clk
hsusb2_stp
hsusb2_dir
hsusb2_nxt
hsusb1_tll_
dir
sys_secure_
indicator
mmc3_dat5
mm1_rxdm
-
hsusb1_tll_
nxt
-
-
-
-
-
-
uart1_rx
hsusb2_tll_
clk
-
-
-
-
-
mm2_rxdp
-
hsusb2_tll_
stp
hsusb2_tll_
dir
mm2_rxdm
mm2_rxrcv
mm2_txse0
hsusb2_tll_
nxt
hsusb2_
data0
hsusb2_tll_
data0
hsusb2_
data1
hsusb2_tll_
data1
(1) NA in table stands for Not Applicable.
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2.4 Signal Description
Many signals are available on multiple pins according to the software configuration of the pin multiplexing
options.
1. SIGNAL NAME: The signal name
2. DESCRIPTION: Description of the signal
3. TYPE: Type = Ball type for this specific function:
–
–
–
–
–
–
I = Input
O = Output
Z = High-impedance
D = Open Drain
DS = Differential
A = Analog
4. BALL BOTTOM: Associated ball(s) bottom
5. BALL TOP: Associated ball(s) top
6. SUBSYSTEM PIN MULTIPLEXING: Contains a list of the pin multiplexing options at the
module/subsystem level. The pin function is selected at the module/system level.
Note: The Subsystem Multiplexing Signals are not described in Table 2-1 through Table 2-4.
2.4.1 External Memory Interfaces
Table 2-5. External Memory Interfaces – GPMC Signals Description
SIGNAL
NAME [1]
DESCRIPTION [2]
TYPE [3]
BALL
BOTTOM
(CBB Pkg.)
[4]
BALL TOP
(CBB Pkg.)
[5]
BALL
BOTTOM
(CUS Pkg.)
[4]
SUBSYSTEM PIN
MULTIPLEXING
[6]
gpmc_a1
General-purpose memory address bit 1
General-purpose memory address bit 2
General-purpose memory address bit 3
General-purpose memory address bit 4
General-purpose memory address bit 5
General-purpose memory address bit 6
General-purpose memory address bit 7
General-purpose memory address bit 8
General-purpose memory address bit 9
General-purpose memory address bit 10
O
O
O
O
O
O
O
O
O
O
N4 / K1
M4 / L1
L4 / L2
K4 / P2
T3 / T1
R3 / V1
N3 / V2
M3 / W2
L3 / H2
K3 / K2
AC15 / M2
AB15 / M1
AC16 / N2
AB16 / N1
AC17 / R2
AB17 / R1
AC18 / T2
AB18 / T1
AC19 / AB3
AB19 / AC3
K4/ L2
K3/ M1
K2/ M2
J4/ N2
J3/ M3
J2/ P1
J1/ P2
H1/ R1
H2/ R2
G2/ T2
gpmc_a17/
gpmc_d0
gpmc_a2
gpmc_a3
gpmc_a4
gpmc_a5
gpmc_a6
gpmc_a7
gpmc_a8
gpmc_a9
gpmc_a10
gpmc_a18/
gpmc_d1
gpmc_a19/
gpmc_d2
gpmc_a20/
gpmc_d3
gpmc_a21/
gpmc_d4
gpmc_a22/
gpmc_d5
gpmc_a23/
gpmc_d6
gpmc_a24/
gpmc_d7
gpmc_a25/
gpmc_d8
gpmc_a26/
gpmc_d9
gpmc_a11
gpmc_a12
gpmc_a13
gpmc_a14
gpmc_a15
gpmc_a16
gpmc_a17
General-purpose memory address bit 11
General-purpose memory address bit 12
General-purpose memory address bit 13
General-purpose memory address bit 14
General-purpose memory address bit 15
General-purpose memory address bit 16
General-purpose memory address bit 17
O
O
O
O
O
O
O
P1
R1
R2
T2
AB4
AC4
AB6
AC6
AB7
AC7
AC15
U1
R3
T3
U2
V1
V2
K4
gpmc_d10
gpmc_d11
gpmc_d12
gpmc_d13
gpmc_d14
gpmc_d15
gpmc_a1
W1
Y1
N4
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Table 2-5. External Memory Interfaces – GPMC Signals Description (continued)
SIGNAL
NAME [1]
DESCRIPTION [2]
TYPE [3]
BALL
BOTTOM
(CBB Pkg.)
[4]
BALL TOP
(CBB Pkg.)
[5]
BALL
BOTTOM
(CUS Pkg.)
[4]
SUBSYSTEM PIN
MULTIPLEXING
[6]
gpmc_a18
gpmc_a19
gpmc_a20
gpmc_a21
gpmc_a22
gpmc_a23
gpmc_a24
gpmc_a25
gpmc_a26
gpmc_d0
gpmc_d1
gpmc_d2
gpmc_d3
gpmc_d4
gpmc_d5
gpmc_d6
gpmc_d7
gpmc_d8
gpmc_d9
General-purpose memory address bit 18
General-purpose memory address bit 19
General-purpose memory address bit 20
General-purpose memory address bit 21
General-purpose memory address bit 22
General-purpose memory address bit 23
General-purpose memory address bit 24
General-purpose memory address bit 25
General-purpose memory address bit 26
GPMC Data bit 0
O
O
M4
L4
AB15
AC16
AB16
AC17
AB17
AC18
AB18
AC19
AB19
M2
K3
K2
J4
gpmc_a2
gpmc_a3
O
K4
T3
R3
N3
M3
L3
gpmc_a4
O
J3
gpmc_a5
O
J2
gpmc_a6
O
J1
gpmc_a7
O
H1
H2
G2
L2
gpmc_a8
O
gpmc_a9
O
K3
K1
L1
gpmc_a10
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
gpmc_a1/ gpmc_d0
gpmc_a2/ gpmc_d1
gpmc_a3/ gpmc_d2
gpmc_a4/ gpmc_d3
gpmc_a5/ gpmc_d4
gpmc_a6/ gpmc_d5
gpmc_a7 /gpmc_d6
gpmc_a8/ gpmc_d7
gpmc_a9/ gpmc_d8
GPMC Data bit 1
M1
M1
M2
N2
M3
P1
P2
R1
R2
T2
GPMC Data bit 2
L2
N2
GPMC Data bit 3
P2
T1
V1
V2
W2
H2
K2
N1
GPMC Data bit 4
R2
GPMC Data bit 5
R1
GPMC Data bit 6
T2
GPMC Data bit 7
T1
GPMC Data bit 8
AB3
AC3
GPMC Data bit 9
gpmc_a10/
gpmc_d9
gpmc_d10
gpmc_d11
gpmc_d12
gpmc_d13
gpmc_d14
gpmc_d15
GPMC Data bit 10
GPMC Data bit 11
GPMC Data bit 12
GPMC Data bit 13
GPMC Data bit 14
GPMC Data bit 15
IO
IO
IO
IO
IO
IO
P1
R1
R2
T2
AB4
AC4
AB6
AC6
AB7
AC7
U1
R3
T3
U2
V1
V2
gpmc_a11/
gpmc_d10
gpmc_a12/
gpmc_d11
gpmc_a13/
gpmc_d12
gpmc_a14/
gpmc_d13
W1
Y1
gpmc_a15/
gpmc_d14
gpmc_a16/
gpmc_d15
gpmc_ncs0
gpmc_ncs1
gpmc_ncs2
gpmc_ncs3
gpmc_ncs4
gpmc_ncs5
gpmc_ncs6
gpmc_ncs7
gpmc_io_dir
GPMC Chip Select bit 0
GPMC Chip Select bit 1
GPMC Chip Select bit 2
GPMC Chip Select bit 3
GPMC Chip Select bit 4
GPMC Chip Select bit 5
GPMC Chip Select bit 6
GPMC Chip Select bit 7
O
O
O
O
O
O
O
O
O
G4
H3
V8
U8
T8
R8
P8
N8
N8
Y2
Y1
E2
NA
NA
D2
F4
-
-
-
-
-
-
-
-
-
NA
NA
NA
NA
NA
NA
NA
G5
F3
G4
G4
GPMC IO direction control for use with
external transceivers
gpmc_clk
GPMC clock
O
O
T4
F3
W2
W1
W2
F1
-
-
gpmc_nadv_al Address Valid or Address Latch Enable
e
gpmc_noe
gpmc_nwe
Output Enable
Write Enable
O
O
G2
F4
V2
V1
F2
-
-
G3
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Table 2-5. External Memory Interfaces – GPMC Signals Description (continued)
SIGNAL
NAME [1]
DESCRIPTION [2]
TYPE [3]
BALL
BOTTOM
(CBB Pkg.)
[4]
BALL TOP
(CBB Pkg.)
[5]
BALL
BOTTOM
(CUS Pkg.)
[4]
SUBSYSTEM PIN
MULTIPLEXING
[6]
gpmc_nbe0_cl Lower Byte Enable. Also used for
O
G3
AC12
K5
-
e
Command Latch Enable
gpmc_nbe1
gpmc_nwp
gpmc_wait0
gpmc_wait1
gpmc_wait2
gpmc_wait3
Upper Byte Enable
O
O
I
U3
H1
M8
L8
NA
AB10
AB12
AC10
NA
L1
E1
C1
NA
NA
C2
-
-
-
-
-
-
Flash Write Protect
External indication of wait
External indication of wait
External indication of wait
External indication of wait
I
I
K8
J8
I
NA
Table 2-6. External Memory Interfaces – SDRC Signals Description
SIGNAL NAME
DESCRIPTION
TYPE(1)
BALL BOTTOM
(CBB Pkg.)
BALL TOP
(CBB Pkg.)
BALL BOTTOM
(CUS Pkg.)
sdrc_d0
SDRAM data bit 0
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
O
D6
C6
J2
J1
D7
C5
sdrc_d1
SDRAM data bit 1
SDRAM data bit 2
SDRAM data bit 3
SDRAM data bit 4
SDRAM data bit 5
SDRAM data bit 6
SDRAM data bit 7
SDRAM data bit 8
SDRAM data bit 9
SDRAM data bit 10
SDRAM data bit 11
SDRAM data bit 12
SDRAM data bit 13
SDRAM data bit 14
SDRAM data bit 15
SDRAM data bit 16
SDRAM data bit 17
SDRAM data bit 18
SDRAM data bit 19
SDRAM data bit 20
SDRAM data bit 21
SDRAM data bit 22
SDRAM data bit 23
SDRAM data bit 24
SDRAM data bit 25
SDRAM data bit 26
SDRAM data bit 27
SDRAM data bit 28
SDRAM data bit 29
SDRAM data bit 30
SDRAM data bit 31
SDRAM bank select 0
sdrc_d2
B6
G2
C6
sdrc_d3
C8
G1
B5
sdrc_d4
C9
F2
D9
sdrc_d5
A7
F1
D10
C7
sdrc_d6
B9
D2
sdrc_d7
A9
D1
B7
sdrc_d8
C14
B14
C15
B16
D17
C17
B17
D18
D11
B10
C11
D12
C12
A11
B13
D14
C18
A19
B19
B20
D20
A21
B21
C21
H9
B13
A13
B14
A14
B16
A16
B19
A19
B3
B11
C12
B12
D13
C13
B14
A14
B15
C9
sdrc_d9
sdrc_d10
sdrc_d11
sdrc_d12
sdrc_d13
sdrc_d14
sdrc_d15
sdrc_d16
sdrc_d17
sdrc_d18
sdrc_d19
sdrc_d20
sdrc_d21
sdrc_d22
sdrc_d23
sdrc_d24
sdrc_d25
sdrc_d26
sdrc_d27
sdrc_d28
sdrc_d29
sdrc_d30
sdrc_d31
sdrc_ba0
A3
E12
B8
B5
A5
B9
B8
C10
B10
D12
E13
E15
D15
C15
B16
C16
D16
B17
B18
C18
A8
B9
A9
B21
A21
D22
D23
E22
E23
G22
G23
AB21
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Table 2-6. External Memory Interfaces – SDRC Signals Description (continued)
SIGNAL NAME
DESCRIPTION
TYPE(1)
BALL BOTTOM
(CBB Pkg.)
BALL TOP
(CBB Pkg.)
BALL BOTTOM
(CUS Pkg.)
sdrc_ba1
sdrc_a0
SDRAM bank select 1
SDRAM address bit 0
SDRAM address bit 1
SDRAM address bit 2
SDRAM address bit 3
SDRAM address bit 4
SDRAM address bit 5
SDRAM address bit 6
SDRAM address bit 7
SDRAM address bit 8
SDRAM address bit 9
SDRAM address bit 10
SDRAM address bit 11
SDRAM address bit 12
SDRAM address bit 13
SDRAM address bit 14
Chip select 0
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
IO
O
O
O
O
O
H10
A4
AC21
N22
N23
P22
P23
R22
R23
T22
T23
U22
U23
V22
V23
W22
W23
Y22
M22
M23
A11
B11
J22
D18
A4
sdrc_a1
B4
B4
sdrc_a2
B3
D6
sdrc_a3
C5
B3
sdrc_a4
C4
B2
sdrc_a5
D5
C3
sdrc_a6
C3
E3
sdrc_a7
C2
F6
sdrc_a8
C1
E10
E9
sdrc_a9
D4
sdrc_a10
sdrc_a11
sdrc_a12
sdrc_a13
sdrc_a14
sdrc_ncs0
sdrc_ncs1
sdrc_clk
sdrc_nclk
sdrc_cke0
sdrc_cke1
sdrc_nras
sdrc_ncas
D3
E7
D2
G6
D1
G7
E2
F7
E1
F9
H11
H12
A13
A14
H16
H17
H14
H13
A19
B19
A10
A11
B20
C20
D19
C19
Chip select 1
Clock
Clock Invert
Clock Enable 0
Clock Enable 1
J23
SDRAM Row Access
L23
L22
SDRAM column address
strobe
sdrc_nwe
sdrc_dm0
sdrc_dm1
sdrc_dm2
sdrc_dm3
sdrc_dqs0
sdrc_dqs1
sdrc_dqs2
sdrc_dqs3
SDRAM write enable
Data Mask 0
O
O
H15
B7
K23
C1
A20
B6
Data Mask 1
O
A16
B11
C20
A6
A17
A6
B13
A7
Data Mask 2
O
Data Mask 3
O
A20
C2
A16
A5
Data Strobe 0
Data Strobe 1
Data Strobe 2
Data Strobe 3
IO
IO
IO
IO
A17
A10
A20
B17
B6
A13
A8
B20
A17
(1) Type = Ball type for this specific function (I = Input, O = Output, Z = high-impedance, D = Open Drain, DS = Differential, A = Analog).
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2.4.2 Video Interfaces
Table 2-7. Video Interfaces – CAM Signals Description
SIGNAL NAME
cam_hs
DESCRIPTION
TYPE(1)
BALL BOTTOM
(CBB Pkg.)
BALL BOTTOM
(CUS Pkg.)
Camera Horizontal Synchronization
Camera Vertical Synchronization
Camera Clock Output a
IO
IO
O
O
I
A24
A23
A22
E18
cam_vs
cam_xclka
cam_xclkb
cam_d0
C25
B22
Camera Clock Output b
B26
C22
Camera digital image data bit 0
Camera digital image data bit 1
Camera digital image data bit 2
Camera digital image data bit 3
Camera digital image data bit 4
Camera digital image data bit 5
Camera digital image data bit 6
Camera digital image data bit 7
Camera digital image data bit 8
Camera digital image data bit 9
Camera digital image data bit 10
Camera digital image data bit 11
Camera field identification
AG17
AH17
B24
AB18
AC18
G19
cam_d1
I
cam_d2
I
cam_d3
I
C24
F19
cam_d4
I
D24
G20
cam_d5
I
A25
B21
cam_d6
I
K28
L24
cam_d7
I
L28
K24
cam_d8
I
K27
J23
cam_d9
I
L27
K23
cam_d10
cam_d11
cam_fld
I
B25
F21
I
C26
G21
IO
I
C23
H24
cam_pclk
cam_wen
cam_strobe
cam_global_reset
Camera pixel clock
C27
J19
Camera Write Enable
I
B23
F18
Flash strobe control signal
O
IO
D25
J20
Global reset is used strobe
synchronization
C23 / AH3 / AA21
H24/ AA2/ AB20
cam_shutter
Mechanical shutter control signal
O
B23 / AF3 / T21
F18/ Y2/ AA18
(1) Type = Ball type for this specific function (I = Input, O = Output, Z = high-impedance, D = Open Drain, DS = Differential, A = Analog).
Table 2-8. Video Interfaces – DSS Signals Description
SIGNAL NAME
DESCRIPTION
TYPE(1)
BALL BOTTOM
(CBB Pkg.)
BALL BOTTOM
(CUS Pkg.)
dss_pclk
LCD Pixel Clock
O
O
D28
D26
G22
E22
dss_hsync
dss_vsync
dss_acbias
dss_data0
dss_data1
dss_data2
dss_data3
dss_data4
dss_data5
dss_data6
dss_data7
dss_data8
dss_data9
dss_data10
dss_data11
LCD Horizontal Synchronization
LCD Vertical Synchronization
AC bias control (STN) or pixel data enable (TFT) output
LCD Pixel Data bit 0
O
D27
F22
O
E27
J21
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
AG22 / H26
AH22 / H25
AG23 / E28
AH23 / J26
AG24 / AC27
AH24 / AC28
E26
AC19
AB19
AD20
AC20
AD21
AC21
D24
LCD Pixel Data bit 1
LCD Pixel Data bit 2
LCD Pixel Data bit 3
LCD Pixel Data bit 4
LCD Pixel Data bit 5
LCD Pixel Data bit 6
LCD Pixel Data bit 7
F28
E23
LCD Pixel Data bit 8
F27
E24
LCD Pixel Data bit 9
G26
F23
LCD Pixel Data bit 10
AD28
AC22
AC23
LCD Pixel Data bit 11
AD27
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Table 2-8. Video Interfaces – DSS Signals Description (continued)
SIGNAL NAME
DESCRIPTION
TYPE(1)
BALL BOTTOM
(CBB Pkg.)
BALL BOTTOM
(CUS Pkg.)
dss_data12
dss_data13
dss_data14
dss_data15
dss_data16
dss_data17
dss_data18
dss_data19
dss_data20
dss_data21
dss_data22
dss_data23
LCD Pixel Data bit 12
LCD Pixel Data bit 13
LCD Pixel Data bit 14
LCD Pixel Data bit 15
LCD Pixel Data bit 16
LCD Pixel Data bit 17
LCD Pixel Data bit 18
LCD Pixel Data bit 19
LCD Pixel Data bit 20
LCD Pixel Data bit 21
LCD Pixel Data bit 22
LCD Pixel Data bit 23
IO
IO
IO
IO
IO
IO
IO
IO
O
AB28
AB27
AA28
AA27
G25
AB22
Y22
W22
V22
J22
H27
G23
G24
H23
D23
K22
V21
W21
H26
H25
E28
O
J26
O
AC27
AC28
O
(1) Type = Ball type for this specific function (I = Input, O = Output, Z = high-impedance, D = Open Drain, DS = Differential, A = Analog).
Table 2-9. Video Interfaces – RFBI Signals Description
SIGNAL
NAME
DESCRIPTION
TYPE(1)
BALL BOTTOM
(CBB Pkg.)
BALL BOTTOM
(CUS Pkg.)
SUBSYSTEM PIN
MULTIPLEXING(2)
rfbi_a0
RFBI command/data control
1st LCD chip select
RFBI data bus 0
O
O
E27
D26
J21
E22
dss_acbias
dss_hsync
dss_data0
dss_data1
dss_data2
dss_data3
dss_data4
dss_data5
dss_data6
dss_data7
dss_data8
dss_data9
dss_data10
dss_data11
dss_data12
dss_data13
dss_data14
dss_data15
dss_pclk
rfbi_cs0
rfbi_da0
rfbi_da1
rfbi_da2
rfbi_da3
rfbi_da4
rfbi_da5
rfbi_da6
rfbi_da7
rfbi_da8
rfbi_da9
rfbi_da10
rfbi_da11
rfbi_da12
rfbi_da13
rfbi_da14
rfbi_da15
rfbi_rd
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
O
AG22
AH22
AG23
AH23
AG24
AH24
E26
AC19
AB19
AD20
AC20
AD21
AC21
D24
RFBI data bus 1
RFBI data bus 2
RFBI data bus 3
RFBI data bus 4
RFBI data bus 5
RFBI data bus 6
RFBI data bus 7
F28
E23
RFBI data bus 8
F27
E24
RFBI data bus 9
G26
F23
RFBI data bus 10
RFBI data bus 11
RFBI data bus 12
RFBI data bus 13
RFBI data bus 14
RFBI data bus 15
Read enable for RFBI
Write Enable for RFBI
AD28
AD27
AB28
AB27
AA28
AA27
D28
AC22
AC23
AB22
Y22
W22
V22
G22
rfbi_wr
O
D27
F22
dss_vsync
dss_data16
rfbi_te_vsync0 tearing effect removal and Vsync input
from 1st LCD
I
G25
J22
rfbi_hsync0
Hsync for 1st LCD
I
H27
G23
dss_data17
(1) Type = Ball type for this specific function (I = Input, O = Output, Z = high-impedance, D = Open Drain, DS = Differential, A = Analog).
(2) The subsystem pin multiplexing options are not described in Table 2-1 and Table 2-3.
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Table 2-10. Video Interfaces – TV Signals Description
SIGNAL NAME
DESCRIPTION
TYPE(1)
BALL BOTTOM
(CBB Pkg.)
BALL BOTTOM
(CUS Pkg.)
tv_out1
tv_out2
tv_vfb1
TV analog output Composite: tv_out1
TV analog output S-VIDEO: tv_out2
O
O
O
Y28
W28
Y27
AB24
AA23
AB23
tv_vfb1: Feedback through external
resistorto composite
tv_vfb2
tv_vref
tv_vfb2: Feedback through external
resistorto S-VIDEO
O
I
W27
W26
Y23
Y24
External capacitor
(1) Type = Ball type for this specific function (I = Input, O = Output, Z = high-impedance, D = Open Drain, DS = Differential, A = Analog).
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2.4.3 Serial Communication Interfaces
Table 2-11. Serial Communication Interfaces – HDQ/1-Wire Signals Description
SIGNAL NAME
DESCRIPTION
TYPE(1)
BALL BOTTOM
(CBB Pkg.)
BALL BOTTOM
(CUS Pkg.)
hdq_sio
Bidirectional HDQ 1-Wire control and data
Interface. Output is open drain.
IOD
J25
A24
1. Type = Ball type for this specific function (I = Input, O = Output, Z = high-impedance, D = Open Drain,
DS = Differential, A = Analog).
Table 2-12. Serial Communication Interfaces – I2C Signals Description
SIGNAL NAME
DESCRIPTION
TYPE(1)
BALL BOTTOM
(CBB Pkg.)
BALL BOTTOM
(CUS Pkg.)
INTER-INTEGRATED CIRCUIT INTERFACE (I2C1)
i2c1_scl
I2C Master Serial clock. Output is open
drain.
I2C Serial Bidirectional Data. Output is open
drain.
IOD
IOD
K21
J21
K20
K21
i2c1_sda
INTER-INTEGRATED CIRCUIT INTERFACE (I2C3)
i2c3_scl
I2C Master Serial clock. Output is open
drain.
I2C Serial Bidirectional Data. Output is open
drain.
IOD
IOD
O
AF14
AG14
J25
AC13
AC12
A24
i2c3_sda
i2c3_sccbe
TBD
INTER-INTEGRATED CIRCUIT INTERFACE (I2C2)
i2c2_scl
I2C Master Serial clock. Output is open
drain.
I2C Serial Bidirectional Data. Output is open
drain.
IOD
IOD
AF15
AE15
AC15
AC14
i2c2_sda
i2c2_sccbe
i2c4_scl
TBD
O
J25
A24
Y16
I2C Master Serial clock. Output is open
drain.
IOD
AD26
i2c4_sda
I2C Serial Bidirectional Data. Output is open
drain.
IOD
AE26
Y15
(1) Type = Ball type for this specific function (I = Input, O = Output, Z = high-impedance, D = Open Drain, DS = Differential, A = Analog).
Table 2-13. Serial Communication Interfaces – McBSP LP Signals Description
SIGNAL NAME
DESCRIPTION
TYPE(1)
BALL BOTTOM
(CBB Pkg.)
BALL BOTTOM
(CUS Pkg.)
MULTICHANNEL SERIAL (McBSP LP 1)
mcbsp1_dr
mcbsp1_clkr
mcbsp1_fsr
mcbsp1_dx
mcbsp1_clkx
mcbsp1_fsx
mcbsp_clks
Received serial data
Receive Clock
I
U21
Y8 / Y21
AA21
V21
Y18
V7 / W19
AB20
W18
IO
IO
IO
IO
IO
I
Receive frame synchronization
Transmitted serial data
Transmit clock
W21
V18
Transmit frame synchronization
K26
AA19
AA18
External clock input (shared by McBSP1, 2,
3, 4, and 5)
T21
MULTICHANNEL SERIAL (McBSP LP 2)
mcbsp2_dr
mcbsp2_dx
mcbsp2_clkx
Received serial data
Transmitted serial data
Combined serial clock
I
R21
M21
N21
V19
R20
T2
IO
IO
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Table 2-13. Serial Communication Interfaces – McBSP LP Signals Description (continued)
SIGNAL NAME
DESCRIPTION
TYPE(1)
BALL BOTTOM
(CBB Pkg.)
BALL BOTTOM
(CUS Pkg.)
mcbsp2_fsx
Combined frame synchronization
IO
P21
V20
MULTICHANNEL SERIAL (McBSP LP 3)
mcbsp3_dr
mcbsp3_dx
mcbsp3_clkx
mcbsp3_fsx
Received serial data
I
AE6 / AB25 / U21
AF6 / AB26 / V21
AF5 / AA25 / W21
AE5 / AD25 / K26
V5 / Y18
V6 / W18
W4 / V18
V4 / AA19
Transmitted serial data
Combined serial clock
IO
IO
IO
Combined frame synchronization
MULTICHANNEL SERIAL (McBSP LP 4)
mcbsp4_dr
mcbsp4_dx
mcbsp4_clkx
mcbsp4_fsx
Received serial data
I
R8 / AD1
P8 / AD2
T8 / AE1
N8 / AC1
G5
F3
F4
G4
Transmitted serial data
Combined serial clock
IO
IO
IO
Combined frame synchronization
MULTICHANNEL SERIAL (McBSP LP 5)
mcbsp5_dr
mcbsp5_dx
mcbsp5_clkx
mcbsp5_fsx
Received serial data
I
AE11
AF13
AF10
AH9
AC5
AC8
AC1
AD2
Transmitted serial data
Combined serial clock
IO
IO
IO
Combined frame synchronization
(1) Type = Ball type for this specific function (I = Input, O = Output, Z = high-impedance, D = Open Drain, DS = Differential, A = Analog)
Table 2-14. Serial Communication Interfaces – McSPI Signals Description
SIGNAL NAME
DESCRIPTION
TYPE(1)
BALL BOTTOM
(CBB Pkg.)
BALL BOTTOM
(CUS Pkg.)
MULTICHANNEL SERIAL PORT INTERFACE (McSPI1)
mcspi1_clk
SPI Clock
IO
IO
IO
IO
AB3
AB4
AA4
AC2
T5
R4
T4
T6
mcspi1_simo
mcspi1_somi
mcspi1_cs0
Slave data in, master data out
Slave data out, master data in
SPI Enable 0, polarity configured by
software
mcspi1_cs1
mcspi1_cs2
mcspi1_cs3
SPI Enable 1, polarity configured by
software
O
O
O
AC3
AB1
AB2
NA
NA
R5
SPI Enable 2, polarity configured by
software
SPI Enable 3, polarity configured by
software
MULTICHANNEL SERIAL PORT INTERFACE (McSPI2)
mcspi2_clk
SPI Clock
IO
IO
IO
IO
AA3
Y2
N5
N4
N3
M5
mcspi2_simo
mcspi2_somi
mcspi2_cs0
Slave data in, master data out
Slave data out, master data in
Y3
SPI Enable 0, polarity configured by
software
Y4
mcspi2_cs1
SPI Enable 1, polarity configured by
software
O
V3
M4
MULTICHANNEL SERIAL PORT INTERFACE (McSPI3)
mcspi3_clk
SPI Clock
IO
IO
IO
IO
H26 / AE2 / AE13
H25 / AG5 / AF11
E28 / AH5 / AG12
J26 / AF4 / AH12
G24 / Y1 / AD8
H23 / AB5 / AD6
D23 / AB3 / AC6
K22 / V3 / AC7
mcspi3_simo
mcspi3_somi
mcspi3_cs0
Slave data in, master data out
Slave data out, master data in
SPI Enable 0, polarity configured by
software
mcspi3_cs1
SPI Enable 1, polarity configured by
software
O
AC27 / AG4 / AH14
V21 / W3 / AD9
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Table 2-14. Serial Communication Interfaces – McSPI Signals Description (continued)
SIGNAL NAME
DESCRIPTION
TYPE(1)
BALL BOTTOM
(CBB Pkg.)
BALL BOTTOM
(CUS Pkg.)
MULTICHANNEL SERIAL PORT INTERFACE (McSPI4)
mcspi4_clk
SPI Clock
IO
IO
IO
IO
Y8 / Y21
V21
V7 / W19
W18
mcspi4_simo
mcspi4_somi
mcspi4_cs0
Slave data in, master data out
Slave data out, master data in
U21
Y18
SPI Enable 0, polarity configured by
software
K26
AA19
(1) Type = Ball type for this specific function (I = Input, O = Output, Z = high-impedance, D = Open Drain, DS = Differential, A = Analog)
Table 2-15. Serial Communication Interfaces – UARTs Signals Description
SIGNAL NAME
DESCRIPTION
TYPE(1)
BALL BOTTOM
(CBB Pkg.)
BALL BOTTOM
(CUS Pkg.)
UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER (UART1)
uart1_cts
uart1_rts
uart1_rx
uart1_tx
UART1 Clear To Send
UART1 Request To Send
UART1 Receive data
UART1 Transmit data
I
AG22 / W8 / T21
AH22 / AA9
AC19 / AC2 / AA18
W6 / AB19
O
I
F28 / Y8 / AE7
E26 / AA8
E23 / V7 / AC3
D24 / W7
O
UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER (UART2)
uart2_cts
uart2_rts
uart2_rx
uart2_tx
UART2 Clear To Send
UART2 Request To Send
UART2 Receive data
UART2 Transmit data
I
AF6 / AB26
AE6 / AB25
AE5 / AD25
AF5 / AA25
V6
V5
V4
W4
O
I
O
UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER (UART3) / IrDA
uart3_cts_rctx
UART3 Clear To Send (input), Remote
TX (output)
IO
H18 / U26
A23 / U23
uart3_rts_sd
uart3_rx_irrx
UART3 Request To Send, IR enable
O
I
H19 / U27
B23 / U24
UART3 Receive data, IR and Remote
RX
AG24 / H20 / U28
AD21 / B24 / T23
uart3_tx_irtx
UART3 Transmit data, IR TX
O
AH24 / H21 / T27
AC21 / C23 / T24
(1) Type = Ball type for this specific function (I = Input, O = Output, Z = high-impedance, D = Open Drain, DS = Differential, A = Analog)
Table 2-16. Serial Communication Interfaces – USB Signals Description
SIGNAL NAME
DESCRIPTION
TYPE(1)
BALL BOTTOM
(CBB Pkg.)
BALL BOTTOM
(CUS Pkg.)
HIGH-SPEED UNIVERSAL SERIAL BUS INTERFACE (HSUSB0)
hsusb0_clk
Dedicated for external transceiver 60-MHz clock input from
PHY
I
T28
R21
hsusb0_stp
hsusb0_dir
Dedicated for external transceiver Stop signal
O
I
T25
R28
R23
P23
Dedicated for external transceiver Data direction control from
PHY
hsusb0_nxt
Dedicated for external transceiver Next signal from PHY
Dedicated for external transceiver Bidirectional data bus
Dedicated for external transceiver Bidirectional data bus
Dedicated for external transceiver Bidirectional data bus
Dedicated for external transceiver Bidirectional data bus
I
T26
T27
U28
U27
U26
U25
R22
T24
T23
U24
U23
W24
hsusb0_data0
hsusb0_data1
hsusb0_data2
hsusb0_data3
hsusb0_data4
IO
IO
IO
IO
IO
Dedicated for external transceiver Bidirectional data bus
additional signals for 12-pin ULPI operation
hsusb0_data5
Dedicated for external transceiver Bidirectional data bus
additional signals for 12-pin ULPI operation
IO
V28
V23
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Table 2-16. Serial Communication Interfaces – USB Signals Description (continued)
SIGNAL NAME
hsusb0_data6
hsusb0_data7
DESCRIPTION
TYPE(1)
BALL BOTTOM
(CBB Pkg.)
BALL BOTTOM
(CUS Pkg.)
Dedicated for external transceiver Bidirectional data bus
additional signals for 12-pin ULPI operation
IO
V27
W23
Dedicated for external transceiver Bidirectional data bus
additional signals for 12-pin ULPI operation
IO
V26
T22
MM_FSUSB3
mm3_rxdm
mm3_rxdp
Vminus receive data (not used in 3- or 4-pin configurations)
Vplus receive data (not used in 3- or 4-pin configurations)
Differential receiver signal input (not used in 3-pin mode)
Single-ended zero. Used as VM in 4-pin VP_VM mode.
USB data. Used as VP in 4-pin VP_VM mode.
Transmit enable
IO
IO
IO
IO
IO
IO
AE3
AH3
AD1
AE1
AD2
AC1
NA
NA
NA
NA
NA
NA
mm3_rxrcv
mm3_txse0
mm3_txdat
mm3_txen_n
MM_FSUSB2
mm2_rxdm
mm2_rxdp
Vminus receive data (not used in 3- or 4-pin configurations)
Vplus receive data (not used in 3- or 4-pin configurations)
Differential receiver signal input (not used in 3-pin mode)
Single-ended zero. Used as VM in 4-pin VP_VM mode.
USB data. Used as VP in 4-pin VP_VM mode.
Transmit enable
IO
IO
IO
IO
IO
IO
AH7
AF7
AG8
AH8
AB2
V3
AD11
AC9
AC11
AD12
R5
mm2_rxrcv
mm2_txse0
mm2_txdat
mm2_txen_n
MM_FSUSB1
mm1_rxdm
mm1_rxdp
M4
Vminus receive data (not used in 3- or 4-pin configurations)
Vplus receive data (not used in 3- or 4-pin configurations)
Differential receiver signal input (not used in 3-pin mode)
Single-ended zero. Used as VM in 4-pin VP_VM mode.
USB data. Used as VP in 4-pin VP_VM mode.
Transmit enable
IO
IO
IO
IO
IO
IO
AG9
AF10
AF11
AG12
AH12
AH14
AD5
AC1
AD6
AC6
AC7
AD9
mm1_rxrcv
mm1_txse0
mm1_txdat
mm1_txen_n
HSUSB3_TLL
hsusb3_tll_clk
Dedicated for external transceiver 60-MHz clock input from
PHY
O
W8
NA
hsusb3_tll_stp
hsusb3_tll_dir
Dedicated for external transceiver Stop signal
I
AH3
AF3
NA
NA
dedicated for external transceiver Data direction control from
PHY
O
hsusb3_tll_nxt
hsusb3_tll_data0
hsusb3_tll_data1
hsusb3_tll_data2
hsusb3_tll_data3
hsusb3_tll_data4
hsusb3_tll_data5
hsusb3_tll_data6
hsusb3_tll_data7
HSUSB2
Dedicated for external transceiver Next signal from PHY
Dedicated for external transceiver Bidirectional data bus
Dedicated for external transceiver Bidirectional data bus
Dedicated for external transceiver Bidirectional data bus
Dedicated for external transceiver Bidirectional data bus
Dedicated for external transceiver Bidirectional data bus
Dedicated for external transceiver Bidirectional data bus
Dedicated for external transceiver Bidirectional data bus
Dedicated for external transceiver Bidirectional data bus
O
AE3
AD1
AE1
AD2
AC1
AF6
AE6
AF5
AE5
NA
NA
NA
NA
NA
NA
NA
NA
NA
IO
IO
IO
IO
IO
IO
IO
IO
hsusb2_clk
Dedicated for external transceiver 60-MHz clock input from
PHY
O
AE7
AC3
hsusb2_stp
hsusb2_dir
Dedicated for external transceiver Stop signal
O
I
AF7
AG7
AC9
Dedicated for external transceiver Data direction control from
PHY
AC10
hsusb2_nxt
Dedicated for external transceiver Next signal from PHY
Dedicated for external transceiver Bidirectional data bus
I
AH7
AG8
AD11
AC11
hsusb2_data0
IO
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Table 2-16. Serial Communication Interfaces – USB Signals Description (continued)
SIGNAL NAME
DESCRIPTION
TYPE(1)
BALL BOTTOM
(CBB Pkg.)
BALL BOTTOM
(CUS Pkg.)
hsusb2_data1
hsusb2_data2
hsusb2_data3
hsusb2_data4
Dedicated for external transceiver Bidirectional data bus
Dedicated for external transceiver Bidirectional data bus
Dedicated for external transceiver Bidirectional data bus
IO
IO
IO
IO
AH8
AB2
V3
AD12
R5
M4
Dedicated for external transceiver Bidirectional data bus
additional signals for 12-pin ULPI operation
Y2
N4
hsusb2_data5
hsusb2_data6
hsusb2_data7
Dedicated for external transceiver Bidirectional data bus
additional signals for 12-pin ULPI operation
IO
IO
IO
Y3
Y4
N3
M5
N5
Dedicated for external transceiver Bidirectional data bus
additional signals for 12-pin ULPI operation
Dedicated for external transceiver Bidirectional data bus
additional signals for 12-pin ULPI operation
AA3
HSUSB2_TLL
hsusb2_tll_clk
Dedicated for external transceiver 60-MHz clock input from
PHY
O
AE7
AC3
hsusb2_tll_stp
hsusb2_tll_dir
Dedicated for external transceiver Stop signal
I
AF7
AG7
AC9
Dedicated for external transceiver data direction control from
PHY
O
AC10
hsusb2_tll_nxt
Dedicated for external transceiver Next signal from PHY
Dedicated for external transceiver Bidirectional data bus
Dedicated for external transceiver Bidirectional data bus
Dedicated for external transceiver Bidirectional data bus
Dedicated for external transceiver Bidirectional data bus
O
AH7
AG8
AH8
AB2
V3
AD11
AC11
AD12
R5
hsusb2_tll_data0
hsusb2_tll_data1
hsusb2_tll_data2
hsusb2_tll_data3
hsusb2_tll_data4
IO
IO
IO
IO
IO
M4
Dedicated for external transceiver Bidirectional data bus
additional signals for 12-pin ULPI operation
Y2
N4
hsusb2_tll_data5
hsusb2_tll_data6
hsusb2_tll_data7
Dedicated for external transceiver Bidirectional data bus
additional signals for 12-pin ULPI operation
IO
IO
IO
Y3
Y4
N3
M5
N5
Dedicated for external transceiver Bidirectional data bus
additional signals for 12-pin ULPI operation
Dedicated for external transceiver Bidirectional data bus
additional signals for 12-pin ULPI operation
AA3
HSUSB1
hsusb1_clk
Dedicated for external transceiver 60-MHz clock input from
PHY
O
AE10
AD3
hsusb1_stp
hsusb1_dir
Dedicated for external transceiver Stop signal
O
I
AF10
AF9
AC1
AC4
Dedicated for external transceiver data direction control from
PHY
hsusb1_nxt
Dedicated for external transceiver Next signal from PHY
Dedicated for external transceiver Bidirectional data bus
Dedicated for external transceiver Bidirectional data bus
Dedicated for external transceiver Bidirectional data bus
Dedicated for external transceiver Bidirectional data bus
I
AG9
AF11
AG12
AH12
AH14
AE11
AD5
AD6
AC6
AC7
AD9
AC5
hsusb1_data0
hsusb1_data1
hsusb1_data2
hsusb1_data3
hsusb1_data4
IO
IO
IO
IO
IO
Dedicated for external transceiver Bidirectional data bus
additional signals for 12-pin ULPI operation
hsusb1_data5
hsusb1_data6
hsusb1_data7
Dedicated for external transceiver Bidirectional data bus
additional signals for 12-pin ULPI operation
IO
IO
IO
AH9
AF13
AE13
AD2
AC8
AD8
Dedicated for external transceiver Bidirectional data bus
additional signals for 12-pin ULPI operation
Dedicated for external transceiver Bidirectional data bus
additional signals for 12-pin ULPI operation
HSUSB1_TLL
hsusb1_tll_clk
Dedicated for external transceiver 60-MHz clock input from
PHY
O
AE10
AD3
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Table 2-16. Serial Communication Interfaces – USB Signals Description (continued)
SIGNAL NAME
DESCRIPTION
TYPE(1)
BALL BOTTOM
(CBB Pkg.)
BALL BOTTOM
(CUS Pkg.)
hsusb1_tll_stp
hsusb1_tll_dir
Dedicated for external transceiver Stop signal
I
AF10
AF9
AC1
AC4
Dedicated for external transceiver data direction control from
PHY
O
hsusb1_tll_nxt
Dedicated for external transceiver Next signal from PHY
Dedicated for external transceiver Bidirectional data bus
Dedicated for external transceiver Bidirectional data bus
Dedicated for external transceiver Bidirectional data bus
Dedicated for external transceiver Bidirectional data bus
O
AG9
AF11
AG12
AH12
AH14
AE11
AD5
AD6
AC6
AC7
AD9
AC5
hsusb1_tll_data0
hsusb1_tll_data1
hsusb1_tll_data2
hsusb1_tll_data3
hsusb1_tll_data4
IO
IO
IO
IO
IO
Dedicated for external transceiver Bidirectional data bus
additional signals for 12-pin ULPI operation
hsusb1_tll_data5
hsusb1_tll_data6
hsusb1_tll_data7
Dedicated for external transceiver Bidirectional data bus
additional signals for 12-pin ULPI operation
IO
IO
IO
AH9
AF13
AE13
AD2
AC8
AD8
Dedicated for external transceiver Bidirectional data bus
additional signals for 12-pin ULPI operation
Dedicated for external transceiver Bidirectional data bus
additional signals for 12-pin ULPI operation
(1) Type = Ball type for this specific function (I = Input, O = Output, Z = high-impedance, D = Open Drain, DS = Differential, A = Analog)
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2.4.4 Removable Media Interfaces
Table 2-17. Removable Media Interfaces – MMC/SDIO Signals Description
SIGNAL NAME
DESCRIPTION
TYPE(1)
BALL BOTTOM
(CBB Pkg.)
BALL BOTTOM
(CUS Pkg.)
MULTIMEDIA MEMORY CARD (MMC1) / SECURE DIGITAL IO (SDIO1)
mmc1_clk
MMC/SD Output Clock
O
N28
M27
N27
N26
N25
P28
P27
P26
R27
R25
M23
L23
mmc1_cmd
mmc1_dat0
mmc1_dat1
mmc1_dat2
mmc1_dat3
mmc1_dat4
mmc1_dat5
mmc1_dat6
mmc1_dat7
MMC/SD command signal
MMC/SD Card Data bit 0 / SPI Serial Input
MMC/SD Card Data bit 1
MMC/SD Card Data bit 2
MMC/SD Card Data bit 3
MMC/SD Card Data bit 4
MMC/SD Card Data bit 5
MMC/SD Card Data bit 6
MMC/SD Card Data bit 7
IO
IO
IO
IO
IO
IO
IO
IO
IO
M22
M21
M20
N23
N22
N21
N20
P24
MULTIMEDIA MEMORY CARD (MMC2) / SECURE DIGITAL IO (SDIO2)
mmc2_clk
MMC/SD Output Clock
O
O
AE2
AE4
Y1
mmc2_dir_dat0
Direction control for DAT0 signal case an external transceiver
used
AB2
mmc2_dir_dat1
mmc2_dir_dat2
mmc2_dir_dat3
Direction control for DAT1 and DAT3 signals case an external
transceiver used
O
O
O
AH3
AF19
AE21
AA2
AC17
AB16
Direction control for DAT2 signal case an external transceiver
used
Direction control for DAT4, DAT5, DAT6, and DAT7 signals
case an external transceiver used
mmc2_clkin
mmc2_dat0
mmc2_dat1
mmc2_dat2
mmc2_dat3
mmc2_dat4
mmc2_dat5
mmc2_dat6
mmc2_dat7
mmc2_dir_cmd
MMC/SD input Clock
I
AE3
AH5
AA1
AB3
MMC/SD Card Data bit 0
MMC/SD Card Data bit 1
MMC/SD Card Data bit 2
MMC/SD Card Data bit 3
MMC/SD Card Data bit 4
MMC/SD Card Data bit 5
MMC/SD Card Data bit 6
MMC/SD Card Data bit 7
IO
IO
IO
IO
IO
IO
IO
IO
O
AH4
Y3
AG4
W3
AF4
V3
AE4 / AB3
AH3 / AB4
AF3 / AA4
AE3 / AC2
AF3
AB2 / T5
AA2 / R4
Y2 / T4
AA1 / T6
Y2
Direction control for CMD signal case an external transceiver
is used
mmc2_cmd
MMC/SD command signal
IO
AG5
AB5
MULTIMEDIA MEMORY CARD (MMC3) / SECURE DIGITAL IO (SDIO3)
mmc3_clk
MMC/SD Output Clock
O
AB1 / AF10
AC3 / AE10
AE4 / AE11
AH3 / AH9
AF3 / AF13
AE3 / AE13
AF11
AC1
AD3
mmc3_cmd
mmc3_dat0
mmc3_dat1
mmc3_dat2
mmc3_dat3
mmc3_dat4
mmc3_dat5
mmc3_dat6
mmc3_dat7
MMC/SD command signal
MMC/SD Card Data bit 0 / SPI Serial Input
MMC/SD Card Data bit 1
MMC/SD Card Data bit 2
MMC/SD Card Data bit 3
MMC/SD Card Data bit 4
MMC/SD Card Data bit 5
MMC/SD Card Data bit 6
MMC/SD Card Data bit 7
IO
IO
IO
IO
IO
IO
IO
IO
IO
AB2 / AC5
AA2 / AD2
Y2 / AC8
AA1 / AD8
AD6
AG9
AD5
AF9
AC4
AH14
AD9
(1) Type = Ball type for this specific function (I = Input, O = Output, Z = high-impedance, D = Open Drain, DS = Differential, A = Analog)
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2.4.5 Test Interfaces
Table 2-18. Test Interfaces – ETK Signals Description
SIGNAL NAME
DESCRIPTION
TYPE(1)
BALL BOTTOM
(CBB Pkg.)
BALL BOTTOM
(CUS Pkg.)
etk_ctl
etk_clk
etk_d0
etk_d1
etk_d2
etk_d3
etk_d4
etk_d5
etk_d6
etk_d7
etk_d8
etk_d9
etk_d10
etk_d11
etk_d12
etk_d13
etk_d14
etk_d15
ETK trace ctl
ETK trace clock
ETK data 0
ETK data 1
ETK data 2
ETK data 3
ETK data 4
ETK data 5
ETK data 6
ETK data 7
ETK data 8
ETK data 9
ETK data 10
ETK data 11
ETK data 12
ETK data 13
ETK data 14
ETK data 15
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
AE10
AF10
AF11
AG12
AH12
AE13
AE11
AH9
AD3
AC1
AD6
AC6
AC7
AD8
AC5
AD2
AF13
AH14
AF9
AC8
AD9
AC4
AG9
AE7
AD5
AC3
AF7
AC9
AG7
AH7
AC10
AD11
AC11
AD12
AG8
AH8
(1) Type = Ball type for this specific function (I = Input, O = Output, Z = high-impedance, D = Open Drain, DS = Differential, A = Analog)
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Table 2-19. Test Interfaces – JTAG Signals Description
SIGNAL NAME
DESCRIPTION
TYPE(1)
BALL BOTTOM
(CBB Pkg.)
BALL BOTTOM
(CUS Pkg.)
jtag_ntrst
jtag_tck
Test Reset
Test Clock
I
AA17
AA13
AA12
AA18
AA20
AA19
AA11
AA10
AB7
AB6
I
jtag_rtck
ARM Clock Emulation
Test Mode Select
Test Data Input
Test Data Output
Test emulation 0
Test emulation 1
O
IO
I
AA7
jtag_tms_tmsc
jtag_tdi
AA9
AB10
AB9
jtag_tdo
O
IO
IO
jtag_emu0
jtag_emu1
AC24
AD24
(1) Type = Ball type for this specific function (I = Input, O = Output, Z = high-impedance, D = Open Drain, DS = Differential, A = Analog)
Table 2-20. Test Interfaces – SDTI Signals Description
SIGNAL
NAME
DESCRIPTION
TYPE(1)
BALL BOTTOM
(CBB Pkg.)
BALL BOTTOM
(CUS Pkg.)
SUBSYSTEM
SIGNAL
MULTIPLEXING(2)
sdti_clk
sdti_txd0
sdti_txd1
sdti_txd2
sdti_txd3
Serial clock dual edge
O
O
O
O
O
AF7 / AA11 / AG8
AC9 / AC24 / AC11
etk_d11 / jtag_emu0 /
etk_d14
Serial data out (System Trace
messages)
AG7 / AA10 / AA11 AC10 / AD24 / AC24
etk_d12 / jtag_emu1 /
jtag_emu0
Serial data out (System Trace
messages)
AH7 / AA10
AG8
AD11 / AD24
AC11
etk_d13 / jtag_emu1
Serial data out (System Trace
messages)
etk_d14
Serial data out (System Trace
messages)
AH8
AD12
etk_d15
(1) Type = Ball type for this specific function (I = Input, O = Output, Z = high-impedance, D = Open Drain, DS = Differential, A = Analog)
(2) The subsystem pin multiplexing options are not described in Table 2-1 and Table 2-3
2.4.6 Miscellaneous
Table 2-21. Miscellaneous – GP Timer Signals Description
SIGNAL NAME
gpt8_pwm_evt
gpt9_pwm_evt
gpt10_pwm_evt
gpt11_pwm_evt
DESCRIPTION
TYPE(1)
BALL BOTTOM
(CBB Pkg.)
BALL BOTTOM
(CUS Pkg.)
PWM or event for GP
timer 8
IO
N8 / AD25 / V3
T8 / AB26 / Y2
R8 / AB25 / Y3
P8 / AA25 / Y4
G4/ M4
F4 / N4
G5 / N3
F3 / M5
PWM or event for GP
timer 9
IO
PWM or event for GP
timer 10
IO
PWM or event for GP
timer 11
IO
(1) Type = Ball type for this specific function (I = Input, O = Output, Z = high-impedance, D = Open Drain, DS = Differential, A = Analog)
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2.4.7 General-Purpose IOs
Table 2-22. General-Purpose IOs Signals Description(2)
SIGNAL NAME
DESCRIPTION
TYPE(1)
BALL BOTTOM
(CBB Pkg.)
BALL BOTTOM
(CUS Pkg.)
gpio_0
gpio_1
General-purpose IO 0
General-purpose IO 1
General-purpose IO 2
General-purpose IO 3
General-purpose IO 4
General-purpose IO 5
General-purpose IO 6
General-purpose IO 7
General-purpose IO 8
General-purpose IO 9
General-purpose IO 10
General-purpose IO 11
General-purpose IO 12
General-purpose IO 13
General-purpose IO 14
General-purpose IO 15
General-purpose IO 16
General-purpose IO 17
General-purpose IO 18
General-purpose IO 19
General-purpose IO 20
General-purpose IO 21
General-purpose IO 22
General-purpose IO 23
General-purpose IO 24
General-purpose IO 25
General-purpose IO 26
General-purpose IO 27
General-purpose IO 28
General-purpose IO 29
General-purpose IO 30
General-purpose IO 31
General-purpose IO 34
General-purpose IO 35
General-purpose IO 36
General-purpose IO 37
General-purpose IO 38
General-purpose IO 39
General-purpose IO 40
General-purpose IO 41
General-purpose IO 42
General-purpose IO 43
General-purpose IO 44
General-purpose IO 45
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
AF26
AF25
AH26
AG26
AE14
AF18
AF19
AE21
AF21
AF22
AG25
AA11
AF10
AE10
AF11
AG12
AH12
AE13
AE11
AH9
AF13
AH14
AF9
AG9
AE7
AF7
AG7
AH7
AG8
AH8
AF24
AA10
N4
W16
Y13
AB12
AC16
AD17
AD18
AC17
AB16
AA15
AD23
Y7
gpio_2
gpio_3
gpio_4
gpio_5
gpio_6
gpio_7
gpio_8
gpio_9
gpio_10
gpio_11
gpio_12
gpio_13
gpio_14
gpio_15
gpio_16
gpio_17
gpio_18
gpio_19
gpio_20
gpio_21
gpio_22
gpio_23
gpio_24
gpio_25
gpio_26
gpio_27
gpio_28
gpio_29
gpio_30
gpio_31
gpio_34
gpio_35
gpio_36
gpio_37
gpio_38
gpio_39
gpio_40
gpio_41
gpio_42
gpio_43
gpio_44
gpio_45
AC24
AC1
AD3
AD6
AC6
AC7
AD8
AC5
AD2
AC8
AD9
AC4
AD5
AC3
AC9
AC10
AD11
AC11
AD12
Y10
AD24
K4
M4
K3
L4
K2
K4
J4
T3
J3
R3
J2
N3
J1
M3
H1
L3
H2
K3
G2
H2
R2
K2
T2
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Table 2-22. General-Purpose IOs Signals Description(2) (continued)
SIGNAL NAME
DESCRIPTION
TYPE(1)
BALL BOTTOM
(CBB Pkg.)
BALL BOTTOM
(CUS Pkg.)
gpio_46
gpio_47
gpio_48
gpio_49
gpio_50
gpio_51
gpio_52
gpio_53
gpio_54
gpio_55
gpio_56
gpio_57
gpio_58
gpio_59
gpio_60
gpio_61
gpio_62
gpio_63
gpio_64
gpio_65
gpio_66
gpio_67
gpio_68
gpio_69
gpio_70
gpio_71
gpio_72
gpio_73
gpio_74
gpio_75
gpio_76
gpio_77
gpio_78
gpio_79
gpio_80
gpio_81
gpio_82
gpio_83
gpio_84
gpio_85
gpio_86
gpio_87
gpio_88
gpio_89
gpio_90
gpio_91
General-purpose IO 46
General-purpose IO 47
General-purpose IO 48
General-purpose IO 49
General-purpose IO 50
General-purpose IO 51
General-purpose IO 52
General-purpose IO 53
General-purpose IO 54
General-purpose IO 55
General-purpose IO 56
General-purpose IO 57
General-purpose IO 58
General-purpose IO 59
General-purpose IO 60
General-purpose IO 61
General-purpose IO 62
General-purpose IO 63
General-purpose IO 64
General-purpose IO 65
General-purpose IO 66
General-purpose IO 67
General-purpose IO 68
General-purpose IO 69
General-purpose IO 70
General-purpose IO 71
General-purpose IO 72
General-purpose IO 73
General-purpose IO 74
General-purpose IO 75
General-purpose IO 76
General-purpose IO 77
General-purpose IO 78
General-purpose IO 79
General-purpose IO 80
General-purpose IO 81
General-purpose IO 82
General-purpose IO 83
General-purpose IO 84
General-purpose IO 85
General-purpose IO 86
General-purpose IO 87
General-purpose IO 88
General-purpose IO 89
General-purpose IO 90
General-purpose IO 91
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
P1
R1
U1
R3
R2
T3
T2
U2
W1
V1
Y1
V2
H3
NA
V8
NA
U8
D2
T8
F4
R8
G5
P8
F3
N8
G4
T4
W2
G3
K5
U3
L1
H1
E1
L8
NA
K8
NA
J8
C2
D28
D26
D27
E27
AG22
AH22
AG23
AH23
AG24
AH24
E26
F28
F27
G26
AD28
AD27
AB28
AB27
AA28
AA27
G25
H27
H26
H25
E28
J26
G22
E22
F22
J21
AC19
AB19
AD20
AC20
AD21
AC21
D24
E23
E24
F23
AC22
AC23
AB22
Y22
W22
V22
J22
G23
G24
H23
D23
K22
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Table 2-22. General-Purpose IOs Signals Description(2) (continued)
SIGNAL NAME
DESCRIPTION
TYPE(1)
BALL BOTTOM
(CBB Pkg.)
BALL BOTTOM
(CUS Pkg.)
gpio_92
gpio_93
General-purpose IO 92
General-purpose IO 93
General-purpose IO 94
General-purpose IO 95
General-purpose IO 96
General-purpose IO 97
General-purpose IO 98
General-purpose IO 99
General-purpose IO 100
General-purpose IO 101
General-purpose IO 102
General-purpose IO 103
General-purpose IO 104
General-purpose IO 105
General-purpose IO 106
General-purpose IO 107
General-purpose IO 108
General-purpose IO 109
General-purpose IO 110
General-purpose IO 111
General-purpose IO 112
General-purpose IO 113
General-purpose IO 114
General-purpose IO 115
General-purpose IO 116
General-purpose IO 117
General-purpose IO 118
General-purpose IO 119
General-purpose IO 120
General-purpose IO 121
General-purpose IO 122
General-purpose IO 123
General-purpose IO 124
General-purpose IO 125
General-purpose IO 126
General-purpose IO 127
General-purpose IO 128
General-purpose IO 129
General-purpose IO 130
General-purpose IO 131
General-purpose IO 132
General-purpose IO 133
General-purpose IO 134
General-purpose IO 135
General-purpose IO 136
General-purpose IO 137
IO
IO
IO
IO
IO
IO
IO
I
AC27
AC28
A24
V21
W21
A22
gpio_94
gpio_95
A23
E18
gpio_96
C25
B22
gpio_97
C27
J19
gpio_98
C23
H24
gpio_99
AG17
AH17
B24
AB18
AC18
G19
gpio_100
gpio_101
gpio_102
gpio_103
gpio_104
gpio_105
gpio_106
gpio_107
gpio_108
gpio_109
gpio_110
gpio_111
gpio_112
gpio_113
gpio_114
gpio_115
gpio_116
gpio_117
gpio_118
gpio_119
gpio_120
gpio_121
gpio_122
gpio_123
gpio_124
gpio_125
gpio_126
gpio_127
gpio_128
gpio_129
gpio_130
gpio_131
gpio_132
gpio_133
gpio_134
gpio_135
gpio_136
gpio_137
I
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
I
C24
F19
D24
G20
A25
B21
K28
L24
L28
K24
K27
J23
L27
K23
B25
F21
C26
G21
B26
C22
AG19
AH19
AG18
AH18
P21
NA
I
NA
I
NA
I
NA
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
V20
N21
T21
R21
V19
M21
R20
N28 / T28
M27 / T25
N27 / R28
N26
M23 / R21
L23 / R23
M22 / P23
M21
N25 / T26
P28 / T27
D25 / P27
P26
M20
N23
J20 / N22
N21
R27
N20
R25
P24
AE2 / U28
AG5 / U27
AH5
Y1 / T23
AB5 / U24
AB3
AH4
Y3
AG4
W3
AF4
V3
AE4
AB2
AH3
AA2
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Table 2-22. General-Purpose IOs Signals Description(2) (continued)
SIGNAL NAME
DESCRIPTION
TYPE(1)
BALL BOTTOM
(CBB Pkg.)
BALL BOTTOM
(CUS Pkg.)
gpio_138
gpio_139
gpio_140
gpio_141
gpio_142
gpio_143
gpio_144
gpio_145
gpio_146
gpio_147
gpio_148
gpio_149
gpio_150
gpio_151
gpio_152
gpio_153
gpio_154
gpio_155
gpio_156
gpio_157
gpio_158
gpio_159
gpio_160
gpio_161
gpio_162
gpio_163
gpio_164
gpio_165
gpio_166
gpio_167
gpio_168
gpio_169
gpio_170
gpio_171
gpio_172
gpio_173
gpio_174
gpio_175
gpio_176
gpio_177
gpio_178
gpio_179
gpio_180
gpio_181
gpio_182
gpio_183
General-purpose IO 138
General-purpose IO 139
General-purpose IO 140
General-purpose IO 141
General-purpose IO 142
General-purpose IO 143
General-purpose IO 144
General-purpose IO 145
General-purpose IO 146
General-purpose IO 147
General-purpose IO 148
General-purpose IO 149
General-purpose IO 150
General-purpose IO 151
General-purpose IO 152
General-purpose IO 153
General-purpose IO 154
General-purpose IO 155
General-purpose IO 156
General-purpose IO 157
General-purpose IO 158
General-purpose IO 159
General-purpose IO 160
General-purpose IO 161
General-purpose IO 162
General-purpose IO 163
General-purpose IO 164
General-purpose IO 165
General-purpose IO 166
General-purpose IO 167
General-purpose IO 168
General-purpose IO 169
General-purpose IO 170
General-purpose IO 171
General-purpose IO 172
General-purpose IO 173
General-purpose IO 174
General-purpose IO 175
General-purpose IO 176
General-purpose IO 177
General-purpose IO 178
General-purpose IO 179
General-purpose IO 180
General-purpose IO 181
General-purpose IO 182
General-purpose IO 183
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
AF3
AE3
AF6
AE6
AF5
AE5
AB26
AB25
AA25
AD25
AA8
AA9
W8
Y2
AA1
V6
V5
W4
V4
NA
NA
NA
NA
W7
W6
AC2
V7
Y8
AE1
AD1
AD2
AC1
Y21
AA21
V21
U21
T21
K26
W21
H18
H19
H20
H21
B23
AF15
U26
J25
NA
NA
NA
NA
W19
AB20
W18
Y18
AA18
AA19
V18
A23
B23
B24
C23
F18
AC15
U23
A24
T5
AB3
AB4
AA4
AC2
AC3
AB1
AB2
AA3
Y2
R4
T4
T6
NA
NA
R5
N5
N4
Y3
N3
Y4
M5
V3
M4
AE15
AC14
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Table 2-22. General-Purpose IOs Signals Description(2) (continued)
SIGNAL NAME
DESCRIPTION
TYPE(1)
BALL BOTTOM
(CBB Pkg.)
BALL BOTTOM
(CUS Pkg.)
gpio_184
gpio_185
gpio_186
gpio_188
gpio_189
gpio_190
gpio_191
General-purpose IO 184
General-purpose IO 185
General-purpose IO 186
General-purpose IO 188
General-purpose IO 189
General-purpose IO 190
General-purpose IO 191
IO
IO
IO
IO
IO
IO
IO
AF14
AG14
AE22
U25
AC13
AC12
AE6
W24
V23
V28
V27
W23
T22
V26
(1) Type = Ball type for this specific function (I = Input, O = Output, Z = high-impedance, D = Open Drain, DS = Differential, A = Analog)
(2) NA in table stands for Not Applicable.
(3) The subsystem pin multiplexing options are not described in Table 2-1 and Table 2-3
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2.4.8 System and Miscellaneous Terminals
Table 2-23. System and Miscellaneous Signals Description
SIGNAL NAME
DESCRIPTION
TYPE(1) BALL BOTTOM
(CBB Pkg.)
BALL TOP
(CBB Pkg.)
BALL BOTTOM
(CUS Pkg.)
sys_32k
32-kHz clock input
I
I
AE25
AE17
NA
NA
AA16
AD15
sys_xtalin
Main input clock. Oscillator input or LVCMOS at 19.2,
13, or 12 MHz.
sys_xtalout
sys_altclk
Output of oscillator
O
I
AF17
J25
NA
NA
AD14
A24
Alternate clock source selectable for GPTIMERs
(maximum 54 MHz), USB (48 MHz), or NTSC/PAL
(54 MHz)
sys_clkreq
Request from OMAP3515/03 device for system clock
(open source type)
IO
AF25
NA
Y13
sys_clkout1
sys_clkout2
sys_boot0
Configurable output clock1
Configurable output clock2
Boot configuration mode bit 0
Boot configuration mode bit 1
Boot configuration mode bit 2
Boot configuration mode bit 3
Boot configuration mode bit 4
Boot configuration mode bit 5
Boot configuration mode bit 6
Power On Reset
O
AG25
AE22
AH26
AG26
AE14
AF18
AF19
AE21
AF21
AH25
AF24
AF26
AD26
AE26
AF22
U8
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
Y7
O
AA6
I
AB12
AC16
AD17
AD18
AC17
AB16
AA15
AA10
Y10
sys_boot1
I
sys_boot2
I
sys_boot3
I
sys_boot4
I
sys_boot5
I
sys_boot6
I
I
sys_nrespwron
sys_nreswarm
sys_nirq
Warm Boot Reset (open drain output)
External FIQ input
IOD
I
W16
Y16
sys_nvmode1
sys_nvmode2
sys_off_mode
sys_ndmareq0
Indicates the voltage mode
Indicates the voltage mode
Indicates the voltage mode
O
O
O
I
Y15
AD23
D2
External DMA request 0 (system expansion). Level
(active low) or edge (falling) selectable.
sys_ndmareq1
sys_ndmareq2
sys_ndmareq3
External DMA request 1 (system expansion). Level
(active low) or edge (falling) selectable.
I
I
T8 / J8
L3 / R8
K3 / P8
AG9
NA
NA
NA
NA
NA
NA
NA
F4 / C2
H2 / G5
G2 / F3
AD5
External DMA request 2 (system expansion). Level
(active low) or edge (falling) selectable.
External DMA request 3 (system expansion). Level
(active low) or edge (falling) selectable.
I
sys_secure_
indicator
MSECURE transactions indicator
O
O
I
sys_drm_
msecure
MSECURE output
AF9
AC4
adpllv2d_
dithering_en1
adpll dithering enable
adpll dithering enable
AA21
AC3
AB20
NA
adpllv2d_
I
dithering_en2
sys_ipmcsws
sys_opmcsws
pop_int0_ft
Reserved
AI
AO
O
B1
NA
NA
A1
A2
Reserved
A1
POP dedicated control signal
POP dedicated control signal
POP dedicated control signal
AG11
AH11
AH16
AB9
AC9
AC14
TBD
TBD
TBD
pop_int1_ft
O
pop_tq_temp_
sense_ft
NA
pop_reset_rp_ft
POP dedicated control signal
NA
AG13
AB11
TBD
(1) Type = Ball type for this specific function (I = Input, O = Output, Z = high-impedance, D = Open Drain, DS = Differential, A = Analog)
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2.4.9 Power Supplies
Table 2-24. Power Supplies Signals Description(1)
SIGNAL NAME
vdd_mpu
DESCRIPTION
BALL BOTTOM
(CBB Pkg.)
BALL TOP
(CBB Pkg.)
BALL BOTTOM
(CUS Pkg.)
ARM power domain
Y9 / W9 / T9 / R9 / M9 /
L9 / J9 / Y10 / U10 / T10 /
R10 / N10 / M10 / L10 /
J10 / Y11 / W11 / K11 /
J11 / W12 / K13 / Y14 /
K14 / J14 / Y15 / W15 /
J15
NA
W13/ W12/ V13/ V12/
U13/ U12/ T8/ T7/ R8/ R7/
R6/ N8/ N7/ N6/ M12/ M8/
M7/ M6/ L12/ L11/ J10/
J9/ H10/ H9/ G10/ G9/F10
vdd_core
Core power domain
AC4 / J4 / H4 / D8 / AE9 /
D9 / D15 / Y16 / AE18 /
Y18 / W18 / K18 / J18 /
AE19 / Y19 / U19 / T19 /
N19 / M19 / J19 / Y20 /
W20 / V20 / U20 / P20 /
N20 / K20 / J20 / D22 /
D23 / AE24 / M25 / L25 /
E25
NA
T20/ T19/ T18/ T17/ R19/
R18/ R17/ M15/ M14/ L15/
L14/ K19/ K18/ K17/ J18/
J17/ H13/ H12/ G13/ G12/
F13/ F12
cap_vdd_wkup
Wakeup/EMU/memory
AA15
NA
Y12
domains, connect capacitor
bg_testout
Used for band gap test
U4
NA
NA
AD1
G18
vdds_dpll_dll
DLL IO power domain (1.8
V): internal connection to
PLL_VDDS, power supply for
3PLL (1.8 V)
K15
vpp
eFuse programmation
Video DAC power plane
Video DAC ground plane
IO power plane
G1
V25
Y26
NA
NA
NA
NA
B1
vdda_dac
vssa_dac
vdds
AB13
AB15
AD3 / AD4 / W4 / AF8 /
AE8 / AF16 / AE16 / AF23
/ AE23 / F25 / F26 /
AG27/ AE27/ AG20/ H28/
AG21/P25
Y9 / W10 / W9 / V10 / V9
/ U10 / N19 / N18 / N17 /
M19 / M18 / M17 / H8
vdds_mem
Memory IO power plane
U1 / J1 / F1 / J2 / F2 / R4 AC5 / P1 / H1 / F23 / E1 / K8 / K7 / K6 / J8 / J7 / J6 /
/ B5 / A5 / AH6 / B8 / A8 / C23 / A4 / A7 / A10 / A15
H15 / G16 / G15 / F16 /
F15 / E16
B12 / A12 / D16 / C16 /
B18 / A18 / B22 / A22 /
G28 / C28
/ A18
vdds_dpll_per
vdds_wkup_bg
Peripheral DPLLs power rail
AA16
AA14
NA
NA
U17
For wakeup LDO and VDDA
(2 LDOs SRAM and BG)
AA13
vss
Ground
AG2 / U2 / B2 / AG3 / W3
/ P3 / J3 / E3 / A3 / P4 /
H2 / B18 / AC20 / AB5 /
AB14 / AB20 / P2 / F22 /
W15/ V16/ V15/ U16/
U15/ U14/ U11/ U9/T16/
E4 / AG6 / D7 / C7 / V9 / E2 / C22 / B4 / B7 / B10 / T15/ T14/ T13/ T12/ T11/
U9 / P9 / N9 / K9 / W10 /
V10 / P10 / K10 / D10 /
C10 / AF12 / AE12 / Y12 /
K12 / J12 / Y13 / W13 /
J13 / D13 / C13 / W14 /
K16 / J16 / Y17 / W17 /
K17 / J17 / W19 / V19 /
R19 / P19 / L19 / K19 /
D19 / C19 / AF20 / AE20 /
T20 / R20 / M20 / L20 /
D21 / C22 / AC25 / Y25 /
W25 / AC26 / R26 / L26 /
A26 / G27 / B27/ AA26/
M28/ AG16/ AH21
B15
T10/ T9/ R15/ R14/ R11/
R10/ P17/ P15/ P14/
P13/P12/ P11/ P10/ P8/
N16/ N15/ N14/ N13/ N12/
N11/ N10/ N9/ M16/ M13/
M11/ M10/ M9/ L17/ L13/
L10/ L8/ K15/ K14/ K11/
K10/ J16/ J15/ J14/ J13/
J12/ J11/H16/ H14/ H11
vdds_sram
SRAM LDOs
W16
NA
AA12
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Table 2-24. Power Supplies Signals Description(1) (continued)
SIGNAL NAME
DESCRIPTION
BALL BOTTOM
(CBB Pkg.)
BALL TOP
(CBB Pkg.)
BALL BOTTOM
(CUS Pkg.)
vdds_mmc1
MMC IO power domain for
CMD, CLK, and DAT(0..7)
K25
NA
NA
NA
N24
cap_vdd_sram_mpu
cap_vdd_sram_core
pop_ddr_vdd_ft
SRAM LDO capacitance for
VDDRAM1
V4
U8
SRAM LDO capacitance for
VDDRAM2
L21
H17
TBD
POPed SDRAM power
A15 / J28 / M1 / AF28 /
AE28
AA23 / Y23 / K1 / H23 /
A12
pop_flash_vpp_ft
pop_flash_vdd_ft
POPed flash vpp
AH13
AC11
TBD
TBD
POPed flash power
N1 / AA1 / AF1 / AH10 /
AH15
AC8 / AC13 / AA1 / U1 /
L1
pop_vss_ft
POPed devices ground
B15 / J27 / M2 / M26 / N2 AB8 / AB13 / AA2 / AA22
TBD
/ AA2 / AF2 / AF27 /
AG10 / AG15
/ U2 / L2 / K2 / K22 / H22
/ B12
(1) NA = Not Applicable.
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3 ELECTRICAL CHARACTERISTICS
3.1 Power Domains
The OMAP3515/03 device integrates enhanced features that dynamically adapt energy consumption
according to application needs and performance requirements.
The OMAP3515/03 device includes an enhanced power-management scheme based on:
•
•
•
•
•
•
Nine independent functional voltage domains on chip partitioning
Multiple voltage domains
Voltage scaling support
Enhanced memory retention support
Optimized device off mode
Centralized management of power, reset, and clock
The external power supplies of OMAP3515/03 are:
•
•
•
•
•
•
•
•
•
•
•
vdd_mpu for the ARM
vdd_core for macros
vdds for IO macros
vdds_mem for memory macros
vdds_sram for SRAM LDOs
vdds_dpll_dll for DLL IO
vdds_dpll_per for peripheral DPLLs
vdds_wkup_bg for wakeup LDO and VDDA (2 LDOs: SRAM and BandGap)
vdda_dac for video DAC
vdds_mmc1 for MMC IO
vpp for eFuse
The supply voltages are detailed in Table 3-3.
Figure 3-1 illustrates the power domains:
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vdd_mpu
vdds_dpll_dll
DLL/DCDL
BandGap
vdds_wkup_bg
LDO3
1.0 V/1.2 V
SRAM1
ARRAY
WKUP
EMU
LDO
cap_vdd_wkup
vdds_mem
MPU
in 1.8 V
out 1.2 V
BCK
MEM
cap_vdd_sram_mpu
DPLL_MPU
SRAM 1 LDO
0 V/1.0 V/1.2 V
vdds
vdd_mpu domain
vdds_sram
vpp
vdd_core
eFUSE
LDO
SRAM2
in 1.8 V
out 1.2 V
ARRAY
SRAM 2 LDO
Core
0 V/1.0 V/1.2 V
cap_vdd_sram_core
DPLL_CORE
vdds_mmc1
MMC1
LDO
LDO
in 1.8 V
out 1.2 V
tv_ref
(for capacitor)
HSDIVIDER
Periph1
DPLL4
vdds_dpll_per
vdda_dac
LDO
HSDIVIDER
Dual Video DAC
LDO
Periph2
in 1.8 V
out 1.2 V
DPLL5
vdd_core domain
vss
vssa_dac
OMAP Device
030-003
Figure 3-1. OMAP3515/03 Power Domains
This power domain segmentation switches off (or places in retention state) domains that are unused while
keeping others active. This implementation is based on internal switches that independently control each
power domain.
A power domain regular logic is attached to one of the device VDD supplies through a primary domain
switch. When the primary switch is open, most of the logic supply is off, resulting in a low-leakage state of
the domain. Embedded switches are implemented for all power domains except the wake-up domain. This
allows the domain to be powered off, if not being used, to give maximum power savings. For more
information, see the PRCM chapter of the OMAP35xx ES2.0 Technical Reference Manual (TRM)
[literature number SPRUFA5].
All domain output signals at the interface between power domains are connected through isolation latch
cells. These cells ensure a proper electrical isolation between the domains and an appropriate interface
state at the domain boundaries.
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3.2 Absolute Maximum Ratings
The following list of absolute maximum ratings is specified over operating junction temperature range.
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the
device. These are stress ratings only and functional operation of the device at these or any other
conditions beyond those indicated under recommended operating conditions is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
The OMAP3515/03 device adheres to EIA/JESD22–A114, Electrostatic Discharge (ESD) Sensitivity
Testing Human Body Model (HBM). Minimum pass level for HBM is ±2 kV.
Table 3-1. Absolute Maximum Ratings Over Operating Junction Temperature Range
PARAMETER
MIN
MAX
UNIT
vdd_mpu
vdd_core
Supply voltage range for core macros
–0.5
1.6
V
vdds
Second supply voltage range for 1.8-V I/O macros
–0.5
2.25
V
vdds_mem
VPAD
vdda
VESD
Voltage range at PAD
–0.5
–0.5
Vdds + 0.5
2.43
V
V
V
Supply voltage range for analog macros
ESD stress voltage(1)
HBM (human body model)(4)
CDM (charged device model)(5)
2000
500
IIOI
Current-pulse injection on each I/O pin(3)
Clamp current for an input or output
Storage temperature range(2)
200
mA
mA
°C
Iclamp
Tstg
–20
–65
20
150
(1) Electrostatic discharge (ESD) to measure device sensitivity/immunity to damage caused by electrostatic discharges into the device.
(2) These temperatures extreme do not simulate actual operating conditions but exaggerate any faults that might exist.
(3) Each device is tested with I/O pin injection of 200 mA with a stress voltage of 1.5 times maximum vdd at room temperature.
(4) JEDEC JESD22–A114 D with the following exception-no connect pins are not stressed. 2000V Human Body Model (HBM)
(5) JEDEC JESD22–C101C with the following exception-split out pin groupings to eliminate cumulative stress effect
This section includes the maximum power consumption for each power domain (core, etc.). Table 3-2
summarizes the power consumption at the ball level.
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Table 3-2. Estimated Maximum Power Consumption At Ball Level
PARAMETER
MAX
UNIT
Signal
Description
vdd_mpu
Processors
OMAP3515 (SmartReflex™ Enabled)
OMAP3515 (SmartReflex™ Disabled)
OMAP3503 (SmartReflex™ Enabled)
OMAP3503 (SmartReflex™ Disabled)
OMAP3515 (SmartReflex™ Enabled)
OMAP3515 (SmartReflex™ Disabled)
OMAP3503 (SmartReflex™ Enabled)
OMAP3503 (SmartReflex™ Disabled)
680
850
680
850
430
500
320
370
65
mA
vdd_core
Core
mA
vdda_dac
vdss_dpll_dll
vdds_dpll_per
vdds_sram
vdds_wkup_bg
vdds_mem
vdds
Video DAC
mA
mA
mA
mA
mA
mA
mA
mA
mA
DLL + DPLL MPU, and core
25
DPLL peripheral 1 and peripheral 2
15
Processors and core LDO (LDO1 and LDO2)
Bandgap, wakeup + LDO, EMU off
Standard I/Os (SRDC+GPMC)
Standard I/Os (all excluding SRDC and GPMC)
MMC I/O(1)
41
6
37
63
vdds_mmc1
vpp
20
eFuse
50
(1) MMC card and I/O card are not included.
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3.3 Recommended Operating Conditions
All OMAP3515/03 modules are used under the operating conditions contained in Table 3-3.
Table 3-3. Recommended Operating Conditions(3)
PARAMETER
DESCRIPTION
MIN
NOM
MAX
UNIT
VDD1 (vdd_mpu)(1)
OMAP processor OPP5: Overdrive
core supply
VDD1NOM
-
1.19 - 1.35
VDD1NOM
+
V
V
V
V
V
V
V
V
(0.04*VDD1NOM
VDD1NOM
(0.04*VDD1NOM
VDD1NOM
(0.04*VDD1NOM
VDD1NOM
(0.04*VDD1NOM
VDD1NOM
(0.04*VDD1NOM
VDD2NOM
(0.04*VDD2NOM
VDD2NOM
(0.04*VDD2NOM
VDD2NOM
)
)
)
)
)
)
)
)
(0.04*VDD1NOM
VDD1NOM
(0.04*VDD1NOM
VDD1NOM
(0.04*VDD1NOM
VDD1NOM
(0.04*VDD1NOM
VDD1NOM
(0.04*VDD1NOM
VDD2NOM
(0.04*VDD2NOM
VDD2NOM
(0.04*VDD2NOM
VDD2NOM
)
)
)
)
)
)
)
)
OPP4: Mid-Overdrive
-
1.07 - 1.27
1.00 - 1.20
0.90 - 1.00
0.80 - 0.90
0.95-1.15
0.85-1.00
0.80-0.90
+
OPP3: Nominal
-
+
OPP2: Low-Power
OPP1: Ultra Low-Power
-
+
-
+
VDD2 (vdd_core)(1)
OMAP processor OPP3: Nominal
core logic supply
-
+
OPP2: Low-Power
-
+
OPP1: Ultra Low-Power
-
+
(0.04*VDD2NOM
(0.04*VDD2NOM
vdds
Supply voltage for I/O macros
Supply voltage for memory I/O macros
Supply voltage for MMC1 macro in 1.8-V mode
Supply voltage for MMC1 macro in 3-V mode
Wakeup LDO
1.71
1.8
1.8
1.8
3
1.89
V
V
V
V
V
V
V
V
V
V
V
V
°C
vdds_mem
vdds_mmc1
1.71
1.89
1.71
1.89
2.7
3.3
vdds_wkup_bg
vdda_dac
vdds_sram
vdds_dpll_per
vdds_dpll_dll
vpp(2)
1.71
1.8
1.8
1.8
1.8
1.8
1.89
Analog supply voltage for video DAC
SRAM LDOs
1.71
1.89
1.71
1.89
Peripherals DPLLs power supply
Supply voltage for DPLLs I/Os
eFuse programming
1.71
1.89
1.71
1.89
vss
Ground
0
0
0
0
0
–
0
0
vssa_dac
TJ
Dedicated ground for DAC
Operating junction temperature range
90
(1) Voltage can be adapted using SmartReflex™. When not using SmartReflex™, the highest nominal voltage must be used for the OPP
selected. For example, vdd_mpu must be set to 1.20V+/-4% when using OPP3. OPP = operating point.
(2) It is recommended not to connect this pin. It is just used for eFuse programming on package unit.
(3) Using the device at OPP5 (Overdrive) or using multiple OPPs may impact product lifetime. For assistance in understanding the
relationship between actual application conditions, temperature, and Power on Hours (POH) see the OMAP 35xx Use Conditions and
Product Life applications note (literature number SPRATBD).
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3.4 DC Electrical Characteristics
Table 3-4 summarizes the dc electrical characteristics.
Table 3-4. DC Electrical Characteristics
PARAMETER
MIN
NOM
MAX
UNIT
LVCMOS Pin Buffers - CBB: N28, M27, N27, N26, N25, P28 / CUS: M23, L23, M22, M21, M20, N23
VIH
VIL
High-level input voltage
Low-level input voltage
High-level output voltage(3)
vdds = 1.8 V
vdds = 3.0 V
vdds = 1.8 V
vdds = 3.0 V
vdds = 1.8 V
vdds = 3.0 V
0.65 × vdds
0.625 × vdds
–0.3
vdds + 0.3
vdds + 0.3
0.35 × vdds
0.25 × vdds
V
V
V
–0.3
VOH
vdds – 0.2
0.75 × vdds
VOH
VOL
Low-level output voltage(3)
vdds = 1.8 V
vdds = 3.0 V
0.2
V
0.125 × vdds
VOL
tT
Input transition time (rise time, tR or fall time, Normal Mode
10
3
ns
tF evaluated between 10% and 90% at PAD)
High-Speed
Mode
LVDS/CMOS Pin Buffers - CBB: AG19, AH19, AG18, AH18, AG17, AH17/ CUS: AB18, AC18
Low-Power Receiver (LP-RX)
VIL
Low-level input threshold
500
300
mV
mV
mV
VIH
High-level input threshold
Input hysteresis
800
25
VHYS
Ultralow-Power Receiver (ULP-RX)
VIL-ULPM Low-level input threshold, ULPM
VIH High-level input threshold
High-Speed Receiver (HS-RX)
mV
mV
880
70
VIDTH
Differential input high threshold
mV
mV
mV
mV
mV
mV
VIDTL
Differential input low threshold
Maximum differential input voltage
Single-ended input low voltage
Single-ended input high voltage
Common-mode voltage
–70
270
VIDMAX
VILHS
–40
70
VIHHS
460
330
VCMRXDC
LVDS/CMOS Pin Buffers - CBB: K28, L28, K27, L27/ CUS: L24, K24, J23, K23
VCM
Vos
Vid
tT
Input common mode voltage range
Receiver Input dc offset
600
–20
140
267
900
1200
20
mV
mV
Receiver input differential amplitude
200
400
533
mVpp
ps
Input transition time (rise time, tR or fall time, tF evaluated
between 10% and 90% at PAD)
LVDS/CMOS Pin Buffers - CBB: AG22, AH22, AG23, AH23, AG24, AH24/ CUS: AC19, AB19, AD20, AC20, AD21, AC21
High-Speed Transceiver (HS-TX)
VOHHS
|VOD
VCMTX
HS output high voltage
360
270
250
mV
mV
mV
|
HS transmit differential voltage
HS transmit static common mode voltage
140
150
200
200
Low-Power Transceiver (LP-TX)
VOL
VOH
Thevenin output low level
Thevenin output high level
–50
1.1
50
mV
V
1.2
1.3
Low-Power Receiver (LP-RX)
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Table 3-4. DC Electrical Characteristics (continued)
PARAMETER
Low-level input threshold
MIN
NOM
MAX
UNIT
mV
VIL
550
VIH
High-level input threshold
Input hysteresis
880
25
mV
VHYST
mV
Ultralow-Power Receiver (ULP-RX)
VIL-ULPS Low-level input threshold, ULPM
VIH High-level input threshold
300
mV
mV
880
subLVDS/CMOS Pin Buffers - CBB: AA27, AA28, AB27, AB28, AD27, AD28, AC28, AC27/ CUS: V22, W22, Y22, AB22, AC23, AC22,
W21, V21
Vod
Vocm
tT
Differential voltage range @ RL = 100 Ω
100
0.8
150
0.9
200
1
mV
V
Common mode voltage range
Input transition time (Vod rise time, tR or Vod fall time, tF
evaluated between 20% and 80% at PAD)
200
500
ps
Standard LVCMOS Pin Buffers
VIH
High-level input voltage (Standard LVCMOS)
Low-level input voltage (Standard LVCMOS)
Hysteresis voltage at an input(1)
0.65 × vdds
V
V
V
V
VIL
0
0.35 × vdds
VHYS
VOH
0.1
High-level output voltage, driver enabled,
pullup or pulldown disabled
IO = IOH or
IO = –2 mA
vdds – 0.45
vdds – 0.40
IO = IOH < |–2|
mA
VOL
Low-level output voltage with , driver enabled, IO = IOL or
0.45
V
pullup or pulldown disabled
IO = 2 mA
IO = IOL < 2 mA
0.40
10(2)
tT
Input transition time (rise time, tR or fall time, tF evaluated
between 10% and 90% at PAD)
0
ns
II
Input current with VI = VI max
–1
1
µA
µA
IOZ
Off-state output current for output in high impedance with driver
only, driver disabled
–20
20
Off-state output current for output in high impedance with
driver/receiver/pullup only, driver disabled, pullup not inhibited
–100
100
Off-state output current for output in high impedance with
driver/receiver/pulldown only, driver disabled, pulldown not
inhibited
IZ
Total leakage current through the PAD connection of a
driver/receiver combination that may include a pullup or pulldown.
The driver output is disabled and the pullup or pulldown is
inhibited.
–20
20
µA
(1) Vhys is the magnitude of the difference between the positive-going threshold voltage VT+ and the negative-going voltage VT-
.
(2) This global value may be overridden on a per interface basis if another value is explicitly defined for that interface (for example, I2C).
(3) With 100 µA sink / source current at vdds_min.
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3.5 Core Voltage Decoupling
For module performance, decoupling capacitors are required to suppress the switching noise generated
by high frequency and to stabilize the supply voltage. A decoupling capacitor is most effective when it is
close to the device because this minimizes the inductance of the circuit board wiring and interconnects.
Table 3-5 summarizes the power supplies decoupling characteristics.
Table 3-5. Core Voltage Decoupling Characteristics
PARAMETER
MIN
50
TYP
100
100
100
1
MAX
120
UNIT
nF
nF
nF
µF
µF
µF
nF
nF
nF
nF
nF
Cvdd_mpu(1)
Cvdd_core(1)
50
120
Cvdds_sram
Ccap_vdd_sram_mpu
Ccap_vdd_sram_core
Cvdd_wkup
0.7
0.7
0.7
1.3
1.3
1.3
1
1
Cvdds_wkup_bg
Cvdds_dpll_dll
Cvdds_dpll_per
Cvdda_dac
100
100
100
100
100
Cvdds_mmc1
(1) 1 capacitor per 2 to 4 balls
Figure 3-2 illustrates an example of power supply decoupling.
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OMAP Device
vdds_sram
Cvdds_sram
vdds_sram
vdda_dac
vdda_dac
cap_vdd_sram_mpu
Ccap_vdd_sram_mpu
Ccap_vdd_sram_core
Cvdda_dac
SRAM_LDO1
Video DAC
vssa_dac
cap_vdd_sram_core
vdds_wkup_bg
SRAM_LDO2
BG
vdds_wkup_bg
Cvdds_wkup_bg
WKUP_LDO
DPLL_MPU
vdds_mmc1
Cvdds_mmc1
vdds_mmc1
cap_vdd_wkup
MMC IOs
Cvdd_wkup
vdds_dpll_dll
vdds_dpll_dll
Cvdds_dpll_dll
DPLL_CORE
DPLL5
vdds_dpll_per
vdds_dpll_per
Cvdds_dpll_per
DPLL4
Core
Vdd_core
vdd_mpu
Cvdd_mpu
Vdd_mpu
vdd_core
VSS
MPU
Cvdd_core
030-004
(1) Decoupling capacitors must be placed as closed as possible to the power ball. Choose the ground located closest to the power pin
for each decoupling capacitor. Place the decoupling capacitor Ci in a group of 1, 2, or 3 balls; the total must be equal to the
decoupling requirement. In case you interconnect powers, first insert the decoupling capacitor and then interconnect the powers.
(2) The decoupling capacitor value depends on the board characteristics.
Figure 3-2. Power Supply Decoupling
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3.6 Power-up and Power-down
This section provides the timing requirements for the OMAP3515/03 hardware signals.
3.6.1 Power-up Sequence
The following steps give an example of power-up sequence supported by the OMAP3515/03 device.
1. VDDS and VDDS_MEM are ramped ensuring a level on the IO domain and sys_nrespwron must be
low. At the same time, VDDS_SRAM and VDDS_WKUP_BG can also be ramped.
2. Once VDDS_WKUP_BG rail is stabilized, VDD_CORE can be ramped.
3. Once VDD_CORE is stabilized, then VDD_MPU can be ramped.
4. VDDS_DPLL_DLL and VDDS_DPLL_PER rails can be ramped at any time during the above
sequence.
5. sys_nrespwron can be released as soon as the VDDS_PLL_DLL rail is stabilized, and sys_xtalin and
sys_32k clocks are stabilized.
6. During the whole sequence above, sys_nreswarm is held low by OMAP3515/03. sys_nreswarm is
released after the eFuse check has been performed; that is, after sys_nrespwron is released.
7. The other power supplies can then be turned on upon software request.
Figure 3-3 shows the power-up sequence.
Note: If an external square clock is provided, it could be started after sys_nrespwron release provided it is
clean: no glitch, stable frequency, and duty cycle.
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1.8 V
VDDS_WKUP_BG
1.8 V
VDDS_MEM, VDDS,
VDDS_SRAM,
1.2 V
VDD_CORE
VDD_MPU
1.2 V
1.8 V
VDDS_DPLL_DLL
VDDS_DPLL_PER
1.8 V
sys_32k
sys_nrespwron
Sys_xtalin
EFUSE.RSTPWRON (internal)
sys_nreswarm
VDDS_MMC1,
VDDA_DAC, VPP
030-005
Figure 3-3. Power-up Sequence
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3.6.2 Power-down Sequence
The OMAP3515/03 device proceeds with the power-down sequence shown in Figure 3-4.
sys_nrespwron
VDDS_MMC1,
VDDA_DAC
VDDS_WKUP_BG
VDD_MPU
VDD_CORE
VDDS_MEM, VDDS,
VDDS_SRAM
VDDS_DPLL_DLL,
VDDS_DPLL_PER
sys_32kin
Sys.clk
030-006
Figure 3-4. Power-down Sequence
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4 CLOCK SPECIFICATIONS
The OMAP3515/03 device has three external input clocks, a low frequency (sys_32k), a high frequency
(sys_xtalin), and an optional (sys_altclk). The OMAP3515/03 device has two configurable output clocks,
sys_clkout1 and sys_clkout2.
Figure 4-1 shows the interface to the external clock sources and clock outputs.
OMAP
sys_32k
Power IC
Alternate Clock Source Selectable (54, 48 MHz or other [up
to 54 MHz])
sys_altclk
To Peripherals (From OSC_CLK: 12, 13,16.8, 19.2, 26, or
38.4 MHz)
sys_clkout1
sys_clkout2
sys_xtalout
To Peripherals (From OSC_CLK: 12,13, 16.8, 19.2, 26, or
38.4 MHz, core_clk [DPLL, up to 332 MHz], DPLL-96 MHz
or DPLL-54 MHz outputs with a divider of 1, 2, 4, 8, or 16)
To Quartz (Oscillator output) or Unconnected
sys_xtalin
sys_clkreq
sys_xtalout
sys_xtalin
To Quartz (Oscillator input) or Square Clock
Clock Request. To Square Clock Source or from Peripherals
sys_xtalout
Unconnected
Oscillator
is Bypassed
Oscillator
is Used
sys_xtalin
Square
Clock
Source
sys_clkreq
sys_clkreq
GPin
030-007
Figure 4-1. Clock Interface
The OMAP3515/03 device operation requires the following three input clocks:
•
•
•
The 32-kHz frequency is used for low frequency operation. It supplies the wake-up domain for
operation in lowest power mode (off mode). This clock is provided through the sys_32k pin.
The system alternative clock can be used (through the sys_altclk pin) to provide alternative 48 or 54
MHz or other clock source (up to 54 MHz).
The system clock input (12, 13, 16.8, 19.2, 26, or 38.4 MHz) is used to generate the main source clock
of the OMAP3515/03 device. It supplies the DPLLs as well as several OMAP modules. The system
clock input can be connected to either:
–
A crystal oscillator clock managed by sys_xtalin and sys_xtalout. In this case, the sys_clkreq is
used as an input (GPIN).
–
A CMOS digital clock through the sys_xtalin pin. In this case, the sys_clkreq is used as an output to
request the external system clock.
The OMAP3515/03 outputs externally two clocks:
•
sys_clkout1 can output the oscillator clock (12, 13, 16.8, 19.2, 26, or 38.4 MHz) at any time. It can be
controlled by software or externally using sys_clkreq control. When the device is in the off state, the
sys_clkreq can be asserted to enable the oscillator and activate the sys_clkout1 without waking up the
device. The off state polarity of sys_clkout1 is programmable.
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•
sys_clkout2 can output the oscillator clock (12, 13, 16.8, 19.2, 26, or 38.4 MHz), core_clk (core DPLL
output), 96 MHz or 54 MHz. It can be divided by 2, 4, 8, or 16 and its off state polarity is
programmable. This output is active only when the core power domain is active.
For more information on the OMAP3515/03 Applications Processor clocking structure, see the Power,
Reset, and Clock management (PRCM) chapter of the OMAP35xx Applications Processor TRM (literature
number SPRUFA5).
4.1 Input Clock Specifications
The clock system accepts three input clock sources:
•
•
•
32-kHz digital CMOS clock
Crystal oscillator clock or CMOS digital clock (12, 13, 16.8, 19.2, 26, or 38.4 MHz)
Alternate clock (48 or 54 MHz, or other up to 54 MHz)
4.1.1 Clock Source Requirements
Table 4-1 illustrates the requirements to supply a clock to the OMAP3515/03 device.
Table 4-1. Clock Source Requirements
PAD
CLOCK FREQUENCY
STABILITY
± 200 ppm
± 50 ppm
± 25 ppm
± 50 ppm
DUTY CYCLE
40% to 60%
45% to 55%
JITTER
< 1%
TRANSITION
< 20 ns
sys_32k
32.768 kHz
sys_xtalout 12, 13, 16.8, 19.2, 26, or 38.4 MHz Crystal
< 3.6 ns
sys_xtalin
sys_altclk
Square
48 or 54 MHz
40% to 60%
< 1%
< 5 ns
4.1.2 External Crystal Description
To supply a 12-, 13-, 16.8-, or 19.2-MHz clock to the OMAP3515/03, an external crystal can be connected
to the sys_xtalin and sys_xtalout pins. Figure 4-2 describes the crystal implementation.
OMAP Device
sys_xtalin
sys_xtalout
Optional Rbias
Optional Rd
Cf2
Cf1
Crystal
030-008
Figure 4-2. Crystal Implementation(1)(2)(3)(4)
(1) On the PCB, the oscillator components (crystal, foot capacitors, optional Rbias and Rd) must be located close to the package. All these
components must be routed first with the lowest possible number of board vias.
(2) An optional resistor Rd can be added in series with the crystal to debug or filter the harmonics; a footprint must be reserved on the PCB
for use with 10-MHz crystals and feature low-drive levels.
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(3) A 120-kΩ internal bias resistor Rbias is used. The feedback resistor Rbias provides negative feedback to the oscillator to put it in the
linear operating region; thus oscillation begins when power is applied.
(4) Cf1 and Cf2 represent the total capacitance of the PCB and components excluding the power IC and crystal. Their values in fact depend
on the crystal datasheet. In the datasheet of the crystal, the frequency is specified at a specific load capacitor value which is the
equivalent capacitor of the two capacitors Cf1 and Cf2 connected to sys_xtalin and sys_xtalout. The frequency of the oscillations
depends on the value of the capacitors (10 pF corresponds to a load capacitor of 5 pF for the crystal).
The crystal must be in the fundamental mode of operation and parallel resonant. Table 4-2 summarizes
the required electrical constraints.
Table 4-2. Crystal Electrical Characteristics
NAME
DESCRIPTION
Parallel resonance crystal frequency(1)
Load capacitance for crystal parallel resonance
Crystal ESR (12 and 13 MHz)(1)
MIN
TYP
MAX
UNIT
MHz
pF
fp
12, 13, 16.8, or 19.2
5
CL
20
80
50
7
ESR12&13
Ω
ESR16.8&19.2 Crystal ESR (16.8 and 19.2 MHz)(1)
Ω
Co
Crystal shunt capacitance
Crystal motional inductance for fp = 12 MHz
Crystal motional capacitance
Crystal drive level
1
5
pF
Lm
35
100
0.5
300
5
mH
fF
Cm
DL
mW
kΩ
kΩ
Rbias
RpdXI
Internal bias resistor
30
120
Pulldown resistor on sys_xtalin when oscillator is
disabled
(1) Measured with the load capacitance specified by the crystal manufacturer. This load is defined by the foot capacitances tied in series. If
CL = 20 pF, then both foot capacitors will be Cf1 = Cf2 = 40 pF. Parasitic capacitance from package and board must also be taken in
account.
(2) The crystal motional resistance Rm is related to the equivalent series resistance (ESR) by the following formula:
2
C
0
ESR=R 1+
m
C
L
When selecting a crystal, the system design must take into account the temperature and aging
characteristics of a crystal versus the user environment and expected lifetime of the system. Table 4-3
details the switching characteristics of the oscillator and the input requirements of the 12-, 13-, 16.8-, or
19.2-MHz input clock.
Table 4-3. Base Oscillator Switching Characteristics
NAME
fp
tsX
DESCRIPTION
MIN
TYP
MAX
UNIT
MHz
ms
Oscillation frequency
Start-up time(1)(2)
12, 13, 16.8, or 19.2
8
(1) Start-up time defined as time interval between oscillator control signal release and sys_xtalin amplitude at 50% of its final value (vdd and
vdds supplies ramped and stable). The start-up time can be performed in function of the crystal characteristics. 8-ms minimum only
when using the internal oscillator; it is programmable after reset for wake-up. At power-on reset, the time is adjustable using the pin
itself. The reset must be released when the oscillator or clock source is stable. Before the processor boots up and the oscillator is set to
bypass mode, there is a start-up time when the internal oscillator is in application mode and receives a square wave. The start-up time
in this case is about 100 µs.
(2) For fp = 12 or 13 MHz: CL = 13.5 pF and Lm = 35 mH
For fp = 16.8 or 19.2 MHz: CL = 9 pF and Lm = 15 mH
4.1.3 Clock Squarer Input Description
A 1.8-V CMOS clock squarer is another source that can supply a 12-, 13-, 16.8-, 19.2-, 26-, or 38.4-MHz
clock to the OMAP3515/03. An analog clock squarer function converts a low-amplitude sinusoidal clock
into a low-jitter digital signal. It can be connected to input pin sys_xtalin (sys_xtalout unconnected).
Figure 4-3 illustrates the effective connections.
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OMAP Device
Oscillator
In Bypass Mode
sys_clkreq
sys_xtalin
sys_xtalout
Clock Squarer Source
030-010
Figure 4-3. Clock Squarer Source Connection
To connect a digital clock source, the oscillator is configured in bypass mode(1). The sys_clkreq(2) pin is an
OMAP3515/03 output which can be used to switch the clock source on or off.
1. Pin sys_xtalout is not used in this mode. It must be left unconnected.
2. Once the system is powered up, the clock squarer source or crystal oscillator source can be applied;
however, this affects the performance. The input source must be configured after power up to attain
the desired system requirements.
Table 4-4 summarizes the electrical constraints required by the clock squarer used in the fundamental
mode of operation.
Table 4-4. Base Oscillator Electrical Characteristics (in Bypass Mode)
NAME
DESCRIPTION
MIN
TYP
MAX
UNIT
MHz
ms
f
Frequency(1)
Start-up time
12, 13, 16.8, 19.2, 26, or 38.4
(2)
tsX
RpdXI
IDDQ
Pulldown resistor on sys_xtalin when oscillator is disabled
5
1
kΩ
Current consumption on VDDS when sys_xtalin = 0 and in
power-down mode
µA
(1) Measured with the load capacitance specified by the manufacturer. Parasitic capacitance from package and board must also be taken in
account.
(2) Before the processor boots up and the oscillator is set to bypass mode, there is a start-up time when the internal oscillator is in
application mode and receives a square wave. The start-up time in this case is about 100 µs.
Table 4-5 details the input requirements of the 12-, 13-, 16.8-, 19.2-, 26-, or 38.4-MHz input clock.
Table 4-5. 12-, 13-, 16.8-, 19.2-, 26-, or 38.4-MHz Input Clock Squarer Timing Requirements
NAME
OCS0
DESCRIPTION
MIN
TYP
MAX
UNIT
MHz
ns
1 / tc(xtalin)
tw(xtalin)
tJ(xtalin)
Frequency, sys_xtalin
12, 13, 16.8, 19.2, 26, or 38.4
OCS1
OCS2
OCS3
OCS4
OCS5
Pulse duration, sys_xtalin low or high
Peak-to-peak jitter(1), sys_xtalin
Rise time, sys_xtalin
0.45 * tc(xtalin)
–1%
0.55 * tc(xtalin)
1%
3.6
3.6
±25
tR(xtalin)
tF(xtalin)
tJ(xtalin)
ns
ns
Fall time, sys_xtalin
Frequency stability, sys_xtalin
ppm
(1) Peak-to-peak jitter is defined as the difference between the maximum and the minimum output periods on a statistical population of 300
period samples. The sinusoidal noise is added on top of the vdds supply voltage.
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OCS0
OCS1
OCS1
sys.xtalin
030-011
Figure 4-4. Crystal Oscillator in Bypass Mode
4.1.4 External 32-kHz CMOS Input Clock
A 32.768-kHz clock signal (often abbreviated to 32-kHz) can be supplied by an external 1.8-V CMOS
signal on pin sys_32k.
Table 4-6 summarizes the electrical constraints imposed to the clock source.
Table 4-6. 32-kHz Input Clock Source Electrical Characteristics
NAME
DESCRIPTION
Frequency
MIN
TYP
MAX
UNIT
kHz
pF
f
32.768
CI
Input capacitance
0.44
Amplitude of input clock
1.71
1.8(1)
1.89
V
(1) Voltage stress up to the maximum voltage values shown above operation at TJ of 25°C.
Table 4-7 details the input requirements of the 32-kHz input clock.
Table 4-7. 32-kHz Input Clock Source Timing Requirements
NAME
CK0
DESCRIPTION
Frequency, sys_32k
MIN
TYP
MAX
UNIT
1 / tc(32k)
tw(32k)
tR(32k)
tF(32k)
32.768
kHz
ns
CK1
CK3
CK4
CK5
Pulse duration, sys_32k low or high
Rise time, sys_32k
0.40 * tc(32k)
0.60 * tc(32k)
20
20
ns
Fall time, sys_32k
ns
tJ(32k)
Frequency stability, sys_32k
±200
ppm
CK0
CK1
CK1
sys_32k
030-012
Figure 4-5. 32-kHz CMOS Clock
4.1.5 External sys_altclk CMOS Input Clock
A 48- or 54-MHz clock signal can be supplied by an external 1.8-V CMOS signal on pin sys_altclk.
Table 4-8 summarizes the electrical constraints imposed by the clock source.
Table 4-8. 48- or 54-MHz Input Clock Source Electrical Characteristics
NAME
DESCRIPTION
Frequency
MIN
TYP
MAX
UNIT
MHz
pF
f
48 or 54
CI
Input capacitance
0.74
Amplitude of input clock
1.71
1.8(1)
1.89
V
(1) Voltage stress up to the maximum voltage values shown above operation at TJ of 25°C.
Table 4-9 details the input requirements of the 48- or 54-MHz input clock.
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Table 4-9. 48- or 54-MHz Input Clock Source Timing Requirements
NAME
ALT0
DESCRIPTION
MIN
TYP
MAX
UNIT
MHz
ns
1 / tc(altclk)
tw(altclk)
Frequency, sys_altclk
48 or 54
ALT1
Pulse duration, sys_altclk low or
high
0.40 * tc(altclk)
0.60 * tc(altclk)
ALT2
ALT3
ALT4
ALT5
tJ(altclk)
tR(altclk)
tF(altclk)
tJ(altclk)
Peak-to-peak jitter(1), sys_altclk
–1%
1%
5
Rise time, sys_altclk
ns
ns
Fall time, sys_altclk
5
Frequency stability, sys_altclk
± 50
ppm
(1) Peak-to-peak jitter is defined as the difference between the maximum and the minimum output periods on a statistical population of 300
period samples. The sinusoidal noise is added on top of the vdds supply voltage.
ALT0
ALT1
ALT1
sys_altclk
030-013
Figure 4-6. Alternate CMOS Clock
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4.2 Output Clock Specifications
Two output clocks (pin sys_clkout1 and pin sys_clkout2) are available:
•
sys_clkout1 can output the oscillator clock (12, 13, 16.8, 19.2, 26, or 38.4 MHz) at any time. It can be
controlled by software or externally using sys_clkreq control. When the device is in the off state, the
sys_clkreq can be asserted to enable the oscillator and activate the sys_clkout1 without waking up the
device. The off state polarity of sys_clkout1 is programmable.
•
sys_clkout2 can output sys_clk (12, 13, 16.8, 19.2, 26, or 38.4 MHz), CORE_CLK (core DPLL output,
332 MHz maximum), APLL-96 MHz, or APLL-54 MHz. It can be divided by 2, 4, 8, or 16 and its off
state polarity is programmable. This output is active only when the core domain is active.
Table 4-10 summarizes the sys_clkout1 output clock electrical characteristics.
Table 4-10. sys_clkout1 Output Clock Electrical Characteristics
NAME
DESCRIPTION
MIN
TYP
MAX
UNIT
MHz
pF
f
Frequency
12, 13, 16.8, 19.2, 26, or 38.4
CI
Load capacitance(1)
f(max) = 38.4 MHz
f(max) = 26 MHz
70
125
Amplitude of output clock
1.71
1.8(2)
1.89
V
(1) The load capacitance is adapted to a frequency.
(2) Voltage stress up to the maximum voltage values shown above operation at TJ of 25°C.
Table 4-11 details the sys_clkout1 output clock timing characteristics.
Table 4-11. sys_clkout1 Output Clock Switching Characteristics
NAME
DESCRIPTION
Frequency
MIN
TYP
12, 13, 16.8, 19.2, 26, or 38.4
0.60 *
tc(CLKOUT1)
3.31
MAX
UNIT
MHz
ns
f
1 / CO0
CO1
tw(CLKOUT1)
Pulse duration, sys_clkout1 low or high
0.40 *
tc(CLKOUT1)
CO2
CO3
tR(CLKOUT1)
tF(CLKOUT1)
Rise time, sys_clkout1(1)
Fall time, sys_clkout1(1)
ns
ns
3.31
(1) With a load capacitance of 25 pF.
CO0
CO1
CO1
sys_clkout
030-014
Figure 4-7. sys_clkout1 System Output Clock
Table 4-12 summarizes the sys_clkout2 output clock electrical characteristics.
Table 4-12. sys_clkout2 Output Clock Electrical Characteristics
NAME
DESCRIPTION
MIN
TYP
MAX
UNIT
MHz
pF
f
Frequency
322
Cl
Load capacitance(1)
f(max) = 166 MHz
f(max) = 96 MHz
f(max) = 65 MHz
8
20
25
Amplitude of output clock
1.71
1.8(2)
1.89
V
(1) The load capacitance is adapted to a frequency.
(2) Voltage stress up to the maximum voltage values shown above, operation at TJ = 25°C.
Table 4-13 details the sys_clkout2 output clock timing characteristics.
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Table 4-13. sys_clkout2 Output Clock Switching Characteristics
NAME
DESCRIPTION
Frequency
MIN
TYP
MAX
UNIT
MHz
ns
f
1 / CO0
322
CO1
CO2
CO3
tw(CLKOUT2)
tR(CLKOUT2)
tF(CLKOUT2)
Pulse duration, sys_clkout2 low or high
Rise time, sys_clkout2(1)
Fall time, sys_clkout2(1)
0.40 * tc(CLKOUT2)
0.60 * tc(CLKOUT2)
3.7
4.3
ns
ns
(1) With a load capacitance of 25 pF.
CO0
CO1
CO1
sys_clkout
030-015
Figure 4-8. sys_clkout2 System Output Clock
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4.3 DPLL and DLL Specifications
The OMAP3515/03 integrates six DPLLs and a DLL. The PRM and CM drive five of them, while the sixth
(not supported) is controlled by the display controller.
The five main DPLLs are:
•
•
•
•
•
DPLL1 (MPU)
DPLL2 (not supported on OMAP3515/03 devices)
DPLL3 (Core)
DPLL4 (Peripherals)
DPLL5 (Second Peripherals DPLL)
Figure 4-9 illustrates the DLL and DPLL implementation.
OMAP
vdds_dpll_dll
Power Rail
DPLL1
DPLL2
DPLL3
DPLL4
DLL
DPLL5
vdds_dpll_per
030-016
(1) DPLL2 is not supported on OMAP3515/03 devices.
Figure 4-9. DPLL and DLL Implementation
For more information on the OMAP3530/25 Applications Processor DPLLs and clocking structure, see the
Power, Reset, and Clock management (PRCM) chapter of the OMAP35xx Applications Processor TRM
(literature number SPRUFA5).
4.3.1 Digital Phase-Locked Loop (DPLL)
The DPLL provides all interface clocks and some functional clocks (such as the processor clocks) of the
OMAP3515/03 device.
DPLL1 and DPLL2 get an always-on clock used to produce the synthesized clock. They get a high-speed
bypass clock used to switch the DPLL output clock on this high-speed clock during bypass mode.
The high-speed bypass clock is an L3 divided clock (programmable by 1 or 2) that saves DPLL processor
power consumption when the processor does not need to run faster than the L3 clock speed, or optimizes
performance during frequency scaling.
Each DPLL synthesized frequency is set by programming M (multiplier) and N (divider) factors. In addition,
all DPLL outputs can be controlled by an independent divider (M2 to M6).
The clock generating DPLLs of the OMAP3515/03 device have following features:
•
•
Independent power domain per DPLL
Controlled by clock-manager (CM)
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•
•
Fed with always-on system clock with independent gating control per DPLL
Analog part supplied through dedicated power supply (1.8 V) and an embedded LDO to get rid of
1-MHz noise
•
Up to five independent output dividers for simultaneous generation of multiple clock frequencies
4.3.1.1 DPLL1 (MPU)
DPLL1 is located in the MPU subsystem and supplies all clocks of the subsystem. All MPU subsystem
clocks are internally generated in the subsystem. When the core domain is on, it can use the DPLL3
(CORE DPLL) output as a high-frequency bypass input clock.
4.3.1.2 DPLL3 (CORE)
DPLL3 supplies all interface clocks and also a few module functional clocks. It can be also source of the
emulation trace clock. It is located in the core domain area. All interface clocks and a few module
functional clocks are generated in the CM. When the core domain is on, it can be used as a bypass input
to DPLL1 and DPLL2.
4.3.1.3 DPLL4 (Peripherals)
DPLL4 generates clocks for the peripherals. It supplies five clock sources: 96-MHz functional clocks to
subsystems and peripherals, 54 MHz to TV DAC, display functional clock, camera sensor clock, and
emulation trace clock. It is located in the core domain area. All interface clocks and few module functional
clocks are generated in the CM. Its outputs to the DSS, PER, and EMU domains are propagated with
always-on clock trees.
4.3.1.4 DPLL5 (Second peripherals DPLL)
DPLL5 supplies the 120-MHz functional clock to the CM.
4.3.2 Delay-Locked Loops (DLL)
The SDRC includes analog-controlled delay technology for interfacing high-speed mobile DDR memory
components. For more information, see the SDRC-GPMC chapter of the OMAP35xx ES2.0 Technical
Reference Manual (TRM) [literature number TBD]. A DLL is a calibration module used on dynamic track of
voltage and temperature variations, as well as to compensate the silicon process dispersion.
The SDRC DLL has four modes of operation:
1. APPLICATION MODE 0: used to generate 72° delay
2. APPLICATION MODE 1: used to generate 90° delay
3. MODEMAXDELAY: used for low frequency operation where we do not have the requirement of
accurate 72° or 90° phase shift
4. IDLE MODE: a low-power state that allows the DLL to gain lock quickly on exit from this mode
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4.3.3 DPLLs and DLL Characteristics
Several specifications characterize the six DPLLs.
Table 4-14 summarizes the DPLL characteristics and assumes testing over recommended operating
conditions.
Table 4-14. DPLL Characteristics
NAME
vdds_dpll_per
vdds_dpll_dll
TJ
PARAMETER
MIN
1.71
1.71
–40
TYP
1.8
1.8
25
MAX
1.89
1.89
107
UNIT
V
COMMENTS(4)
At module pins (+5%, –10%)
V
Junction temperature
Frequency lock time(2)
°C
Will not unlock after lock over this range for
slow temperature drifts
tlock
71.4
37.1
166.7
46.7
4.8
200
104
µs
µs
µs
µs
µs
150 FINT cycles; FREQSEL3 = 0
780 FINT cycles; FREQSEL3 = 1
350 FINT cycles; FREQSEL3 = 0
980 FINT cycles; FREQSEL3 = 1
10 FINT cycles
plock
Phase lock time
466.7
130.7
13.3
trelock
Relock time – frequency
lock(3)
Lowcurrstby = 0; FREQSEL3 = 0
100 FINT cycles
4.8
19
13.3
53.3
53.3
200
µs
µs
µs
µs
µs
µs
µs
Lowcurrstby = 0; FREQSEL3 = 1
40 FINT cycles
Lowcurrstby = 1; FREQSEL3 = 0
400 FINT cycles
19
Lowcurrstby = 1; FREQSEL3 = 1
150 FINT cycles
prelock
Relock time – Phase lock(3)
71.4
11.9
95.2
26.7
Lowcurrstby = 0; FREQSEL3 = 0
250 FINT cycles
33.3
266.7
74.7
Lowcurrstby = 0; FREQSEL3 = 1
200 FINT cycles
Lowcurrstby = 1; FREQSEL3 = 0
560 FINT cycles
Lowcurrstby = 1; FREQSEL3 = 1
(1) Input frequencies below 0.75 MHz are possible with performance penalty.
(2) Maximum frequency for nominal conditions. Speed binning possible above fmax.
(3) Relock time assumes typical operating conditions, 4°C maximum temperature drift (see the Functional Specification for more detailed
information).
(4) freqsel needs to be programmed accordingly to reference clock and DPLL divider (register setting), Lowcurrstdby depends on the targeted
DPLL power state (dynamic).
Lowcurrstdby = 0 then DPLL is in normal mode
Lowcurrstdby = 1 then DPLL is in low-power mode
Table 4-15 shows the DPLL1 clock frequency ranges.
Note: The DPLL1 clock frequency ranges depend on the VDD1 (vdd_mpu) operating point.
Table 4-15. DPLL1 Clock Frequency Ranges
Clock Signal
Description
Max
Unit
DPLL1_ALWON
_FCLK
DPLL1 reference clock input,
taken from PRM SYS_CLK.
TBD
MHz
DPLL1 high-frequency bypass
clock input, taken from CM
CORE_CLK.
DPLL1_FCLK
TBD
MHz
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Table 4-15. DPLL1 Clock Frequency Ranges (continued)
Clock Signal
Description
Max
600
550
500
500
500
600
550
500
250
125
Unit
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
OPP5
OPP4
OPP3
OPP2
OPP1
OPP5
OPP4
OPP3
OPP2
OPP1
DPLL1 internal clock signal,
generated through DPLL1
Multiplier and Divider.
DPLL1:
CLKOUTX2
DPLL1 output clock, generated
from CLKOUT_M2X2.
MPU_CLK
Table 4-16 through Table 4-18 show the DPLL3 clock frequency ranges.
Note: The DPLL3 clock frequency ranges depend on the VDD2 (vdd_core) operating point and the L3
clock speed configuration.
Table 4-16. DPLL3 Clock Frequency Ranges, VDD2 OPP3
Config 1
Config 2
Config 3
(166 MHz)
(133 MHz)
(100 MHz)
Unit
Clock Signal
Description
Min
Max
Min
Max
Min
Max
DPLL3 input reference clock, generated
by PRM.
DPLL3_ALWON_FCLK
TBD
50
TBD
TBD
50
TBD
TBD
50
TBD
MHz
MHz
MHz
DPLL3 internal clock signal, generated
through DPLL3 Multiplier and Divider.
DPLL3: CLKOUTX2
DPLL3: CLKOUT
664
332
532
266
400
200
DPLL3 internal clock signal, generated
by dividing DPLL3 CLKOUTX2 by 2.
25
25
25
Output of clock manager (CM),
generated directly from DPLL3
CLKOUT_M2.
CM: CORE_CLK
CM: L3_ICLK
CM: L4_ICLK
-
-
-
332
166
83
-
-
-
266
133
66.5
-
-
-
200
100
50
MHz
MHz
MHz
Output of clock manager (CM),
generated using DPLL3 CLKOUT_M2X2
and divider.
Output of clock manager (CM),
generated using CM L3_ICLK and
divider.
SGX input clock, taken from CM
CORE_CLK.
SGX
-
-
-
110.67
166
-
-
-
88.67
133
-
-
-
66.67
100
MHz
MHz
MHz
SDRC input clock, taken from CM
L3_ICLK.
SDRC
GPMC
GPMC input clock, taken from CM
L3_ICLK.
83
66.5
100
Table 4-17. DPLL3 Clock Frequency Ranges, VDD2 OPP2
Config 1
(83 MHz)
Config 2
(100 MHz)
Unit
Clock Signal
Description
Min
Max
Min
Max
DPLL3 input reference clock, generated by
PRM.
DPLL3_ALWON_FCLK
TBD
TBD
TBD
50
TBD
400
200
MHz
MHz
MHz
DPLL3 internal clock signal, generated through
DPLL3 Multiplier and Divider.
DPLL3: CLKOUTX2
DPLL3: CLKOUT
50
25
664
332
DPLL3 internal clock signal, generated by
dividing DPLL3 CLKOUTX2 by 2.
25
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Table 4-17. DPLL3 Clock Frequency Ranges, VDD2 OPP2 (continued)
Config 1
(83 MHz)
Config 2
(100 MHz)
Unit
Clock Signal
Description
Min
Max
Min
Max
Output of clock manager (CM), generated
directly from DPLL3 CLKOUT_M2.
CM: CORE_CLK
-
-
-
166
-
-
-
200
MHz
MHz
MHz
Output of clock manager (CM), generated using
DPLL3 CLKOUT_M2X2 and divider.
CM: L3_ICLK
CM: L4_ICLK
83
100
50
Output of clock manager (CM), generated using
CM L3_ICLK and divider.
41.5
SGX
SGX input clock, taken from CM CORE_CLK.
SDRC input clock, taken from CM L3_ICLK.
GPMC input clock, taken from CM L3_ICLK.
-
-
-
55.53
83
-
-
-
66.67
100
50
MHz
MHz
MHz
SDRC
GPMC
83
Table 4-18. DPLL3 Clock Frequency Ranges, VDD2 OPP1
Config 1
(400 MHz)
Unit
Clock Signal
Description
Min Max
DPLL3_ALWON_FCLK
DPLL3 input reference clock, generated by PRM.
TBD
50
TBD
664
MHz
MHz
DPLL3 internal clock signal, generated through DPLL3
Multiplier and Divider.
DPLL3: CLKOUTX2
DPLL3: CLKOUT
CM: CORE_CLK
CM: L3_ICLK
DPLL3 internal clock signal, generated by dividing DPLL3
CLKOUTX2 by 2.
25
-
332
83
MHz
MHz
MHz
MHz
Output of clock manager (CM), generated directly from DPLL3
CLKOUT_M2.
Output of clock manager (CM), generated using DPLL3
CLKOUT_M2X2 and divider.
-
41.5
20.75
Output of clock manager (CM), generated using CM L3_ICLK
and divider.
CM: L4_ICLK
-
SGX
SGX input clock, taken from CM CORE_CLK.
SDRC input clock, taken from CM L3_ICLK.
GPMC input clock, taken from CM L3_ICLK.
-
-
-
N/A
41.5
41.5
MHz
MHz
MHz
SDRC
GPMC
Table 4-19 summarizes the DLL characteristics.
Table 4-19. DLL Characteristics
PARAMETER
MIN
1.71
–40
66
NOM
1.8
MAX
1.89
107
133
166
15
UNIT
V
COMMENTS
Supply voltage vdds_dpll_dll
Junction operating temperature
Input clock frequency
25
°C
120
120
MHz
APPLICATION MODE 0
APPLICATION MODE 1
83
Input load(2)
Lock time(3)
fF
Clocks
ns
500
500
372
2
Relock time
IDLE to MODEMAXDELAY
(Mode transitions through idle mode)
150
1
Clocks
µs
IDLE to APPLICATION MODE 1 or 0
IDLE to APPLICATION MODE @133 MHz
IDLE to APPLICATION MODE @166 MHz
1
1.5
µs
(1) May be lower due to SmartReflex operation.
(2) This parameter is design goal and is not tested on silicon.
(3) Lock signal would go high from power down within 500 clocks. Lock signal switches to low state when the input clock is switched off
after 3 µs.
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4.3.4 DPLL and DLL Noise Isolation
The DPLL and DLL require dedicated power supply pins to isolate the core analog circuit from the
switching noise generated by the core logic that can cause jitter on the clock output signal. Guard rings
are added to the cell to isolate it from substrate noise injection.
The vdd supplies are the most sensitive to noise; decoupling capacitance is recommended below the
supply rails. The maximum input noise level allowed is 30 mVPP for frequencies below 1 MHz.
Figure 4-10 illustrates an example of a noise filter.
OMAP Device
Noise Filter
vdds_dpll_dll
C
DPLL_MPU
DPLL_CORE
DPLL2
DLL
Noise Filter
vdds_dpll_per
C
DPLL5
DPLL4
030-017
(1) DPLL2 is not supported on OMAP3515/03 devices.
Figure 4-10. DPLL and DLL Noise Filter(1)
Table 4-20 specifies the noise filter requirements.
Table 4-20. DPLL and DLL Noise Filter Requirements
NAME
MIN
TYP
MAX
UNIT
nF
Filtering capacitor
100
(1) The capacitors must be inserted between power and ground as close as possible.
(2) This circuit is provided only as an example.
(3) The filter must be located as close as possible to the device.
(4) No filtering required if noise is below 10 mVPP
.
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5 VIDEO DAC SPECIFICATIONS
A dual-display interface equips the OMAP3515/03 processor. This display subsystem provides the
necessary control signals to interface the memory frame buffer directly to the external displays (TV-set).
Two (one per channel) 10-bit current steering DACs are inserted between the DSS and the TV set to
generate the video analog signal. One of the video DACs also includes TV detection and power-down
mode. Figure 5-1 illustrates the OMAP3515/03 DAC architecture. For more information, see the DSS
chapter of the OMAP35xx ES2.0 Technical Reference Manual (TRM) [literature number TBD].
OMAP Device
TV DCT
tv_vfb1
DIN1[9:0]
TVOUT
BUFFER
Video DAC 1
tv_out1
DSS
tv_vfb2
DIN2[9:0]
TVOUT
Video DAC 2
BUFFER
tv_out2
V_ref
vdda_dac
vssa_dac
tv_vref
CBG
030-018
Figure 5-1. Video DAC Architecture
The following paragraphs detail the 10-bit DAC interface pinout, static and dynamic specifications, and
noise requirements. The operating conditions and absolute maximum ratings are detailed in Table 5-2 and
Table 5-4.
5.1 Interface Description
Table 5-1 summarizes the external pins of the video DAC.
Table 5-1. External Pins of 10-bit Video DAC
PIN NAME
I/O
DESCRIPTION
tv_out1
O
TV analog output composite
DAC1 video output. An external resistor is connected between this
node and tv_vfb1. The nominal value of ROUT1 is 1650 Ω. Finally,
note that this is the output node that drives the load (75 Ω).
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Table 5-1. External Pins of 10-bit Video DAC (continued)
PIN NAME
I/O
DESCRIPTION
tv_out2
O
TV analog output S-VIDEO
DAC2 video output. An external resistor is connected between this
node and tv_vfb2. The nominal value of ROUT2 is 1650 Ω. Finally,
note that this is the output node that drives the load (75 Ω).
tv_vref
tv_vfb1
tv_vfb2
I
Reference output voltage from internal
bandgap
A decoupling capacitor (CBG) needs to be connected for optimum
performance.
O
O
Amplifier feedback node
Amplifier feedback node. An external resistor is connected between
this node and tv_out1. The nominal value of ROUT1 is 1650 Ω (1%).
Amplifier feedback node
Amplifier feedback node. An external resistor is connected between
this node and tv_out2. The nominal value of ROUT2 is 1650 Ω (1%).
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5.2 Electrical Specifications Over Recommended Operating Conditions
(TMIN to TMAX, vdda_dac = 1.8 V, ROUT1/2 = 1650 Ω, RLOAD = 75 Ω, unless otherwise noted)
Table 5-2. DAC – Static Electrical Specification
PARAMETER
Resolution
DC ACCURACY
CONDITIONS/ASSUMPTIONS
MIN
TYP
MAX
UNIT
R
10
Bits
INL(1)
DNL(2)
Integral nonlinearity
–1
–1
1
1
LSB
LSB
Differential nonlinearity
ANALOG OUTPUT
-
Full-scale output voltage
RLOAD = 75 Ω
0,7
0.88
50
1
V
mV
-
Output offset voltage
Output offset voltage drift
Gain error
-
20
mV/°C
% FS
Ω
-
–17
19
RVOUT
Output impedance
67.5
75
82.5
REFERENCE
VREF
-
Reference voltage range
Reference noise density
0.525
3700
0.55
129
0.575
4200
V
100-kHz reference noise
bandwidth
RSET
PSRR
Full-scale current adjust resistor
Reference PSRR(3) (Up to 6 MHz)
4000
40
Ω
dB
POWER CONSUMPTION
Ivdda-up
Analog Supply Current(4)
-
2 channels, no load
2 channels
8
mA
mA
Analog supply driving a 75-Ω load
50
(RMS)
Ivdda-up (peak) Peak analog supply current:
Lasts less than 1 ns
60
2
mA
mA
Ivdd-up
Digital supply current(5)
Measured at fCLK = 54 MHz, fOUT
= 2 MHz sine wave, vdd = 1.3 V
Ivdd-up (peak)
Ivdda-down
Ivdd-down
Peak digital supply current(6)
Analog power at power-down
Digital power at power-down
Lasts less than 1 ns
T = 30°C, vdda = 1.8 V
T = 30°C, vdd = 1.3 V
2.5
1.5
1
mA
mA
mA
(1) The INL is measured at the output of the DAC (accessible at an external pin during bypass mode).
(2) The DNL is measured at the output of the DAC (accessible at an external pin during bypass mode).
(3) Assuming a capacitor of 0.1 µF at the tv_ref node.
(4) The analog supply current Ivdda is directly proportional to the full-scale output current IFS and is insensitive to fCLK
.
(5) The digital supply current IVDD is dependent on the digital input waveform, the DAC update rate fCLK, and the digital supply VDD.
(6) The peak digital supply current occurs at full-scale transition for duration less than 1 ns.
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(TMIN to TMAX, vdda_dac = 1.8 V, ROUT1/2 = 1650 Ω, RLOAD = 75 Ω, unless otherwise noted)
Table 5-3. Video DAC – Dynamic Electrical Specification
PARAMETER
Output update rate
Clock jitter
CONDITIONS/ASSUMPTIONS
MIN
TYP
MAX
UNIT
MHz
ps
(1)
fCLK
Equal to input clock frequency
54
rms clock jitter required in order to assure
10-bit accuracy
40
Attenuation at 5.1 MHz
Attenuation at 54 MHz(1)
Output settling time
Corner frequency for signal
Image frequency
0.1
25
0.5
30
85
1.5
33
dB
dB
ns
tST
Time from the start of the output transition to
output within ± 1 LSB of final value.
tRout
tFout
BW
Output rise time
Output fall time
Measured from 10% to 90% of full-scale
transition
25
25
ns
ns
Measured from 10% to 90% of full-scale
transition
Signal bandwidth
Differential gain(2)
Differential phase(2)
Within bandwidth
6
1.5%
1
MHz
deg.
dB
SFDR
SNR
fCLK = 54 MHz, fOUT = 1 MHz
fCLK = 54 MHz, fOUT = 1 MHz
45
55(3)
Signal-to-noise ratio
dB
1 kHz to 6 MHz bandwidth
PSRR
Power supply rejection ratio Up to 6 MHz
20(4)
–50
dB
dB
Crosstalk Between the two video
channels
–40
(1) For internal input clock information, For more information, see the DSS chapter of the OMAP35xx ES2.0 Technical Reference Manual
(TRM) [literature number TBD].
(2) The differential gain and phase value is for dc coupling. Note that there is degradation for the ac coupling.
(3) The SNR value is for dc coupling. Note that there is a 6-dB degradation for ac coupling.
(4) The PSSR value is for dc coupling. Note that there is a 10-dB degradation for ac coupling.
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5.3 Analog Supply (vdda_dac) Noise Requirements
In order to assure 10-bit accuracy of the DAC analog output, the analog supply vdda_dac has to meet the
noise requirements stated in this section.
The DAC Power Supply Rejection Ratio is defined as the relative variation of the full-scale output current
divided by the supply variation. Thus, it is expressed in percentage of Full-Scale Range (FSR) per volt of
DIOUT
100×
IOUTFS
% FSR
PSRRDAC
=
V
VAC
supply variation as shown in the following equation:
Depending on frequency, the PSRR is defined in Table 5-4.
Table 5-4. Video DAC – Power Supply Rejection Ratio
Supply Noise Frequency
PSRR % FSR/V
0 to 100 kHz
> 100 kHz
1
The rejection decreases 20 dB/dec.
Example: at 1 MHz the PSRR is 10% of FSR/V
A graphic representation is shown in Figure 5-2.
PSRR (% FSR/V)
First pole of
DAC output load
10
1
f
1 MHz
100 kHz
030-019
Figure 5-2. Video DAC – Power Supply Rejection Ratio
To ensure that the DAC SFDR specification is met, the PSRR values and the clock jitter requirements
translate to the following limits on vdda_dac (for the Video DAC).
The maximum peak-to-peak noise on vdda (ripple) is defined in Table 5-5:
Table 5-5. Video DAC – Maximum Peak-to-Peak Noise on vdda_dac
Tone Frequency
0 to 100 kHz
> 100 kHz
Maximum Peak-to-Peak Noise on vdda_dac
< 30 mVpp
Decreases 20 dB/dec.
Example: at 1 MHz the maximum is 3 mVpp
The maximum noise spectral density (white noise) is defined in Table 5-6:
Table 5-6. Video DAC – Maximum Noise Spectral Density
Supply Noise Bandwidth
0 to 100 kHz
Maximum Supply Noise Density
< 20 µV / √Hz
> 100 kHz
Decreases 20 dB/dec.
Example: at 1 MHz the maximum noise density is 2 µ / √Hz
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Because the DAC PSRR deteriorates at a rate of 20 dB/dec after 100 kHz, it is highly recommended to
have vdda_dac low pass filtered (proper decoupling) (see the illustrated application: Section 5.4, External
Component Value Choice).
5.4 External Component Value Choice
The full-scale output voltage VOUTMAX is regulated by the reference amplifier, and is set by an internal
resistor RSET. IOUTMAX can be expressed as:
IOUTMAX = IREF /8 * (63 + 15/16)
Where:
VREF = 0.5V
IREF = VREF/RSET
The output current IOUT appearing at DAC output is a function of both the input code and IOUTMAX and can
be expressed as:
IOUT = (DAC_CODE/1023) * IOUTMAX
Where:
DAC_CODE = 0 to 1023 is the DAC input code in decimal.
The output voltage is:
VOUT = IOUT *N* RCABLE
Where:
(N = amplifier gain = 21)
RCABLE = 75 Ω (cable typical impedance)
The TV-out buffer requires a per channel external resistors: ROUT1/2. The equation below can be used to
select different resistor values (if necessary):
ROUT = (N+1) RCABLE = 1650 Ω
Recommended parameter values are:
Table 5-7. Video DAC – Recommended External Components Values
Recommended Value
UNIT
nF
CBG
100
ROUT1/2
1650
Ω
In order to limit the reference noise bandwidth and to suppress transients on VREF, it is necessary to
connect a large decoupling capacitor BG) between the tv_vref and vssa_dac pins.
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6 TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS
6.1 Timing Test Conditions
All timing requirements and switching characteristics are valid over the recommended operating conditions
of Table 3-3, unless otherwise specified.
6.2 Interface Clock Specifications
6.2.1 Interface Clock Terminology
The Interface clock is used at the system level to sequence the data and/or control transfers accordingly
with the interface protocol.
6.2.2 Interface Clock Frequency
The two interface clock characteristics are:
•
•
The maximum clock frequency
The maximum operating frequency
The interface clock frequency documented in this document is the maximum clock frequency, which
corresponds to the maximum frequency programmable on this output clock. This frequency defines the
maximum limit supported by the OMAP3515/03 IC and doesn’t take into account any system consideration
(PCB, peripherals).
The system designer will have to consider these system considerations and OMAP3515/03 IC timings
characteristics as well, to define properly the maximum operating frequency, which corresponds to the
maximum frequency supported to transfer the data on this interface.
6.2.3 Clock Jitter Specifications
Jitter is a phase noise, which may alter different characteristics of a clock signal. The jitter specified in this
document is the time difference between the typical cycle period and the actual cycle period affected by
noise sources on the clock. The cycle (or period) jitter terminology identifies this type of jitter.
Cycle (or Period) Jitter
Tn-1
Tn
Tn+1
Max. Cycle Jitter = Max (Ti)
Min. Cycle Jitter = Min (Ti)
Jitter Standard Deviation (or rms Jitter) = Standard Deviation (Ti)
030-020
Figure 6-1. Cycle (or Period) Jitter
6.2.4 Clock Duty Cycle Error
The duty cycle error is the ratio between either the high-level pulse duration or the low-level pulse duration
and the cycle time of a clock signal.
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6.3 Timing Parameters
The timing parameter symbols used in the timing requirement and switching characteristic tables are
created in accordance with JEDEC Standard 100. To shorten the symbols, some pin names and other
related terminologies have been abbreviated as follows:
Table 6-1. Timing Parameters
LOWERCASE SUBSCRIPTS
Symbols
Parameter
Cycle time (period)
Delay time
c
d
dis
en
h
Disable time
Enable time
Hold time
su
START
t
Setup time
Start bit
Transition time
Valid time
v
w
Pulse duration (width)
Unknown, changing, or don’t care level
High
X
H
L
Low
V
Valid
IV
AE
FE
LE
Z
Invalid
Active Edge
First Edge
Last Edge
High impedance
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6.4 External Memory Interfaces
The OMAP3515/03 processor includes the following external memory interfaces:
•
•
General-purpose memory controller (GPMC)
SDRAM controller (SDRC)
6.4.1 General-Purpose Memory Controller (GPMC)
The GPMC is the OMAP3515/03 unified memory controller used to interface external memory devices
such as:
•
•
•
Asynchronous SRAM-like memories and ASIC devices
Asynchronous page mode and synchronous burst NOR flash
NAND flash
6.4.1.1 GPMC/NOR Flash Interface Synchronous Timing
Table 6-3 and Table 6-4 assume testing over the recommended operating conditions (see Figure 6-2
through Figure 6-5) and electrical characteristic conditions.
Table 6-2. GPMC/NOR Flash Synchronous Mode Timing Conditions
TIMING CONDITION PARAMETER
Input Conditions
VALUE
UNIT
tR
Input signal rise time
Input signal fall time
1.8
1.8
ns
ns
tF
Output Conditions
CLOAD
Output load capacitance
15.94
pF
Table 6-3. GPMC/NOR Flash Interface Timing Requirements – Synchronous Mode
NO.
PARAMETER
1.15 V
MAX
1.0 V
0.9 V
UNIT
MIN
MIN
MAX
MIN
MAX
F12 tsu(DV-CLKH)
F13 th(CLKH-DV)
F21 tsu(WAITV-CLKH)
F22 th(CLKH-WAITV)
Setup time, read gpmc_d[15:0]
valid before gpmc_clk high
1.9
1.9
3.2
ns
ns
ns
ns
Hold time, read gpmc_d[15:0]
valid after gpmc_clk high
Setup time, gpmc_waitx(1) valid
before gpmc_clk high
Hold Time, gpmc_waitx(1) valid
after gpmc_clk high
2.5
1.9
2.5
2.5
1.9
2.5
2.5
3.2
2.5
(1) Wait monitoring support is limited to a WaitMonitoringTime value > 0. For a full description of wait monitoring feature, see the
OMAP35xx Technical Reference Manual (literature number ).
Table 6-4. GPMC/NOR Flash Interface Switching Characteristics – Synchronous Mode
NO.
PARAMETER
1.15 V
1.0 V
0.9 V
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
F0
F1
tc(CLK)
Cycle time(15), output
clock gpmc_clk period
10
12.05
25
ns
ns
tw(CLKH)
Typical pulse duration,
output clock gpmc_clk
high
0.5 P(12)
0.5 P(12)
0.5 P(12)
0.5 P(12)
0.5 P(12)
0.5 P(12)
F1
tw(CLKL)
tdc(CLK)
Typical pulse duration,
output clock gpmc_clk low
0.5 P(12)
–500
0.5 P(12)
500
0.5 P(12)
–602
0.5 P(12)
602
0.5 P(12)
–1250
0.5 P(12)
1250
ns
ps
Duty cycle error, output
clk gpmc_clk
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Table 6-4. GPMC/NOR Flash Interface Switching Characteristics – Synchronous Mode (continued)
NO.
PARAMETER
1.15 V
1.0 V
0.9 V
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
tj(CLK)
Jitter standard
33.3
33.3
33.3
ps
deviation(16), output clock
gpmc_clk
tR(CLK)
tF(CLK)
Rise time, output clock
gpmc_clk
1.6
1.6
2
2
2
2
ns
ns
Fall time, output clock
gpmc_clk
tR(DO)
Rise time, output data
Fall time, output data
2
2
2
2
2
2
ns
ns
ns
tF(DO)
F2
F3
F4
F5
F6
td(CLKH-nCSV)
Delay time, gpmc_clk
rising edge to
F(6) – 1.9
E(5) – 1.9
B(2) – 4.1
–2.1
F(6) + 3.3
F(6) – 1.8
E(5) – 1.8
B(2) – 4.1
–2.1
F(6) + 4.1 F(6) – 2.6 F(6) + 4.9
E(5) + 4.1 E(5) – 2.6 E(5) + 4.9
B(2) + 2.1 B(2) – 4.9 B(2) + 2.6
–2.6
gpmc_ncsx(11) transition
td(CLKH-nCSIV)
td(ADDV-CLK)
td(CLKH-ADDIV)
td(nBEV-CLK)
Delay time, gpmc_clk
rising edge to
E(5) + 3.3
B(2) + 2.1
ns
ns
ns
ns
gpmc_ncsx(11) invalid
Delay time, address bus
valid to gpmc_clk first
edge
Delay time, gpmc_clk
rising edge to
gpmc_a[16:1] invalid
Delay time,
B(2) – 1.1
B(2) + 2.1
B(2) – 0.9
B(2) + 1.9 B(2) – 2.6 B(2) + 2.6
gpmc_nbe0_cle,
gpmc_nbe1 valid to
gpmc_clk first edge
F7
td(CLKH-nBEIV)
Delay time, gpmc_clk
rising edge to
D(4) – 2.1 D(4) + 1.1 D(4) – 1.9 D(4) + 0.9 D(4) – 2.6 D(4) + 2.6
ns
gpmc_nbe0_cle,
gpmc_nbe1 invalid
F8
td(CLKH-nADV)
Delay time, gpmc_clk
rising edge to
gpmc_nadv_ale transition
G(7) – 1.9 G(7) + 4.1 G(7) – 2.1 G(7) + 4.1 G(7) – 2.6 G(7) + 4.9
D(4) – 1.9 D(4) + 4.1 D(4) – 2.1 D(4) + 4.1 D(4) – 2.6 D(4) + 4.9
H(8) – 2.1 H(8) + 2.1 H(8) – 2.1 H(8) + 2.1 H(8) – 2.6 H(8) + 4.9
ns
ns
ns
F9
td(CLKH-nADVIV) Delay time, gpmc_clk
rising edge to
gpmc_nadv_ale invalid
F10
td(CLKH-nOE)
Delay time, gpmc_clk
rising edge to gpmc_noe
transition
F11
F14
td(CLKH-nOEIV)
td(CLKH-nWE)
Delay time, gpcm rising
edge to gpmc_noe invalid
E(5) – 2.1
I(9) – 1.9
E(5) + 2.1
I(9) + 4.1
E(5) – 2.1
I(9) – 2.1
E(5) + 2.1 E(5) – 2.6 E(5) + 4.9
ns
ns
Delay time, gpmc_clk
rising edge to gpmc_nwe
transition
I(9) + 4.1
I(9) – 2.6
I(9) + 4.9
J(10) + 2.6
J(10) + 2.6
F15
F17
F18
F19
F20
td(CLKH-Data)
td(CLKH-nBE)
tW(nCSV)
Delay time, gpmc_clk
rising edge to data bus
transition
J(10) – 2.1 J(10) + 1.1 J(10) – 1.9 J(10) + 0.9
J(10)
2.6
–
–
ns
ns
Delay time, gpmc_clk
rising edge to
gpmc_nbex_cle transition
J(10) – 2.1 J(10) + 1.1 J(10) – 1.9 J(10) + 0.9
J(10)
2.6
Pulse duration, Read
A(1)
A(1)
A(1)
A(1)
A(1)
A(1)
ns
ns
gpmc_ncsx(11)
Write
low
tW(nBEV)
Pulse duration, Read
C(3)
C(3)
C(3)
C(3)
C(3)
C(3)
ns
ns
gpmc_nbe0_cle,
gpmc_nbe1 low
Write
tW(nADVV)
Pulse duration, Read
K(13)
K(13)
K(13)
K(13)
K(13)
K(13)
ns
ns
gpmc_nadv_ale
Write
low
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(1) For single read: A = (CSRdOffTime – CSOnTime) * (TimeParaGranularity + 1) * GPMC_FCLK period
For burst read: A = (CSRdOffTime – CSOnTime + (n – 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK period
For burst write: A = (CSWrOffTime – CSOnTime + (n – 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK period
with n being the page burst access number.
(2) B = ClkActivationTime * GPMC_FCLK
(3) For single read: C = RdCycleTime * (TimeParaGranularity + 1) * GPMC_FCLK
For burst read: C = (RdCycleTime + (n – 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK
For burst write: C = (WrCycleTime + (n – 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK with n being the
page burst access number.
(4) For single read: D = (RdCycleTime – AccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK
For burst read: D = (RdCycleTime – AccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK
For burst write: D = (WrCycleTime – AccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK
(5) For single read: E = (CSRdOffTime – AccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK
For burst read: E = (CSRdOffTime – AccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK
For burst write: E = (CSWrOffTime – AccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK
(6) For nCS falling edge (CS activated):
–
Case GpmcFCLKDivider = 0:
F = 0.5 * CSExtraDelay * GPMC_FCLK
Case GpmcFCLKDivider = 1:
–
–
–
F = 0.5 * CSExtraDelay * GPMC_FCLK if (ClkActivationTime and CSOnTime are odd) or (ClkActivationTime and CSOnTime
are even)
–
F = (1 + 0.5 * CSExtraDelay) * GPMC_FCLK otherwise
–
Case GpmcFCLKDivider = 2:
–
–
–
F = 0.5 * CSExtraDelay * GPMC_FCLK if ((CSOnTime – ClkActivationTime) is a multiple of 3)
F = (1 + 0.5 * CSExtraDelay) * GPMC_FCLK if ((CSOnTime – ClkActivationTime – 1) is a multiple of 3)
F = (2 + 0.5 * CSExtraDelay) * GPMC_FCLK if ((CSOnTime – ClkActivationTime – 2) is a multiple of 3)
(7) For ADV falling edge (ADV activated):
–
Case GpmcFCLKDivider = 0:
G = 0.5 * ADVExtraDelay * GPMC_FCLK
Case GpmcFCLKDivider = 1:
–
–
–
G = 0.5 * ADVExtraDelay * GPMC_FCLK if (ClkActivationTime and ADVOnTime are odd) or (ClkActivationTime and
ADVOnTime are even)
–
G = (1 + 0.5 * ADVExtraDelay) * GPMC_FCLK otherwise
–
Case GpmcFCLKDivider = 2:
–
–
–
G = 0.5 * ADVExtraDelay * GPMC_FCLK if ((ADVOnTime – ClkActivationTime) is a multiple of 3)
G = (1 + 0.5 * ADVExtraDelay) * GPMC_FCLK if ((ADVOnTime – ClkActivationTime – 1) is a multiple of 3)
G = (2 + 0.5 * ADVExtraDelay) * GPMC_FCLK if ((ADVOnTime – ClkActivationTime – 2) is a multiple of 3)
For ADV rising edge (ADV deactivated) in Reading mode:
–
Case GpmcFCLKDivider = 0:
G = 0.5 * ADVExtraDelay * GPMC_FCLK
Case GpmcFCLKDivider = 1:
–
–
–
G = 0.5 * ADVExtraDelay * GPMC_FCLK if (ClkActivationTime and ADVRdOffTime are odd) or (ClkActivationTime and
ADVRdOffTime are even)
–
G = (1 + 0.5 * ADVExtraDelay) * GPMC_FCLK otherwise
–
Case GpmcFCLKDivider = 2:
–
–
–
G = 0.5 * ADVExtraDelay * GPMC_FCLK if ((ADVRdOffTime – ClkActivationTime) is a multiple of 3)
G = (1 + 0.5 * ADVExtraDelay) * GPMC_FCLK if ((ADVRdOffTime – ClkActivationTime – 1) is a multiple of 3)
G = (2 + 0.5 * ADVExtraDelay) * GPMC_FCLK if ((ADVRdOffTime – ClkActivationTime – 2) is a multiple of 3)
For ADV rising edge (ADV deactivated) in Writing mode:
–
Case GpmcFCLKDivider = 0:
G = 0.5 * ADVExtraDelay * GPMC_FCLK
Case GpmcFCLKDivider = 1:
–
–
–
G = 0.5 * ADVExtraDelay * GPMC_FCLK if (ClkActivationTime and ADVWrOffTime are odd) or (ClkActivationTime and
ADVWrOffTime are even)
–
G = (1 + 0.5 * ADVExtraDelay) * GPMC_FCLK otherwise
–
Case GpmcFCLKDivider = 2:
–
–
–
G = 0.5 * ADVExtraDelay * GPMC_FCLK if ((ADVWrOffTime – ClkActivationTime) is a multiple of 3)
G = (1 + 0.5 * ADVExtraDelay) * GPMC_FCLK if ((ADVWrOffTime – ClkActivationTime – 1) is a multiple of 3)
G = (2 + 0.5 * ADVExtraDelay) * GPMC_FCLK if ((ADVWrOffTime – ClkActivationTime – 2) is a multiple of 3)
(8) For OE falling edge (OE activated):
–
Case GpmcFCLKDivider = 0:
H = 0.5 * OEExtraDelay * GPMC_FCLK
Case GpmcFCLKDivider = 1:
–
–
–
H = 0.5 * OEExtraDelay * GPMC_FCLK if (ClkActivationTime and OEOnTime are odd) or (ClkActivationTime and OEOnTime
are even)
–
H = (1 + 0.5 * OEExtraDelay) * GPMC_FCLK otherwise
–
Case GpmcFCLKDivider = 2:
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–
–
–
H = 0.5 * OEExtraDelay * GPMC_FCLK if ((OEOnTime – ClkActivationTime) is a multiple of 3)
H = (1 + 0.5 * OEExtraDelay) * GPMC_FCLK if ((OEOnTime – ClkActivationTime – 1) is a multiple of 3)
H = (2 + 0.5 * OEExtraDelay) * GPMC_FCLK if ((OEOnTime – ClkActivationTime – 2) is a multiple of 3)
For OE rising edge (OE deactivated):
–
GpmcFCLKDivider = 0:
H = 0.5 * OEExtraDelay * GPMC_FCLK
Case GpmcFCLKDivider = 1:
–
–
–
H = 0.5 * OEExtraDelay * GPMC_FC if (ClkActivationTime and OEOffTime are odd) or (ClkActivationTime and OEOffTime are
even)
–
H = (1 + 0.5 * OEExtraDelay) * GPMC_FCLK otherwise
–
Case GpmcFCLKDivider = 2:
–
–
–
H = 0.5 * OEExtraDelay * GPMC_FCLK if ((OEOffTime – ClkActivationTime) is a multiple of 3)
H = (1 + 0.5 * OEExtraDelay) * GPMC_FCLK if ((OEOffTime – ClkActivationTime – 1) is a multiple of 3)
H = (2 + 0.5 * OEExtraDelay) * GPMC_FCLK if ((OEOffTime – ClkActivationTime – 2) is a multiple of 3)
(9) For WE falling edge (WE activated):
–
Case GpmcFCLKDivider = 0:
I = 0.5 * WEExtraDelay * GPMC_FCLK
Case GpmcFCLKDivider = 1:
–
–
–
I = 0.5 * WEExtraDelay * GPMC_FCLK if (ClkActivationTime and WEOnTime are odd) or (ClkActivationTime and WEOnTime
are even)
–
I = (1 + 0.5 * WEExtraDelay) * GPMC_FCLK otherwise
–
Case GpmcFCLKDivider = 2:
–
–
–
I = 0.5 * WEExtraDelay * GPMC_FCLK if ((WEOnTime – ClkActivationTime) is a multiple of 3)
I = (1 + 0.5 * WEExtraDelay) * GPMC_FCLK if ((WEOnTime – ClkActivationTime – 1) is a multiple of 3)
I = (2 + 0.5 * WEExtraDelay) * GPMC_FCLK if ((WEOnTime – ClkActivationTime – 2) is a multiple of 3)
For WE rising edge (WE deactivated):
–
Case GpmcFCLKDivider = 0:
I = 0.5 * WEExtraDelay * GPMC_FCLK
Case GpmcFCLKDivider = 1:
–
–
–
I = 0.5 * WEExtraDelay * GPMC_FCLK if (ClkActivationTime and WEOffTime are odd) or (ClkActivationTime and WEOffTime
are even)
–
I = (1 + 0.5 * WEExtraDelay) * GPMC_FCLK otherwise
–
Case GpmcFCLKDivider = 2:
–
–
–
I = 0.5 * WEExtraDelay * GPMC_FCLK if ((WEOffTime – ClkActivationTime) is a multiple of 3)
I = (1 + 0.5 * WEExtraDelay) * GPMC_FCLK if ((WEOffTime – ClkActivationTime – 1) is a multiple of 3)
I = (2 + 0.5 * WEExtraDelay) * GPMC_FCLK if ((WEOffTime – ClkActivationTime – 2) is a multiple of 3)
(10) J = GPMC_FCLK period
(11) In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. In gpmc_waitx, x is equal to 0, 1, 2, or 3.
(12) P = gpmc_clk period
(13) For read: K = (ADVRdOffTime – ADVOnTime) * (TimeParaGranularity + 1) * GPMC_FCLK
For write: K = (ADVWrOffTime – ADVOnTime) * (TimeParaGranularity + 1) * GPMC_FCLK
(14) GPMC_FCLK is General-Purpose Memory Controller internal functional clock.
(15) Related to the gpmc_clk output clock maximum and minimum frequencies programmable in the I/F module by setting the
GPMC_CONFIG1_CSx configuration register bit field GpmcFCLKDivider.
(16) The jitter probability density can be approximated by a Gaussian function.
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F1
F0
F1
gpmc_clk
F2
F3
F18
gpmc_ncsx
F4
gpmc_a[10:1]
Valid Address
F19
F6
F7
gpmc_nbe0_cle
F19
gpmc_nbe1
F6
F8
F8
F20
F9
gpmc_nadv_ale
gpmc_noe
F10
F11
F13
F12
D 0
gpmc_d[15:0]
gpmc_waitx
gpmc_io_dir
OUT
IN
OUT
030-021
In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. In gpmc_waitx, x is equal to 0, 1, 2, or 3.
Figure 6-2. GPMC/NOR Flash – Synchronous Single Read – (GpmcFCLKDivider = 0)
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F1
F0
F1
gpmc_clk
F2
F3
gpmc_ncsx
gpmc_a[10:1]
gpmc_nbe0_cle
gpmc_nbe1
F4
F6
Valid Address
F7
F7
F6
F8
F8
F9
gpmc_nadv_ale
gpmc_noe
F10
F11
F13
F13
F12
F12
D 3
gpmc_d[15:0]
gpmc_waitx
gpmc_io_dir
D 0
F22
D 1
D 2
F21
OUT
IN
OUT
030-022
In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. In gpmc_waitx, x is equal to 0, 1, 2, or 3.
Figure 6-3. GPMC/NOR Flash – Synchronous Burst Read – 4x16-bit (GpmcFCLKDivider = 0)
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F1
F1
F0
gpmc_clk
F2
F3
gpmc_ncsx
F4
gpmc_a[10:1]
Valid Address
F17
F17
F6
F17
F17
F17
F17
gpmc_nbe0_cle
gpmc_nbe1
gpmc_nadv_ale
gpmc_nwe
F6
F8
F8
F9
F14
F14
F15
D 1
F15
D 2
F15
gpmc_d[15:0]
gpmc_waitx
D 0
D 3
gpmc_io_dir
OUT
030-023
In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. In gpmc_waitx, x is equal to 0, 1, 2, or 3.
Figure 6-4. GPMC/NOR Flash – Synchronous Burst Write – (GpmcFCLKDivider = 0)
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F1
F0
F1
gpmc_clk
F2
F3
gpmc_ncsx
gpmc_nbe0_cle
gpmc_nbe1
F6
F6
F4
F7
Valid
F7
Valid
gpmc_a[26:17]
Address (MSB)
F5
F12
F13
F4
F12
gpmc_a[16:1]_d[15:0]
gpmc_nadv_ale
gpmc_noe
Address (LSB)
F8
D0
D1 D2
D3
F8
F9
F10
F11
gpmc_waitx
gpmc_io_dir
OUT
IN
OUT
030-024
In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. In gpmc_waitx, x is equal to 0, 1, 2, or 3.
Figure 6-5. GPMC/Multiplexed NOR Flash – Synchronous Burst Read
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F1
F1
F0
gpmc_clk
F2
F3
gpmc_ncsx
F4
gpmc_a[26:17]
Address (MSB)
F17
F17
F6
F17
F17
F17
F17
gpmc_nbe0_cle
gpmc_nbe1
F6
F8
F8
F9
gpmc_nadv_ale
gpmc_nwe
F14
F14
F15
D 1
F15
D 2
F15
gpmc_d[15:0]
gpmc_waitx
Address (LSB)
D 0
D 3
gpmc_io_dir
OUT
030-025
In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. In gpmc_waitx, x is equal to 0, 1, 2, or 3.
Figure 6-6. GPMC/Multiplexed NOR Flash – Synchronous Burst Write
6.4.1.2 GPMC/NOR Flash Interface Asynchronous Timing
Table 6-7 and Table 6-8 assume testing over the recommended operating conditions (see Figure 6-7
through Figure 6-12) and electrical characteristic conditions.
Table 6-5. GPMC/NOR Flash Asynchronous Mode Timing Conditions
TIMING CONDITION PARAMETER
Input Conditions
VALUE
UNIT
tR
Input signal rise time
Input signal fall time
1.8
1.8
ns
ns
tF
Output Conditions
CLOAD
Output load capacitance
15.94
pF
Table 6-6. GPMC/NOR Flash Interface Asynchronous Timing – Internal Parameters(1)(2)
NO.
PARAMETER
1.15 V
MAX
1.0 V
0.9 V
UNIT
MIN
MIN
MAX
MIN
MAX
FI1
FI2
FI3
FI4
Maximum output data generation delay from internal
functional clock
6.5
9.1
13.7
ns
ns
ns
ns
Maximum input data capture delay by internal
functional clock
4
5.6
9.1
9.1
8.1
Maximum device select generation delay from internal
functional clock
6.5
6.5
13.7
13.7
Maximum address generation delay from internal
functional clock
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Table 6-6. GPMC/NOR Flash Interface Asynchronous Timing – Internal Parameters(1)(2) (continued)
NO.
PARAMETER
1.15 V
MAX
1.0 V
0.9 V
UNIT
MIN
MIN
MAX
MIN
MAX
FI5
FI6
FI7
FI8
FI9
Maximum address valid generation delay from internal
functional clock
6.5
6.5
6.5
6.5
100
9.1
13.7
ns
ns
ns
ns
ps
Maximum byte enable generation delay from internal
functional clock
9.1
9.1
9.1
170
13.7
13.7
13.7
200
Maximum output enable generation delay from internal
functional clock
Maximum write enable generation delay from internal
functional clock
Maximum functional clock skew
(1) The internal parameters table must be used to calculate Data Access Time stored in the corresponding CS register bit field. Internal
parameters are referred to the GPMC functional internal clock which is not provided externally.
(2) Internal parameters are referred to the GPMC functional internal clock which is not provided externally.
Table 6-7. GPMC/NOR Flash Interface Timing Requirements – Asynchronous Mode
NO.
PARAMETER
1.15 V
1.0 V
0.9 V
UNIT
MIN MAX
MIN
MAX
MIN
MAX
FA5(1)
tacc(DAT)
Data maximum access
time
H(5)
P(4)
H(5)
H(5)
GPMC_FCLK cycles
GPMC_FCLK cycles
FA20(3) tacc1-pgmode(DAT) Page mode successive
P(4)
P(4)
data maximum access
time
FA21(2) tacc2-pgmode(DAT) Page mode first data
maximum access time
H(5)
H(5)
H(5)
GPMC_FCLK cycles
(1) The FA5 parameter illustrates the amount of time required to internally sample input Data. It is expressed in number of GPMC functional
clock cycles. From start of read cycle and after FA5 functional clock cycles, input Data is internally sampled by active functional clock
edge. FA5 value must be stored inside the AccessTime register bit field.
(2) The FA21 parameter illustrates amount of time required to internally sample first input Page Data. It is expressed in number of GPMC
functional clock cycles. From start of read cycle and after FA21 functional clock cycles, First input Page Data is internally sampled by
active functional clock edge. FA21 value must be stored inside the AccessTime register bit field.
(3) The FA20 parameter illustrates amount of time required to internally sample successive input Page Data. It is expressed in number of
GPMC functional clock cycles. After each access to input Page Data, next input Page Data is internally sampled by active functional
clock edge after FA20 functional clock cycles. The FA20 value must be stored in the PageBurstAccessTime register bit field.
(4) P = PageBurstAccessTime * (TimeParaGranularity + 1)
(5) H = AccessTime * (TimeParaGranularity + 1)
Table 6-8. GPMC/NOR Flash Interface Switching Characteristics – Asynchronous Mode
NO.
PARAMETER
1.15 V
1.0 V
0.9 V
UNIT
MIN
MAX
2.0
MIN
MAX
2.0
MIN
MAX
2.0
tR(DO)
Rise time, output data
ns
ns
ns
ns
tF(DO)
Fall time, output data
Pulse duration, Read
2.0
2.0
2.0
FA0
tW(nBEV)
N(12)
N(12)
N(12)
N(12)
N(12)
N(12)
gpmc_nbe0_cl
e, gpmc_nbe1
Write
valid time
FA1
FA3
tW(nCSV)
Pulse duration, Read
A(1)
A(1)
A(1)
A(1)
A(1)
A(1)
ns
ns
gpmc_ncsx(13)
Write
v low
td(nCSV-nADVIV)
Delay time,
gpmc_ncsx(13)
valid to
Read
Write
B(2) – 0.2
B(2) – 0.2
B(2) + 2.0
B(2) + 2.0
B(2) – 0.2
B(2) – 0.2
B(2) + 2.6
B(2) + 2.6
B(2) – 0.2
B(2) – 0.2
B(2) + 3.7
B(2) + 3.7
ns
ns
gpmc_nadv_al
e invalid
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Table 6-8. GPMC/NOR Flash Interface Switching Characteristics – Asynchronous Mode (continued)
NO.
PARAMETER
1.15 V
1.0 V
0.9 V
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
FA4
td(nCSV-nOEIV)
Delay time,
C(3) – 0.2
C(3) + 2.0
C(3) – 0.2
C(3) + 2.6
C(3) – 0.2
C(3) + 3.7
ns
gpmc_ncsx(13) valid to
gpmc_noe invalid
(Single read)
FA9
td(AV-nCSV)
Delay time, address
bus valid to
J(9) – 0.2
J(9) – 0.2
J(9) + 2.0
J(9) + 2.0
J(9) – 0.2
J(9) – 0.2
J(9) + 2.6
J(9) + 2.6
J(9) – 0.2
J(9) – 0.2
J(9) + 3.7
J(9) + 3.7
ns
ns
gpmc_ncsx(13) valid
FA10 td(nBEV-nCSV)
Delay time,
gpmc_nbe0_cle,
gpmc_nbe1 valid to
gpmc_ncsx(13) valid
FA12 td(nCSV-nADVV)
FA13 td(nCSV-nOEV)
FA16 tw(AIV)
Delay time,
K(10) – 0.2 K(10) + 2.0 K(10) – 0.2 K(10) + 2.6 K(10) – 0.2 K(10) + 3.7
ns
ns
ns
gpmc_ncsx(13) valid to
gpmc_nadv_ale valid
Delay time,
L(11) – 0.2 L(11) + 2.0 L(11) – 0.2 L(11) + 2.6 L(11) – 0.2 L(11) + 3.7
gpmc_ncsx(13) valid to
gpmc_noe valid
Address invalid
duration between 2
successive R/W
accesses
G(7)
G(7)
G(7)
FA18 td(nCSV-nOEIV)
Delay time,
I(8) – 0.2
I(8) + 2.0
I(8) – 0.2
I(8) + 2.6
I(8) – 0.2
I(8) + 3.7
ns
gpmc_ncsx(13) valid to
gpmc_noe invalid
(Burst read)
FA20 tw(AV)
Pulse duration, address
valid – 2nd, 3rd, and
4th accesses
D(4)
D(4)
D(4)
ns
ns
ns
FA25 td(nCSV-nWEV)
Delay time,
E(5) – 0.2
F(6) – 0.2
E(5) + 2.0
F(6) + 2.0
E(5) – 0.2
F(6) – 0.2
E(5) + 2.6
F(6) + 2.6
E(5) – 0.2
F(6) – 0.2
E(5) + 3.7
F(6) + 3.7
gpmc_ncsx(13) valid to
gpmc_nwe valid
FA27 td(nCSV-nWEIV)
Delay time,
gpmc_ncsx(13) valid to
gpmc_nwe invalid
FA28 td(nWEV-DV)
FA29 td(DV-nCSV)
Delay time, gpmc_ new
valid to data bus valid
2.0
2.6
3.7
ns
ns
Delay time, data bus
valid to gpmc_ncsx(13)
valid
J(9) – 0.2
J(9) + 2.0
J(9) – 0.2
J(9) + 2.6
J(9) – 0.2
J(9) + 3.7
FA37 td(nOEV-AIV)
Delay time, gpmc_noe
valid to
2.0
2.6
3.7
ns
gpmc_a[16:1]_d[15:0]
address phase end
(1) For single read: A = (CSRdOffTime – CSOnTime) * (TimeParaGranularity + 1) * GPMC_FCLK
For single write: A = (CSWrOffTime – CSOnTime) * (TimeParaGranularity + 1) * GPMC_FCLK
For burst read: A = (CSRdOffTime – CSOnTime + (n – 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK
For burst write: A = (CSWrOffTime – CSOnTime + (n – 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK with n
being the page burst access number
(2) For reading: B = ((ADVRdOffTime – CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (ADVExtraDelay – CSExtraDelay)) * GPMC_FCLK
For writing: B = ((ADVWrOffTime – CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (ADVExtraDelay – CSExtraDelay)) * GPMC_FCLK
(3) C = ((OEOffTime – CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (OEExtraDelay – CSExtraDelay)) * GPMC_FCLK
(4) D = PageBurstAccessTime * (TimeParaGranularity + 1) * GPMC_FCLK
(5) E = ((WEOnTime – CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (WEExtraDelay – CSExtraDelay)) * GPMC_FCLK
(6) F = ((WEOffTime – CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (WEExtraDelay – CSExtraDelay)) * GPMC_FCLK
(7) G = Cycle2CycleDelay * GPMC_FCLK
(8) I = ((OEOffTime + (n – 1) * PageBurstAccessTime – CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (OEExtraDelay – CSExtraDelay)) *
GPMC_FCLK
(9) J = (CSOnTime * (TimeParaGranularity + 1) + 0.5 * CSExtraDelay) * GPMC_FCLK
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(10) K = ((ADVOnTime – CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (ADVExtraDelay – CSExtraDelay)) * GPMC_FCLK
(11) L = ((OEOnTime – CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (OEExtraDelay – CSExtraDelay)) * GPMC_FCLK
(12) For single read: N = RdCycleTime * (TimeParaGranularity + 1) * GPMC_FCLK
For single write: N = WrCycleTime * (TimeParaGranularity + 1) * GPMC_FCLK
For burst read: N = (RdCycleTime + (n – 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK
For burst write: N = (WrCycleTime + (n – 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK
(13) In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7.
GPMC_FCLK
gpmc_clk
FA5
FA1
gpmc_ncsx
FA9
gpmc_a[10:1]
Valid Address
FA0
FA10
gpmc_nbe0_cle
gpmc_nbe1
Valid
FA0
Valid
FA10
FA3
FA12
gpmc_nadv_ale
FA4
FA13
gpmc_noe
gpmc_d[15:0]
Data IN 0
Data IN 0
gpmc_waitx
gpmc_io_dir
OUT
IN
OUT
030-026
Figure 6-7. GPMC/NOR Flash – Asynchronous Read – Single Word Timing(1)(2)(3)
(1) In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. In gpmc_waitx, x is equal to 0, 1, 2, or 3.
(2) FA5 parameter illustrates amount of time required to internally sample input data. It is expressed in number of GPMC functional clock
cycles. From start of read cycle and after FA5 functional clock cycles, input data is internally sampled by active functional clock edge.
FA5 value must be stored inside AccessTime register bit field.
(3) GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.
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GPMC_FCLK
gpmc_clk
FA5
FA5
FA1
FA1
gpmc_ncsx
FA16
FA9
FA9
gpmc_a[10:1]
Address 0
FA0
Address 1
FA0
FA10
FA10
gpmc_nbe0_cle
gpmc_nbe1
Valid
FA0
Valid
FA0
Valid
Valid
FA10
FA10
FA3
FA12
FA3
FA12
gpmc_nadv_ale
FA4
FA4
FA13
FA13
gpmc_noe
Data Upper
gpmc_d[15:0]
gpmc_waitx
gpmc_io_dir
OUT
IN
OUT
IN
030-027
Figure 6-8. GPMC/NOR Flash – Asynchronous Read – 32-bit Timing(1)(2)(3)
(1) In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. In gpmc_waitx, x is equal to 0, 1, 2, or 3.
(2) FA5 parameter illustrates amount of time required to internally sample input data. It is expressed in number of GPMC functional clock
cycles. From start of read cycle and after FA5 functional clock cycles, input data is internally sampled by active functional clock edge.
FA5 value must be stored inside AccessTime register bit field.
(3) GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.
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GPMC_FCLK
gpmc_clk
FA21
FA20
FA20
FA20
FA1
gpmc_ncsx
FA9
gpmc_a[10:1]
Add0
Add1
Add2
Add3
Add4
FA0
FA10
FA10
gpmc_nbe0_cle
FA0
gpmc_nbe1
FA12
gpmc_nadv_ale
FA18
FA13
gpmc_noe
D3
gpmc_d[15:0]
D0
D1
D2
D3
gpmc_waitx
gpmc_io_dir
OUT
OUUTT
IN
030-028
Figure 6-9. GPMC/NOR Flash – Asynchronous Read – Page Mode 4x16-bit Timing(1)(2)(3)(4)
(1) In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. In gpmc_waitx, x is equal to 0, 1, 2, or 3.
(2) FA21 parameter illustrates amount of time required to internally sample first input page data. It is expressed in number of GPMC
functional clock cycles. From start of read cycle and after FA21 functional clock cycles, first input page data is internally sampled by
active functional clock edge. FA21 value must be stored inside AccessTime register bit field.
(3) FA20 parameter illustrates amount of time required to internally sample successive input page data. It is expressed in number of GPMC
functional clock cycles. After each access to input page data, next input page data is internally sampled by active functional clock edge
after FA20 functional clock cycles. FA20 is also the duration of address phases for successive input page data (excluding first input
page data). FA20 value must be stored in PageBurstAccessTime register bit field.
(4) GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.
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gpmc_fclk
gpmc_clk
FA1
gpmc_ncsx
FA9
gpmc_a[10:1]
Valid Address
FA0
FA10
gpmc_nbe0_cle
FA0
FA10
gpmc_nbe1
FA3
FA12
gpmc_nadv_ale
FA27
FA25
gpmc_nwe
FA29
gpmc_d[15:0]
gpmc_waitx
gpmc_io_dir
Data OUT
OUT
030-029
In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. In gpmc_waitx, x is equal to 0, 1, 2, or 3.
Figure 6-10. GPMC/NOR Flash – Asynchronous Write – Single Word Timing
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GPMC_FCLK
gpmc_clk
FA1
FA5
gpmc_ncsx
FA9
gpmc_a[26:17]
Address (MSB)
FA0
FA10
FA10
gpmc_nbe0_cle
gpmc_nbe1
Valid
FA0
Valid
FA3
FA12
gpmc_nadv_ale
FA4
FA13
gpmc_noe
gpmc_a[16:1]_d[15:0]
gpmc_io_dir
FA29
FA37
Data IN
Data IN
Address (LSB)
OUT
OUT
IN
gpmc_waitx
030-030
Figure 6-11. GPMC/Multiplexed NOR Flash – Asynchronous Read – Single Word Timing(1)(2)(3)
(1) In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. In gpmc_waitx, x is equal to 0, 1, 2, or 3.
(2) FA5 parameter illustrates amount of time required to internally sample input data. It is expressed in number of GPMC functional clock
cycles. From start of read cycle and after FA5 functional clock cycles, input data is internally sampled by active functional clock edge.
FA5 value must be stored inside AccessTime register bit field.
(3) GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.
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gpmc_fclk
gpmc_clk
FA1
gpmc_ncsx
FA9
gpmc_a[26:17]
Address (MSB)
FA0
FA10
gpmc_nbe0_cle
FA0
FA10
gpmc_nbe1
FA3
FA12
gpmc_nadv_ale
FA27
FA25
gpmc_nwe
gpmc_a[16:1]_d[15:0]
gpmc_waitx
FA29
Valid Address (LSB)
FA28
Data OUT
gpmc_io_dir
OUT
030-031
In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. In gpmc_waitx, x is equal to 0, 1, 2, or 3.
Figure 6-12. GPMC/Multiplexed NOR Flash – Asynchronous Write – Single Word Timing
6.4.1.3 GPMC/NAND Flash Interface Timing
Table 6-10 through Table 6-12 assume testing over the recommended operating conditions (see
Figure 6-13 through Figure 6-16) and electrical characteristic conditions.
Table 6-9. GPMC/NAND Flash Asynchronous Mode Timing Conditions
TIMING CONDITION PARAMETER
Input Conditions
VALUE
UNIT
tR
Input signal rise time
Input signal fall time
1.8
1.8
ns
ns
tF
Output Conditions
CLOAD
Output load capacitance
15.94
pF
Table 6-10. GPMC/NAND Flash Interface Asynchronous Timing – Internal Parameters(1)(2)
NO.
PARAMETER
1.15 V
1.0 V
0.9 V
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
GNFI1
GNFI2
GNFI3
Maximum output data generation delay from
internal functional clock
6.5
9.1
13.7
ns
ns
ns
Maximum input data capture delay by internal
functional clock
4
5.6
9.1
8.1
Maximum device select generation delay from
internal functional clock
6.5
13.7
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Table 6-10. GPMC/NAND Flash Interface Asynchronous Timing – Internal Parameters(1)(2) (continued)
NO.
PARAMETER
1.15 V
1.0 V
0.9 V
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
GNFI4
GNFI5
GNFI6
GNFI7
GNFI8
Maximum address latch enable generation delay
from internal functional clock
6.5
9.1
13.7
ns
ns
ns
ns
ps
Maximum command latch enable generation
delay from internal functional clock
6.5
6.5
6.5
100
9.1
9.1
9.1
170
13.7
13.7
13.7
200
Maximum output enable generation delay from
internal functional clock
Maximum write enable generation delay from
internal functional clock
Maximum functional clock skew
(1) Internal parameters table must be used to calculate data access time stored in the corresponding CS register bit field.
(2) Internal parameters are referred to the GPMC functional internal clock which is not provided externally.
Table 6-11. GPMC/NAND Flash Interface Timing Requirements
NO.
PARAMETER
1.15 V
1.0 V
0.9 V
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
GNF12(1) tacc(DAT)
Data maximum access time
J(2)
J(2)
J(2)
GPMC_FCLK
cycles
(1) The GNF12 parameter illustrates the amount of time required to internally sample input data. It is expressed in number of GPMC
functional clock cycles. From start of the read cycle and after GNF12 functional clock cycles, input data is internally sampled by the
active functional clock edge. The GNF12 value must be stored inside AccessTime register bit field.
(2) J = AccessTime * (TimeParaGranularity + 1)
Table 6-12. GPMC/NAND Flash Interface Switching Characteristics
NO.
PARAMETER
1.15 V
1.0 V
0.9 V
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
tR(DO)
Rise time, output
data
2.0
2.0
2.0
ns
ns
ns
tF(DO)
Fall time, output
data
2.0
2.0
2.0
GNF0
GNF1
tw(nWEV)
Pulse duration,
gpmc_nwe valid
time
A(1)
A(1)
A(1)
td(nCSV-nWEV)
tw(CLEH-nWEV)
tw(nWEV-DV)
Delay time,
gpmc_ncsx(13)
valid to
B(2) – 0.2
C(3) – 0.2
D(4) – 0.2
E(5) – 0.2
F(6) – 0.2
B(2) + 2.0
C(3) + 2.0
D(4) + 2.0
E(5) + 2.0
F(6) + 2.0
B(2) – 0.2
C(3) – 0.2
D(4) – 0.2
E(5) – 0.2
F(6) – 0.2
B(2) + 2.6
C(3) + 2.6
D(4) + 2.6
E(5) + 2.6
F(6) + 2.6
B(2) – 0.2
C(3) – 0.2
D(4) – 0.2
E(5) – 0.2
F(6) – 0.2
B(2) + 3.7
C(3) + 3.7
D(4) + 3.7
E(5) + 3.7
F(6) + 3.7
ns
ns
ns
ns
ns
gpmc_nwe valid
GNF2
GNF3
GNF4
GNF5
Delay time,
gpmc_nbe0_cle
high to gpmc_nwe
valid
Delay time,
gpmc_d[15:0]
valid to
gpmc_nwe valid
tw(nWEIV-DIV)
Delay time,
gpmc_nwe invalid
to gpmc_d[15:0]
invalid
tw(nWEIV-CLEIV)
Delay time,
gpmc_nwe invalid
to
gpmc_nbe0_cle
invalid
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Table 6-12. GPMC/NAND Flash Interface Switching Characteristics (continued)
NO.
PARAMETER
1.15 V
1.0 V
0.9 V
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
GNF6
tw(nWEIV-nCSIV)
tw(ALEH-nWEV)
tw(nWEIV-ALEIV)
Delay time,
G(7) – 0.2 G(7) + 2.0
G(7) – 0.2
G(7) + 2.6 G(7) – 0.2 G(7) + 3.7
ns
gpmc_nwe invalid
to gpmc_ncsx(13)
invalid
GNF7
GNF8
Delay time,
gpmc_nadv_ale
High to
C(3) – 0.2
F(6) – 0.2
C(3) + 2.0
F(6) + 2.0
C(3) – 0.2
F(6) – 0.2
C(3) + 2.6
F(6) + 2.6
C(3) – 0.2
F(6) – 0.2
C(3) + 3.7
F(6) + 3.7
ns
ns
gpmc_nwe valid
Delay time,
gpmc_nwe invalid
to
gpmc_nadv_ale
invalid
GNF9
tc(nWE)
Cycle time, Write
cycle time
H(8)
H(8)
H(8)
ns
ns
GNF10
td(nCSV-nOEV)
Delay time,
gpmc_ncsx(13)
valid to gpmc_noe
valid
I(9) – 0.2
I(9) + 2.0
I(9) – 0.2
I(9) + 2.6
I(9) – 0.2
I(9) + 3.7
GNF13
tw(nOEV)
Pulse duration,
gpmc_noe valid
time
K(10)
K(10)
K(10)
ns
GNF14
GNF15
tc(nOE)
Cycle time, Read
cycle time
L(11)
L(11)
L(11)
ns
ns
tw(nOEIV-nCSIV)
Delay time,
M(12) – 0.2 M(12) + 2.0 M(12) – 0.2 M(12) + 2.6 M(12) – 0.2 M(12) + 3.7
gpmc_noe invalid
to gpmc_ncsx(13)
invalid
(1) A = (WEOffTime – WEOnTime) * (TimeParaGranularity + 1) * GPMC_FCLK
(2) B = ((WEOnTime – CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (WEExtraDelay – CSExtraDelay)) * GPMC_FCLK
(3) C = ((WEOnTime – ADVOnTime) * (TimeParaGranularity + 1) + 0.5 * (WEExtraDelay – ADVExtraDelay)) * GPMC_FCLK
(4) D = (WEOnTime * (TimeParaGranularity + 1) + 0.5 * WEExtraDelay ) * GPMC_FCLK
(5) E = (WrCycleTime – WEOffTime * (TimeParaGranularity + 1) – 0.5 * WEExtraDelay ) * GPMC_FCLK
(6) F = (ADVWrOffTime – WEOffTime * (TimeParaGranularity + 1) + 0.5 * (ADVExtraDelay – WEExtraDelay ) * GPMC_FCLK
(7) G = (CSWrOffTime – WEOffTime * (TimeParaGranularity + 1) + 0.5 * (CSExtraDelay – WEExtraDelay ) * GPMC_FCLK
(8) H = WrCycleTime * (1 + TimeParaGranularity) * GPMC_FCLK
(9) I = ((OEOnTime – CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (OEExtraDelay – CSExtraDelay)) * GPMC_FCLK
(10) K = (OEOffTime – OEOnTime) * (1 + TimeParaGranularity) * GPMC_FCLK
(11) L = RdCycleTime * (1 + TimeParaGranularity) * GPMC_FCLK
(12) M = (CSRdOffTime – OEOffTime * (TimeParaGranularity + 1) + 0.5 * (CSExtraDelay – OEExtraDelay ) * GPMC_FCLK
(13) In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7.
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GPMC_FCLK
gpmc_ncsx
GNF1
GNF2
GNF6
GNF5
gpmc_nbe0_cle
gpmc_nadv_ale
gpmc_noe
GNF0
gpmc_nwe
GNF3
GNF4
gpmc_a[16:1]_d[15:0]
In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7.
Command
030-032
Figure 6-13. GPMC/NAND Flash – Command Latch Cycle Timing
GPMC_FCLK
gpmc_ncsx
GNF1
GNF6
gpmc_nbe0_cle
gpmc_nadv_ale
gpmc_noe
GNF7
GNF8
GNF9
GNF0
gpmc_nwe
GNF3
GNF4
gpmc_a[16:1]_d[15:0]
Address
030-033
In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7.
Figure 6-14. GPMC/NAND Flash – Address Latch Cycle Timing
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GPMC_FCLK
GNF12
GNF10
GNF15
gpmc_ncsx
gpmc_nbe0_cle
gpmc_nadv_ale
GNF14
GNF13
gpmc_noe
gpmc_a[16:1]_d[15:0]
DATA
gpmc_waitx
030-034
Figure 6-15. GPMC/NAND Flash – Data Read Cycle Timing(1)(2)(3)
(1) The GNF12 parameter illustrates amount of time required to internally sample input data. It is expressed in number of GPMC functional
clock cycles. From start of read cycle and after GNF12 functional clock cycles, input data is internally sampled by active functional clock
edge. The GNF12 value must be stored inside AccessTime register bit field.
(2) GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.
(3) In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. In gpmc_waitx, x is equal to 0 ,1, 2, or 3.
GPMC_FCLK
GNF1
GNF6
gpmc_ncsx
gpmc_nbe0_cle
gpmc_nadv_ale
gpmc_noe
GNF9
GNF0
gpmc_nwe
GNF3
GNF4
gpmc_a[16:1]_d[15:0]
DATA
030-035
In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. In gpmc_waitx, x is equal to 0 or 1.
Figure 6-16. GPMC/NAND Flash – Data Write Cycle Timing
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6.4.2 SDRAM Controller Subsystem (SDRC)
The SDRAM controller subsystem (SDRC) module provides connectivity between the
OMAP3530/2530/2530/2530/25 Applications Processor and external DRAM memory components. The
SDRC module only supports low-power double-data-rate (LPDDR) SDRAM devices. Memory devices can
be interfaced to the SDRC using a stacked-memory approach or through the printed circuit board (PCB).
The stacked-memory approach uses the package-on-package memory interface pins (available only on
CBB package).
The approach to specifying interface timing for the SDRC memory bus is different than on other interfaces
such as the general-purpose memory controller (GPMC) and the multi-channel buffered serial ports
(McBSPs). For these other interfaces the device timing was specified in terms of data manual
specifications and I/O buffer information specification (IBIS) models.
For the SDRC memory bus, the approach is to specify compatible memory devices and provide the
printed circuit board (PCB) solution and guidelines directly to the user. Texas Instruments (TI) has
performed the simulation and system characterization to ensure all interface timings in this solution are
met. The complete PCB memory system solution is documented in the TBD application report (literature
number SPRATBD). Guidelines on using the stacked-memory approach are described in the TBD
application report (literature number SPRATBD).
TI only supports designs that use supported memory devices and follow the board design guidelines
outlined in the SPRATBD application report.
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6.5 Video Interfaces
6.5.1 Camera Interface
The camera subsystem provides the system interfaces and the processing capability to connect raw, YUV,
or JPEG image sensor modules to the OMAP3515/03 device for video-preview, video-record, and
still-image-capture applications. The camera subsystem supports up to two simultaneous pixel flows but
only one of them can use the video processing hardware:
•
PARALLEL: the parallel interface data must go through the video processing hardware.
6.5.1.1 Parallel Camera Interface Timing
The parallel camera interface is a 12-bit interface which can be used in two modes:
1. SYNC mode: progressive and interlaced image sensor modules for 8-, 10-, 11-, and 12-bit data. The
pixel clock can be up to 75 MHz in 12-bit mode. The pixel clock can be up to 130 MHz in 8-bit packed
mode.
2. ITU mode provides an ITU-R BT 656 compatible data stream with progressive image sensor modules
only in 8- and 10-bit configurations. The pixel clock can be up to 150 MHz in 8-bit packed mode (up to
75 MHz in 10-bit mode)
6.5.1.1.1 SYNC Normal Mode
6.5.1.1.1.1 12-Bit SYNC Normal – Progressive Mode
Table 6-14 and Table 6-15 assume testing over the recommended operating conditions and electrical
characteristic conditions (see Figure 6-17).
Table 6-13. ISP Timing Conditions – 12-Bit SYNC Normal – Progressive Mode
TIMING CONDITION PARAMETER
Input Conditions
VALUE
UNIT
tR
Input signal rise time
Input signal fall time
2.7
2.7
ns
ns
tF
Output Condition
CLOAD
Output load capacitance
8.6
pF
Table 6-14. ISP Timing Requirements – 12-Bit SYNC Normal – Progressive Mode(4)
NO.
PARAMETER
1.15 V
MAX
1.0 V
UNIT
MIN
MIN
MAX
ISP17
ISP18
ISP18
tc(pclk)
Cycle time(1), cam_pclk period
Typical pulse duration, cam_pclk high
Typical pulse duration, cam_pclk low
Duty cycle error, cam_pclk
13.3
22.2
ns
ns
ns
ps
ps
ns
tW(pclkH)
tW(pclkL)
tdc(pclk)
tj(pclk)
0.5*P(2)
0.5*P(2)
0.5*P(2)
0.5*P(2)
667
133
1111
200
Cycle jitter(3), cam_pclk
ISP19
ISP20
ISP21
tsu(dV-pclkH)
Setup time, cam_d[11:0] valid before cam_pclk rising
edge
1.82
1.82
1.82
3.25
3.25
3.25
th(pclkH-dV)
tsu(dV-vsH)
Hold time, cam_d[11:0] valid after cam_pclk rising
edge
ns
ns
Setup time, cam_vs valid before cam_pclk rising
edge
ISP22
ISP23
th(pclkH-vsV)
tsu(dV-hsH)
Hold time, cam_vs valid after cam_pclk rising edge
1.82
1.82
3.25
3.25
ns
ns
Setup time, cam_hs valid before cam_pclk rising
edge
ISP24
ISP25
th(pclkH-hsV)
tsu(dV-hsH)
Hold time, cam_hs valid after cam_pclk rising edge
1.82
1.82
3.25
3.25
ns
ns
Setup time, cam_wen valid before cam_pclk rising
edge
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Table 6-14. ISP Timing Requirements – 12-Bit SYNC Normal – Progressive Mode(4) (continued)
NO.
PARAMETER
1.15 V
MAX
1.0 V
UNIT
MIN
MIN
MAX
ISP26
th(pclkH-hsV)
Hold time, cam_wen valid after cam_pclk rising edge
1.82
3.25
ns
(1) Related with the input maximum frequency supported by the ISP module.
(2) P = cam_pclk period in ns
(3) Maximum cycle jitter supported by cam_pclk input clock.
(4) The timing requirements are assured for the cycle jitter and duty cycle error conditions specified.
Table 6-15. ISP Switching Characteristics – 12-Bit SYNC Normal – Progressive Mode
NO.
PARAMETER
1.15 V
1.0 V
UNIT
MIN
MAX
MIN
MAX
ISP15
ISP16
ISP16
tc(xclk)
Cycle time(1), cam_xclk period
Typical pulse duration, cam_xclk high
Typical pulse duration, cam_xclk low
Duty cycle error, cam_xclk
4.6
4.6
ns
ns
ns
ps
ps
ns
ns
tW(xclkH)
tW(xclkL)
tdc(xclk)
tj(xclk)
0.5*PO(2)
0.5*PO(2)
0.5*PO(2)
0.5*PO(2)
231
231
Jitter standard deviation(3), cam_xclk
33
33
tR(xclk)
tF(xclk)
Rise time, cam_xclk
0.93
0.93
0.93
0.93
Fall time, cam_xclk
(1) Related with the cam_xclk maximum and minimum frequencies programmable in the ISP module.
Warning: The camera sensor or the camera module must be disabled to change the frequency configuration. For more information, see
the OMAP35xx ES2.0 Technical Reference Manual (TRM) [literature number SPRUF98].
(2) PO = cam_xclk period in ns
(3) The jitter probability density can be approximated by a Gaussian function.
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ISP16
ISP15
ISP16
cam_xclki
ISP17
ISP18
ISP18
cam_pclk
ISP19
ISP20
ISP22
cam_vs
ISP21
cam_hs
ISP23
D(n-1)
ISP24
D(1)
cam_d[11:0]
D(0)
D(n-3) D(n-2)
D(0)
D(n-1)
ISP25
ISP26
cam_wen
cam_fld
030-056
Figure 6-17. ISP – 12-Bit SYNC Normal – Progressive Mode(1)(2)(3)(4)(5)(6)(7)(8)
(1) The polarity of cam_pclk, cam_fld, cam_vs, and cam_hs are configurable. If the cam_hs, cam_vs, and cam_fld signals are output, the
signal length can be set.
(2) The parallel camera in SYNC mode supports progressive image sensor modules and 8-, 10-, 11-, or 12-bit data.
(3) When the image sensor has fewer than 12 data lines, it must be connected to the lower data lines and the unused lines must be
grounded.
(4) However, it is possible to shift the data to 0, 2, or 4 data internal lanes.
(5) The bit configurations are: cam_d[11:4] or cam_d[7:0] in 8-bit mode, cam_d[11:2] or cam_d[9:0] in 10-bit mode, cam_d[10:0] in 11-bit
mode, and cam_d[11:0] in 12-bit mode.
(6) Optionally, the data write to memory can be qualified by the external cam_wen signal.
(7) The cam_wen signal can be used as a external memory write-enable signal. The data is stored to memory only if cam_hs, cam_vs, and
cam_wen signals are asserted.
(8) In cam_xclki; I is equal to a or b.
6.5.1.1.1.2 8-bit Packed SYNC – Progressive Mode
Table 6-17 and Table 6-18 assume testing over the recommended operating conditions and electrical
characteristic conditions (see Figure 6-18).
Table 6-16. ISP Timing Conditions – 8-bit Packed SYNC – Progressive Mode
TIMING CONDITION PARAMETER
Input Conditions
VALUE
UNIT
tR
Input signal rise time
Input signal fall time
2.5
2.5
ns
ns
tF
Output Conditions
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Table 6-16. ISP Timing Conditions – 8-bit Packed SYNC – Progressive Mode (continued)
TIMING CONDITION PARAMETER
Output load capacitance
VALUE
UNIT
CLOAD
8.6
pF
Table 6-17. ISP Timing Requirements – 8-bit Packed SYNC – Progressive Mode(4)
NO.
PARAMETER
1.15 V
MAX
1.0 V
UNIT
MIN
MIN
MAX
ISP3
ISP4
ISP4
tc(pclk)
Cycle time(1), cam_pclk period
Typical pulse duration, cam_pclk high
Typical pulse duration, cam_pclk low
Duty cycle error, cam_pclk
7.7
15.4
ns
ns
ns
ps
ps
ns
tW(pclkH)
tW(pclkL)
tdc(pclk)
tj(pclk)
0.5*P(2)
0.5*P(2)
0.5*P(2)
0.5*P(2)
385
83
769
167
Cycle jitter(3), cam_pclk
ISP5
ISP6
ISP7
tsu(dV-pclkH)
Setup time, cam_d[11:0] valid before cam_pclk
rising edge
1.08
1.08
1.08
2.27
2.27
2.27
th(pclkH-dV)
tsu(dV-vsH)
Hold time, cam_d[11:0] valid after cam_pclk rising
edge
ns
ns
Setup time, cam_vs valid before cam_pclk rising
edge
ISP8
ISP9
th(pclkH-vsV)
tsu(dV-hsH)
Hold time, cam_vs valid after cam_pclk rising edge
1.08
1.08
2.27
2.27
ns
ns
Setup time, cam_hs valid before cam_pclk rising
edge
ISP10
ISP11
th(pclkH-hsV)
tsu(dV-hsH)
Hold time, cam_hs valid after cam_pclk rising edge
1.08
1.08
2.27
2.27
ns
ns
Setup time, cam_wen valid before cam_pclk rising
edge
ISP12
th(pclkH-hsV)
Hold time, cam_wen valid after cam_pclk rising edge
1.08
2.27
ns
(1) Related with the input maximum frequency supported by the ISP module.
(2) P = cam_pclk period in ns.
(3) Maximum cycle jitter supported by cam_pclk input clock.
(4) The timing requirements are assured for the cycle jitter and duty cycle error conditions specified.
Table 6-18. ISP Switching Characteristics – 8-bit packed SYNC – Progressive Mode
NO.
PARAMETER
1.15 V
1.0 V
UNIT
MIN
MAX
MIN
MAX
ISP1
ISP2
ISP2
tc(xclk)
Cycle time(1), cam_xclk period
Typical pulse duration, cam_xclk high
Typical pulse duration, cam_xclk low
Duty cycle error, cam_xclk
4.6
4.6
ns
ns
ns
ps
ps
ns
ns
tW(xclkH)
tW(xclkL)
tdc(xclk)
tj(xclk)
0.5*PO(2)
0.5*PO(2)
0.5*PO(2)
0.5*PO(2)
231
67
231
67
Jitter standard deviation(3), cam_xclk
tR(xclk)
tF(xclk)
Rise time, cam_xclk
0.93
0.93
0.93
0.93
Fall time, cam_xclk
(1) Related with the cam_xclk maximum and minimum frequencies programmable in the ISP module.
Warning: You must disable the camera sensor or the camera module to change the frequency configuration. For more information, see
the OMAP35xx ES2.0 Technical Reference Manual (TRM) [literature number SPRUF98].
(2) PO = cam_xclk period in ns
(3) The jitter probability density can be approximated by a Gaussian function.
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ISP1
ISP2
ISP2
cam_xclki
ISP4
ISP3
ISP4
cam_pclk
ISP5
ISP6
cam_vs
ISP7
ISP8
cam_hs
ISP9
D(n-1)
ISP10
D(1)
cam_d[7:0]
D(0)
D(n-3) D(n-2)
D(0)
D(n-1)
ISP12
ISP11
cam_wen
cam_fld
030-059
Figure 6-18. ISP – 8-bit Packed SYNC – Progressive Mode(1)(2)(3)(4)(5)
(1) The polarity of cam_pclk, cam_fld, cam_vs, and cam_hs are configurable.
(2) The image sensor must be connected to the lower data lines and the unused lines must be grounded. However, it is possible to shift the
data to 0, 2, or 4 data internal lanes. The bit configurations are: cam_d[11:4] or cam_d[7:0] in 8-bit packed mode.
(3) Optionally, the data write to memory can be qualified by the external cam_wen signal. The cam_wen signal can be used as a external
memory write-enable signal. The data is stored to memory only if cam_hs, cam_vs, and cam_wen signals are asserted. The polarity of
cam_fld is programmable.
(4) The camera module can pack 8-bit data into 16 bits. It doubles the maximum pixel clock. This mode can be particularly useful to transfer
a YCbCr data stream or compressed stream to memory at very high speed.
(5) In cam_xclki; I is equal to a or b.
6.5.1.1.1.3 12-Bit SYNC Normal – Interlaced Mode
Table 6-20 and Table 6-21 assume testing over the recommended operating conditions and electrical
characteristic conditions (see Figure 6-19).
Table 6-19. ISP Timing Conditions – 12-Bit SYNC Normal – Interlaced Mode
TIMING CONDITION PARAMETER
Input Conditions
VALUE
UNIT
tR
Input signal rise time
Input signal fall time
2.7
2.7
ns
ns
tF
Output Conditions
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Table 6-19. ISP Timing Conditions – 12-Bit SYNC Normal – Interlaced Mode (continued)
TIMING CONDITION PARAMETER
Output load capacitance
VALUE
UNIT
CLOAD
8.6
pF
Table 6-20. ISP Timing Requirements – 12-Bit SYNC Normal – Interlaced Mode(4)
NO.
PARAMETER
1.15 V
1.0 V
UNIT
MIN
MAX
MIN
MAX
ISP17
ISP18
ISP18
tc(pclk)
Cycle time(1), cam_pclk period
Typical pulse duration, cam_pclk high
Typical pulse duration, cam_pclk low
Duty cycle error, cam_pclk
13.3
22.2
ns
ns
ns
ps
ps
ns
tW(pclkH)
tW(pclkL)
tdc(pclk)
tj(pclk)
0.5*P(2)
0.5*P(2)
0.5*P(2)
0.5*P(2)
667
133
1111
200
Cycle jitter(3), cam_pclk
ISP19
ISP20
ISP21
tsu(dV-pclkH)
Setup time, cam_d[11:0] valid before cam_pclk
rising edge
1.82
1.82
1.82
3.25
th(pclkH-dV)
tsu(dV-vsH)
Hold time, cam_d[11:0] valid after cam_pclk rising
edge
3.25
3.25
ns
ns
Setup time, cam_vs valid before cam_pclk rising
edge
ISP22
ISP23
th(pclkH-vsV)
tsu(dV-hsH)
Hold time, cam_vs valid after cam_pclk rising edge
1.82
1.82
3.25
3.25
ns
ns
Setup time, cam_hs valid before cam_pclk rising
edge
ISP24
ISP25
th(pclkH-hsV)
tsu(dV-hsH)
Hold time, cam_hs valid after cam_pclk rising edge
1.82
1.82
3.25
3.25
ns
ns
Setup time, cam_wen valid before cam_pclk rising
edge
ISP26
ISP27
ISP28
th(pclkH-hsV)
tsu(dV-fldH)
th(pclkH-fldV)
Hold time, cam_wen valid after cam_pclk rising
edge
1.82
1.82
1.82
3.25
3.25
3.25
ns
ns
ns
Setup time, cam_fld valid before cam_pclk rising
edge
Hold time, cam_fld valid after cam_pclk rising edge
(1) Related with the input maximum frequency supported by the ISP module.
(2) P = cam_lclk period in ns.
(3) Maximum cycle jitter supported by cam_pclk input clock.
(4) The timing requirements are assured for the cycle jitter and duty cycle error conditions specified.
Table 6-21. ISP Switching Characteristics – 12-Bit SYNC Normal – Interlaced Mode
NO.
PARAMETER
1.15 V
1.0 V
UNIT
MIN
MAX
MIN
MAX
ISP15
ISP16
ISP16
tc(xclk)
Cycle time(1), cam_xclk period
Typical pulse duration, cam_xclk high
Typical pulse duration, cam_xclk low
Duty cycle error, cam_xclk
4.6
4.6
ns
ns
ns
ps
ps
ns
ns
tW(xclkH)
tW(xclkL)
tdc(xclk)
tj(xclk)
0.5*PO(2)
0.5*PO(2)
0.5*PO(2)
0.5*PO(2)
231
231
Jitter standard deviation(3), cam_xclk
33
33
tR(xclk)
tF(xclk)
Rise time, cam_xclk
0.93
0.93
0.93
0.93
Fall time, cam_xclk
(1) Related with the cam_xclk maximum and minimum frequencies programmable in the ISP module.
Warning: You must disable the camera sensor or the camera module to change the frequency configuration. For more information, see
the OMAP35xx ES2.0 Technical Reference Manual (TRM) [literature number SPRUF98].
(2) PO = cam_xclk period in ns.
(3) The jitter probability density can be approximated by a Gaussian function.
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ISP16
ISP15
ISP16
cam_xclki
ISP18
ISP18
ISP17
cam_pclk
ISP20
ISP19
cam_vs
cam_hs
FRAME(0)
FRAME(0)
ISP21
ISP22
L(0)
L(n-1)
L(0)
ISP23
D(1)
ISP24
D(n-1)
cam_d[11:0]
D(0)
D(n-3) D(n-2)
D(n-1)
D(0)
D(2)
ISP25
ISP26
cam_wen
ISP28
ISP27
cam_fld
PAIR
IMPAIR
030-057
Figure 6-19. ISP – 12-Bit SYNC Normal – Interlaced Mode(1)(2)(3)(4)(5)(6)(7)(8)
(1) The polarity of cam_pclk, cam_fld, cam_vs, and cam_hs are configurable. If the cam_hs, cam_vs, and cam_fld signals are output, the
signal length can be set.
(2) The parallel camera in SYNC mode supports interlaced image sensor modules and 8-, 10-, 11-, or 12-bit data.
(3) When the image sensor has fewer than 12 data lines, it must be connected to the lower data lines and the unused lines must be
grounded.
(4) It is possible to shift the data to 0, 2, or 4 data internal lanes.
(5) The bit configurations are: cam_d[11:4] or cam_d[7:0] in 8-bit mode, cam_d[11:2] or cam_d[9:0] in 10-bit mode, cam_d[10:0] in 11-bit
mode, and cam_d[11:0] in 12-bit mode.
(6) Optionally, the data write to memory can be qualified by the external cam_wen signal.
(7) The cam_wen signal can be used as a external memory write-enable signal. The data is stored to memory only if cam_hs, cam_vs, and
cam_wen signals are asserted.
(8) In cam_xclki; I is equal to a or b.
6.5.1.1.1.4 8-bit Packed SYNC – Interlaced Mode
Table 6-23 and Table 6-24 assume testing over the recommended operating conditions and electrical
characteristic conditions (see Figure 6-20).
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Table 6-22. ISP Timing Conditions – 8-bit Packed SYNC – Interlaced Mode
TIMING CONDITION PARAMETER
VALUE
UNIT
Input Conditions
tR
Input signal rise time
Input signal fall time
2.5
2.5
ns
ns
tF
Output Conditions
CLOAD
Output load capacitance
8.6
pF
Table 6-23. ISP Timing Requirements – 8-bit Packed SYNC – Interlaced Mode(4)
NO.
PARAMETER
1.15 V
1.0 V
UNIT
MIN
MAX
MIN
MAX
ISP3
ISP4
ISP4
tc(pclk)
Cycle time(1), cam_pclk period
Typical pulse duration, cam_pclk high
Typical pulse duration, cam_pclk low
Duty cycle error, cam_pclk
7.7
15.4
ns
ns
ns
ps
ps
ns
tW(pclkH)
tW(pclkL)
tdc(pclk)
tj(pclk)
0.5*P(2)
0.5*P(2)
0.5*P(2)
0.5*P(2)
385
83
769
167
Cycle jitter(3), cam_pclk
ISP5
ISP6
ISP7
tsu(dV-pclkH)
Setup time, cam_d[11:0] valid before cam_pclk
rising edge
1.08
1.08
1.08
2.27
2.27
2.27
th(pclkH-dV)
tsu(dV-vsH)
Hold time, cam_d[11:0] valid after cam_pclk rising
edge
ns
ns
Setup time, cam_vs valid before cam_pclk rising
edge
ISP8
ISP9
th(pclkH-vsV)
tsu(dV-hsH)
Hold time, cam_vs valid after cam_pclk rising edge
1.08
1.08
2.27
2.27
ns
ns
Setup time, cam_hs valid before cam_pclk rising
edge
ISP10 th(pclkH-hsV)
ISP11 tsu(dV-hsH)
Hold time, cam_hs valid after cam_pclk rising edge
1.08
1.08
2.27
2.27
ns
ns
Setup time, cam_wen valid before cam_pclk rising
edge
ISP12 th(pclkH-hsV)
ISP13 tsu(dV-fldH)
Hold time, cam_wen valid after cam_pclk rising edge
1.08
1.08
2.27
2.27
ns
ns
Setup time, cam_fld valid before cam_pclk rising
edge
ISP14 th(pclkH-fldV)
Hold time, cam_fld valid after cam_pclk rising edge
1.08
2.27
ns
(1) Related with the input maximum frequency supported by the ISP module.
(2) P = cam_lclk period in ns.
(3) Maximum cycle jitter supported by cam_pclk input clock.
(4) The timing requirements are assured for the cycle jitter and duty cycle error conditions specified.
Table 6-24. ISP Switching Characteristics – 8-bit Packed SYNC – Interlaced Mode
NO.
PARAMETER
1.15 V
1.0 V
UNIT
MIN
MAX
MIN
MAX
ISP16
ISP2
ISP2
tc(xclk)
Cycle time(1), cam_xclk period
Typical pulse duration, cam_xclk high
Typical pulse duration, cam_xclk low
Duty cycle error, cam_xclk
4.6
4.6
ns
ns
ns
ps
ps
ns
ns
tW(xclkH)
tW(xclkL)
tdc(xclk)
tj(xclk)
0.5*PO(2)
0.5*PO(2)
0.5*PO(2)
0.5*PO(2)
231
67
231
67
Jitter standard deviation(3), cam_xclk
tR(xclk)
tF(xclk)
Rise time, cam_xclk
0.93
0.93
0.93
0.93
Fall time, cam_xclk
(1) Related with the cam_xclk maximum and minimum frequencies programmable in the ISP module.
Warning: You must disable the camera sensor or the camera module to change the frequency configuration. For more information, see
the OMAP35xx ES2.0 Technical Reference Manual (TRM) [literature number SPRUF98].
(2) PO = cam_xclk period in ns.
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(3) The jitter probability density can be approximated by a Gaussian function.
ISP2
ISP1
ISP2
cam_xclki
ISP4
ISP3
ISP4
cam_pclk
ISP6
ISP5
cam_vs
cam_hs
FRAME(0)
FRAME(0)
ISP7
ISP8
L(0)
L(n-1)
L(0)
ISP9
D(1)
ISP10
D(n-1)
cam_d[7:0]
cam_wen
D(0)
D(n-3)
D(n-2)
D(n-1)
D(0)
D(2)
ISP11
ISP12
ISP14
ISP13
cam_fld
PAIR
IMPAIR
030-060
Figure 6-20. ISP – 8-bit Packed SYNC – Interlaced Mode(1)(2)(3)(4)(5)
(1) The polarity of cam_pclk, cam_fld, cam_vs, and cam_hs are configurable.
(2) The image sensor must be connected to the lower data lines and the unused lines must be grounded. However, it is possible to shift the
data to 0, 2, or 4 data internal lanes. The bit configurations are: cam_d[11:4] or cam_d[7:0] in 8-bit packed mode.
(3) Optionally, the data write to memory can be qualified by the external cam_wen signal. The cam_wen signal can be used as a external
memory write-enable signal. The data is stored to memory only if cam_hs, cam_vs, and cam_wen signals are asserted.
(4) The camera module can pack 8-bit data into 16 bits. It doubles the maximum pixel clock. This mode can be particularly useful to transfer
a YCbCr data stream or compressed stream to memory at very high speed.
(5) In cam_xclki; I is equal to a or b.
6.5.1.1.2 ITU Mode
Table 6-26 and Table 6-27 assume testing over the recommended operating conditions and electrical
characteristic conditions (see Figure 6-21).
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Table 6-25. ISP Timing Conditions – ITU Mode
TIMING CONDITION PARAMETER
VALUE
UNIT
Input Conditions
tR
Input signal rise time
Input signal fall time
2.7
2.7
ns
ns
tF
Output Conditions
CLOAD
Output load capacitance
8.6
pF
Table 6-26. ISP Timing Requirements – ITU Mode(4)
NO.
PARAMETER
1.15 V
1.0 V
UNIT
MIN
MAX
MIN
MAX
ISP17
ISP18
ISP18
tc(pclk)
Cycle time(1), cam_pclk period
Typical pulse duration, cam_pclk high
Typical pulse duration, cam_pclk low
Duty cycle error, cam_pclk
13.3
22.2
ns
ns
ns
ps
ps
ns
tW(pclkH)
tW(pclkL)
tdc(pclk)
tj(pclk)
0.5*P(2)
0.5*P(2)
0.5*P(2)
0.5*P(2)
667
133
1111
200
Cycle jitter(3), cam_pclk
ISP23
ISP24
tsu(dV-pclkH)
Setup time, cam_d[9:0] valid before cam_pclk
rising edge
1.82
1.82
3.25
3.25
th(pclkH-dV)
Hold time, cam_d[9:0] valid after cam_pclk rising
edge
ns
(1) Related with the input maximum frequency supported by the ISP module.
(2) P = cam_lclk period in ns.
(3) Maximum cycle jitter supported by cam_lclk input clock.
(4) The timing requirements are assured for the cycle jitter and duty cycle error conditions specified.
Table 6-27. ISP Switching Characteristics – ITU Mode
NO.
PARAMETER
1.15 V
1.0 V
UNIT
MIN
MAX
MIN
MAX
ISP15
ISP16
ISP16
tc(xclk)
Cycle time(1), cam_xclk period
Typical pulse duration, cam_xclk high
Typical pulse duration, cam_xclk low
Duty cycle error, cam_xclk
4.6
4.6
ns
ns
ns
ps
ps
ns
ns
tW(xclkH)
tW(xclkL)
tdc(xclk)
tj(xclk)
0.5*PO(2)
0.5*PO(2)
0.5*PO(2)
0.5*PO(2)
231
231
Jitter standard deviation(3), cam_xclk
33
33
tR(xclk)
tF(xclk)
Rise time, cam_xclk
0.93
0.93
0.93
0.93
Fall time, cam_xclk
(1) Related with the cam_xclk maximum and minimum frequencies programmable in the ISP module.
Warning: The camera sensor or the camera module must be disabled to change the frequency configuration. For more information, see
the OMAP35xx ES2.0 Technical Reference Manual (TRM) [literature number SPRUF98].
(2) PO = cam_xclk period in ns
(3) The jitter probability density can be approximated by a Gaussian function.
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ISP16
ISP15
ISP16
cam_xclki
cam_pclk
ISP17
ISP18
ISP18
ISP23
D (0)
ISP24
D(0)
D(n-1)
D(n-1)
cam_d[9:0]
SOF
EOF
SOF
EOF
030-058
Figure 6-21. ISP – ITU Mode(1)(2)
(1) The unused lines must be grounded and the data bus must be connected to the lower data lines. It is possible to shift the data to 0, 2, or
4 data internal lanes. The different configurations are: cam_d[11:4] or cam_d[7:0] in 8-bit mode and cam_d[11:2] or cam_d[9:0] in 10-bit
mode.
(2) The parallel camera in ITU mode supports progressive camera modules.
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6.5.2 Display Subsystem (DSS)
The display subsystem (DSS) provides the logic to display the video frame from external (SDRAM) or
internal (SRAM) memory on an LCD panel or a TV set. The DSS integrates a display controller, a remote
frame buffer module (RFBI), and a TV-out module. It can be used in two configurations:
•
LCD display support in:
–
–
Bypass mode (RFBI module bypassed)
RFBI mode (through RFBI module)
•
TV display support (not discussed in this document because of its analog IO signals)
The two display supports can be active at the same time.
6.5.2.1 LCD Display Support in Bypass Mode
Two types of LCD panel are supported:
•
•
Thin film transistor (TFT) or active matrix technology
Supertwisted nematic (STN) or passive matrix technology
Both configurations are discussed in the following paragraphs.
6.5.2.1.1 LCD Display in TFT Mode
Table 6-28 assumes testing over the recommended operating conditions (see Figure 6-22).
Table 6-28. LCD Display Interface Switching Characteristics in TFT Mode(3)(4)
NO.
PARAMETER
1.15 V
1.0 V
UNIT
MIN
MAX
MIN
MAX
DL0 td(PCLKA-HSYNCT)
DL1 td(PCLKA-VSYNCT)
DL2 td(PCLKA-ACBIASA)
DL3 td(PCLKA-DATAV)
Delay time, dss_pclk active edge to dss_hsync
transition
–3.9
3.9
–4.6
4.6
ns
ns
ns
ns
Delay time, dss_pclk active edge to dss_vsync
transition
–3.9
–3.9
–3.9
3.9
3.9
3.9
–4.6
–4.6
–4.6
13.5
4.6
4.6
4.6
Delay time, dss_pclk active edge to dss_acbias
active level
Delay time, dss_pclk active edge to dss_data bus
valid
Cycle time(2), dss_pclk
DL4 tc(PCLK)
DL5 tw(PCLK)
13.5
0.45*P(1)
ns
ns
Pulse duration, dss_pclk low or high
0.55*P(1) 0.45*P(1) 0.55*P(1)
(1) P = dss_pclk period.
(2) The pixel clock frequency is software programmable via the pixel clock divider configuration from 1 to 255 division range in the
DISPC_DIVISOR register.
(3) The capacitive load is equivalent to 25 pF at 1.15 V and 30 pF at 1.0 V.
(4) For more information, see the DSS chapter of the OMAP35xx ES2.0 Technical Reference Manual (TRM) [literature number TBD].
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DL5
DL4
dss_pclk
DL1
dss_vsync
DL0
dss_hsync
DL2
dss_acbias
DL3
dss_data[23:0]
030-061
Figure 6-22. LCD Display in TFT Mode(1)(2)(3)(4)
(1) The pixel data bus depends on the use of 8-, 9-, 12-, 16-, 18-, or 24-bit per pixel data output pins.
(2) The pixel clock frequency is programmable.
(3) All timings not illustrated in the waveform are programmable by software, control signal polarity, and driven edge of dss_pclk.
(4) For more information, see the DSS chapter of the OMAP35xx ES2.0 Technical Reference Manual (TRM) [literature number TBD].
6.5.2.1.2 LCD Display in STN Mode
Table 6-29 assumes testing over the recommended operating conditions (see Figure 6-23).
Table 6-29. LCD Display Interface Switching Characteristics in STN Mode(3)(4)(5)
NO.
PARAMETER
1.15 V
1.0 V
UNIT
MIN
MAX
MIN
MAX
DL3 td(PCLKA-DATAV)
Delay time, dss_pclk active edge to dss_data bus
valid
–7
7
–7
7
ns
DL4 tc(PCLK)
DL5 tw(PCLK)
Cycle time(2), dss_pclk
22.7
0.45*P(1)
22.7
0.45*P(1)
ns
ns
Pulse duration, dss_pclk low or high
0.55*P(1)
0.55*P(1)
(1) P = dss_pclk period.
(2) The pixel clock frequency is software programmable via the pixel clock divider configuration from 1 to 255 division range in the
DISPC_DIVISOR register.
(3) The DSS in STN mode is used with 4 or 8 pins only; unused pixel data bits always remain low.
(4) The capacitive load is equivalent to 40 pF.
(5) For more information, see the DSS chapter of the OMAP35xx ES2.0 Technical Reference Manual (TRM) [literature number TBD].
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DL5
DL4
dss_pclk
dss_vsync
dss_hsync
dss_acbias
DL3
dss_data[23:0]
030-062
Figure 6-23. LCD Display in STN Mode(1)(2)(3)(4)(5)
(1) The pixel data bus depends on the use 4-, 8-, 12-, 16-, 18-, or 24-bit per pixel data output pins.
(2) All timings not illustrated in the waveform are programmable by software, control signal polarity, and driven edge of dss_pclk.
(3) dss_vsync width must be programmed to be as small as possible.
(4) The pixel clock frequency is programmable.
(5) For more information, see the DSS chapter of the OMAP35xx ES2.0 Technical Reference Manual (TRM) [literature number TBD].
6.5.2.2 LCD Display Support in RFBI Mode
Table 6-31 and Table 6-32 assume testing over the recommended operating conditions (see Figure 6-24
through Figure 6-26).
Table 6-30. LCD Timing Conditions – RFBI Mode
TIMING CONDITION PARAMETER
Input Conditions
VALUE
UNIT
tR
Input signal rise time
Input signal fall time
15
15
ns
ns
tF
Output Conditions
CLOAD
Output load capacitance
30
pF
Table 6-31. LCD Display Interface Timing Requirements in RFBI Mode
NO.
PARAMETER
1.15 V
1.0 V
UNIT
MIN
2.5
MAX
MIN
2.5
MAX
DR16 ts(DAV-RDH)
DR17 th(RDH-DAIV)
Setup time, rfbi_da[15:0] valid to rfbi_rd high
Hold time, rfbi_rd high to rfbi_da[15:0] invalid
2.5 + I(1)
2.5 + I(1)
2.5 + I(1)
2.5 + I(1)
ns
ns
2.5
2.5
(1) I = ((REOffTime – AccessTime) * (TimeParaGranularity + 1) * L4CLK
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Table 6-32. LCD Display Interface Switching Characteristics in RFBI Mode
NO.
PARAMETER
1.15 V
1.0 V
UNIT
MIN
MAX
MIN
MAX
DR2
tw(rfbi_wrH)
Pulse duration, rfbi_wr high
Pulse duration, rfbi_wr low
Delay time, rfbi_a0 transition to rfbi_wr low
Delay time, rfbi_a0 transition to rfbi_wr high
Delay time, rfbi_csx(10) low to rfbi_wr low
Delay time, rfbi_wr high to rfbi_csx(10) high
Delay time, rfbi_wr low to rfbi_da[15:0] valid
Delay time, rfbi_a0 high to rfbi_rd low
Delay time, rfbi_csx(10) low to rfbi_rd low
Pulse duration, rfbi_rd high
Pulse duration, rfbi_rd low
A(1)
B(2)
A(1)
B(2)
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DR3
tw(rfbi_wrL)
DR4
td(rfbi_a0-rfbi_wrL)
td(rfbi_a0-rfbi_wrH)
td(rfbi_csx-rfbi_wrL)
td(rfbi_wrH-rfbi_csH)
td(rfbi_wrL-rfbi_daV)
td(rfbi_a0H-rfbi_rdL)
td(rfbi_csL-rfbi_rdL)
tw(rfbi_rdH)
A(1) – 2.5
C(3) – 2.5
C(3) – 2.5
D(4) – 2.5
B(2) – 2.5
F(6) – 2.5
A(1) + 2.5
C(3) + 2.5
C(3) + 2.5
D(4) + 2.5
B(2) + 2.5
F(6) + 2.5
A(1) – 2.5
C(3) – 2.5
C(3) – 2.5
D(4) – 2.5
B(2) – 2.5
F(6) – 2.5
A(1) + 2.5
C(3) + 2.5
C(3) + 2.5
D(4) + 2.5
B(2) + 2.5
F(6) + 2.5
DR5
DR6
DR7
DR8
DR9
DR10
DR12
DR13
DR14
DR15
G(7) – 2.5 G(7) + 2.5 G(7) – 2.5 G(7) + 2.5
J(9)
E(5)
J(9)
E(5)
tw(rfbi_rdL)
td(rfbi_rdL-rfbi_csL)
td(rfbi_rdH-rfbi_csH)
tR(rfbi_wr)
Delay time, rfbi_rd low to rfbi_csx(10) low
Delay time, rfbi_rd high to rfbi_csx(10) high
Rise time, rfbi_wr
H(8) – 2.5
H(8) – 2.5
H(8) + 2.5
H(8) + 2.5
H(8) – 2.5
H(8) – 2.5
H(8) + 2.5
H(8) + 2.5
15
15
tF(rfbi_wr)
Fall time, rfbi_wr
15
15
tR(rfbi_a0)
Rise time, rfbi_a0
15
15
tF(rfbi_a0)
Fall time, rfbi_a0
15
15
tR(rfbi_csx)
Rise time, rfbi_csx
15
15
tF(rfbi_csx)
Fall time, rfbi_csx
15
15
tR(rfbi_da[15:0])
tF(rfbi_da[15:0])
tR(rfbi_rd)
Rise time, rfbi_da[15:0]
15
15
Fall time, rfbi_da[15:0]
15
15
Rise time, rfbi_rd
15
15
tF(rfbi_rd)
Fall time, rfbi_rd
15
15
(1) A = (WEOnTime) * (TimeParaGranularity + 1) * L4CLK
(2) B = (WEOffTime – WEOnTime) * (TimeParaGranularity + 1) * L4CLK
(3) C = (WEOnTime – CSOnTime) * (TimeParaGranularity + 1) * L4CLK
(4) D = (CSOffTime – WEOffTime) * (TimeParaGranularity + 1) * L4CLK
(5) E = (REOffTime – REOnTime) * (TimeParaGranularity + 1) * L4CLK
(6) F = REOnTime * (TimeParaGranularity + 1) * L4CLK
(7) G = (REOnTime – CSOnTime) * (TimeParaGranularity + 1) * L4CLK
(8) H = (CSOffTime – REOffTime) * (TimeParaGranularity + 1) * L4CLK
(9) J = (REOnTime) * L4CLK
(10) In RFBI_nCSx, x stands for 0 or 1.
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WECycleTime
CSOffTime
WEOnTime
CSOffTime
CSOnTime
DR4
DR5
rfbi_a0
rfbi_csx
rfbi_wr
DR6
DR7
DR1
DR3
DR2
DR8
rfbi_da[15:0]
rfbi_rd
DATA0
030-063
Figure 6-24. LCD Display Interface in RFBI Mode – Command / Data Write Mode(1)(2)
(1) In rfbi_csx, x is equal to 0 or 1.
(2) For more information, see the DSS chapter of the OMAP35xx ES2.0 Technical Reference Manual (TRM) [literature number TBD].
RECycleTime
CSOffTime
REOffTime
REOnTime
CSOnTime
DR9
DR10
rfbi_a0
DR14
DR15
rfbi_csx
DR11
DR12
DR13
rfbi_rd
DR16
DATA0
DR17
rfbi_da[15:0]
rfbi_wd
030-064
Figure 6-25. LCD Display Interface in RFBI Mode – Data Read Mode(1)(2)
(1) In rfbi_csx, x is equal to 0 or 1.
(2) For more information, see the DSS chapter of the OMAP35xx ES2.0 Technical Reference Manual (TRM) [literature number TBD].
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WECycleTime
CSOffTime
WEOnTime
CSOnTime
CSOffTime
DR4
DR5
rfbi_a0
DR6
DR7
rfbi_csx
rfbi_wr
DR1
DR3
DR2
DR8
rfbi_da[15:0]
rfbi_rd
DATA0
030-065
Figure 6-26. LCD Display Interface in RFBI Mode – Data Read-to-Write and Write-to-Read Modes(1)(2)
(1) In rfbi_csx, x is equal to 0 or 1.
(2) For more information, see the DSS chapter of the OMAP35xx ES2.0 Technical Reference Manual (TRM) [literature number TBD].
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6.6 Serial Communications Interfaces
6.6.1 Multichannel Buffered Serial Port (McBSP) Timing
There are five McBSP modules called McBSP1 through McBSP5. McBSP provides a full-duplex, direct
serial interface between the OMAP3515/03 device and other devices in a system such as other
application devices or codecs. It can accommodate a wide range of peripherals and clocked
frame-oriented protocols (I2S, PCM, and TDM) due to its high level of versatility.
The McBSP1-5 modules may support two types of data transfer at the system level:
•
The full-cycle mode, for which one clock period is used to transfer the data, generated on one edge
and captured on the same edge (one clock period later).
•
The half-cycle mode, for which one half clock period is used to transfer the data, generated on one
edge and captured on the opposite edge (one half clock period later). Note that a new data is
generated only every clock period, which secures the required hold time.
The interface clock (CLKX/CLKR) activation edge (data/frame sync capture and generation) has to be
configured accordingly with the external peripheral (activation edge capability) and the type of data
transfer required at the system level.
The OMAP3515/03 McBSP1-5 timing characteristics are described for both rising and falling activation
edges. McBSP1 supports:
•
•
6-pin mode: dx and dr as data pins; clkx, clkr, fsx, and fsr as control pins.
4-pin mode: dx and dr as data pins; clkx and fsx pins as control pins. The clkx and fsx pins are
internally looped back via software configuration, respectively, to the clkr and fsr internal signals for
data receive.
McBSP2, 3, 4, and 5 support only the 4-pin mode.
The following sections describe the timing characteristics for applications in normal mode (that is,
OMAP3515/03 McBSPx connected to one peripheral) and TDM applications in multipoint mode.
6.6.1.1 McBSP in Normal Mode
Table 6-33. McBSP Timing Conditions—Normal Mode
TIMING CONDITION PARAMETER
Input Conditions
VALUE
UNIT
tR
Input signal rise time
Input signal fall time
2
2
ns
ns
tF
Output Conditions
CLOAD
Output load capacitance
10
pF
Table 6-34. McBSP Output Clock Pulse Duration
NO.
PARAMETER
1.15 V
1.0 V
UNIT
MIN
MAX
MIN
MAX
tW(CLKH)
tW(CLKL)
tdc(CLK)
Typical pulse duration, mcbsp1_clkr / mcbspx_clkx
high(2)
0.5*P(1)
0.5*P(1)
ns
ns
ns
Typical pulse duration, mcbsp1_clkr / mcbspx_clkx
low(2)
Duty cycle error, mcbsp1_clkr / mcbspx_clkx(2)
0.5*P(1)
0.5*P(1)
–0.75
0.75
–0.75
0.75
(1) P = mcbsp1_clkr / mcbspx_clkx clock period.
(2) In mcbspx, x identifies the McBSP number: 1, 2, 3, 4, or 5.
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6.6.1.1.1 Receive Timing with Rising Edge as Activation Edge
Table 6-35 through Table 6-40 assume testing over the recommended operating conditions (see
Figure 6-27 through Figure 6-28).
Table 6-35. McBSP1, 2, and 3 (Sets #2 and #3) Timing Requirements – Rising Edge and Receive Mode(1)
NO.
PARAMETER
1.15 V
MIN MAX
1.0 V
MIN MAX
UNIT
B3
tsu(DRV-CLKAE)
Setup time, mcbspx_dr valid before mcbsp1_clkr /
mcbspx_clkx active edge
Master
Slave
3.5
3.7
1
7.7
7.9
1
ns
ns
ns
ns
ns
B4
th(CLKAE-DRV)
Hold time, mcbspx_dr valid after mcbsp1_clkr /
mcbspx_clkx active edge
Master
Slave
0.4
3.7
0.4
7.9
B5
B6
tsu(FSV-CLKAE)
th(CLKAE-FSV)
Setup time, mcbsp1_fsr / mcbspx_fsx valid before mcbsp1_clkr /
mcbspx_clkx active edge
Hold time, mcbsp1_fsr / mcbspx_fsx valid after mcbsp1_clkr /
mcbspx_clkx active edge
0.5
0.5
ns
Table 6-36. McBSP1, 2, and 3 (Sets #2 and #3) Switching Characteristics – Rising Edge and Receive
Mode(1)
NO.
PARAMETER
1.15 V
1.0 V
UNIT
MIN
0.7
MAX
MIN
0.7
MAX
B2
td(CLKAE-FSV)
Delay time, mcbsp1_clkr / mcbspx_clkx active edge to mcbsp1_fsr /
mcbspx_fsx valid
14.8
29.6
ns
(1) In mcbspx, x identifies the McBSP number: 1, 2, or 3. Note that for the McBSP3, these timings concern only Set #2 (multiplexing mode
on UART pins) and Set #3 (multiplexing mode on McBSP1 pins).
Table 6-37. McBSP4 (Set #1) Timing Requirements – Rising Edge and Receive Mode(1)
NO.
B3
PARAMETER
1.15 V
MIN MAX
1.0 V
MIN MAX
UNIT
tsu(DRV-CLKXAE)
Setup time, mcbspx_dr valid before
mcbspx_clkx active edge
Master
Slave
2.7
3.7
1
7.7
7.9
1
ns
ns
ns
ns
ns
ns
B4
th(CLKXAE-DRV)
Hold time, mcbspx_dr valid after mcbspx_clkx
active edge
Master
Slave
0.4
3.7
0.5
0.4
7.9
0.5
B5
B6
tsu(FSXV-CLKXAE)
th(CLKXAE-FSXV)
Setup time mcbspx_fsx valid before mcbspx_clkx active edge
Hold Time mcbspx_fsx valid after mcbspx_clkx active edge
Table 6-38. McBSP4 (Set #1) Switching Characteristics – Rising Edge and Receive Mode(1)
NO.
PARAMETER
1.15 V
1.0 V
UNIT
MIN
0.7
MAX
MIN MAX
B2
td(CLKXAE-FSXV)
Delay time, mcbspx_clkx active edge to mcbspx_fsx valid
16.6
0.7
33.1
ns
(1) In mcbspx, x identifies the McBSP number: 4. Note that for the McBSP4, these timings concern only Set #1: multiplexing mode by
default. The McBSP4 is also multiplexed on GPMC pins (Set #2): the corresponding timings are specified in Table 6-39 and Table 6-40.
Table 6-39. McBSP3 (Set #1), 4 (Set #2), and 5 Timing Requirements – Rising Edge and Receive Mode(1)
NO.
PARAMETER
1.15 V
MIN MAX
1.0 V
MIN MAX
UNIT
B3
tsu(DRV-CLKXAE)
Setup time, mcbspx_dr valid before
mcbspx_clkx active edge
Master
Slave
5.6
5.8
1
12
12.2
1
ns
ns
ns
ns
B4
th(CLKXAE-DRV)
Hold time, mcbspx_dr valid after mcbspx_clkx Master
active edge
Slave
0.4
0.4
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Table 6-39. McBSP3 (Set #1), 4 (Set #2), and 5 Timing Requirements – Rising Edge and Receive Mode(1)
(continued)
NO.
PARAMETER
1.15 V
MIN MAX
1.0 V
MIN MAX
UNIT
B5
B6
tsu(FSXV-CLKXAE)
th(CLKXAE-FSXV)
Setup time, mcbspx_fsx valid before mcbspx_clkx active edge
Hold time, mcbspx_fsx valid after mcbspx_clkx active edge
5.8
0.5
12.2
0.5
ns
ns
Table 6-40. McBSP3 (Set #1), 4 (Set #2), and 5 Switching Requirements – Rising Edge and Receive
Mode(1)
NO.
PARAMETER
1.15 V
1.0 V
MAX
44.4
UNIT
MIN
0.7
MAX
MIN
B2
td(CLKXAE-FSXV)
Delay time, mcbspx_clkx active edge to mcbspx_fsx valid
22.2
0.7
ns
(1) In mcbspx, x identifies the McBSP number: 3, 4, or 5. Note that for the McBSP3, these timings concern only Set #1: multiplexing mode
by default. The McBSP3 is also multiplexed on UART pins (Set #2) and on McBSP1 pins (Set #3): the corresponding timings are
specified in Table 6-37 and Table 6-38.
For the McBSP4, these timings concern only Set #2 (multiplexing mode on GPMC pins).
mcbspx_clkr
B2
B2
mcbspx_fsr
mcbspx_dr
B3
B4
D7
D6
D5
030-068
Figure 6-27. McBSP Rising Edge Receive Timing in Master Mode
mcbspx_clkr
mcbspx_fsr
mcbspx_dr
B5
B6
B3
B4
D7
D6
D5
030-069
Figure 6-28. McBSP Rising Edge Receive Timing in Slave Mode
6.6.1.1.2 Transmit Timing with Rising Edge as Activation Edge
Table 6-41 through Table 6-46 assume testing over the recommended operating conditions (see
Figure 6-29 and Figure 6-30).
Table 6-41. McBSP1, 2, and 3 (Sets #2 and #3) Timing Requirements – Rising Edge and Transmit Mode(1)
NO.
PARAMETER
1.15 V
MAX
1.0 V
UNIT
MIN
MIN
MAX
B5
B6
tsu(FSXV-CLKXAE)
th(CLKXAE-FSXV)
Setup time, mcbspx_fsx valid before mcbspx_clkx
active edge
3.7
7.9
ns
ns
Hold time, mcbspx_fsx valid after mcbspx_clkx active
edge
0.5
0.5
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Table 6-42. McBSP1, 2, and 3 (Sets #2 and #3) Switching Characteristics – Rising Edge and Transmit
Mode(1)
NO.
PARAMETER
1.15 V
1.0 V
UNIT
MIN
MAX
MIN
MAX
B2
B8
td(CLKXAE-FSXV)
td(CLKXAE-DXV)
Delay time, mcbspx_clkx active edge to mcbspx_fsx
valid
0.7
14.8
0.7
29.6
ns
Delay time, mcbspx_clkx active edge to Master
0.6
0.6
14.8
14.8
0.6
0.6
29.6
29.6
ns
ns
mcbspx_dx valid
Slave
(1) In mcbspx, x identifies the McBSP number: 1, 2, or 3. Note that for the McBSP3, these timings concern only Set #2 (multiplexing mode
on UART pins) and Set #3 (multiplexing mode on McBSP1 pins).
Table 6-43. McBSP4 (Set #1) Timing Requirements – Rising Edge and Transmit Mode(1)
NO.
PARAMETER
1.15 V
MAX
1.0 V
UNIT
MIN
MIN
MAX
B5
B6
tsu(FSXV-CLKXAE)
th(CLKXAE-FSXV)
Setup time, mcbspx_fsx valid before mcbspx_clkx
active edge
3.7
7.9
ns
ns
Hold time, mcbspx_fsx valid after mcbspx_clkx active
edge
0.5
0.5
Table 6-44. McBSP4 (Set #1) Switching Characteristics – Rising Edge and Transmit Mode(1)
NO.
PARAMETER
1.15 V
1.0 V
UNIT
MIN
MAX
MIN
MAX
B2
B8
td(CLKXAE-FSXV)
td(CLKXAE-DXV)
Delay time, mcbspx_clkx active edge to
mcbspx_fsx valid
0.7
16.6
0.7
33.1
ns
Delay time, mcbspx_clkx active edge
to mcbspx_dx valid
Master
Slave
0.6
0.6
16.6
17.3
0.6
0.6
33.1
33.1
ns
ns
(1) In mcbspx, x identifies the McBSP number: 4. Note that for the McBSP4, these timings concern only Set #1: multiplexing mode by
default. The McBSP4 is also multiplexed on GPMC pins (Set #2): the corresponding timings are specified in Table 6-45.
Table 6-45. McBSP3 (Set #1), 4 (Set #2), and 5 Timing Requirements – Rising Edge and Transmit Mode(1)
NO.
PARAMETER
1.15 V
MAX
1.0 V
UNIT
MIN
MIN
MAX
B5
B6
tsu(FSXV-CLKXAE)
th(CLKXAE-FSXV)
Setup time, mcbspx_fsx valid before mcbspx_clkx
active edge
5.8
12.2
ns
ns
Hold time, mcbspx_fsx valid after mcbspx_clkx active
edge
0.5
0.5
Table 6-46. McBSP 3 (Set #1), 4 (Set #2), and 5 Switching Requirements – Rising Edge and Transmit
Mode(1)
NO.
PARAMETER
1.15 V
1.0 V
UNIT
MIN
MAX
MIN
MAX
B2
B8
td(CLKXAE-FSXV)
td(CLKXAE-DXV)
Delay time, mcbspx_clkx active edge to mcbspx_fsx
valid
0.7
22.2
0.7
44.4
ns
Delay time, mcbspx_clkx active edge to Master
0.6
0.6
22.2
22.2
0.6
0.6
44.4
44.4
ns
ns
mcbspx_dx valid
Slave
(1) In mcbspx, x identifies the McBSP number: 3, 4 or 5. Note that for the McBSP3, these timings concern only Set #1: multiplexing mode
by default. The McBSP3 is also multiplexed on UART pins (Set #2) and on McBSP1 pins (Set #3): the corresponding timings are
specified in the table above. For the McBSP4, these timings concern only Set #2 (multiplexing mode on GPMC pins).
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mcbspx_clkx
B2
B2
B8
mcbspx_fsx
mcbspx_dx
D7
D6
D5
030-070
Figure 6-29. McBSP Rising Edge Transmit Timing in Master Mode
mcbspx_clkx
mcbspx_fsx
mcbspx_dx
B5
B6
B8
D7
D6
D5
030-071
Figure 6-30. McBSP Rising Edge Transmit Timing in Slave Mode
6.6.1.1.3 Receive Timing with Falling Edge as Activation Edge
Table 6-47 through Table 6-52 assume testing over the recommended operating conditions (see
Figure 6-31 and Figure 6-32).
Table 6-47. McBSP1, 2, and 3 (Sets #2 and #3) Timing Requirements – Falling Edge and Receive Mode(1)
NO.
PARAMETER
1.15 V
MAX
1.0 V
UNIT
MIN
3.5
3.7
1
MIN
7.7
7.9
1
MAX
B3
tsu(DRV-CLKAE)
Setup time, mcbspx_dr valid before
mcbsp1_clkr / mcbspx_clkx active edge
Master
Slave
ns
ns
ns
ns
ns
B4
th(CLKAE-DRV)
Hold time, mcbspx_dr valid after
mcbsp1_clkr / mcbspx_clkx active edge
Master
Slave
0.4
3.7
0.4
7.9
B5
B6
tsu(FSV-CLKAE)
th(CLKAE-FSV)
Setup time, mcbsp1_fsr / mcbspx_fsx valid before
mcbsp1_clkr /mcbspx_clkx active edge
Hold time, mcbsp1_fsr / mcbspx_fsx valid after
mcbsp1_clkr /mcbspx_clkx active edge
0.5
0.5
ns
Table 6-48. McBSP1, 2, and 3 (Sets #2 and #3) Switching Characteristics – Falling Edge and Receive
Mode(1)
NO.
PARAMETER
1.15 V
1.0 V
UNIT
MIN
MAX
MIN
MAX
B2
td(CLKAE-FSV)
Delay time, mcbsp1_clkr / mcbspx_clkx active edge to
mcbsp1_fsr / mcbspx_fsx valid
0.7
14.8
0.7
29.6
ns
(1) In mcbspx, x identifies the McBSP number: 1, 2, or 3. Note that for the McBSP3, these timings concern only Set #2 (multiplexing mode
on UART pins) and Set #3 (multiplexing mode on McBSP1 pins).
Table 6-49. McBSP4 (Set #1) Timing Requirements – Falling Edge and Receive Mode(1)
NO.
B3
PARAMETER
1.15 V
MAX
1.0 V
UNIT
MIN
2.7
3.7
1
MIN
7.7
7.9
1
MAX
tsu(DRV-CLKXAE)
Setup time, mcbspx_dr valid before
mcbspx_clkx active edge
Master
Slave
ns
ns
ns
ns
B4
th(CLKXAE-DRV)
Hold time, mcbspx_dr valid after
mcbspx_clkx active edge
Master
Slave
0.4
0.4
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Table 6-49. McBSP4 (Set #1) Timing Requirements – Falling Edge and Receive Mode(1) (continued)
NO.
PARAMETER
1.15 V
MAX
1.0 V
UNIT
MIN
MIN
MAX
B5
B6
tsu(FSXV-CLKXAE)
th(CLKXAE-FSXV)
Setup time mcbspx_fsx valid before mcbspx_clkx active
edge
3.7
7.9
ns
ns
Hold time mcbspx_fsx valid after mcbspx_clkx active
edge
0.5
0.5
Table 6-50. McBSP4 (Set #1) Switching Characteristics – Falling Edge and Receive Mode(1)
NO.
PARAMETER
1.15 V
MAX
16.6
1.0 V
UNIT
MIN
MIN
MAX
B2
td(CLKXAE-FSXV)
Delay time, mcbspx_clkx active edge to mcbspx_fsx valid
0.7
0.7
33.1
ns
(1) In mcbspx, x identifies the McBSP number: 4. Note that for the McBSP4, these timings concern only Set #1: multiplexing mode by
default. The McBSP4 is also multiplexed on GPMC pins (Set #2): the corresponding timings are specified in Table 6-51.
Table 6-51. McBSP3 (Set #1), 4 (Set #2), and 5 Timing Requirements – Falling Edge and Receive Mode(1)
NO.
PARAMETER
1.15 V
MAX
1.0 V
UNIT
MIN
5.6
5.8
1
MIN
12
MAX
B3
tsu(DRV-CLKXAE)
Setup time, mcbspx_dr valid before
mcbspx_clkx active edge
Master
Slave
ns
ns
ns
ns
ns
12.2
1
B4
th(CLKXAE-DRV)
Hold time, mcbspx_dr valid after mcbspx_clkx Master
active edge
Slave
0.4
5.8
0.4
12.2
B5
B6
tsu(FSXV-CLKXAE) Setup time, mcbspx_fsx valid before mcbspx_clkx active
edge
th(CLKXAE-FSXV)
Hold time, mcbspx_fsx valid after mcbspx_clkx active
edge
0.5
0.5
ns
Table 6-52. McBSP3 (Set #1), 4 (Set #2), and 5 Switching Requirements – Falling Edge and Receive
Mode(1)
NO.
PARAMETER
1.15 V
1.0 V
UNIT
MIN
MAX
MIN
MAX
B2
td(CLKXAE-FSXV)
Delay time, mcbspx_clkx active edge to mcbspx_fsx
valid
0.7
22.2
0.7
44.4
ns
(1) In mcbspx, x identifies the McBSP number: 3, 4, or 5. Note that for the McBSP3, these timings concern only Set #1: multiplexing mode
by default. The McBSP3 is also multiplexed on UART pins (Set #2) and on McBSP1 pins (Set #3): the corresponding timings are
specified in the table above. For the McBSP4, these timings concern only Set #2 (multiplexing mode on GPMC pins).
mcbspx_clkr
B2
B2
mcbspx_fsr
mcbspx_dr
B3
B4
D7
D6
D5
030-072
Figure 6-31. McBSP Falling Edge Receive Timing in Master Mode
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mcbspx_clkr
B5
B6
mcbspx_fsr
mcbspx_dr
B3
B4
D7
D6
D5
030-073
Figure 6-32. McBSP Falling Edge Receive Timing in Slave Mode
6.6.1.1.4 Transmit Timing with Falling Edge as Activation Edge
Table 6-53 through Table 6-58 assume testing over the recommended operating conditions (see
Figure 6-33 and Figure 6-34).
Table 6-53. McBSP1, 2, and 3 (Sets #2 and #3) Timing Requirements – Falling Edge and Transmit Mode(1)
NO.
PARAMETER
1.15 V
MAX
1.0 V
UNIT
MIN
MIN
MAX
B5
B6
tsu(FSXV-CLKXAE)
th(CLKXAE-FSXV)
Setup time, mcbspx_fsx valid before mcbspx_clkx
active edge
3.7
7.9
ns
ns
Hold time, mcbspx_fsx valid after mcbspx_clkx
active edge
0.5
0.5
Table 6-54. McBSP1, 2, and 3 (Sets #2 and #3) Switching Characteristics – Falling Edge and Transmit
Mode(1)
NO.
PARAMETER
1.15 V
1.0 V
UNIT
MIN
MAX
MIN
MAX
B2
B8
td(CLKXAE-FSXV)
td(CLKXAE-DXV)
Delay time, mcbspx_clkx active edge to mcbspx_fsx
valid
0.7
14.8
0.7
29.6
ns
Delay time, mcbspx_clkx active edge to Master
0.6
0.6
14.8
14.8
0.6
0.6
29.6
29.6
ns
ns
mcbspx_dx valid
Slave
(1) In mcbspx, x identifies the McBSP number: 1, 2, or 3. Note that for the McBSP3, these timings concern only Set #2 (multiplexing mode
on UART pins) and Set #3 (multiplexing mode on McBSP1 pins).
Table 6-55. McBSP4 (Set #1) Timing Requirements – Falling Edge and Transmit Mode(1)
NO.
PARAMETER
1.15 V
1.0 V
UNIT
MIN
MAX
MIN
MAX
B5
B6
tsu(FSXV-CLKXAE)
th(CLKXAE-FSXV)
Setup time, mcbspx_fsx valid before
mcbspx_clkx active edge
3.7
7.9
ns
ns
Hold time, mcbspx_fsx valid after mcbspx_clkx
active edge
0.5
0.5
Table 6-56. McBSP4 (Set #1) Switching Characteristics – Falling Edge and Transmit Mode(1)
NO.
PARAMETER
1.15 V
1.0 V
UNIT
MIN
MAX
MIN
MAX
B2
B8
td(CLKXAE-FSXV)
td(CLKXAE-DXV)
Delay time, mcbspx_clkx active edge to mcbspx_fsx
valid
0.7
16.6
0.7
33.1
ns
Delay time, mcbspx_clkx active edge to
mcbspx_dx valid
Master
Slave
0.6
0.6
16.6
17.3
0.6
0.6
33.1
33.1
ns
ns
(1) In mcbspx, x identifies the McBSP number: 4. Note that for the McBSP4, these timings concern only Set #1: multiplexing mode by
default. The McBSP4 is also multiplexed on GPMC pins (Set #2): the corresponding timings are specified in Table 6-57.
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Table 6-57. McBSP3 (Set #1), 4 (Set #2), and 5 Timing Requirements – Falling Edge and Transmit Mode(1)
NO.
PARAMETER
1.15 V
1.0 V
UNIT
MIN
MAX
MIN
MAX
B5
B6
tsu(FSXV-CLKXAE)
th(CLKXAE-FSXV)
Setup time, mcbspx_fsx valid before mcbspx_clkx
active edge
5.8
12.2
ns
ns
Hold time, mcbspx_fsx valid after mcbspx_clkx
active edge
0.5
0.5
Table 6-58. McBSP3 (Set #1), 4 (Set #2), and 5 Switching Requirements – Falling Edge and Transmit
Mode(1)
NO.
PARAMETER
1.15 V
MIN
1.0 V
MAX
UNIT
MAX
22.2
22.2
22.2
MIN
0.7
0.6
0.6
B2
B8
td(CLKXAE-FSXV)
td(CLKXAE-DXV)
Delay time, mcbspx_clkx active edge to mcbspx_fsx valid
0.7
0.6
0.6
44.4
44.4
44.4
ns
ns
ns
Delay time, mcbspx_clkx active edge to
mcbspx_dx valid
Master
Slave
(1) In mcbspx, x identifies the McBSP number: 3, 4, or 5. Note that for the McBSP3, these timings concern only Set #1: multiplexing mode
by default. The McBSP3 is also multiplexed on UART pins (Set #2) and on McBSP1 pins (Set #3): the corresponding timings are
specified in Table 6-57. For the McBSP4, these timings concern only Set #2 (multiplexing mode on GPMC pins).
mcbspx_clkx
B2
B2
mcbspx_fsx
mcbspx_dx
B8
D7
D6
D5
030-074
Figure 6-33. McBSP Falling Edge Transmit Timing in Master Mode
mcbspx_clkx
mcbspx_fsx
mcbspx_dx
B5
B6
B8
D7
D6
D5
030-075
Figure 6-34. McBSP Falling Edge Transmit Timing in Slave Mode
6.6.1.2 McBSP in TDM—Multipoint Mode (McBSP3)
For TDM application in multipoint mode, OMAP3515/03 is considered as a slave. Table 6-60 and
Table 6-61 assume testing over the operating conditions and electrical characteristic conditions described
below.
Table 6-59. McBSP3 Timing Conditions—TDM in Multipoint Mode
TIMING CONDITION PARAMETER
VALUE
UNIT
MIN
MAX
Input Conditions
tR
tF
Input signal rising time
Input signal falling time
1.0
1.0
8.5
8.5
ns
ns
Output Conditions
CLOAD Output Load Capacitance
40
pF
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Table 6-60. McBSP3 Timing Requirements—TDM in Multipoint Mode(2)
NO.
PARAMETER
1.15 V
1.0 V
UNIT
MIN
MAX
MIN
MAX
tW(CLKH)
Cycle Time, mcbsp3_clkx
162.8
162.8
ns
ns
ns
ns
ns
tW(CLKH)
Typical Pulse duration, mcbsp3_clkx high
Typical Pulse duration, mcbsp3_clkx low
Duty cycle error, mcbsp3_clkx
0.5*P(1)
0.5*P(1)
0.5*P(1)
0.5*P(1)
tW(CLKL)
tdc(CLK)
–8.14
8.14
–8.14
8.14
B3(3)
tsu(DRV-CLKAE)
Setup time, mcbsp3_dr valid before
mcbsp3_clkx active edge
9
9
B4(3)
B5(3)
B6(3)
th(CLKAE-DRV)
tsu(FSV-CLKAE)
th(CLKAE-FSV)
Hold time, mcbsp3_dr valid after mcbsp3_clkx
active edge
2.4
9
2.4
9
ns
ns
ns
Setup time, mcbsp3_fsx valid before
mcbsp3_clkx active edge
Hold time, mcbsp3_fsx valid after
mcbsp3_clkx active edge
2.4
2.4
(1) P = mcbsp3_clkx period in ns
(2) For McBSP3, these timings concern only Set #3 (multiplexing mode in McBSP1 pins).
(3) See Section 6.6.1.1, McBSP in Normal Mode for corresponding figures.
Table 6-61. McBSP3 Switching Characteristics—TDM in Multipoint Mode(1)
NO.
B8(2)
PARAMETER
1.15 V
1.0 V
UNIT
MIN
MAX
MIN
MAX
td(CLKXAE-DXV) Delay time, mcbsp3_clkx active edge to
mcbsp3_dx valid
0.6
16.8
0.6
29.6
ns
(1) For McBSP3, these timings concern only Set #3 (multiplexing mode in McBSP1 pins).
(2) See Section 6.6.1.1, McBSP in Normal Mode for corresponding figures.
6.6.2 Multichannel Serial Port Interface (McSPI) Timing
The multichannel SPI is a master/slave synchronous serial bus. The McSPI1 module supports up to four
peripherals and the others (McSPI2, McSPI3, and McSPI4) support up to two peripherals. The following
timings are applicable to the different configurations of McSPI in master/slave mode for any McSPI and
any channel (n).
6.6.2.1 McSPI in Slave Mode
Table 6-62 and Table 6-63 assume testing over the recommended operating conditions (see Figure 6-35).
Table 6-62. McSPI Interface Timing Requirements – Slave Mode(1)(4)
NO.
PARAMETER
1.15 V
MAX
1.0 V
UNIT
MIN
MIN
MAX
SS0 tc(CLK)
Cycle time, mcspix_clk
41.7
83.3
ns
ns
ns
SS1 tw(CLK)
Pulse duration, mcspix_clk high or low
0.45*P(3) 0.55*P(3) 0.45*P(3)
0.55*P(3)
SS2 tsu(SIMOV-CLKAE)
Setup time, mcspix_simo valid before mcspix_clk
active edge
4.2
9.5
SS3 th(SIMOV-CLKAE)
SS4 tsu(CS0V-CLKFE)
SS5 th(CS0I-CLKLE)
Hold time, mcspix_simo valid after mcspix_clk active
edge
4.6
9.9
ns
ns
ns
Setup time, mcspix_cs0 valid before mcspix_clk first
edge
13.8
13.8
28.6
28.6
Hold time, mcspix_cs0 invalid after mcspix_clk last
edge
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Table 6-63. McSPI Interface Switching Requirements(2)(4)(5)(6)
NO.
PARAMETER
1.15 V
1.0 V
UNIT
MIN
MAX
MIN
MAX
SS6 td(CLKAE-SOMIV)
SS7 td(CS0AE-SOMIV)
Delay time, mcspix_clk active edge to mcspix_somi
shifted
1.8
15.9
3.2
31.7
ns
ns
Delay time, mcspix_cs0 active edge to Modes 0 and 2
mcspix_somi shifted
15.9
31.7
(1) The input timing requirements are given by considering a rise time and a fall time of 4 ns.
(2) The capacitive load is equivalent to 20 pF.
(3) P = mcspix_clk clock period
(4) In mcspix, x is equal to 1, 2, 3, or 4.
(5) The polarity of mcspix_clk and the active edge (rising or falling) on which mcspix_simo is driven and mcspix_somi is latched is all
software configurable.
(6) This timing applies to all configurations regardless of mcspix_clk polarity and which clock edges are used to drive output data and
capture input data.
Mode 0 & 2
mcspix_cs0(EPOL=1)
SS0
SS4
SS1
SS5
mcspix_clk(POL=0)
mcspix_clk(POL=1)
SS0
SS1
SS2
SS3
Bit n-1
SS7
Bit n-1
mcspix_simo
mcspix_somi
Bit n-2
SS6
Bit n-3
Bit n-4
Bit n-4
Bit 0
Bit n-2
Bit n-3
Bit 0
Mode 1 & 3
mcspix_cs0(EPOL=1)
mcspix_clk(POL=0)
mcspix_clk(POL=1)
SS0
SS1
SS0
SS1
SS4
SS5
SS3
SS2
Bit n-1
SS6
Bit n-1
mcspix_simo
mcspix_somi
Bit n-2
Bit n-2
Bit n-3
Bit 1
Bit 0
Bit 0
Bit n-3
Bit 1
030-076
Figure 6-35. McSPI Interface – Transmit and Receive in Slave Mode(1)(2)
(1) The active clock edge (rising or falling) on which mcspi_somi is driven and mcspi_simo data is latched is software configurable with the
bit MSPI_CHCONFx[0] = PHA and the bit MSPI_CHCONFx[1] = POL.
(2) The polarity of mcspix_csi is software configurable with the bit MSPI_CHCONFx[6] = EPOL In mcspix, x is equal to 1, 2, 3, or 4.
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6.6.2.2 McSPI in Master Mode
Table 6-64 and Table 6-65 assume testing over the recommended operating conditions (see Figure 6-36).
Table 6-64. McSPI1, 2, and 4 Interface Timing Requirements – Master Mode(1)(4)
NO.
PARAMETER
1.15 V
MAX
1.0 V
UNIT
MIN
MIN
MAX
SM2 tsu(SOMIV-CLKAE)
SM3 th(SOMIV-CLKAE)
Setup time, mcspix_somi valid before mcspix_clk
active edge
1.1
1.5
ns
ns
Hold time, mcspix_somi valid after mcspix_clk active
edge
1.9
2.8
Table 6-65. McSPI1, 2, and 4 Interface Switching Characteristics – Master Mode(2)(4)(5)
NO.
PARAMETER
1.15 V
MAX
1.0 V
MAX
UNIT
MIN
MIN
SM0
SM1
tc(CLK)
tw(CLK)
Cycle time, mcspix_clk
20.8
41.7
ns
ns
Pulse duration, mcspix_clk high or low
0.45*P(3) 0.55*P(3) 0.45*P( 0.55*P(3)
3)
SM4
SM5
td(CLKAE-SIMOV)
td(CSnA-CLKFE)
Delay time, mcspix_clk active edge to mcspix_simo
shifted
–2.1
5
–2.1
11.3
ns
ns
ns
ns
ns
ns
Delay time, mcspix_csi active to
mcspix_clk first edge
Modes 1
and 3
A(7) – 3.1
B(8) – 3.1
B(8) – 3.1
A(7) – 3.1
A(7)
4.4
–
Modes 0
and 2
B(8)
4.4
–
SM6
SM7
td(CLKLE-CSnI)
Delay time, mcspix_clk last edge to
mcspix_csi inactive
Modes 1
and 3
B(8)
4.4
–
Modes 0
and 2
A(7)
4.4
–
td(CSnAE-SIMOV)
Delay time, mcspix_csi active edge to Modes 0
mcspix_simo shifted and 2
5.0
11.3
(1) The input timing requirements are given by considering a rise time and a fall time of 4 ns.
(2) Timings are given for a maximum load capacitance of 20 pF for spix_csn signals, 30 pF for spix_clk and spix_simo signals with x = 1 or
2, and 20 pF for spi4_clk and spi4_simo signals.
(3) P = mcspix_clk clock period
(4) In mcspix, x is equal to 1, 2, or 4. In mcspix_csn, n is equal to 0, 1, 2, or 3 for x equal to 1, n is equal to 0 or 1 for x equal to 2 and 4.
(5) The polarity of mcspix_clk and the active edge (rising or falling) on which mcspix_simo is driven and mcspix_somi is latched is all
software configurable.
(6) This timing applies to all configurations regardless of mcspix_clk polarity and which clock edges are used to drive output data and
capture input data.
(7) Case P = 20.8 ns, A = (TCS+0.5)*P(3) (TCS is a bit field of MSPI_CHCONFx[26:25] register). Case P > 20.8 ns, A = TCS*P(3) (TCS is a
bitfield of MSPI_CHCONFx[26:25] register). For more information, see the McSPI chapter of the OMAP35xx ES2.0 Technical Reference
Manual (TRM) [literature number TBD].
(8) B = TCS*P (TCS is a bit field of MSPI_CHCONFx[26:25] register). For more information, see the McSPI chapter of the OMAP35xx
ES2.0 Technical Reference Manual (TRM) [literature number TBD].
Table 6-66 and Table 6-67 assume testing over the recommended operating conditions (see Figure 6-36).
Table 6-66. McSPI 3 Interface Timing Requirements – Master Mode(1)(4)
NO.
PARAMETER
1.15 V
MAX
1.0 V
UNIT
MIN
MIN
MAX
SM2 tsu(SOMIV-CLKAE)
SM3 th(SOMIV-CLKAE)
Setup time, mcspi3_somi valid before
mcspi3_clk active edge
1.5
4.3
ns
ns
Hold time, mcspi3_somi valid after mcspi3_clk
active edge
2.8
5.9
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Table 6-67. McSPI3 Interface Switching Requirements – Master Mode(2)(4)(5)
NO.
PARAMETER
1.15 V
1.0 V
UNIT
MIN
MAX
MIN
83.3
MAX
SM0 tc(CLK)
Cycle time, mcspix_clk
41.7
ns
ns
ns
SM1 tw(CLK)
Pulse duration, mcspix_clk high or low
0.45*P(3)
0.55*P(3)
11.3
0.45*P(3)
0.55*P(3)
23.6
SM4 td(CLKAE-SIMOV)
Delay time, mcspix_clk active edge to
mcspix_simo shifted
–2.1
–5.3
SM5 td(CSnA-CLKFE)
SM6 td(CLKLE-CSnI)
SM7 td(CSnAE-SIMOV)
Delay time, mcspix_csi active Modes 1
–4.4 + A(6)
–4.4 + B(7)
–4.4 + A(6)
–4.4 + B(7)
–10.1 + A(6)
–10.1 + B(7)
–10.1 + A(6)
–10.1 + B(7)
ns
ns
ns
ns
ns
to mcspix_clk first edge
and 3
Modes 0
and 2
Delay time, mcspix_clk last
edge to mcspix_csi inactive
Modes 1
and 3
Modes 0
and 2
Delay time, mcspix_csi active Modes 0
edge to mcspix_simo shifted and 2
11.3
23.6
(1) The input timing requirements are given by considering a rise time and a fall time of 4 ns.
(2) The capacitive load is equivalent to 20 pF.
(3) P = mcspi3_clk clock period
(4) In mcspi3_csn, n is equal to 0 or 1. The polarity of mcspi3_clk and the active edge (rising or falling) on which mcspi3_simo is driven and
mcspi3_somi is latched is all software configurable.
(5) This timing applies to all configurations regardless of McSPI3_CLK polarity and which clock edges are used to drive output data and
capture input data.
(6) Case P = 20.8 ns, A = (TCS + 0.5)*P(3) (TCS is a bit field of MSPI_CHCONFx[26:25] register). Case P > 20.8 ns, A = TCS*P(3) (TCS is
a bit field of MSPI_CHCONFx[26:25] register). For more information, see the McSPI chapter of the OMAP35xx ES2.0 Technical
Reference Manual (TRM) [literature number TBD].
(7) B = TCS*P (TCS is a bit field of MSPI_CHCONFx[26:25] register). For more information, see the McSPI chapter of the OMAP35xx
ES2.0 Technical Reference Manual (TRM) [literature number TBD].
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Mode 0 & 2
mcspix_csn(EPOL=1)
mcspix_clk(POL=0)
mcspix_clk(POL=1)
mcspix_simo
SM0
SM1
SM5
SM6
SM0
SM1
SM7
SM4
Bit n-2
Bit n-1
SM2
Bit n-3
Bit n-4
Bit n-4
Bit 0
SM3
Bit n-1
mcspix_somi
Bit n-2
Bit n-3
Bit 0
Mode 1 & 3
mcspix_csn(EPOL=1)
mcspix_clk(POL=0)
SM0
SM1
SM0
SM1
SM5
SM6
mcspix_clk(POL=1)
mcspix_simo
SM4
Bit n-1
SM2
Bit n-2
Bit n-2
Bit n-3
Bit 1
Bit 0
SM3
mcspix_somi
Bit n-1
Bit n-3
Bit 1
Bit 0
030-077
Figure 6-36. McSPI Interface – Transmit and Receive in Master Mode(1)(2)(3)
(1) The active clock edge (rising or falling) on which mcspix_simo is driven and mcspi_somi data is latched is software configurable with the
bit MSPI_CHCONFx[0] = PHA and the bit MSPI_CHCONFx[1] = POL.
(2) The polarity of mcspix_csi is software configurable with the bit MSPI_CHCONFx[6] = EPOL.
(3) In mcspix, x is equal to 1. In mcspix_csn, n is equal to 0, 1, 2, or 3.
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6.6.3 Multiport Full-Speed Universal Serial Bus (USB) Interface
The OMAP3515/03 processor provides three USB ports working in full- and low-speed data transactions
(up to 12Mbit/s).
Connected to either a serial link controller (TLL modes) or a serial PHY (PHY interface modes) it supports:
•
•
•
6-pin (Tx: Dat/Se0 or Tx: Dp/Dm) unidirectional mode
4-pin bidirectional mode
3-pin bidirectional mode
6.6.3.1 Multiport Full-Speed Universal Serial Bus (USB) – Unidirectional Standard 6-pin Mode
Table 6-69 and Table 6-70 assume testing over the recommended operating conditions (see Figure 6-37).
Table 6-68. Low-/Full-Speed USB Timing Conditions – Unidirectional Standard 6-pin Mode
TIMING CONDITION PARAMETER
Input Conditions
VALUE
UNIT
tR
Input signal rise time
Input signal fall time
2.0
2.0
ns
ns
tF
Output Conditions
CLOAD
Output load capacitance
15.0
pF
Table 6-69. Low-/Full-Speed USB Timing Requirements – Unidirectional Standard 6-pin Mode
NO.
PARAMETER
1.15 V
MIN MAX
1.0 V
UNIT
MIN
MAX
FSU1
FSU2
FSU3
FSU4
td(Vp,Vm)
td(Vp,Vm)
td(RCVU0)
td(RCVU1)
Time duration, mmx_rxdp and mmx_rxdm low together during
transition
14.0
14.0
ns
ns
ns
ns
Time duration, mmx_rxdp and mmx_rxdm high together during
transition
8.0
8.0
14.0
8.0
Time duration, mmx_rrxcv undefine during a single end 0
(mmx_rxdp and mmx_rxdm low together)
14.0
8.0
Time duration, mmx_rxrcv undefine during a single end 1
(mmx_rxdp and mmx_rxdm high together)
(1) In mmx, x is equal to 0, 1, or 2.
Table 6-70. Low-/Full-Speed USB Switching Characteristics – Unidirectional Standard 6-pin Mode
NO.
PARAMETER
1.15 V
MIN
1.0 V
UNIT
MAX
84.8
84.8
1.5
MIN
81.8
81.8
MAX
84.8
84.8
1.5
FSU5
FSU6
FSU7
FSU8
FSU9
td(TXENL-DATV)
td(TXENL-SE0V)
ts(DAT-SE0)
td(DATI-TXENH)
td(SE0I-TXENH)
tR(do)
Delay time, mmx_txen_n low to mmx_txdat valid
Delay time, mmx_txen_n low to mmx_txse0 valid
Skew between mmx_txdat and mmx_txse0 transition
Delay time, mmx_txdat invalid to mmx_txen_n high
Delay time, mmx_txse0 invalid to mmx_txen_n high
Rise time, mmx_txen_n
81.8
81.8
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
81.8
81.8
81.8
81.8
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
tF(do)
Fall time, mmx_txen_n
tR(do)
Rise time, mmx_txdat
tF(do)
Fall time, mmx_txdat
tR(do)
Rise time, mmx_txse0
tF(do)
Fall time, mmx_txse0
(1) In mmx, x is equal to 0, 1, or 2.
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Transmit
mmx_txen_n
Receive
FSU5
FSU6
FSU8
mmx_txdat
mmx_txse0
mmx_rxdp
mmx_rxdm
mmx_rxrcv
FSU7
FSU9
FSU1
FSU1
FSU3
FSU2
FSU2
FSU4
030-080
In mmx, x is equal to 0, 1, or 2.
Figure 6-37. Low-/Full-Speed USB – Unidirectional Standard 6-pin Mode
6.6.3.2 Multiport Full-Speed Universal Serial Bus (USB) – Bidirectional Standard 4-pin Mode
Table 6-72 and Table 6-73 assume testing over the recommended operating conditions (see Figure 6-38).
Table 6-71. Low-/Full-Speed USB Timing Conditions – Bidirectional Standard 4-pin Mode
TIMING CONDITION PARAMETER
VALUE
UNIT
Input Conditions
tR
Input signal rise time
Input signal fall time
2.0
2.0
ns
ns
tF
Output Conditions
CLOAD
Output load capacitance
15.0
pF
Table 6-72. Low-/Full-Speed USB Timing Requirements – Bidirectional Standard 4-pin Mode
NO.
PARAMETER
1.15 V
MAX
1.0 V
UNIT
MIN
MIN
MAX
FSU10 td(DAT,SE0)
FSU11 td(DAT,SE0)
FSU12 td(RCVU0)
FSU13 td(RCVU1)
Time duration, mmx_txdat and mmx_txse0 low together
during transition
14.0
14.0
ns
ns
ns
ns
Time duration, mmx_txdat and mmx_txse0 high together
during transition
8.0
8.0
14.0
8.0
Time duration, mmx_rrxcv undefine during a single end 0
(mmx_txdat and mmx_txse0 low together)
14.0
8.0
Time duration, mmx_rxrcv undefine during a single end 1
(mmx_txdat and mmx_txse0 high together)
(1) In mmx, x is equal to 0, 1, or 2.
Table 6-73. Low-/Full-Speed USB Switching Characteristics – Bidirectional Standard 4-pin Mode
NO.
PARAMETER
1.15 V
MAX
1.0 V
UNIT
MIN
81.8
81.8
MIN
81.8
81.8
MAX
84.8
84.8
1.5
FSU14
FSU15
FSU16
td(TXENL-DATV)
td(TXENL-SE0V)
ts(DAT-SE0)
Delay time, mmx_txen_n low to mmx_txdat valid
Delay time, mmx_txen_n low to mmx_txse0 valid
84.8
84.8
1.5
ns
ns
ns
Skew between mmx_txdat and mmx_txse0
transition
FSU17
td(DATV-TXENH)
Delay time, mmx_txdat invalid before mmx_txen_n
high
81.8
81.8
ns
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Table 6-73. Low-/Full-Speed USB Switching Characteristics – Bidirectional Standard 4-pin Mode
(continued)
NO.
PARAMETER
1.15 V
MAX
1.0 V
UNIT
MIN
MIN
MAX
FSU18
td(SE0V-TXENH)
Delay time, mmx_txse0 invalid before mmx_txen_n
high
81.8
81.8
ns
tR(txen)
tF(txen)
tR(dat)
tF(dat)
tR(se0)
tF(se0)
Rise time, mmx_txen_n
Fall time, mmx_txen_n
Rise time, mmx_txdat
Fall time, mmx_txdat
Rise time, mmx_txse0
Fall time, mmx_txse0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
ns
ns
ns
ns
ns
ns
(1) In mmx, x is equal to 0, 1, or 2.
Transmit
FSU16
mmx_txen_n
mmx_txdat
mmx_txse0
mmx_rxrcv
Receive
FSU10
FSU14
FSU15
FSU17
FSU18
FSU11
FSU11
FSU13
FSU10
FSU12
030-081
In mmx, x is equal to 0, 1, or 2.
Figure 6-38. Low-/Full-Speed USB – Bidirectional Standard 4-pin Mode
6.6.3.3 Multiport Full-Speed Universal Serial Bus (USB) – Bidirectional Standard 3-pin Mode
Table 6-75 and Table 6-76 assume testing over the recommended operating conditions below (see
Figure 6-39).
Table 6-74. Low-/Full-Speed USB Timing Conditions – Bidirectional Standard 3-pin Mode
TIMING CONDITION PARAMETER
VALUE
UNIT
Input Conditions
tR
Input signal rise time
Input signal fall time
2.0
2.0
ns
ns
tF
Output Conditions
CLOAD
Output load capacitance
15.0
pF
Table 6-75. Low-/Full-Speed USB Timing Requirements – Bidirectional Standard 3-pin Mode
NO.
PARAMETER
1.15 V
MAX
1.0 V
UNIT
MIN
MIN
MAX
FSU19
FSU20
td(DAT,SE0)
td(DAT,SE0)
Time duration, mmx_txdat and mmx_txse0 low together
during transition
14.0
14.0
ns
ns
Time duration, mmx_tsdat and mmx_txse0 high
together during transition
8.0
8.0
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(1) In mmx, x is equal to 0, 1, or 2.
Table 6-76. Low-/Full-Speed USB Switching Characteristics – Bidirectional Standard 3-pin Mode
NO.
PARAMETER
1.15 V
1.0 V
UNIT
MIN
81.8
81.8
MAX
84.8
84.8
1.5
MIN
81.8
81.8
MAX
84.8
84.8
1.5
FSU21
FSU22
FSU23
td(TXENL-DATV)
td(TXENL-SE0V)
ts(DAT-SE0)
Delay time, mmx_txen_n low to mmx_txdat valid
Delay time, mmx_txen_n low to mmx_txse0 valid
ns
ns
ns
Skew between mmx_txdat and mmx_txse0
transition
FSU24
FSU25
td(DATI-TXENH)
td(SE0I-TXENH)
Delay time, mmx_txdat invalid to mmx_txen_n
high
81.8
81.8
81.8
81.8
ns
ns
Delay time, mmx_txse0 invalid to mmx_txen_n
high
tR(do)
tF(do)
tR(do)
tF(do)
tR(do)
tF(do)
Rise time, mmx_txen_n
Fall time, mmx_txen_n
Rise time, mmx_txdat
Fall time, mmx_txdat
Rise time, mmx_txse0
Fall time, mmx_txse0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
ns
ns
ns
ns
ns
ns
(1) In mmx, x is equal to 0, 1, or 2.
Transmit
mmx_txen_n
mmx_txdat
mmx_txse0
Receive
FSU21
FSU22
FSU24
FSU19
FSU20
FSU20
FSU23
FSU25
FSU19
030-082
In mmx, x is equal to 0, 1, or 2.
Figure 6-39. Low-/Full-Speed USB – Bidirectional Standard 3-pin Mode
6.6.3.4 Multiport Full-Speed Universal Serial Bus (USB) – Unidirectional TLL 6-pin Mode
Table 6-78 and Table 6-79 assume testing over the recommended operating conditions (see Figure 6-40).
Table 6-77. Low-/Full-Speed USB Timing Conditions – Unidirectional TLL 6-pin Mode
TIMING CONDITION PARAMETER
VALUE
UNIT
Input Conditions
tR
Input signal rise time
Input signal fall time
2
2
ns
ns
tF
Output Conditions
CLOAD
Output load capacitance
15
pF
Table 6-78. Low-/Full-Speed USB Timing Requirements – Unidirectional TLL 6-pin Mode
NO.
PARAMETER
1.15 V
1.0 V
UNIT
MIN
MAX
MIN
MAX
FSUT1
FSUT2
td(SE0,DAT)
td(SE0,DAT)
Time duration, mmx_txse0 and mmx_txdat low
together during transition
14
14
ns
ns
Time duration, mmx_txse0 and mmx_txdat high
together during transition
8
8
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(1) In mmx, x is equal to 0, 1, or 2.
Table 6-79. Low-/Full-Speed USB Switching Characteristics – Unidirectional TLL 6-pin Mode
NO.
PARAMETER
1.15 V
1.0 V
UNIT
MIN
81.8
81.8
81.8
81.8
MAX
84.8
84.8
MIN
81.8
81.8
81.8
81.8
MAX
84.8
84.8
FSUT3
FSUT4
FSUT5
FSUT6
FSUT7
td(TXENH-DPV)
td(TXENH-DMV)
td(DPI-TXENL)
td(DMI-TXENL)
ts(DP-DM)
Delay time, mmx_txen_n high to mmx_rxdp valid
Delay time, mmx_txen_n high to mmx_rxdm valid
Delay time, mmx_rxdp invalid mmx_txen_n low
Delay time, mmx_rxdm invalid mmx_txen_n low
ns
ns
ns
ns
ns
Skew between mmx_rxdp and mmx_rxdm
transition
1.5
1.5
1.5
1.5
FSUT8
ts(DP,DM-RCV)
Skew between mmx_rxdp, mmx_rxdm, and
mmx_rxrcv transition
ns
tR(rxrcv)
tF(rxrcv)
tR(dp)
Rise time, mmx_rxrcv
Fall time, mmx_rxrcv
Rise time, mmx_rxdp
Fall time, mmx_rxdp
Rise time, mmx_rxdm
Fall time, mmx_rxdm
4
4
4
4
4
4
4
4
4
4
4
4
ns
ns
ns
ns
ns
ns
tF(dp)
tR(dm)
tF(dm)
1. In mmx, x is equal to 0, 1, or 2.
mmx_txen_n
mmx_txdat
mmx_txse0
mmx_rxdp
mmx_rxdm
mmx_rxrcv
Transmit
Receive
FSUT1
FSUT2
FSUT1
FSUT2
FSUT3
FSUT4
FSUT5
FSUT6
FSUT7
FSUT8
030-083
In mmx, x is equal to 0, 1, or 2.
Figure 6-40. Low-/Full-Speed USB – Unidirectional TLL 6-pin Mode
6.6.3.5 Multiport Full-Speed Universal Serial Bus (USB) – Bidirectional TLL 4-pin Mode
Table 6-81 and Table 6-82 assume testing over the recommended operating conditions (see Figure 6-41).
Table 6-80. Low-/Full-Speed USB Timing Conditions – Bidirectional TLL 4-pin Mode
TIMING CONDITION PARAMETER
VALUE
UNIT
Input Conditions
tR
Input signal rise time
Input signal fall time
2
2
ns
ns
tF
Output Conditions
CLOAD
Output load capacitance
15
pF
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Table 6-81. Low-/Full-Speed USB Timing Requirements – Bidirectional TLL 4-pin Mode
NO.
PARAMETER
1.15 V
1.0 V
UNIT
MIN
MAX
MIN
MAX
FSUT9
td(DAT,SE0)
Time duration, mmx_txdat and mmx_txse0 low
together during transition
14
14
ns
ns
FSUT10 td(DAT,SE0)
Time duration, mmx_tsdat and mmx_txse0 high
together during transition
8
8
(1) In mmx, x is equal to 0, 1, or 2.
Table 6-82. Low-/Full-Speed USB Switching Characteristics – Bidirectional TLL 4-pin Mode
NO.
PARAMETER
1.15 V
MAX
1.0 V
UNIT
MIN
81.8
81.8
MIN
81.8
81.8
MAX
84.8
84.8
1.5
FSUT11 td(TXENL-DATV)
FSUT12 td(TXENL-SE0V)
FSUT13 ts(DAT-SE0)
Delay time, mmx_txen_n active to mmx_txdat valid
Delay time, mmx_txen_n active to mmx_txse0 valid
84.8
84.8
1.5
ns
ns
ns
Skew between mmx_txdat and mmx_txse0
transition
FSUT14 ts(DP,DM-RCV)
Skew between mmx_rxdp, mmx_rxdm, and
mmx_rxrcv transition
1.5
1.5
ns
FSUT15 td(DATI-TXENL)
Delay time, mmx_txse0 invalid to mmx_txen_n Low
Delay time, mmx_txdat invalid to mmx_txen_n Low
Rise time, mmx_rxrcv
81.8
81.8
81.8
81.8
ns
ns
ns
ns
ns
ns
ns
ns
FSUT16 td(SE0I-TXENL)
tR(rcv)
tF(rcv)
tR(dat)
tF(dat)
tR(se0)
tF(se0)
4
4
4
4
4
4
4
4
4
4
4
4
Fall time, mmx_rxrcv
Rise time, mmx_txdat
Fall time, mmx_txdat
Rise time, mmx_txse0
Fall time, mmx_txse0
(1) In mmx, x is equal to 0, 1, or 2.
mmx_txen_n
Transmit
Receive
FSUT9
FSUT11
FSUT15
FSUT16
FSUT10
mmx_txdat
mmx_txse0
mmx_rxrcv
FSUT12
FSUT13
FSUT9
FSUT10
FSUT14
030-084
In mmx, x is equal to 0, 1, or 2.
Figure 6-41. Low-/Full-Speed USB – Bidirectional TLL 4-pin Mode
6.6.3.6 Multiport Full-Speed Universal Serial Bus (USB) – Bidirectional TLL 3-pin Mode
Table 6-84 and Table 6-85 assume testing over the recommended operating conditions (see Figure 6-42).
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Table 6-83. Low-/Full-Speed USB Timing Conditions – Bidirectional TLL 3-pin Mode
TIMING CONDITION PARAMETER
VALUE
UNIT
Input Conditions
tR
Input signal rise time
Input signal fall time
2
2
ns
ns
tF
Output Conditions
CLOAD
Output load capacitance
15
pF
Table 6-84. Low-/Full-Speed USB Timing Requirements – Bidirectional TLL 3-pin Mode
NO.
PARAMETER
1.15 V
1.0 V
UNIT
MIN
MAX
MIN
MAX
FSUT17 td(DAT,SE0) Time duration, mmx_txdat and mmx_txse0 low
together during transition
14
14
ns
ns
FSUT18 td(DAT,SE0) Time duration, mmx_tsdat and mmx_txse0 high
together during transition
8
8
(1) In mmx, x is equal to 0, 1, or 2.
Table 6-85. Low-/Full-Speed USB Switching Characteristics – Bidirectional TLL 3-pin Mode
NO.
PARAMETER
1.15 V
1.0 V
UNIT
MIN
81.8
81.8
MAX
84.8
84.8
1.5
MIN
81.8
81.8
MAX
84.8
84.8
1.5
FSUT19 td(TXENH-DATV)
FSUT20 td(TXENH-SE0V)
FSUT21 ts(DAT-SE0)
Delay time, mmx_txen_n high to mmx_txdat valid
Delay time, mmx_txen_n high to mmx_txse0 valid
ns
ns
ns
Skew between mmx_txdat and mmx_txse0
transition
FSUT22 td(DATI-TXENL)
Delay time, mmx_txdat invalid mmx_txen_n low
Delay time, mmx_txse0 invalid mmx_txen_n low
Rise time, mmx_txdat
81.8
81.8
81.8
81.8
ns
ns
ns
ns
ns
ns
ns
ns
FSUT23 td(SE0I-TXENL)
tR(dat)
tF(dat)
tR(se0)
tF(se0)
tR(do)
tF(do)
4
4
4
4
4
4
4
4
4
4
4
4
Fall time, mmx_txdat
Rise time, mmx_txse0
Fall time, mmx_txse0
Rise time, mmx_txse0
Fall time, mmx_txse0
(1) In mmx, x is equal to 0, 1, or 2.
Receive
FSUT17
mmx_txen_n
Transmit
FSUT19
FSUT22
FSUT23
FSUT18
mmx_txdat
mmx_txse0
FSUT20
FSUT21
FSUT17
FSUT18
030-085
In mmx, x is equal to 0, 1, or 2.
Figure 6-42. Low-/Full-Speed USB – Bidirectional TLL 3-pin Mode
6.6.4 Multiport High-Speed Universal Serial Bus (USB) Timing
In addition to the full-speed USB controller, a high-speed (HS) USB OTG controller is instantiated inside
OMAP3515/03. It allows high-speed transactions (up to 480 Mbit/s) on the USB ports 0, 1, 2, and 3.
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•
•
Port 0:
12-bit slave mode (SDR)
Port 1 and port 2:
–
–
–
–
12-bit master mode (SDR)
12-bit TLL master mode (SDR)
8-bit TLL master mode (DDR)
•
Port 3:
–
–
12-bit TLL master mode (SDR)
8-bit TLL master mode (DDR)
6.6.4.1 High-Speed Universal Serial Bus (USB) on Port 0 – 12-bit Slave Mode
Table 6-87 and Table 6-88 assume testing over the recommended operating conditions (see Figure 6-43).
Table 6-86. High-Speed USB Timing Conditions – 12-bit Slave Mode
TIMING CONDITION PARAMETER
VALUE
UNIT
Input Conditions
tr
Input Signal Rising Time
Input Signal Falling Time
2.00
2.00
ns
ns
tf
Output Conditions
Cload
Output Load Capacitance
3.50
pF
Table 6-87. High-Speed USB Timing Requirements – 12-bit Slave Mode(3)
NO.
PARAMETER
1.15 V
UNIT
MIN
MAX
60.03
500.00
HSU0
HSU3
HSU4
fp(CLK)
hsusb0_clk clock frequency(1)(2)
Cycle Jitter(2), hsusb0_clk
MHz
ps
tj(CLK)
ts(DIRV-CLKH)
ts(NXTV-CLKH)
th(CLKH-DIRIV)
th(CLKH-NXT/IV)
ts(DATAV-CLKH)
th(CLKH-DATIV)
Setup time, hsusb0_dir valid before hsusb0_clk rising edge
Setup time, hsusb0_nxt valid before hsusb0_clk rising edge
Hold time, hsusb0_dir valid after hsusb0_clk rising edge
Hold time, hsusb0_nxt valid after hsusb0_clk rising edge
Setup time, hsusb0_data[0:7] valid before hsusb0_clk rising edge
Hold time, hsusb0_data[0:7] valid after hsusb0_clk rising edge
6.7
6.7
0.0
0.0
6.7
0.0
ns
ns
ns
ns
HSU5
HSU6
ns
ns
(1) Related with the input maximum frequency supported by the I/F module.
(2) Maximum cycle jitter supported by clk input clock.
(3) The timing requirements are assured for the cycle jitter error condition specified.
Table 6-88. High-Speed USB Switching Characteristics – 12-bit Slave Mode
NO.
PARAMETER
1.15 V
UNIT
MIN
0.5
MAX
HSU1 td(clkL-STPV)
td(clkL-STPIV)
HSU2 td(clkL-DV)
td(clkL-DIV)
Delay time, hsusb0_clk high to output usb0_stp valid
Delay time, hsusb0_clk high to output usb0_stp invalid
Delay time, hsusb0_clk high to output hsusb0_data[0:7] valid
Delay time, hsusb0_clk high to output hsusb0_data[0:7] invalid
Rising time, output signals
9.0
ns
ns
ns
ns
ns
ns
9.0
0.5
tr(do)
2.0
2.0
tf(do)
Falling time, output signals
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HSU0
hsusb0_clk
hsusb0_stp
HSU1
HSU1
HSU3
HSU4
HSU6
hsusb0_dir_&_nxt
hsusb0_data[7:0]
HSU5
HSU2
HSU2
Data_OUT
Data_IN
030-086
Figure 6-43. High-Speed USB – 12-bit Slave Mode
6.6.4.2 High-Speed Universal Serial Bus (USB) on Ports 1 and 2 – 12-bit Master Mode
Table 6-90 and Table 6-91 assume testing over the recommended operating conditions (see Figure 6-44).
Table 6-89. High-Speed USB Timing Conditions – 12-bit Master Mode
TIMING CONDITION PARAMETER
VALUE
UNIT
Input Conditions
tR
Input signal rise time
Input signal fall time
2
2
ns
ns
tF
Output Conditions
CLOAD
Output load capacitance
3
pF
Table 6-90. High-Speed USB Timing Requirements – 12-bit Master Mode(1)
NO.
PARAMETER
1.15 V
UNIT
MIN
9.3
9.3
0.2
0.2
9.3
0.2
MAX
HSU3 ts(DIRV-CLKH)
ts(NXTV-CLKH)
HSU4 th(CLKH-DIRIV)
th(CLKH-NXT/IV)
Setup time, hsusbx_dir valid before hsusbx_clk rising edge
Setup time, hsusbx_nxt valid before hsusbx_clk rising edge
Hold time, hsusbx_dir valid after hsusbx_clk rising edge
Hold time, hsusbx_nxt valid after hsusbx_clk rising edge
Setup time, hsusbx_data[0:7] valid before hsusbx_clk rising edge
Hold time, hsusbx_data[0:7] valid after hsusbx_clk rising edge
ns
ns
ns
ns
ns
ns
HSU5 ts(DATAV-CLKH)
HSU6 th(CLKH-DATIV)
(1) In hsusbx, x is equal to 1 or 2.
Table 6-91. High-Speed USB Switching Characteristics – 12-bit Master Mode(1)
N O.
PARAMETER
1.15 V
UNIT
MIN
MAX
60
HSU0
HSU1
HSU2
fp(CLK)
hsusbx_clk clock frequency
Jitter standard deviation(2), hsusbx_clk
MHz
ps
tj(CLK)
200
13
td(clkL-STPV)
td(clkL-STPIV)
td(clkL-DV)
td(clkL-DIV)
tR(do)
Delay time, hsusbx_clk high to output hsusbx_stp valid
Delay time, hsusbx_clk high to output hsusbx_stp invalid
Delay time, hsusbx_clk high to output hsusbx_data[0:7] valid
Delay time, hsusbx_clk high to output hsusbx_data[0:7] invalid
Rise time, output signals
ns
2
2
ns
13
ns
ns
2
2
ns
tF(do)
Fall time, output signals
ns
(1) In hsusbx, x is equal to 1 or 2.
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(2) The jitter probability density can be approximated by a Gaussian function.
HSU0
hsusbx_clk
HSU1
HSU1
hsusbx_stp
hsusbx_dir_&_nxt
hsusbx_data[7:0]
HSU3
HSU4
HSU5
HSU2
HSU2
HSU6
Data_OUT
Data_IN
030-087
In hsusbx, x is equal to 1 or 2.
Figure 6-44. High-Speed USB – 12-bit Master Mode
6.6.4.3 High-Speed Universal Serial Bus (USB) on Ports 1, 2, and 3 – 12-bit TLL Master Mode
Table 6-93 and Table 6-94 assume testing over the recommended operating conditions (see Figure 6-45).
Table 6-92. High-Speed USB Timing Conditions – 12-bit TLL Master Mode
TIMING CONDITION PARAMETER
Input Conditions
VALUE
UNIT
tR
Input signal rise time
Input signal fall time
2
2
ns
ns
tF
Output Conditions
CLOAD
Output load capacitance
3
pF
Table 6-93. High-Speed USB Timing Requirements – 12-bit TLL Master Mode(1)
NO.
PARAMETER
1.15 V
UNIT
MIN
6
MAX
HSU2 ts(STPV-CLKH)
HSU3 ts(CLKH-STPIV)
HSU4 ts(DATAV-CLKH)
HSU5 th(CLKH-DATIV)
Setup time, hsusbx_tll_stp valid before hsusbx_tll_clk rising edge
Hold time, hsusbx_tll_stp valid after hsusbx_tll_clk rising edge
Setup time, hsusbx_tll_data[7:0] valid before hsusbx_tll_clk rising edge
Hold time, hsusbx_tll_data[7:0] valid after hsusbx_tll_clk rising edge
ns
ns
ns
ns
0
6
0
(1) In hsusbx, x is equal to 1, 2, or 3.
Table 6-94. High-Speed USB Switching Characteristics – 12-bit TLL Master Mode(1)
NO.
PARAMETER
1.15 V
UNIT
MIN
MAX
60
HSU0 fp(CLK)
tj(CLK)
hsusbx_tll_clk clock frequency
Jitter standard deviation(2), hsusbx_tll_clk
MHz
ps
200
9
HSU6 td(CLKL-DIRV)
td(CLKL-DIRIV)
Delay time, hsusbx_tll_clk high to output hsusbx_tll_dir valid
Delay time, hsusbx_tll_clk high to output hsusbx_tll_dir invalid
Delay time, hsusbx_tll_clk high to output hsusbx_tll_nxt valid
Delay time, hsusbx_tll_clk high to output hsusbx_tll_nxt invalid
Delay time, hsusbx_tll_clk high to output hsusbx_tll_data[7:0] valid
Delay time, hsusbx_tll_clk high to output hsusbx_tll_data[7:0] invalid
ns
0
0
0
ns
td(CLKL-NXTV)
9
9
ns
td(CLKL-NXTIV)
HSU7 td(CLKL-DV)
td(CLKL-DIV)
ns
ns
ns
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Table 6-94. High-Speed USB Switching Characteristics – 12-bit TLL Master Mode(1) (continued)
NO.
PARAMETER
1.15 V
UNIT
MIN
MAX
tR(do)
tF(do)
Rise time, output signals
Fall time, output signals
2
2
ns
ns
(1) In hsusbx, x is equal to 1, 2, or 3.
(2) The jitter probability density can be approximated by a Gaussian function.
HSU0
hsusbx_tll_clk
HSU3
HSU2
hsusbx_tll_stp
HSU6
HSU6
HSU7
hsusbx_tll_dir_&_nxt
HSU4
HSU7
HSU5
Data_IN
Data_OUT
hsusbx_tll_data[7:0]
030-088
In hsusbx, x is equal to 1, 2, or 3.
Figure 6-45. High-Speed USB – 12-bit TLL Master Mode
6.6.4.4 High-Speed Universal Serial Bus (USB) on Ports 1, 2, and 3 – 8-bit TLL Master Mode
Table 6-96 and Table 6-97 assume testing over the recommended operating conditions (see Figure 6-46).
Table 6-95. High-Speed USB Timing Conditions – 8-bit TLL Master Mode
TIMING CONDITION PARAMETER
Input Conditions
VALUE
UNIT
tR
Input signal rise time
Input signal fall time
2
2
ns
ns
tF
Output Conditions
CLOAD
Output load capacitance
3
pF
Table 6-96. High-Speed USB Timing Requirements – 8-bit TLL Master Mode(1)
NO.
PARAMETER
1.15 V
UNIT
MIN
6
MAX
HSU2 ts(STPV-CLKH)
HSU3 ts(CLKH-STPIV)
HSU4 ts(DATAV-CLKH)
HSU5 th(CLKH-DATIV)
Setup time, hsusbx_tll_stp valid before hsusbx_tll_clk rising edge
Hold time, hsusbx_tll_stp valid after hsusbx_tll_clk rising edge
Setup time, hsusbx_tll_data[3:0] valid before hsusbx_tll_clk rising edge
Hold time, hsusbx_tll_data[3:0] valid after hsusbx_tll_clk rising edge
ns
ns
ns
ns
0
3
–0.8
(1) In hsusbx, x is equal to 1, 2, or 3.
Table 6-97. High-Speed USB Switching Characteristics – 8-bit TLL Master Mode(1)
NO.
PARAMETER
1.15 V
UNIT
MIN
MAX
60
HSU0
fp(CLK)
tj(CLK)
hsusbx_tll_clk clock frequency
Jitter standard deviation(2), hsusbx_tll_clk
MHz
ps
200
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Table 6-97. High-Speed USB Switching Characteristics – 8-bit TLL Master Mode(1) (continued)
NO.
PARAMETER
1.15 V
UNIT
MIN
MAX
52.4%
9
HSU1
HSU6
tj(CLK)
Duty cycle, hsusbx_tll_clk pulse duration (low and high)
Delay time, hsusbx_tll_clk high to output hsusbx_tll_dir valid
Delay time, hsusbx_tll_clk high to output hsusbx_tll_dir invalid
Delay time, hsusbx_tll_clk high to output hsusbx_tll_nxt valid
Delay time, hsusbx_tll_clk high to output hsusbx_tll_nxt invalid
Delay time, hsusbx_tll_clk high to output hsusbx_tll_data[3:0] valid
Delay time, hsusbx_tll_clk high to output hsusbx_tll_data[3:0] invalid
Rise time, output signals
47.6%
td(CLKL-DIRV)
td(CLKL-DIRIV)
td(CLKL-NXTV)
td(CLKL-NXTIV)
td(CLKL-DV)
td(CLKL-DIV)
tR(do)
ns
ns
ns
ns
ns
ns
ns
ns
0
0
0
9
4
HSU7
HSU8
2
2
tF(do)
Fall time, output signals
(1) In hsusbx, x is equal to 1, 2, or 3.
(2) The jitter probability density can be approximated by a Gaussian function.
HSU0
HSU1
HSU1
hsusbx_tll_clk
HSU3
HSU2
hsusbx_tll_stp
HSU6
HSU6
hsusbx_tll_dir_&_nxt
HSU5
HSU4
HSU5
HSU8
HSU7
HSU4
HSU7
Data_IN
Data_IN_(n+1)
Data_IN_(n+2)
Data_OUT
Data_OUT_(n+1)
hsusbx_tll_data[3:0]
030-089
In hsusbx, x is equal to 1, 2, or 3.
Figure 6-46. High-Speed USB – 8-bit TLL Master Mode
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6.6.5 I2C Interface
The multimaster I2C peripheral provides an interface between two or more devices via an I2C serial bus.
The I2C controller supports the multimaster mode which allows more than one device capable of
controlling the bus to be connected to it. Each I2C device is recognized by a unique address and can
operate as either transmitter or receiver, according to the function of the device. In addition to being a
transmitter or receiver, a device connected to the I2C bus can also be considered as master or slave when
performing data transfers. This data transfer is carried out via two serial bidirectional wires:
•
•
An SDA data line
An SCL clock line
The following sections illustrate the data transfer is in master or slave configuration with 7-bit addressing
format. The I2C interface is compliant with Philips I2C specification version 2.1. It supports standard mode
(up to 100K bits/s), fast mode (up to 400K bits/s) and high-speed mode (up to 3.4Mb/s) .
6.6.5.1 I2C Standard/Fast-Speed Mode
Table 6-98. I2C Standard/Fast-Speed Mode Timings
NO.
PARAMETER(4)
Standard Mode
Fast Mode
UNIT
MIN
MAX
MIN
MAX
fSCL
Clock Frequency, i2cX_scl
100
400
kHz
µs
µs
ns
I1
I2
I3
I4
I5
tw(SCLH)
Pulse Duration, i2cX_scl high
4
0.6
1.3
100(1)
0(2)
tw(SCLL)
Pulse Duration, i2cX_scl low
4.7
250
0(2)
4.7
tsu(SDAV-SCLH)
th(SCLH–SDAV)
tsu(SDAL-SCLH)
Setup time, i2cX_sda valid before i2cX_scl active level
Hold time, i2cX_sda valid after i2cX_scl active level
3.45(3)
0.9(3)
µs
µs
Setup time, i2cX_scl high after i2cX_sda low (for a
START(5) condition or a repeated START condition)
0.6
I6
I7
I8
th(SCLH–SDAH)
th(SCLH–RSTART)
tw(SDAH)
Hold time, i2cX_sda low level after i2cX_scl high level
(STOP condition)
4
4
0.6
0.6
1.3
µs
µs
µs
Hold time, i2cX_sda low level after i2cX_scl high level (for
a repeated START condition)
Pulse duration, i2cX_sda high between STOP and START
conditions
4.7
tR(SCL)
tF(SCL)
tR(SDA)
tF(SDA)
CB
Rise time, i2cX_scl
1000
300
300
300
300
300
400
ns
ns
ns
ns
pF
Fall time, i2cX_scl
Rise time, i2cX_sda
Fall time, i2cX_sda
1000
300
Capacitive load for each bus line
400
(1) A fast-mode I2C-bus device can be used in a standard-mode I2C-bus system, but the requirement tsu(SDAV-SCLH) ≥ 250 ns must then be
met. This is automatically the case if the device does not stretch the low period of the i2cx_scl. If such a device does stretch the low
period of the i2cx_scl, it must output the next data bit to the i2cx_sda line tr(SDA) max + tsu(SDAV-SCLH) = 1000 + 250 = 1250 ns (according
to the standard-mode I2C-bus specification) before the i2cx_scl line is released.
(2) The device provides (via the I2C bus) a hold time of at least 300 ns for the i2cx_sda signal (refer to the fall and rise time of i2cx_scl) to
bridge the undefined region of the falling edge of i2cx_scl.
(3) The maximum th(SCLH-SDA) has only to be met if the device does not stretch the low period of the i2cx_scl signal.
(4) In i2cX, X is equal to 1, 2, 3, or 4. Note that I2C4 is master transmitter only.
(5) After this time, the first clock is generated.
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START REPEAT
START
START
STOP
i2cX_sda
I2
I5
I6
I8
I7
I6
I1
I3
I4
i2cX_scl
030-093
Figure 6-47. I2C – Standard/Fast Mode
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6.6.5.2 I2C High-Speed Mode
Table 6-99. I2C HighSpeed Mode Timings(3)(4)
NO.
PARAMETER
CB = 100 pF MAX
CB = 400 pF MAX
UNIT
MIN
MAX
MIN
MAX
fSCL
Clock frequency, i2cX_scl
Pulse duration, i2cX_scl high
Pulse duration, i2cX_scl low
3.4
1.7
MHz
µs
I1
I2
I3
tw(SCLH)
tw(SCLL)
60(1)
160(1)
10
120(1)
320(1)
10
µs
tsu(SDAV-SCLH)
Setup time, i2cX_sda valid before i2cX_scl
active level
ns
I4
I5
th(SCLH–SDAV)
tsu(SDAL-SCLH)
Hold time, i2cX_sda valid after i2cX_scl active
level
0(4)
70
0(4)
150
µs
µs
Setup time, i2cX_scl high after i2cX_sda low
(for a START(2) condition or a repeated START
condition)
160
160
I6
I7
th(SCLH–SDAH)
Hold time, i2cX_sda low level after i2cX_scl high
level (STOP condition)
160
160
160
160
µs
th(SCLH–RSTART)
Hold time, i2cX_sda low level after i2cX_scl high
level (for a repeated START condition)
ns
tR(SCL)
tR(SCL)
Rise time, i2cX_scl
40
80
80
ns
ns
Rise time, i2cX_scl after a repeated START
condition and after a bit acknowledge
160
tF(SCL)
tR(SDA)
tF(SDA)
Fall time, i2cX_scl
Rise time, i2cX_sda
Fall time, i2cX_sda
40
80
80
80
ns
ns
ns
160
160
(1) HS-mode master devices generate a serial clock signal with a high to low ratio of 1 to 2. tw(SCLL) > 2 × tw(SCLH)
.
(2) After this time, the first clock is generated.
(3) In i2cX, X is equal to 1, 2, 3, or 4. Note that I2C4 is master transmitter only.
(4) The device provides (via the I2C bus) a hold time of at least 300 ns for the i2cx_sda signal (refer to the fall and rise time of i2cx_scl) to
bridge the undefined region of the falling edge of i2cx_scl.
START REPEAT
STOP
I7
i2cX_sda
i2cX_scl
I5
I6
I1
I2
I3
I4
030-094
Figure 6-48. I2C – High-Speed Mode(1)(2)(3)
(1) HS-mode master devices generate a serial clock signal with a high-to-low ratio of 1 to 2. tw(SCLL) > 2 x tw(SCLH)
(2) In i2cX, X is equal to 1, 2, 3, or 4. Note that I2C4 is master transmitter only.
(3) After this time, the first clock is generated.
.
Table 6-100. Correspondence Standard vs. TI Timing References
TI-OMAP
STANDARD-I2C
S/F Mode
FSCL
HS Mode
FSCLH
fSCL
I1
I2
I3
I4
I5
I6
tw(SCLH)
THIGH
THIGH
tw(SCLL)
TLOW
TLOW
tsu(SDAV-SCLH)
th(SCLH-SDAV)
tsu(SDAL-SCLH)
th(SCLH-SDAH)
TSU;DAT
TSU;DAT
TSU;STA
THD;STA
TSU;DAT
TSU;DAT
TSU;STA
THD;STA
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Table 6-100. Correspondence Standard vs. TI Timing References (continued)
TI-OMAP
STANDARD-I2C
S/F Mode
TSU;STO
TBUF
HS Mode
I7
I8
th(SCLH-RSTART)
tw(SDAH)
TSU;STO
6.6.6 HDQ / 1-Wire Interfaces
This module is intended to work with both the HDQ and the 1-Wire protocols. The protocols use a single
wire to communicate between the master and the slave. The protocols employ an asynchronous return to
1 mechanism where, after any command, the line is pulled high.
6.6.6.1 HDQ Protocol
Table 6-101 and Table 6-102 assume testing over the recommended operating conditions (see
Figure 6-49 through Figure 6-52).
Table 6-101. HDQ Timing Requirements
PARAMETER
tCYCD
DESCRIPTION
Bit window
MIN
MAX
UNIT
253
µs
tHW1
Reads 1
68
tHW0
Reads 0
180
tRSPS
Command to host respond time(1)
(1) Defined by software.
Table 6-102. HDQ Switching Characteristics
PARAMETER
DESCRIPTION
MIN
TYP
193
63
MAX
UNIT
tB
Break timing
Break recovery
Bit window
µs
tBR
tCYCH
tDW1
tDW0
253
1.3
Sends1 (write)
Sends0 (write)
101
tB
tBR
HDQ
030-095
Figure 6-49. HDQ Break (Reset) Timing
tCYCH
tHW0
tHW1
HDQ
030-096
Figure 6-50. HDQ Read Bit Timing (Data)
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tCYCD
tDW0
tDW1
HDQ
030-097
Figure 6-51. HDQ Write Bit Timing (Command/Address or Data)
Command _byte_written
0_(LSB)
Data_byte_received
tRSPS
1
Break
1
6
7_(MSB)
0_(LSB)
6
HDQ
030-098
Figure 6-52. HDQ Communication Timing
6.6.6.2 1-Wire Protocol
Table 6-103 and Table 6-104 assume testing over the recommended operating conditions (see
Figure 6-53 through Figure 6-55).
Table 6-103. 1-Wire Timing Requirements
PARAMETER
tPDH
DESCRIPTION
MIN
MAX
UNIT
Presence pulse delay high
Presence pulse delay low
Read bit-zero time
68
µs
tPDL
68 – tPDH
tRDV + tREL
102
Table 6-104. 1-Wire Switching Characteristics
PARAMETER
tRSTL
DESCRIPTION
MIN
TYP
484
484
102
1.3
MAX
UNIT
Reset time low
µs
tRSTH
Reset time high
Write bit cycle time
Write bit-one time
Write bit-zero time
Recovery time
tSLOT
tLOW1
tLOW0
101
134
13
tREC
tLOWR
Read bit strobe time
tRSTH
tPDL
tRTSL
tPDH
1-WIRE
030-099
Figure 6-53. 1-Wire Break (Reset) Timing
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tSLOT_and_ tREC
tRDV_and_ tREL
tLOWR
1-WIRE
030-100
Figure 6-54. 1-Wire Read Bit Timing (Data)
tSLOT_and_tREC
tLOW0
1-WIRE
tLOW1
030-101
Figure 6-55. 1-Wire Write Bit Timing (Command/Address or Data)
6.6.7 UART IrDA Interface
The IrDA module can operate in three different modes:
•
•
•
Slow infrared (SIR) (≤115.2 Kbits/s)
Medium infrared (MIR) (0.576 Mbits/s and 1.152 Mbits/s)
Fast infrared (FIR) (4 Mbits/s)
For more information about this interface, see the UART/IrDA chapter in the OMAP35xx ES2.0 Technical
Reference Manual (TRM) [literature number TBD].
Pulse duration
90%
90%
50%
50%
10%
10%
tr
tf
030-118
Figure 6-56. UART IrDA Pulse Parameters
6.6.7.1 IrDA—Receive Mode
Table 6-105. UART IrDA—Signaling Rate and Pulse Duration—Receive Mode
ELECTRICAL PULSE DURATION
SIGNALING RATE
UNIT
MIN
NOMINAL
SIR
MAX
2.4 Kbit/s
9.6 Kbit/s
19.2 Kbit/s
1.41
1.41
1.41
78.1
19.5
9.75
88.55
22.13
11.07
µs
µs
µs
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Table 6-105. UART IrDA—Signaling Rate and Pulse Duration—Receive Mode
(continued)
ELECTRICAL PULSE DURATION
SIGNALING RATE
UNIT
MIN
1.41
1.41
1.41
NOMINAL
4.87
3.25
1.62
MIR
MAX
5.96
4.34
2.23
38.4 Kbit/s
57.6 Kbit/s
115.2 Kbit/s
µs
µs
µs
0.576 Mbit/s
1.152 Mbit/s
297.2
149.6
416
518.8
258.4
ns
ns
208
FIR
4.0 Mbit/s (Single pulse)
4.0 Mbit/s (Double pulse)
67
125
164
289
ns
ns
190
250
Table 6-106. UART IrDA—Rise and Fall Time—Receive
Mode
PARAMETER
MAX
UNIT
tR
tF
Rising time,
uart3_rx_irrx
200
ns
Falling time,
uart3_rx_irrx
200
ns
6.6.7.2 IrDA—Transmit Mode
Table 6-107. UART IrDA—Signaling Rate and Pulse Duration—Transmit Mode
SIGNALING RATE
ELECTRICAL PULSE DURATION
UNIT
MIN
NOMINAL
SIR
MAX
2.4 Kbit/s
9.6 Kbit/s
78.1
19.5
9.75
4.87
3.25
1.62
78.1
19.5
9.75
4.87
3.25
1.62
MIR
78.1
19.5
9.75
4.87
3.25
1.62
µs
µs
µs
µs
µs
µs
19.2 Kbit/s
38.4 Kbit/s
57.6 Kbit/s
115.2 Kbit/s
0.576 Mbit/s
1.152 Mbit/s
414
206
416
419
211
ns
ns
208
FIR
4.0 Mbit/s (Single pulse)
4.0 Mbit/s (Double pulse)
123
248
125
128
253
ns
ns
250
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6.7 Removable Media Interfaces
6.7.1 High-Speed Multimedia Memory Card (MMC) and Secure
Digital IO Card (SDIO) Timing
The MMC/SDIO host controller provides an interface to high-speed and
standard MMC, SD memory cards, or SDIO cards. The application interface is
responsible for managing transaction semantics. The MMC/SDIO host
controller deals with MMC/SDIO protocol at transmission level, packing data,
adding CRC, start/end bit, and checking for syntactical correctness.
There are three MMC interfaces on the OMAP3515/03:
•
MMC/SD/SDIO Interface 1:
–
–
1.8 V/3 V support
8 bits
•
MMC/SD/SDIO Interface 2:
–
–
–
1.8 V support
8 bits
4 bits with external transceiver allowing to support 3 V peripherals.
Transceiver direction control signals are multiplexed with the upper four
data bits.
•
MMC/SD/SDIO Interface 3:
–
–
1.8 V support
8 bits
6.7.1.1 MMC/SD/SDIO in SD Identification Mode
Table 6-109 and Table 6-110 assume testing over the recommended operating conditions and electrical
characteristic conditions.
Table 6-108. MMC/SD/SDIO Timing Conditions – SD Identification Mode
TIMING CONDITION PARAMETER
VALUE
UNIT
SD Identification Mode
Input Conditions
tR
Input signal rise time
Input signal fall time
10
10
ns
ns
tF
Output Conditions
CLOAD
Output load capacitance
40
pF
Table 6-109. MMC/SD/SDIO Timing Requirements – SD Identification Mode(1)(2)(3)
NO.
PARAMETER
1.15 V
1.0 V
UNIT
MIN
MAX
MIN
MAX
SD Identification Mode
MMC/SD/SDIO Interface 1 (1.8 V IO)
HSSD3/SD3 tsu(CMDV-CLKIH)
Setup time, mmc1_cmd valid before
mmc1_clk rising clock edge
1198.4
1249.2
1198.4
1249.2
ns
ns
HSSD4/SD4 tsu(CLKIH-CMDIV)
Hold time, mmc1_cmd valid after
mmc1_clk rising clock edge
MMC/SD/SDIO Interface 1 (3.0 V IO)
HSSD3/SD3 tsu(CMDV-CLKIH)
HSSD4/SD4 tsu(CLKIH-CMDIV)
MMC/SD/SDIO Interface 2
Setup time, mmc1_cmd valid before
mmc1_clk rising clock edge
1198.4
1249.2
1198.4
1249.2
ns
ns
Hold time, mmc1_cmd valid after
mmc1_clk rising clock edge
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Table 6-109. MMC/SD/SDIO Timing Requirements – SD Identification Mode(1)(2)(3) (continued)
NO.
PARAMETER
1.15 V
1.0 V
UNIT
MIN
MAX
MIN
MAX
HSSD3/SD3 tsu(CMDV-CLKIH)
HSSD4/SD4 tsu(CLKIH-CMDIV)
Setup time, mmc2_cmd valid before
mmc2_clk rising clock edge
1198.4
1198.4
ns
ns
Hold time, mmc2_cmd valid after
mmc2_clk rising clock edge
1249.2
1249.2
MMC/SD/SDIO Interface 3
HSSD3/SD3 tsu(CMDV-CLKIH)
Setup time, mmc3_cmd valid before
mmc3_clk rising clock edge
1198.4
1249.2
1198.4
1249.2
ns
ns
HSSD4/SD4 tsu(CLKIH-CMDIV)
Hold time, mmc3_cmd valid after
mmc3_clk rising clock edge
(1) Timing parameters are referred to output clock specified in Table 6-110.
(2) The timing requirements are assured for the cycle jitter and duty cycle error conditions specified in Table 6-110.
(3) Corresponding figures showing timing parameters are common with other interface modes. (See SD and HS SD modes).
Table 6-110. MMC/SD/SDIO Switching Characteristics – SD Identification Mode(4)
NO.
PARAMETER
1.15 V
1.0 V
UNIT
MIN
MAX
MIN
MAX
SD Identification Mode
HSSD1/SD1 tc(clk)
HSSD2/SD2 tW(clkH)
HSSD2/SD2 tW(clkL)
tdc(clk)
Cycle time(1), output clk period
2500
2500
ns
ns
ns
ns
ps
Typical pulse duration, output clk high
Typical pulse duration, output clk low
Duty cycle error, output clk
X(5)*PO(2)
Y(6)*PO(2)
X(5)*PO(2)
Y(6)*PO(2)
125
125
tj(clk)
Jitter standard deviation(3), output clk
200
200
MMC/SD/SDIO Interface 1 (1.8 V IO)
tc(clk)
Rise time, output clk
10
10
10
10
ns
ns
ns
ns
ns
tW(clkH)
tW(clkL)
tdc(clk)
Fall time, output clk
Rise time, output data
Fall time, output data
10
10
10
10
HSSD5/SD5 td(CLKOH-CMD) Delay time, mmc1_clk rising clock edge to
mmc1_cmd transition
6.3
6.3
6.3
2492.7
6.3
6.3
6.3
2492.7
MMC/SD/SDIO Interface 1 (3.0 V IO)
tc(clk)
Rise time, output clk
Fall time, output clk
Rise time, output data
Fall time, output data
10
10
0
0
ns
ns
ns
ns
ns
tW(clkH)
tW(clkL)
tdc(clk)
10
10
10
10
HSSD5/SD5 td(CLKOH-CMD) Delay time, mmc1_clk rising clock edge to
mmc1_cmd transition
2492.7
2492.7
MMC/SD/SDIO Interface 2
tc(clk)
Rise time, output clk
Fall time, output clk
Rise time, output data
Fall time, output data
10
10
10
10
ns
ns
ns
ns
ns
tW(clkH)
tW(clkL)
tdc(clk)
10
10
10
10
HSSD5/SD5 td(CLKOH-CMD) Delay time, mmc2_clk rising clock edge to
mmc2_cmd transition
2492.7
2492.7
MMC/SD/SDIO Interface 3
tc(clk)
Rise time, output clk
Fall time, output clk
Rise time, output data
Fall time, output data
10
10
10
10
10
10
10
10
ns
ns
ns
ns
tW(clkH)
tW(clkL)
tdc(clk)
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Table 6-110. MMC/SD/SDIO Switching Characteristics – SD Identification Mode(4) (continued)
NO.
PARAMETER
1.15 V
1.0 V
UNIT
MIN
MAX
2492.7
MIN
MAX
HSSD5/SD5 td(CLKOH-CMD) Delay time, mmc3_clk rising clock edge to
mmc3_cmd transition
6.3
6.3
2492.7
ns
(1) Related with the output clk maximum and minimum frequencies programmable in I/F module.
(2) PO = output clk period in ns.
(3) The jitter probability density can be approximated by a Gaussian function.
(4) Corresponding figures showing timing parameters are common with other interface modes (see SD and HS SD modes).
(5) The X parameter is defined as follows.
CLKD
1 or Even
Odd
X
0.5
(trunk[CLKD/2]+1)/CLKD
For details about clock division factor CLKD, see the OMAP35xx ES2.0 Technical Reference Manual (TRM) [literature number
SPRUF98].
(6) The Y parameter is defined as follows.
CLKD
1 or Even
Odd
Y
0.5
(trunk[CLKD/2])/CLKD
For details about clock division factor CLKD, see the OMAP35xx ES2.0 Technical Reference Manual (TRM) [literature number
SPRUF98].
6.7.1.2 MMC/SD/SDIO in High-Speed MMC Mode
Table 6-112 and Table 6-113 assume testing over the recommended operating conditions and electrical
characteristic conditions (see Figure 6-57 and Figure 6-58).
Table 6-111. MMC/SD/SDIO Timing Conditions – High-Speed MMC Mode
TIMING CONDITION PARAMETER
VALUE
UNIT
High-Speed MMC Mode
Input Conditions
tR
Input signal rise time
Input signal fall time
3
3
ns
ns
tF
Output Conditions
CLOAD
Output load capacitance
30
pF
Table 6-112. MMC/SD/SDIO Timing Requirements – High-Speed MMC Mode(1)(2)(3)(4)
NO.
PARAMETER
1.15 V
1.0 V
UNIT
MIN
MAX
MIN
MAX
High-Speed MMC Mode
MMC/SD/SDIO Interface 1 (1.8 V IO)
MMC3 tsu(CMDV-CLKIH)
MMC4 tsu(CLKIH-CMDIV)
MMC7 tsu(DATxV-CLKIH)
MMC8 tsu(CLKIH-DATxIV)
Setup time, mmc1_cmd valid before mmc1_clk
rising clock edge
5.6
2.3
5.6
2.3
26
1.9
26
ns
ns
ns
ns
Hold time, mmc1_cmd valid after mmc1_clk
rising clock edge
Setup time, mmc1_datx valid before mmc1_clk
rising clock edge
Hold time, mmc1_datx valid after mmc1_clk
rising clock edge
1.9
MMC/SD/SDIO Interface 1 (3.0 V IO)
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Table 6-112. MMC/SD/SDIO Timing Requirements – High-Speed MMC Mode(1)(2)(3)(4) (continued)
NO.
PARAMETER
1.15 V
1.0 V
UNIT
MIN
MAX
MIN
MAX
MMC3 tsu(CMDV-CLKIH)
MMC4 tsu(CLKIH-CMDIV)
MMC7 tsu(DATxV-CLKIH)
MMC8 tsu(CLKIH-DATxIV)
Setup time, mmc1_cmd valid before mmc1_clk
rising clock edge
5.6
26
ns
ns
ns
ns
Hold time, mmc1_cmd valid after mmc1_clk
rising clock edge
2.3
5.6
2.3
1.9
26
Setup time, mmc1_datx valid before mmc1_clk
rising clock edge
Hold time, mmc1_datx valid after mmc1_clk
rising clock edge
1.9
MMC/SD/SDIO Interface 2
MMC3 tsu(CMDV-CLKIH)
Setup time, mmc2_cmd valid before mmc2_clk
rising clock edge
5.6
2.3
5.6
2.3
26
1.9
26
ns
ns
ns
ns
MMC4 tsu(CLKIH-CMDIV)
MMC7 tsu(DATxV-CLKIH)
MMC8 tsu(CLKIH-DATxIV)
Hold time, mmc2_cmd valid after mmc2_clk
rising clock edge
Setup time, mmc2_datx valid before mmc2_clk
rising clock edge
Hold time, mmc2_datx valid after mmc2_clk
rising clock edge
1.9
MMC/SD/SDIO Interface 3
MMC3 tsu(CMDV-CLKIH)
Setup time, mmc3_cmd valid before mmc3_clk
rising clock edge
5.6
2.3
5.6
2.3
26
1.9
26
ns
ns
ns
ns
MMC4 tsu(CLKIH-CMDIV)
MMC7 tsu(DATxV-CLKIH)
MMC8 tsu(CLKIH-DATxIV)
Hold time, mmc3_cmd valid after mmc3_clk
rising clock edge
Setup time, mmc3_datx valid before mmc3_clk
rising clock edge
Hold time, mmc3_datx valid after mmc3_clk
rising clock edge
1.9
(1) Timing parameters are referred to output clock specified in Table 6-113.
(2) The timing requirements are assured for the cycle jitter and duty cycle error conditions specified in Table 6-113.
(3) Corresponding figures showing timing parameters are common with Standard MMC mode (See Figure 6-57 and Figure 6-58)
(4) In datx, x is equal to 1, 2, 3, 4, 5, 6, or 7.
Table 6-113. MMC/SD/SDIO Switching Characteristics – High-Speed MMC Mode(4)(7)
N O.
PARAMETER
1.15 V
1.0 V
UNIT
MIN
MAX
MIN
MAX
High-Speed MMC Mode
MMC1
MMC2
MMC2
tc(clk)
Cycle time(1), output clk period
20.8
41.7
ns
ns
ns
ps
ps
tW(clkH)
tW(clkL)
tdc(clk)
tj(clk)
Typical pulse duration, output clk high
Typical pulse duration, output clk low
Duty cycle error, output clk
X(5)*PO(2)
Y(6)*PO(2)
X(5)*PO(2)
Y(6)*PO(2)
1041.7
200
2083.3
200
Jitter standard deviation(3), output clk
MMC/SD/SDIO Interface 1 (1.8 V IO)
tc(clk)
Rise time, output clk
3
3
3
3
ns
ns
ns
ns
ns
tW(clkH)
tW(clkL)
Fall time, output clk
Rise time, output data
Fall time, output data
3
3
tdc(clk)
3
3
MMC5
MMC6
td(CLKOH-CMD)
Delay time, mmc1_clk rising clock edge to
mmc1_cmd transition
3.7
3.7
14.1
4.1
4.1
34.5
td(CLKOH-DATx)
Delay time, mmc1_clk rising clock edge to
mmc1_datx transition
14.1
34.5
ns
MMC/SD/SDIO Interface 1 (3.0 V IO)
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Table 6-113. MMC/SD/SDIO Switching Characteristics – High-Speed MMC Mode(4)(7) (continued)
N O.
PARAMETER
1.15 V
1.0 V
UNIT
MIN
MAX
MIN
MAX
tc(clk)
Rise time, output clk
3
3
3
3
ns
ns
ns
ns
ns
tW(clkH)
tW(clkL)
Fall time, output clk
Rise time, output data
Fall time, output data
3
3
tdc(clk)
3
3
MMC5
MMC6
td(CLKOH-CMD)
Delay time, mmc1_clk rising clock edge to
mmc1_cmd transition
3.7
3.7
14.1
4.1
4.1
34.5
td(CLKOH-DATx)
Delay time, mmc1_clk rising clock edge to
mmc1_datx transition
14.1
34.5
ns
MMC/SD/SDIO Interface 2
tc(clk)
Rise time, output clk
Fall time, output clk
Rise time, output data
Fall time, output data
3
3
3
3
ns
ns
ns
ns
ns
tW(clkH)
tW(clkL)
tdc(clk)
3
3
3
3
MMC5
MMC6
td(CLKOH-CMD)
Delay time, mmc2_clk rising clock edge to
mmc2_cmd transition
3.7
3.7
14.1
4.1
4.1
34.5
td(CLKOH-DATx)
Delay time, mmc2_clk rising clock edge to
mmc2_datx transition
16.5
36.9
ns
MMC/SD/SDIO Interface 3
tc(clk)
Rise time, output clk
Fall time, output clk
Rise time, output data
Fall time, output data
3
3
3
3
ns
ns
ns
ns
ns
tW(clkH)
tW(clkL)
tdc(clk)
3
3
3
3
MMC5
MMC6
td(CLKOH-CMD)
Delay time, mmc3_clk rising clock edge to
mmc3_cmd transition
3.7
3.7
14.1
4.1
4.1
34.5
td(CLKOH-DATx)
Delay time, mmc3_clk rising clock edge to
mmc3_datx transition
14.1
34.5
ns
(1) Related with the output clk maximum and minimum frequencies programmable in I/F module.
(2) PO = output clk period in ns.
(3) The jitter probability density can be approximated by a Gaussian function.
(4) In datx, x is equal to 1, 2, 3, 4, 5, 6, or 7.
(5) The X parameter is defined as follows.
CLKD
1 or Even
Odd
X
0.5
(trunk[CLKD/2]+1)/CLKD
For details about clock division factor CLKD, see the OMAP35xx ES2.0 Technical Reference Manual (TRM) [literature number
SPRUF98].
(6) The Y parameter is defined as follows.
CLKD
1 or Even
Odd
Y
0.5
(trunk[CLKD/2])/CLKD
For details about clock division factor CLKD, see the OMAP35xx ES2.0 Technical Reference Manual (TRM) [literature number
SPRUF98].
(7) Corresponding figures showing timing parameters are common with Standard MMC mode (See Figure 6-57 and Figure 6-58)
6.7.1.3 MMC/SD/SDIO in Standard MMC Mode and MMC Identification Mode
Table 6-115 and Table 6-116 assume testing over the recommended operating conditions and electrical
characteristic conditions.
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Table 6-114. MMC/SD/SDIO Timing Conditions – Standard MMC Mode and MMC Identification Mode
TIMING CONDITION PARAMETER
Standard MMC Mode and MMC Identification Mode
Input Conditions
VALUE
UNIT
tR
Input signal rise time
Input signal fall time
10
10
ns
ns
tF
Output Conditions
CLOAD
Output load capacitance
30
pF
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Table 6-115. MMC/SD/SDIO Timing Requirements – Standard MMC Mode and MMC Identification Mode(1)(2)
NO.
PARAMETER
1.15 V
1.0 V
UNIT
MIN
MAX
MIN
MAX
Standard MMC Mode and MMC Identification Mode
MMC/SD/SDIO Interface 1 (1.8 V IO)
MMC3 tsu(CMDV-CLKIH)
MMC4 tsu(CLKIH-CMDIV)
MMC7 tsu(DATxV-CLKIH)
MMC8 tsu(CLKIH-DATxIV)
Setup time, mmc1_cmd valid before
mmc1_clk rising clock edge
13.6
8.9
65.7
8.9
ns
ns
ns
ns
Hold time, mmc1_cmd valid after mmc1_clk
rising clock edge
Setup time, mmc1_datx valid before
mmc1_clk rising clock edge
13.6
8.9
65.7
8.9
Hold time, mmc1_datx valid after mmc1_clk
rising clock edge
MMC/SD/SDIO Interface 1 (3.0 V IO)
MMC3 tsu(CMDV-CLKIH)
MMC4 tsu(CLKIH-CMDIV)
MMC7 tsu(DATxV-CLKIH)
MMC8 tsu(CLKIH-DATxIV)
Setup time, mmc1_cmd valid before
mmc1_clk rising clock edge
13.6
8.9
65.7
8.9
ns
ns
ns
ns
Hold time, mmc1_cmd valid after mmc1_clk
rising clock edge
Setup time, mmc1_datx valid before
mmc1_clk rising clock edge
13.6
8.9
65.7
8.9
Hold time, mmc1_datx valid after mmc1_clk
rising clock edge
MMC/SD/SDIO Interface 2
MMC3 tsu(CMDV-CLKIH)
Setup time, mmc2_cmd valid before
mmc2_clk rising clock edge
13.6
8.9
65.7
8.9
ns
ns
ns
ns
MMC4 tsu(CLKIH-CMDIV)
MMC7 tsu(DATxV-CLKIH)
MMC8 tsu(CLKIH-DATxIV)
Hold time, mmc2_cmd valid after mmc2_clk
rising clock edge
Setup time, mmc2_datx valid before
mmc2_clk rising clock edge
13.6
8.9
65.7
8.9
Hold time, mmc2_datx valid after mmc2_clk
rising clock edge
MMC/SD/SDIO Interface 3
MMC3 tsu(CMDV-CLKIH)
Setup time, mmc3_cmd valid before
mmc3_clk rising clock edge
13.6
8.9
65.7
8.9
ns
ns
ns
ns
MMC4 tsu(CLKIH-CMDIV)
MMC7 tsu(DATxV-CLKIH)
MMC8 tsu(CLKIH-DATxIV)
Hold time, mmc3_cmd valid after mmc3_clk
rising clock edge
Setup time, mmc3_datx valid before
mmc3_clk rising clock edge
13.6
8.9
65.7
8.9
Hold time, mmc3_datx valid after mmc3_clk
rising clock edge
(1) Timing parameters are referred to output clock specified in Table 6-116.
(2) The timing requirements are assured for the cycle jitter and duty cycle error conditions specified in Table 6-116.
(3) In datx, x is equal to 1, 2, 3, 4, 5, 6, or 7.
Table 6-116. MMC/SD/SDIO Switching Characteristics – Standard MMC Mode and MMC Identification
Mode
NO.
PARAMETER
1.15 V
1.0 V
UNIT
MIN
MAX
MIN
MAX
MMC Identification Mode
MMC1
MMC2
MMC2
tc(clk)
Cycle time(1), output clk period
2500
2500
ns
ns
ns
ns
ps
tW(clkH)
tW(clkL)
tdc(clk)
tj(clk)
Typical pulse duration, output clk high
Typical pulse duration, output clk low
Duty cycle error, output clk
X(5)*PO(2)
Y(6)*PO(2)
X(5)*PO(2)
Y(6)*PO(2)
125
200
125
200
Jitter standard deviation(3), output clk
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Table 6-116. MMC/SD/SDIO Switching Characteristics – Standard MMC Mode and MMC Identification
Mode (continued)
NO.
PARAMETER
1.15 V
1.0 V
UNIT
MIN
MAX
MIN
MAX
Standard MMC Mode
MMC1
MMC2
MMC2
tc(clk)
Cycle time(1), output clk period
52.1
104.2
ns
ns
ns
ps
ps
tW(clkH)
tW(clkL)
tdc(clk)
tj(clk)
Typical pulse duration, output clk high
Typical pulse duration, output clk low
Duty cycle error, output clk
X(5)*PO(2)
Y(6)*PO(2)
X(5)*PO(2)
Y(6)*PO(2)
2604.2
200
5208.3
200
Jitter standard deviation(3), output clk
MMC/SD/SDIO Interface 1 (1.8 V IO)
tc(clk)
Rise time, output clk
10
10
10
10
ns
ns
ns
ns
ns
tW(clkH)
tW(clkL)
Fall time, output clk
Rise time, output data
Fall time, output data
10
10
tdc(clk)
10
10
MMC5
MMC6
td(CLKOH-CMD)
Delay time, mmc1_clk rising clock edge to
mmc1_cmd transition
4.3
4.3
47.8
4.3
4.3
99.9
td(CLKOH-DATx)
Delay time, mmc1_clk rising clock edge to
mmc1_datx transition
47.8
99.9
ns
MMC/SD/SDIO Interface 1 (3.0 V IO)
tc(clk)
Rise time, output clk
10
10
10
10
ns
ns
ns
ns
ns
tW(clkH)
tW(clkL)
Fall time, output clk
Rise time, output data
Fall time, output data
10
10
tdc(clk)
10
10
MMC5
MMC6
td(CLKOH-CMD)
Delay time, mmc1_clk rising clock edge to
mmc1_cmd transition
4.3
4.3
47.8
4.3
4.3
99.9
td(CLKOH-DATx)
Delay time, mmc1_clk rising clock edge to
mmc1_datx transition
47.8
99.9
ns
MMC/SD/SDIO Interface 2
tc(clk)
Rise time, output clk
Fall time, output clk
Rise time, output data
Fall time, output data
10
10
10
10
ns
ns
ns
ns
ns
tW(clkH)
tW(clkL)
tdc(clk)
10
10
10
10
MMC5
MMC6
td(CLKOH-CMD)
Delay time, mmc2_clk rising clock edge to
mmc2_cmd transition
4.3
4.3
47.8
4.3
4.3
99.9
td(CLKOH-DATx)
Delay time, mmc2_clk rising clock edge to
mmc2_datx transition
47.8
99.9
ns
MMC/SD/SDIO Interface 3
tc(clk)
Rise time, output clk
Fall time, output clk
Rise time, output data
Fall time, output data
10
10
10
10
ns
ns
ns
ns
ns
tW(clkH)
tW(clkL)
tdc(clk)
10
10
10
10
MMC5
MMC6
td(CLKOH-CMD)
Delay time, mmc3_clk rising clock edge to
mmc3_cmd transition
4.3
4.3
47.8
4.3
4.3
99.9
td(CLKOH-DATx)
Delay time, mmc3_clk rising clock edge to
mmc3_datx transition
47.8
99.9
ns
(1) Related with the output clk maximum and minimum frequencies programmable in I/F module.
(2) PO = output clk period in ns.
(3) The jitter probability density can be approximated by a Gaussian function.
(4) In datx, x is equal to 1, 2, 3, 4, 5, 6, or 7.
(5) The X parameter is defined as follows.
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CLKD
X
1 or Even
Odd
0.5
(trunk[CLKD/2]+1)/CLKD
For details about clock division factor CLKD, see the OMAP35xx ES2.0 Technical Reference Manual (TRM) [literature number
SPRUF98].
(6) The Y parameter is defined as follows.
CLKD
1 or Even
Odd
Y
0.5
(trunk[CLKD/2])/CLKD
For details about clock division factor CLKD, see the OMAP35xx ES2.0 Technical Reference Manual (TRM) [literature number
SPRUF98].
MMC1
MMC2
mmcx_clk
MMC3
MMC7
MMC4
mmcx_cmd
MMC8
mmcx_dat[3:0]
030-104
In mmcx, x is equal to 1, 2, or 3.
Figure 6-57. MMC/SD/SDIO – High-Speed and Standard MMC Modes – Data/Command Receive
MMC1
MMC2
mmcx_clk
MMC5
MMC6
MMC5
mmcx_cmd
MMC6
mmcx_dat[3:0]
030-105
In mmcx, x is equal to 1, 2, or 3.
Figure 6-58. MMC/SD/SDIO – High-Speed and Standard MMC Modes – Data/Command Transmit
6.7.1.4 MMC/SD/SDIO in High-Speed SD Mode
Table 6-118 and Table 6-119 assume testing over the recommended operating conditions and electrical
characteristic conditions.
Table 6-117. MMC/SD/SDIO Timing Conditions – High-Speed SD Mode
TIMING CONDITION PARAMETER
VALUE
UNIT
High-Speed SD Mode
Input Conditions
tR
Input signal rise time
Input signal fall time
3
3
ns
ns
tF
Output Conditions
CLOAD
Output load capacitance
40
pF
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Table 6-118. MMC/SD/SDIO Timing Requirements – High-Speed SD Mode(1)(2)(3)
NO.
PARAMETER
1.15 V
1.0 V
UNIT
MIN
MAX
MIN
MAX
High-Speed SD Mode
MMC/SD/SDIO Interface 1 (1.8 V IO)
HSSD3 tsu(CMDV-CLKIH)
HSSD4 tsu(CLKIH-CMDIV)
HSSD7 tsu(DATxV-CLKIH)
HSSD8 tsu(CLKIH-DATxIV)
Setup time, mmc1_cmd valid before
mmc1_clk rising clock edge
5.6
2.3
5.6
2.3
26
1.9
26
ns
ns
ns
ns
Hold time, mmc1_cmd valid after mmc1_clk
rising clock edge
Setup time, mmc1_datx valid before
mmc1_clk rising clock edge
Hold time, mmc1_datx valid after mmc1_clk
rising clock edge
1.9
MMC/SD/SDIO Interface 1 (3.0 V IO)
HSSD3 tsu(CMDV-CLKIH)
HSSD4 tsu(CLKIH-CMDIV)
HSSD7 tsu(DATxV-CLKIH)
HSSD8 tsu(CLKIH-DATxIV)
Setup time, mmc1_cmd valid before
mmc1_clk rising clock edge
5.6
2.3
5.6
2.3
26
1.9
26
ns
ns
ns
ns
Hold time, mmc1_cmd valid after mmc1_clk
rising clock edge
Setup time, mmc1_datx valid before
mmc1_clk rising clock edge
Hold time, mmc1_datx valid after mmc1_clk
rising clock edge
1.9
MMC/SD/SDIO Interface 2
HSSD3 tsu(CMDV-CLKIH)
Setup time, mmc2_cmd valid before
mmc2_clk rising clock edge
5.6
2.3
5.6
2.3
26
1.9
26
ns
ns
ns
ns
HSSD4 tsu(CLKIH-CMDIV)
HSSD7 tsu(DATxV-CLKIH)
HSSD8 tsu(CLKIH-DATxIV)
Hold time, mmc2_cmd valid after mmc2_clk
rising clock edge
Setup time, mmc2_datx valid before
mmc2_clk rising clock edge
Hold time, mmc2_datx valid after mmc2_clk
rising clock edge
1.9
MMC/SD/SDIO Interface 3
HSSD3 tsu(CMDV-CLKIH)
Setup time, mmc3_cmd valid before
mmc3_clk rising clock edge
5.6
2.3
5.6
2.3
26
1.9
26
ns
ns
ns
ns
HSSD4 tsu(CLKIH-CMDIV)
HSSD7 tsu(DATxV-CLKIH)
HSSD8 tsu(CLKIH-DATxIV)
Hold time, mmc3_cmd valid after mmc3_clk
rising clock edge
Setup time, mmc3_datx valid before
mmc3_clk rising clock edge
Hold time, mmc3_datx valid after mmc3_clk
rising clock edge
1.9
(1) Timing Parameters are referred to output clock specified in Table 6-119.
(2) The timing requirements are assured for the cycle jitter and duty cycle error conditions specified in Table 6-119.
(3) In datx, x is equal to 1, 2, 3, 4, 5, 6, or 7.
Table 6-119. MMC/SD/SDIO Switching Characteristics – High-Speed SD Mode
NO.
PARAMETER
1.15 V
1.0 V
UNIT
MIN
MAX
MIN
MAX
High-Speed SD Mode
HSSD1 tc(clk)
HSSD2 tW(clkH)
HSSD2 tW(clkL)
tdc(clk)
Cycle time(1), output clk period
20.8
41.7
ns
ns
ns
ps
ps
Typical pulse duration, output clk high
Typical pulse duration, output clk low
Duty cycle error, output clk
X(5)*PO(2)
Y(6)*PO(2)
X(5)*PO(2)
Y(6)*PO(2)
1041.7
200
2083.3
200
tj(clk)
Jitter standard deviation(3), output clk
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Table 6-119. MMC/SD/SDIO Switching Characteristics – High-Speed SD Mode (continued)
NO.
PARAMETER
1.15 V
1.0 V
UNIT
MIN
MAX
MIN
MAX
MMC/SD/SDIO Interface 1 (1.8 V IO)
tc(clk) Rise time, output clk
tW(clkH)
3
3
3
3
ns
ns
ns
ns
ns
Fall time, output clk
Rise time, output data
Fall time, output data
tW(clkL)
3
3
tdc(clk)
3
3
HSSD5 td(CLKOH-CMD)
Delay time, mmc1_clk rising clock edge to
mmc1_cmd transition
3.7
3.7
14.1
4.1
4.1
34.5
HSSD6 td(CLKOH-DATx)
Delay time, mmc1_clk rising clock edge to
mmc1_datx transition
14.1
34.5
ns
MMC/SD/SDIO Interface 1 (3.0 V IO)
tc(clk) Rise time, output clk
tW(clkH)
3
3
3
3
ns
ns
ns
ns
ns
Fall time, output clk
Rise time, output data
Fall time, output data
tW(clkL)
3
3
tdc(clk)
3
3
HSSD5 td(CLKOH-CMD)
Delay time, mmc1_clk rising clock edge to
mmc1_cmd transition
3.7
3.7
14.1
4.1
4.1
34.5
HSSD6 td(CLKOH-DATx)
Delay time, mmc1_clk rising clock edge to
mmc1_datx transition
14.1
34.5
ns
MMC/SD/SDIO Interface 2
tc(clk)
tW(clkH)
Rise time, output clk
Fall time, output clk
Rise time, output data
Fall time, output data
3
3
3
3
ns
ns
ns
ns
ns
tW(clkL)
3
3
tdc(clk)
3
3
HSSD5 td(CLKOH-CMD)
Delay time, mmc2_clk rising clock edge to
mmc2_cmd transition
3.7
3.7
14.1
4.1
4.1
34.5
HSSD6 td(CLKOH-DATx)
Delay time, mmc2_clk rising clock edge to
mmc2_datx transition
14.1
34.5
ns
MMC/SD/SDIO Interface 3
tc(clk)
tW(clkH)
Rise time, output clk
Fall time, output clk
Rise time, output data
Fall time, output data
3
3
3
3
ns
ns
ns
ns
ns
tW(clkL)
3
3
tdc(clk)
3
3
HSSD5 td(CLKOH-CMD)
Delay time, mmc3_clk rising clock edge to
mmc3_cmd transition
3.7
3.7
14.1
4.1
4.1
34.5
HSSD6 td(CLKOH-DATx)
Delay time, mmc3_clk rising clock edge to
mmc3_datx transition
14.1
34.5
ns
(1) Related with the output clk maximum and minimum frequencies programmable in I/F module.
(2) PO = output clk period in ns.
(3) The jitter probability density can be approximated by a Gaussian function.
(4) In datx, x is equal to 1, 2, 3, 4, 5, 6, or 7.
(5) The X parameter is defined as follows.
CLKD
1 or Even
Odd
X
0.5
(trunk[CLKD/2]+1)/CLKD
For details about clock division factor CLKD, see the OMAP35xx ES2.0 Technical Reference Manual (TRM) [literature number
SPRUF98].
(6) The Y parameter is defined as follows.
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CLKD
1 or Even
Odd
Y
0.5
(trunk[CLKD/2])/CLKD
For details about clock division factor CLKD, see the OMAP35xx ES2.0 Technical Reference Manual (TRM) [literature number
SPRUF98].
HSSD1
HSSD2
mmcx_clk
HSSD3
HSSD7
HSSD4
mmcx_cmd
HSSD8
mmcx_dat[3:0]
030-106
In mmcx, x is equal to 1, 2, or 3.
Figure 6-59. MMC/SD/SDIO – High-Speed SD Mode – Data/Command Receive
HSSD1
HSSD2
mmcx_clk
HSSD5
HSSD6
HSSD5
mmcx_cmd
HSSD6
mmcx_dat[3:0]
030-107
In mmcx, x is equal to 1, 2, or 3.
Figure 6-60. MMC/SD/SDIO – High-Speed SD Mode – Data/Command Transmit
6.7.1.5 MMC/SD/SDIO in Standard SD Mode
Table 6-121 and Table 6-122 assume testing over the recommended operating conditions and electrical
characteristic conditions (see Figure 6-61).
Table 6-120. MMC/SD/SDIO Timing Conditions – Standard SD Mode
TIMING CONDITION PARAMETER
VALUE
UNIT
Standard SD Mode
Input Conditions
tR
Input signal rise time
Input signal fall time
10
10
ns
ns
tF
Output Conditions
CLOAD
Output load capacitance
40
pF
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Table 6-121. MMC/SD/SDIO Timing Requirements – Standard SD Mode(1)(2)(3)
NO.
PARAMETER
1.15 V
1.0 V
UNIT
MIN
MAX
MIN
MAX
Standard SD Mode
MMC/SD/SDIO Interface 1 (1.8 V IO)
SD3 tsu(CMDV-CLKIH)
SD4 tsu(CLKIH-CMDIV)
SD7 tsu(DATxV-CLKIH)
SD8 tsu(CLKIH-DATxIV)
Setup time, mmc1_cmd valid before mmc1_clk
rising clock edge
6.2
19.4
6.2
47.7
19.2
47.7
19.2
ns
ns
ns
ns
Hold time, mmc1_cmd valid after mmc1_clk
rising clock edge
Setup time, mmc1_datx valid before mmc1_clk
rising clock edge
Hold time, mmc1_datx valid after mmc1_clk
rising clock edge
19.4
MMC/SD/SDIO Interface 1 (3.0 V IO)
SD3 tsu(CMDV-CLKIH)
SD4 tsu(CLKIH-CMDIV)
SD7 tsu(DATxV-CLKIH)
SD8 tsu(CLKIH-DATxIV)
Setup time, mmc1_cmd valid before mmc1_clk
rising clock edge
6.2
19.4
6.2
47.7
19.2
47.7
19.2
ns
ns
ns
ns
Hold time, mmc1_cmd valid after mmc1_clk
rising clock edge
Setup time, mmc1_datx valid before mmc1_clk
rising clock edge
Hold time, mmc1_datx valid after mmc1_clk
rising clock edge
19.4
MMC/SD/SDIO Interface 2
SD3 tsu(CMDV-CLKIH)
Setup time, mmc2_cmd valid before mmc2_clk
rising clock edge
6.2
19.4
6.2
47.7
19.2
47.7
19.2
ns
ns
ns
ns
SD4 tsu(CLKIH-CMDIV)
SD7 tsu(DATxV-CLKIH)
SD8 tsu(CLKIH-DATxIV)
Hold time, mmc2_cmd valid after mmc2_clk
rising clock edge
Setup time, mmc2_datx valid before mmc2_clk
rising clock edge
Hold time, mmc2_datx valid after mmc2_clk
rising clock edge
19.4
MMC/SD/SDIO Interface 3
SD3 tsu(CMDV-CLKIH)
Setup time, mmc3_cmd valid before mmc3_clk
rising clock edge
6.2
19.4
6.2
47.7
19.2
47.7
19.2
ns
ns
ns
ns
SD4 tsu(CLKIH-CMDIV)
SD7 tsu(DATxV-CLKIH)
SD8 tsu(CLKIH-DATxIV)
Hold time, mmc3_cmd valid after mmc3_clk
rising clock edge
Setup time, mmc3_datx valid before mmc3_clk
rising clock edge
Hold time, mmc3_datx valid after mmc3_clk
rising clock edge
19.4
(1) Timing parameters are referred to output clock specified in Table 6-122.
(2) The timing requirements are assured for the cycle jitter and duty cycle error conditions specified in Table 6-122.
(3) In datx, x is equal to 1, 2, 3, 4, 5, 6, or 7.
Table 6-122. MMC/SD/SDIO Switching Characteristics – Standard SD Mode
NO.
PARAMETER
1.15 V
1.0 V
UNIT
MIN
MAX
MIN
MAX
Standard SD Mode
SD1 tc(clk)
SD2 tW(clkH)
SD2 tW(clkL)
tdc(clk)
Cycle time(1), output clk period
41.7
83.3
ns
ns
ns
ps
ps
Typical pulse duration, output clk high
Typical pulse duration, output clk low
Duty cycle error, output clk
X(5)*PO(2)
Y(6)*PO(2)
X(5)*PO(2)
Y(6)*PO(2)
2083.3
200
4166.7
200
tj(clk)
Jitter standard deviation(3), output clk
MMC/SD/SDIO Interface 1 (1.8 V IO)
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Table 6-122. MMC/SD/SDIO Switching Characteristics – Standard SD Mode (continued)
NO.
PARAMETER
1.15 V
1.0 V
UNIT
MIN
MAX
10
MIN
MAX
10
tc(clk)
Rise time, output clk
ns
ns
ns
ns
ns
tW(clkH)
tW(clkL)
tdc(clk)
Fall time, output clk
Rise time, output data
Fall time, output data
10
10
10
10
10
10
SD5 td(CLKOH-CMD)
Delay time, mmc1_clk rising clock edge to
mmc1_cmd transition
6.1
6.1
35.5
6.3
6.3
77
SD6 td(CLKOH-DATx)
Delay time, mmc1_clk rising clock edge to
mmc1_datx transition
35.5
77
ns
MMC/SD/SDIO Interface 1 (3.0 V IO)
tc(clk) Rise time, output clk
tW(clkH)
10
10
10
10
10
10
77
ns
ns
ns
ns
ns
Fall time, output clk
Rise time, output data
Fall time, output data
tW(clkL)
10
tdc(clk)
10
SD5 td(CLKOH-CMD)
Delay time, mmc1_clk rising clock edge to
mmc1_cmd transition
6.1
6.1
35.5
6.3
6.3
SD6 td(CLKOH-DATx)
Delay time, mmc1_clk rising clock edge to
mmc1_datx transition
35.5
77
ns
MMC/SD/SDIO Interface 2
tc(clk) Rise time, output clk
tW(clkH)
10
10
10
10
10
10
77
ns
ns
ns
ns
ns
Fall time, output clk
Rise time, output data
Fall time, output data
tW(clkL)
10
tdc(clk)
10
SD5 td(CLKOH-CMD)
Delay time, mmc2_clk rising clock edge to
mmc2_cmd transition
6.1
6.1
35.5
6.3
6.3
SD6 td(CLKOH-DATx)
Delay time, mmc2_clk rising clock edge to
mmc2_datx transition
35.5
77
ns
MMC/SD/SDIO Interface 3
tc(clk) Rise time, output clk
tW(clkH)
10
10
10
10
10
10
77
ns
ns
ns
ns
ns
Fall time, output clk
Rise time, output data
Fall time, output data
tW(clkL)
10
tdc(clk)
10
SD5 td(CLKOH-CMD)
Delay time, mmc3_clk rising clock edge to
mmc3_cmd transition
6.1
6.1
35.5
6.3
6.3
SD6 td(CLKOH-DATx)
Delay time, mmc3_clk rising clock edge to
mmc3_datx transition
35.5
77
ns
(1) Related with the output clk maximum and minimum frequencies programmable in I/F module.
(2) PO = output clk period in ns.
(3) The jitter probability density can be approximated by a Gaussian function.
(4) In datx, x is equal to 1, 2, 3, 4, 5, 6, or 7.
(5) The X parameter is defined as follows.
CLKD
1 or Even
Odd
X
0.5
(trunk[CLKD/2]+1)/CLKD
For details about clock division factor CLKD, see the OMAP35xx ES2.0 Technical Reference Manual (TRM) [literature number
SPRUF98].
(6) The Y parameter is defined as follows.
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CLKD
Y
1 or Even
Odd
0.5
(trunk[CLKD/2])/CLKD
For details about clock division factor CLKD, see the OMAP35xx ES2.0 Technical Reference Manual (TRM) [literature number
SPRUF98].
SD1
SD2
mmcx_clk
SD3
SD4
mmcx_cmd
SD7
SD8
mmcx_dat[3:0]
030-108
In mmcx, x is equal to 1, 2, or 3.
Figure 6-61. MMC/SD/SDIO – Standard SD Mode – Data/Command Receive
SD1
SD2
mmcx_clk
SD5
SD6
SD5
mmcx_cmd
SD6
mmcx_dat[3:0]
030-109
In mmcx, x is equal to 1, 2, or 3.
Figure 6-62. MMC/SD/SDIO – Standard SD Mode – Data/Command Transmit
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6.8 Test Interfaces
The emulation and trace interfaces allow tracing activities of the following CPUs:
•
ARM1136JF-STM through an Embedded Trace Macro-cell (ETM11) dedicated to enable real-time
trace of the ARM subsystem operations and a Serial Debug Trace Interface (SDTI)
All processors can be emulated via JTAG ports.
6.8.1 Embedded Trace Macro Interface (ETM)
Table 6-123 assumes testing over the recommended operating conditions (see Figure 6-63).
Table 6-123. Embedded Trace Macro Interface Switching Characteristics(1)
NO.
PARAMETER
1.15 V
UNIT
MIN
MAX
f
1/tc(CLK)
Frequency, etk_clk
Cycle time(2), etk_clk
166
MHz
ns
ETM0 tc(CLK)
6
ETM1 tW(CLK)
ETM2 td(CLK-CTL)
ETM3 td(CLK-D)
Clock pulse width, etk_clk
2.7
ns
Delay time, etk_clk clock edge to etk_ctl transition
Delay time, etk_clk clock high to etk_d[15:0] transition
–0.5
–0.5
0.5
0.5
ns
ns
(1) The capacitive load is equivalent to 25 pF.
(2) Cycle time is given by considering a jitter of 5%.
ETM0
ETM1
etk_clk
ETM2
etk_ctl
ETM2
ETM3
ETM3
etk_d[15:0]
030-110
Figure 6-63. Embedded Trace Macro Interface
6.8.2 System Debug Trace Interface (SDTI)
The system debug trace interface (SDTI) module provides real-time software tracing functionality to the
OMAP3515/03 device.
The trace interface has four trace data pins and a trace clock pin.
This interface is a dual-edge interface: the data are available on rising and falling edges of sdti_clk but can
be also configured in single edge mode where data are available on falling edge of sdti_clk.
Serial interface operates in clock stop regime: serial clock is not free running, when there is no trace data
there is no trace clock.
6.8.2.1 System Debug Trace Interface in Dual-Edge Mode
Table 6-125 assumes testing over the recommended operating conditions and electrical characteristic
conditions (see Figure 6-64).
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Table 6-124. System Debug Trace Interface Timing Conditions – Dual-Edge Mode
TIMING CONDITION PARAMETER
VALUE
UNIT
Output Conditions
CLOAD
Output load capacitance
25
pF
Table 6-125. System Debug Trace Interface Switching Characteristics – Dual-Edge Mode
NO.
PARAMETER
1.15 V
MAX
1.0 V
UNIT
MIN
MIN
MAX
SD1 tc(CLK)
SD2 tw(CLK)
tdc(CLK)
Cycle time, sdti_clk period
29
29
ns
ns
ns
ns
ns
ns
Typical pulse duration, sdti_clk high or low
Duty cycle error, sdti_clk
Rise time, sdti_clk
0.5*P(1)
0.5*P(1)
–1.2
1.2
5
–1.2
1.2
5
tR(CLK)
tF(CLK)
Fall time, sdti_clk
5
5
SD3 td(CLK-TxD)
Delay time, sdti_clk
transition to sdti_txd[3:0]
transition
Multiplexing mode on etk pins
2.3
2.3
10.9
13.9
2.3
2.3
10.9
13.9
Multiplexing mode on
jtag_emu pins
tR(CLK)
tF(CLK)
Rise time, sdti_txd[3:0]
Fall time, sdti_txd[3:0]
5
5
5
5
ns
ns
(1) P = sdti_clk clock period
SD1
SD2
sdti_clk
SD3
SD3
sdti_txd[3:0]
Header Header Ad[7:4]
Ad[3:0] Da[15:12] Da[11:8] Da[7:4]
Da[3:0]
030-111
Figure 6-64. System Debug Trace Interface – Dual-Edge Mode
6.8.2.2 System Debug Trace Interface in Single-Edge Mode
Table 6-127 assumes testing over the recommended operating conditions and electrical characteristic
conditions (see Figure 6-65).
Table 6-126. System Debug Trace Interface Timing Conditions – Single-Edge Mode
TIMING CONDITION PARAMETER
Output Conditions
VALUE
UNIT
CLOAD
Output load capacitance
25
pF
Table 6-127. System Debug Trace Interface Switching Characteristics – Single-Edge Mode
NO.
PARAMETER
1.15 V
MAX
1.0 V
UNIT
MIN
MIN
MAX
SD1 tc(CLK)
SD2 tw(CLK)
tdc(CLK)
Cycle time, sdti_clk period
29
29
ns
ns
ns
ns
ns
ns
Typical pulse duration, sdti_clk high or low
Duty cycle error, sdti_clk
Rise time, sdti_clk
0.5*P(1)
0.5*P(1)
–1.2
1.2
5
–1.2
1.2
5
tR(CLK)
tF(CLK)
Fall time, sdti_clk
5
5
SD3 td(CLK-TxD)
Delay time, sdti_clk
transition to sdti_txd[3:0]
transition
Multiplexing mode on etk pins
2.3
2.3
26.5
33.2
2.3
2.3
26.5
33.2
Multiplexing mode on jtag_emu
pins
tR(CLK)
Rise time, sdti_txd[3:0]
5
5
ns
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Table 6-127. System Debug Trace Interface Switching Characteristics – Single-Edge Mode (continued)
NO.
PARAMETER
1.15 V
1.0 V
UNIT
MIN
MAX
MIN
MAX
tF(CLK)
Fall time, sdti_txd[3:0]
5
5
ns
(1) P = sdti_clk clock period.
SD1
SD3
SD2
sdti_clk
SD3
Ad[7:4]
sdti_txd[3:0]
Header
Header
Ad[3:0]
Da[15:12]
Da[11:8]
Da[7:4]
Da[3:0]
030-112
Figure 6-65. System Debug Trace Interface – Single-Edge Mode
6.8.3 JTAG Interfaces
OMAP3515/03 JTAG TAP controller handles standard IEEE JTAG interfaces. The following sections
define the timing requirements for several tools used to test the OMAP3515/03 processors as:
•
•
Free running clock tool, like XDS560 and XDS510 tools
Adaptive clock tool, like RealView® ICE tool and Lauterbach™ tool
6.8.3.1 JTAG – Free Running Clock Mode
Table 6-129 and Table 6-130 assume testing over the recommended operating conditions and electrical
characteristic conditions (see Figure 6-66).
Table 6-128. JTAG Timing Conditions – Free Running Clock Mode
TIMING CONDITION PARAMETER
VALUE
UNIT
Input Conditions
tR
Input signal rise time
Input signal fall time
5
5
ns
ns
tF
Output Conditions
CLOAD
Output load capacitance
30
pF
Table 6-129. JTAG Timing Requirements – Free Running Clock Mode(5)
NO.
PARAMETER
1.15 V
1.0 V
UNIT
MIN
MAX
MIN
MAX
JT4 tc(tck)
Cycle time(1), jtag_tck period
25
33
ns
ns
ns
ps
ps
ns
ns
ns
ns
ns
JT5 tw(tckL)
JT6 tw(tckH)
tdc(tck)
Typical pulse duration, jtag_tck low
Typical pulse duration, jtag_tck high
Duty cycle error, jtag_tck
0.5*P(2)
0.5*P(2)
0.5*P(2)
0.5*P(2)
–1250
–1250
1.8
1250
1250
–1667
–1667
1.8
1667
1667
tj(tck)
Cycle jitter(3), jtag_tck
JT7 tsu(tdiV-rtckH)
JT8 th(tdiV-rtckH)
JT9 tsu(tmsV-rtckH)
JT10 th(tmsV-rtckH)
JT12 tsu(emuxV-rtckH)
Setup time, jtag_tdi valid before jtag_rtck high
Hold time, jtag_tdi valid after jtag_rtck high
Setup time, jtag_tms valid before jtag_rtck high
Hold time, jtag_tms valid after jtag_rtck high
Setup time, jtag_emux(4) valid before jtag_rtck
high
0.7
1
1.8
1.8
0.7
1
14.6
19.8
JT13 th(emuxV-rtckH)
Hold time,jtag_emux(4) valid after jtag_rtck high
2
2.7
ns
(1) Related with the input maximum frequency supported by the JTAG module.
(2) P = jtag _tck period in ns.
(3) Maximum cycle jitter supported by jtag _tck input clock.
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(4) x = 0 to 1
(5) The timing requirements are assured for the cycle jitter and duty cycle error conditions specified.
Table 6-130. JTAG Switching Characteristics – Free Running Clock Mode
NO.
PARAMETER
1.15 V
1.0 V
UNIT
MIN
MAX
MIN
MAX
JT1 tc(rtck)
JT2 tw(rtckL)
JT3 tw(rtckH)
tdc(rtck)
Cycle time(1), jtag_rtck period
Typical pulse duration, jtag_rtck low
Typical pulse duration, jtag_rtck high
Duty cycle error, jtag_rtck
25
33
ns
ns
ns
ps
ps
ns
ns
ns
ns
ns
ns
ns
ns
0.5*PO(2)
0.5*PO(2)
0.5*PO(2)
0.5*PO(2)
–1250
1250
–1667
1667
tj(rtck)
Jitter standard deviation(3), jtag_rtck
33.3
4
33.3
4
tR(rtck)
Rise time, jtag_rtck
tF(rtck)
Fall time, jtag_rtck
4
4
JT11 td(rtckL-tdoV)
tR(tdo)
Delay time, jtag_rtck low to jtag_tdo valid
Rise time, jtag_tdo
–5.8
2.7
5.8
4
–7.9
2.7
7.9
4
tF(tdo)
Fall time, jtag_tdo
4
4
JT14 td(rtckH-emuxV)
tR(emux)
Delay time, jtag_rtck high to ,jtag_emux(4) valid
Rise time, jtag_emux(4)
Fall time, jtag_emux(4)
15.1
6
20.4
6
tF(emux)
6
6
(1) Related with the jtag_rtck maximum frequency.
(2) PO = jtag _rtck period in ns.
(3) The jitter probability density can be approximated by a Gaussian function.
(4) x = 0 to 1
JT4
JT1
JT5
JT6
JT3
jtag_tck
JT2
jtag_rtck
JT7
JT8
jtag_tdi
JT9
JT10
JT13
jtag_tms
JT12
jtag_emux(IN)
JT11
jtag_tdo
JT14
jtag_emux(OUT)
030-113
In jtag_emux, x is equal to 0 to 1.
Figure 6-66. JTAG Interface Timing – Free Running Clock Mode
6.8.3.2 JTAG – Adaptive Clock Mode
Table 6-132 and Table 6-133 assume testing over the recommended operating conditions and electrical
characteristic conditions (see Figure 6-67):
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Table 6-131. JTAG Timing Conditions – Adaptive Clock Mode
TIMING CONDITION PARAMETER
VALUE
UNIT
Input Conditions
tR
Input signal rise time
Input signal fall time
5
5
ns
ns
tF
Output Conditions
CLOAD
Output load capacitance
30
pF
Table 6-132. JTAG Timing Requirements – Adaptive Clock Mode(4)
NO.
PARAMETER
1.15 V
1.0 V
UNIT
MIN
MAX
MIN
MAX
JA4
JA5
JA6
tc(tck)
Cycle time(1), jtag_tck period
50
50
ns
ns
ns
ps
ps
ns
ns
ns
ns
tw(tckL)
Typical pulse duration, jtag_tck low
Typical pulse duration, jtag_tck high
Duty cycle error, jtag_tck
0.5*P(2)
0.5*P(2)
0.5*P(2)
0.5*P(2)
tw(tckH)
tdc(lclk)
–2500
–1500
13.8
2500
1500
–2500
–1500
13.8
2500
1500
tj(lclk)
Cycle jitter(3), jtag_tck
JA7
JA8
JA9
tsu(tdiV-tckH)
th(tdiV-tckH)
tsu(tmsV-tckH)
Setup time, jtag_tdi valid before jtag_tck high
Hold time, jtag_tdi valid after jtag_tck high
Setup time, jtag_tms valid before jtag_tck high
Hold time, jtag_tms valid after jtag_tck high
13.8
13.8
13.8
13.8
JA10 th(tmsV-tckH)
13.8
13.8
(1) Related with the input maximum frequency supported by the JTAG module.
(2) P = jtag _tck period in ns.
(3) Maximum cycle jitter supported by jtag _tck input clock.
(4) The timing requirements are assured for the cycle jitter and duty cycle error conditions specified.
Table 6-133. JTAG Switching Characteristics – Adaptive Clock Mode
NO.
PARAMETER
1.15 V
1.0 V
UNIT
MIN
MAX
MIN
MAX
JA1
JA2
JA3
tc(rtck)
Cycle time(1), jtag_rtck period
Typical pulse duration, jtag_rtck low
Typical pulse duration, jtag_rtck high
Duty cycle error, jtag_rtck
Jitter standard deviation(3), jtag_rtck
Rise time, jtag_rtck
50
50
ns
ns
ns
ps
ps
ns
ns
ns
ns
ns
tw(rtckL)
tw(rtckH)
tdc(rtck)
tj(rtck)
0.5*PO(2)
0.5*PO(2)
0.5*PO(2)
0.5*PO(2)
2500
–2500
2500
–2500
33.3
4
33.3
4
tR(rtck)
tF(rtck)
Fall time, jtag_rtck
4
4
JA11 td(rtckL-tdoV)
Delay time, jtag_rtck low to jtag_tdo valid
Rise time, jtag_tdo,
–14.6
14.6
4
–14.6
14.6
4
tR(tdo)
tF(tdo)
Fall time, jtag_tdo
4
4
(1) Related with the jtag _rtck maximum frequency programmable.
(2) PO = jtag _rtck period in ns.
(3) The jitter probability density can be approximated by a Gaussian function.
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JA4
JA5
JA6
jtag_tck
jtag_tdi
JA7
JA9
JA8
JA10
jtag_tms
JA1
JA2
JA3
jtag_rtck
jtag_tdo
JA11
030-114
Figure 6-67. JTAG Interface Timing – Adaptive Clock Mode
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7 PACKAGE CHARACTERISTICS
7.1 Package Thermal Resistance
Table 7-1 provides the thermal resistance characteristics for the recommended package types used on the
OMAP3515/03 Applications Processor.
Table 7-1. OMAP3515/03 Thermal Resistance Characteristics (3)
Package
Power (W)
RθJA(°C/W)
RθJB(°C/W)
RθJC(°C/W)
Board Type
OMAP3515/03
(CBB Pkg.)
TBD
24.46
10.94
0.01
2S2P(1)
OMAP35 15/03
(CUS Pkg.)
TBD
TBD
TBD
TBD
TBD
(1) The board types are defined by JEDEC (reference JEDEC standard JESD51-9, Test Board for Area Array Surface Mount Package
Thermal Measurements).
(2) Not applicable since the POP package has a memory package on top, no heat sink can be used. (TBD)
(3) RθJA (Theta-JA) = Thermal Resistance Junction-to-Ambient, °C/W
RθJB (Theta-JB) = Thermal Resistance Junction-to-Board, °C/W
RθJC (Theta-JC) = Thermal Resistance Junction-to-Case, °C/W
7.2 Device Support
7.2.1 Development Support (TBD)
7.2.2 Device and Development-Support Tool Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
OMAP™ processors and support tools. Each commercial OMAP platform member has one of three
prefixes: X, P, or null (no prefix). Texas Instruments recommends two of three possible prefix designators
for its support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product
development from engineering prototypes (TMDX) through fully qualified production devices/tools (TMDS).
Device development evolutionary flow:
X
Experimental device that is not necessarily representative of the final device’s electrical
specifications and may not use production assembly flow. (TMX definition)
P
Prototype device that is not necessarily the final silicon die and may not necessarily meet
final electrical specifications. (TMP definition)
null
Production version of the silicon die that is fully qualified. (TMS definition)
Support tool development evolutionary flow:
TMDX
TMDS
Development support product that has not yet completed Texas Instruments internal
qualification testing.
Fully qualified development support product.
TMX and TMP devices and TMDX development-support tools are shipped against the following
disclaimer:
“Developmental product is intended for internal evaluation purposes.”
Production devices and TMDS development-support tools have been characterized fully, and the quality
and reliability of the device have been demonstrated fully. TI’s standard warranty applies.
Predictions show that prototype devices (X or P), have a greater failure rate than the standard production
devices. Texas Instruments recommends that these devices not be used in any production system
because their expected end-use failure rate still is undefined. Only qualified production devices are to be
used.
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For additional description of the device nomenclature markings, see the OMAP35xx Applications
Processor Silicon Errata (literature number SPRZ278).
X
OMAP3530
B
CBB
PREFIX
X
P
= Experimental Device
= Prototype Device
null = Production Device
PACKAGE TYPE
DEVICE
CBB = 515 pin PBGA
CUS = 423 pin PBGA
SILICON REVISION
Figure 7-1. Device Nomenclature
7.2.3 Documentation Support
7.2.3.1 Related Documentation from Texas Instruments
The following documents describe the OMAP3515/03 Applications Processor. Copies of these documents
are available on the Internet at www.ti.com. Tip: Enter the literature number in the search box provided at
www.ti.com.
The current documentation that describes the OMAP3515/03 Applications Processor, related peripherals,
and other technical collateral, is available in the TBD product folder at: www.ti.com/tbd.
SPRUF98 OMAP35xx Technical Reference Manual. Collection of documents providing detailed
information on the OMAP3 architecture including power, reset, and clock control, interrupts,
memory map, and switch fabric interconnect. Detailed information on the microprocessor unit
(MPU) subsystem, the image, video, and audio (IVA2.2) subsystem, as well a functional
description of the peripherals supported on OMAP35xx devices is also included.
SPRU889
High-Speed DSP Systems Design Reference Guide. Provides recommendations for
meeting the many challenges of high-speed DSP system design. These recommendations
include information about DSP audio, video, and communications systems for the C5000 and
C6000 DSP platforms.
7.2.3.2 Related Documentation from Other Sources
The following documents are related to the OMAP3515/03 Applications Processor. Copies of these
documents can be obtained directly from the internet or from your Texas Instruments representative.
Cortex™-A8 Technical Reference Manual. This is the technical reference manual for the Cortex-A8
processor. A copy of this document can be obtained via the internet at http://infocenter.arm.com. Please
see the OMAP35xx Applications Processor Silicon Errata (literature number SPRZ278) to determine the
revision of the Cortex-A8 core used on your device.
ARM Core CortexTM-A8 (AT400/AT401) Errata Notice. Provides a list of advisories for the different
revisions of the Cortex-A8 processor. Contact your TI representative for a copy of this document. Please
see the OMAP35xx Applications Processor Silicon Errata (literature number SPRZ278) to determine the
revision of the Cortex-A8 core used on your device.
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PACKAGE OPTION ADDENDUM
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27-Feb-2008
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
XOMAP3503BCBB
XOMAP3515BCBB
ACTIVE
ACTIVE
FCBGA
FCBGA
CBB
515
515
168
168
TBD
TBD
Call TI
Call TI
Call TI
Call TI
CBB
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
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