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OMAP3515 and OMAP3503 Applications Processors

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1 OMAP3515 and OMAP3503 Applications Processors

1.1 Features

12

– 256-KB L2 Cache

• 112KB of ROM

• OMAP3515 and OMAP3503 Devices:

– OMAP™ 3 Architecture

– MPU Subsystem

• 64KB of Shared SRAM

• Endianess:

– ARM Instructions – Little Endian

– ARM Data – Configurable

• External Memory Interfaces:

– SDRAM Controller (SDRC)

•

Up to 720-MHz ARM® Cortex™-A8 Core

NEON™ SIMD Coprocessor

– PowerVR® SGX™ Graphics Accelerator

(OMAP3515 Device Only)

•

Tile-Based Architecture Delivering up to

10 MPoly/sec

•

16- and 32-Bit Memory Controller with

1GB of Total Address Space

Interfaces to Low-Power Double Data

Rate (LPDDR) SDRAM

SDRAM Memory Scheduler (SMS) and

Rotation Engine

•

Universal Scalable Shader Engine: Multi-

threaded Engine Incorporating Pixel and

Vertex Shader Functionality

•

Industry Standard API Support:

OpenGLES 1.1 and 2.0, OpenVG1.0

Fine-Grained Task Switching, Load

Balancing, and Power Management

Programmable High-Quality Image Anti-

Aliasing

– General Purpose Memory Controller (GPMC)

•

16-Bit-Wide Multiplexed Address and

Data Bus

Up to 8 Chip-Select Pins with 128-MB

Address Space per Chip-Select Pin

Glueless Interface to NOR Flash, NAND

Flash (with ECC Hamming Code

– Fully Software-Compatible with ARM9™

– Commercial and Extended Temperature

Grades

• ARM Cortex-A8 Core

– ARMv7 Architecture

Calculation), SRAM, and Pseudo-SRAM

•

Flexible Asynchronous Protocol Control

for Interface to Custom Logic (FPGA,

CPLD, ASICs, and so forth)

Nonmultiplexed Address and Data Mode

(Limited 2-KB Address Space)

•

TrustZone®

Thumb®-2

MMU Enhancements

– In-Order, Dual-Issue, Superscalar

Microprocessor Core

– NEON Multimedia Architecture

– Over 2x Performance of ARMv6 SIMD

– Supports Both Integer and Floating-Point

SIMD

– Jazelle® RCT Execution Environment

Architecture

– Dynamic Branch Prediction with Branch

Target Address Cache, Global History

Buffer, and 8-Entry Return Stack

• System Direct Memory Access (sDMA)

Controller (32 Logical Channels with

Configurable Priority)

• Camera Image Signal Processor (ISP)

– CCD and CMOS Imager Interface

– Memory Data Input

– BT.601 (8-Bit) and BT.656 (10-Bit) Digital

YCbCr 4:2:2 Interface

– Glueless Interface to Common Video

Decoders

– Resize Engine

– Embedded Trace Macrocell (ETM) Support

for Noninvasive Debug

•

Resize Images From 1/4x to 4x

Separate Horizontal and Vertical Control

• ARM Cortex-A8 Memory Architecture:

• Display Subsystem

– 16-KB Instruction Cache (4-Way Set-

Associative)

– Parallel Digital Output

– 16-KB Data Cache (4-Way Set-Associative)

•

Up to 24-Bit RGB

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

All trademarks are the property of their respective owners.

2

PRODUCTION DATA information is current as of publication date. Products conform to

specifications per the terms of the Texas Instruments standard warranty. Production

processing does not necessarily include testing of all parameters.

OMAP3515, OMAP3503

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•

HD Maximum Resolution

Supports Up to 2 LCD Panels

Support for Remote Frame Buffer

Interface (RFBI) LCD Panels

– Three Master and Slave High-Speed Inter-

Integrated Circuit (I²C) Controllers

• Removable Media Interfaces:

– Three Multimedia Card (MMC)/Secure Digital

(SD) with Secure Data I/O (SDIO)

• Comprehensive Power, Reset, and Clock

Management

– 2 10-Bit Digital-to-Analog Converters (DACs)

Supporting:

•

Composite NTSC and PAL Video

Luma and Chroma Separate Video (S-

Video)

– SmartReflex™ Technology

– Dynamic Voltage and Frequency Scaling

(DVFS)

– Rotation 90-, 180-, and 270-Degrees

– Resize Images From 1/4x to 8x

– Color Space Converter

• Test Interfaces

– IEEE 1149.1 (JTAG) Boundary-Scan

Compatible

– ETM Interface

– 8-Bit Alpha Blending

• Serial Communication

– Serial Data Transport Interface (SDTI)

• 12 32-Bit General-Purpose Timers

• 2 32-Bit Watchdog Timers

• 1 32-Bit 32-kHz Sync Timer

• Up to 188 General-Purpose I/O (GPIO) Pins

(Multiplexed with Other Device Functions)

– 5 Multichannel Buffered Serial Ports

(McBSPs)

•

512-Byte Transmit and Receive Buffer

(McBSP1, McBSP3, McBSP4, and

McBSP5)

•

5-KB Transmit and Receive Buffer

(McBSP2)

SIDETONE Core Support (McBSP2 and

McBSP3 Only) For Filter, Gain, and Mix

Operations

• 65-nm CMOS Technologies

• Package-On-Package (POP) Implementation for

Memory Stacking (Not Available in CUS

Package)

•

Direct Interface to I2S and PCM Device

and TDM Buses

128-Channel Transmit and Receive Mode

• Discrete Memory Interface (Not Available in

CBC Package)

• Packages:

– Four Master or Slave Multichannel Serial

Port Interface (McSPI) Ports

– High-, Full-, and Low-Speed USB OTG

Subsystem (12- and 8-Pin ULPI Interface)

– High-, Full-, and Low-Speed Multiport USB

Host Subsystem

– 515-pin s-PBGA Package (CBB Suffix),

.5-mm Ball Pitch (Top), .4-mm Ball Pitch

(Bottom)

– 515-pin s-PBGA Package (CBC Suffix),

.65-mm Ball Pitch (Top), .5-mm Ball Pitch

(Bottom)

•

12- and 8-Pin ULPI Interface or 6-, 4-, and

3-Pin Serial Interface

– 423-pin s-PBGA Package (CUS Suffix),

.65-mm Ball Pitch

•

Supports Transceiverless Link Logic

(TLL)

• 1.8-V I/O and 3.0-V (MMC1 Only),

0.985-V to 1.35-V Adaptive Processor Core

Voltage

– One HDQ™/1-Wire® Interface

0.985-V to 1.35-V Adaptive Core Logic Voltage

Note: These are default Operating Performance

Point (OPP) voltages and could be optimized to

lower values using SmartReflex AVS.

– Three UARTs (One with Infrared Data

Association [IrDA] and Consumer Infrared

[CIR] Modes)

1.2 Applications

•

Portable Navigation Devices

Portable Media Player

Digital Video Camera

Portable Data Collection

Point-of-Sale Devices

Gaming

Web Tablet

Smart White Goods

Smart Home Controllers

2

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1.3 Description

OMAP3515 and OMAP3503 devices are based on the enhanced OMAP 3 architecture.

The OMAP 3 architecture is designed to provide best-in-class video, image, and graphics processing

sufficient to support the following:

•

Streaming video

Video conferencing

High-resolution still image

The device supports high-level operating systems (HLOSs), such as:

•

Linux®

Windows® CE

Android™

This OMAP device includes state-of-the-art power-management techniques required for high-performance

mobile products.

The following subsystems are part of the device:

•

Microprocessor unit (MPU) subsystem based on the ARM Cortex-A8 microprocessor

PowerVR SGX subsystem for 3D graphics acceleration to support display (OMAP3515 device only)

Camera image signal processor (ISP) that supports multiple formats and interfacing options connected

to a wide variety of image sensors

•

Display subsystem with a wide variety of features for multiple concurrent image manipulation, and a

programmable interface supporting a wide variety of displays. The display subsystem also supports

NTSC and PAL video out.

Level 3 (L3) and level 4 (L4) interconnects that provide high-bandwidth data transfers for multiple

initiators to the internal and external memory controllers and to on-chip peripherals

The device also offers:

•

A comprehensive power- and clock-management scheme that enables high-performance, low-power

operation, and ultralow-power standby features. The device also supports SmartReflex adaptative

voltage control. This power-management technique for automatic control of the operating voltage of a

module reduces the active power consumption.

•

Memory-stacking feature using the package-on-package (POP) implementation (CBB and CBC

packages only)

OMAP3515 and OMAP3503 devices are available in a 515-pin s-PBGA package (CBB suffix), 515-pin s-

PBGA package (CBC suffix), and a 423-pin s-PBGA package (CUS suffix). Some features of the CBB and

CBC packages are not available in the CUS package. (See Table 1-1 for package differences).

This data manual presents the electrical and mechanical specifications for the OMAP3515 and

OMAP3503 applications processors. The information in this data manual applies to both the commercial

and extended temperature versions of the OMAP3515 and OMAP3503 applications processors unless

otherwise indicated. This data manual consists of the following sections:

•

Section 2, Terminal Description: assignment, electrical characteristics, multiplexing, and functional

description

•

Section 3, Electrical Characteristics: power domains, operating conditions, power consumption, and

DC characteristics

•

Section 4, Clock Specifications: input and output clocks, DPLL and DLL

Section 5, Video DAC Specifications

Section 6, Timing Requirements and Switching Characteristics

Section 7, Package Characteristics: thermal characteristics, device nomenclature, and mechanical data

for available packaging

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1.4 Functional Block Diagram

Figure 1-1 shows the functional block diagram of the OMAP3515 and OMAP3503 applications processors.

OMAP Applications Processor

CVBS

or

S-Video

Camera

(Parallel)

LCD Panel

Parallel

MPU

Subsystem

Amp

TV

Camera

ISP

Image

Capture

Hardware

Image

Pipeline

and

Preview

ARM Cortex-

A8^TMCore

16K/16K L1$

HS USB

Host

(with

USB

TTL)

HS

Dual Output 3-Layer

Display Processor

(1xGraphics, 2xVideo)

Temporal Dithering

SDTV→QCIF Support

POWERVR

SGX^TM

Graphics

Accelerator

(3515 Only)

32

Channel

System

DMA

USB

OTG

L2$

256K

64

Async

64

32

32 32

32

64

32

L3 Interconnect Network-Hierarchial, Performance, and Power Driven

32 64 32 32

SMS:

32

64K

32

L4 Interconnect

112K

SDRAM

Memory

Scheduler/

Rotation

On-Chip

RAM

2KB

Public/

62KB

Secure

On-Chip

ROM

80KB

Secure/

32KB

BOOT

GPMC:

General

Purpose

Memory

Controller

NAND/

System

Controls

PRCM

Peripherals:

3xUART, 3xHigh-Speed I2C,

5xMcBSP

(2x with Sidetone/Audio Buffer)

4xMcSPI, 6xGPIO,

3xHigh-Speed MMC/SDIO,

HDQ/1 Wire,

2xSmartReflex^TM

Control

Module

NOR

Flash,

SRAM

SDRC:

SDRAM

Memory

Controller

2xMailboxes

12xGPTimers, 2xWDT,

32K Sync Timer

External

Peripherals

Interfaces

Emulation

Debug: SDTI, ETM, JTAG,

External and

Stacked Memories

Coresight^TMDAP

Figure 1-1. OMAP3515 and OMAP3503 Device Functional Block Diagram

4

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Table 1-1. Differences Between CBB, CBC, and CUS Packages

FEATURE

CBB PACKAGE

CBC PACKAGE

CUS PACKAGE

For CBB package pin

For CBC package pin

For CUS package pin

Pin Assignments

assignments see Table 2-1, Ball assignments see Table 2-2, Ball assignments see Table 2-3, Ball

Characteristics (CBB Pkg.)

Characteristics (CBC Pkg.)

Characteristics (CUS Pkg.)

Package-On-Package (POP)

Interface

POP interface supported

POP interface not available

Discrete Memory Interface

supported

Discrete Memory Interface not

supported

Discrete Memory Interface

supported

Discrete Memory Interface

Chip-select pins gpmc_ncs1 and

gpmc_ncs2 are not available

Eight chip-select pins available

Four wait pins available

Eight chip-select pins available

GPMC

Wait pins gpmc_wait1 and

gpmc_wait2 are not available

Four wait pins available

The following signals are either

CTS signal is available on 3 pins available on two (double muxed) CTS signal is available on 3 pins

(triple muxed): uart1_cts (AG22 / or three pins (triple muxed):

(triple muxed): uart1_cts (AC19 /

AC2 / AA18), uart1_rts (W6 /

AB19), uart1_tx (E23 / V7 / AC3),

uart1_rx (D24 / W7)

UART1

UART2

McBSP3

W8 / T21), uart1_rts (AH22 /

AA9), uart1_tx (F28 / Y8 / AE7),

uart1_rx (E26 / AA8)

uart1_cts (AE21 / T19 / W2),

uart1_rts (AE22 / R2), uart1_rx

(H3 / H25 / AE4), uart1_tx (L4 /

G26)

The following signals are

available on two pins (double

muxed): uart2_cts (AF6/AB26),

uart2_rts (AE6/AB25), uart2_tx

(AF5/AA25), uart2_rx

The following signals are

available on one pin only:

uart2_cts (V6), uart2_rts (V5),

uart2_tx (W4), uart2_rx (V4)

available on two pins (double

muxed): uart2_cts (Y24/P3),

uart2_rts (AA24/N3), uart2_tx

(AD22/U3), uart2_rx (AD21/W3)

(AE5/AD25)

The following signals are

available on three pins (triple

The following signals are

available on two pins (triple

The following signals are

available on two pins only

(double muxed): mcbsp3_dx

(V6/W18), mcbsp3_dr (V5/Y18),

mcbsp3_clkx (W4/V18), and

mcbsp3_fsx (V4/AA19)

muxed): mcbsp3_dx (AF6 / AB26 muxed): mcbsp3_dx (U17/ Y24/

/ V21), mcbsp3_dr (AE6 / AB25 / P3), mcbsp3_dr (T20/ AA24 /

U21), mcbsp3_clkx (AF5 / AA25 / N3), mcbsp3_clkx (T17/ AD22 /

W21), and mcbsp3_fsx (AE5 /

AD25 / K26)

U3), mcbsp3_fsx (P20/ AD21 /

W3)

The following signals are

available on three pins (triple

muxed): gpt8_pwm_evt (N8 /

AD25 / V3), gpt9_pwm_evt (T8 / (C5/AD21/V9), gpt9_pwm_evt

AB26 / Y2), gpt10_pwm_evt (R8 (B4/W8/Y24),

/ AB25 / Y3), and

The following signals are

available on three pins (triple

muxed): gpt8_pwm_evt

The following signals are

available on two pins only

(double muxed): gpt8_pwm_evt

(G4/M4), gpt9_pwm_evt (F4/N4),

gpt10_pwm_evt (G5/N3), and

gpt11_pwm_evt (F3/M5)

GP Timer

McBSP4

gpt10_pwm_evt(C4/U8/AA24),

gpt11_pwm_evt (P8 / AA25 / Y4) gpt11_pwm_evt(B5/V8/AD22)

The following signals are

available on two pins (double

muxed): mcbsp4_clkx (T8/AE1), muxed): mcbsp4_clkx (B4 / V3),

mcbsp4_dr (R8/AD1),

mcbsp4_dx (P8/AD2),

mcbsp4_fsx (N8/AC1)

The following signals are

available on two pins (double

The following signals are

available on one pin only:

mcbsp4_clkx (F4), mcbsp4_dr

(G5), mcbsp4_dx (F3),

mcbsp4_fsx (G4)

mcbsp4_dr (C4 / U4),

mcbsp4_dx (B5 / R3),

mcbsp4_fsx (C5 / T3)

HSUSB3_TLL

MM_FSUSB3

Supported

Not supported

Four chip-select pins are

available

Four chip-select pins are

available

Chip-select pins mcspi1_cs1 and

mcspi_cs2 are not available

McSPI1

The following signals are

available on two pins (double

muxed): mmc3_cmd (AC3 /

AE10), and mmc3_clk (AB1 /

AF10)

The following signals are

available on two pins (double

muxed): mmc3_cmd (R8 / AB3), mmc3_cmd (AD3), and

mmc3_clk (R9 / AB2) mmc3_clk (AC1)

The following signals are

available on one pin only:

MMC3

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Table 1-1. Differences Between CBB, CBC, and CUS Packages (continued)

FEATURE

CBB PACKAGE

CBC PACKAGE

CUS PACKAGE

A maximum of 170 GPIO pins

are supported.

The following GPIO pins are not

available: gpio_112, gpio_113,

gpio_114, gpio_115, gpio_52,

gpio_53, gpio_63, gpio_64,

gpio_144, gpio_145, gpio_146,

gpio_147, gpio_152, gpio_153,

gpio_154, gpio_155, gpio_175,

and gpio_176.

A maximum of 188 GPIO pins

are supported.

A maximum of 188 GPIO pins

are supported.

GPIO

Pin muxing restricts the total

number of GPIO pins available at

one time. For more details, see

Table 2-4, Multiplexing

Characteristics (CUS Pkg.).

6

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SPRS505H –FEBRUARY 2008–REVISED OCTOBER 2013

1

OMAP3515 and OMAP3503 Applications

4.2 Output Clock Specifications ....................... 139

4.3 DPLL and DLL Specifications ..................... 141

VIDEO DAC SPECIFICATIONS .................... 147

5.1 Interface Description .............................. 147

Processors ............................................... 1

1.1 Features ............................................. 1

1.2 Applications .......................................... 2

1.3 Description ........................................... 3

1.4 Functional Block Diagram ........................... 4

5

6

5.2

Electrical Specifications Over Recommended

Operating Conditions .............................. 149

5.3

Analog Supply (vdda_dac) Noise Requirements . 151

Revision History .............................................. 8

2

5.4 External Component Value Choice ............... 152

TIMING REQUIREMENTS AND SWITCHING

TERMINAL DESCRIPTION ............................. 9

2.1 Terminal Assignment ................................ 9

2.2 Pin Assignments .................................... 13

2.3 Ball Characteristics ................................. 26

2.4 Multiplexing Characteristics ........................ 85

2.5 Signal Description .................................. 93

ELECTRICAL CHARACTERISTICS ............... 118

3.1 Power Domains ................................... 118

3.2 Absolute Maximum Ratings ....................... 120

3.3 Recommended Operating Conditions ............. 122

3.4 DC Electrical Characteristics ...................... 124

3.5 Core Voltage Decoupling ......................... 127

3.6 Power-up and Power-down ....................... 129

CLOCK SPECIFICATIONS .......................... 133

4.1 Input Clock Specifications ......................... 134

CHARACTERISTICS ................................. 153

6.1 Timing Test Conditions ........................... 153

6.2 Interface Clock Specifications ..................... 153

6.3 Timing Parameters ................................ 154

6.4 External Memory Interfaces ....................... 155

6.5 Video Interfaces ................................... 184

6.6 Serial Communications Interfaces ................ 201

6.7 Removable Media Interfaces ...................... 234

6.8 Test Interfaces .................................... 249

PACKAGE CHARACTERISTICS ................... 255

7.1 Package Thermal Resistance ..................... 255

7.2 Device Support .................................... 255

3

7

4

Contents

7

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Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

This data manual revision history table highlights the technical changes made to the SPRS505F device-

specific data manual to make it an SPRS505H revision.

SEE

ADDITIONS/MODIFICATIONS/DELETIONS

•

Added Android to list of supported Operating Systems

General

3D Mobile Gaming not supported

Updated/Changed incorrect cross-references

Section 1.2

Applications

•

Created Applications section

Updated/Changed supported applications

Table 1-1

•

Moved table to appear after the Functional Block Diagram

Differences Between

CBB, CBC, and

CUS Packages

Updated/Changed the GPIO FEATURE row CUS PACKAGE column "For more details, see ..." cross-

reference to Multiplexing Characteristics (CUS Pkg.) table

Section 3.3

Recommended

Operating

•

Added the paragraph, "The information in the notes below....."

Conditions

Section 6.5.1

Camera Interface

Updated/Changed the paragraph, "The camera subsystem provides..."

8

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2 TERMINAL DESCRIPTION

2.1 Terminal Assignment

Figure 2-1 through Figure 2-5 show the ball locations for the 515- and 423- ball plastic ball grid array (s-

PBGA) packages. through Table 2-25 indicate the signal names and ball grid numbers for both packages.

Note: There are no balls present on the top of the 423-ball s-PBGA package.

AH

AG

AF

AE

AD

AC

AB

AA

Y

W

V

U

T

R

P

N

M

L

K

J

H

G

F

E

D

C

B

A

1

3

5

7

9

11

13

17

19

21

23

25

27

15

2

4

6

8

10

12

14

16

18

20

22

24

26

28

030-001

Figure 2-1. OMAP3515/03 Applications Processor CBB s-PBGA-N515 Package (Bottom View)

TERMINAL DESCRIPTION

9

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AC

AB

AA

Y

W

V

U

T

R

P

N

M

L

K

J

H

G

F

E

D

C

B

A

23

19

17

15

13

11

9

7

5

3

1

21

22

20

18

16

14

12

10

8

6

4

2

030-002

Balls A1, A2, A22, A23, AB1, AB2, AB22, AB23, AC1, AC2, AC22, AC23, B1, B2, B22, and B23 are unused.

Figure 2-2. OMAP3515/03 Applications Processor CBB s-PBGA-N515 Package (Top View)

10

TERMINAL DESCRIPTION

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AF

AE

AD

AC

AB

AA

Y

W

V

U

T

R

P

N

M

L

K

J

H

G

F

E

D

C

B

A

1

2 3 4 5 7 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

6 8

Figure 2-3. OMAP3515/03 Applications Processor CBC s-PBGA-515 Package (Bottom View)

TERMINAL DESCRIPTION

11

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AA

Y

W

V

U

T

R

P

N

M

L

K

J

H

G

F

E

D

C

B

A

21 20 19 18 17 16 15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

Figure 2-4. OMAP3515/03 Applications Processor CBC s-PBGA-515 Package (Top View)

12

TERMINAL DESCRIPTION

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AD

AC

AB

AA

Y

W

V

U

T

R

P

N

M

L

K

J

H

G

F

E

D

C

B

A

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

Figure 2-5. OMAP3515/03 Applications Processor CUS s-PBGA-N423 Package (Bottom View)

2.2 Pin Assignments

2.2.1 Pin Map (Top View)

The following pin maps show the top views of the 515-pin sPBGA package [CBB], the 515-pin sPBGA

package [CBC], and the 423-pin sPBGA package [CUS] pin assignments in four quadrants (A, B, C, and

D).

TERMINAL DESCRIPTION

13

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1

2

3

4

5

6

7

8

9

10

11

12

13

14

pop_a2_a2

vss

sdrc_a0

vdds_mem sdrc_dqs0

sdrc_d5 vdds_mem sdrc_d7

sdrc_dm0 vdds_mem sdrc_d6

sdrc_dqs2 sdrc_d21 vdds_mem sdrc_clk

sdrc_d17 sdrc_dm2 vdds_mem sdrc_d22

sdrc_nclk

sdrc_d9

sdrc_d8

sdrc_d23

A

pop_a1_a1

pop_b1_b1

sdrc_a8

vss

sdrc_a2

sdrc_a6

sdrc_a10

vss

sdrc_a1 vdds_mem sdrc_d2

B

C

D

E

F

G

H

J

sdrc_a7

sdrc_a11

sdrc_a13

sdrc_a4

sdrc_a9

vss

sdrc_a3

sdrc_a5

sdrc_d1

sdrc_d0

vss

sdrc_d3

sdrc_d4

vss

sdrc_d18 sdrc_d20

vss

sdrc_a12

sdrc_a14

vdd_core

sdrc_d16

sdrc_d19

gpmc_nadv

_ale

gpmc_nwe

vdds_mem vdds_mem

gpmc_nbe0

_cle

gpmc_noe

NC

gpmc_ncs0

gpmc_nwp

sdrc_ba0 sdrc_ba1 sdrc_ncs0 sdrc_ncs1 sdrc_ncas sdrc_nras

gpmc_d8 gpmc_ncs1 vdd_core

vdd_mpu vdd_mpu vdd_mpu

gpmc_wait3

gpmc_wait2

vss

vdds_mem vdds_mem

vss

vdd_core

vdd_mpu

vss

vdd_mpu

gpmc_d0

gpmc_d1

gpmc_d9 gpmc_a10 gpmc_a4

vdd_mpu

K

L

gpmc_d2

gpmc_a9

gpmc_a3

gpmc_wait1 vdd_mpu vdd_mpu

pop_y23

_m1

gpmc_wait0 vdd_mpu

vdd_mpu

pop_k2_m2 gpmc_a8

gpmc_a2

gpmc_a1

M

N

pop_u1_n1 pop_l2_n2 gpmc_a7

gpmc_ncs7

gpmc_ncs6

vss

vdd_mpu

vss

gpmc_d10 gpmc_d3

vss

P

A. Top Views are provided to assist in hardware debugging efforts.

Figure 2-6. CBB Pin Map [Quadrant A - Top View]

14

TERMINAL DESCRIPTION

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SPRS505H –FEBRUARY 2008–REVISED OCTOBER 2013

15

16

17

18

19

20

21

22

23

24

25

26

27

28

pop_a12

_a15

pop_a22

_a27

pop_a23

_a28

cam_vs

sdrc_dm1 sdrc_dqs1 vdds_mem sdrc_d25 sdrc_dqs3 sdrc_d29 vdds_mem

cam_hs

cam_d5

vss

A

pop_b12

_b15

pop_b23

_b28

cam_wen

cam_fld

sdrc_d11

sdrc_d14 vdds_mem sdrc_d26

sdrc_d27

sdrc_dm3

sdrc_d28

sdrc_d30 vdds_mem

cam_d2

cam_d3

cam_d10 cam_xclkb

cam_xclka cam_d11

vss

B

C

D

E

F

G

H

J

sdrc_d10 vdds_mem sdrc_d13

vdd_core vdds_mem sdrc_d12

sdrc_d24

sdrc_d15

vss

sdrc_d31

vss

cam_pclk vdds_mem

vdd_core vdd_core

cam_d4 cam_strobe dss_hsync dss_vsync dss_pclk

vdd_core dss_data6 dss_acbias dss_data20

dss_data8 dss_data7

vdds

dss_data16 dss_data9

vss

vdds_mem

vdds

uart3_tx

_irtx

uart3_cts

_rctx

uart3_rts

_sd

uart3_rx

_irrx

sdrc_nwe sdrc_cke0 sdrc_cke1

dss_data19 dss_data18 dss_data17

vdd_core

vss

vdd_core

vss

i2c1_sda

i2c1_scl

vdd_mpu

hdq_sio dss_data21 pop_h22 pop_k1_j28

_j27

vdds_dpll

_dll

vdd_core

vss

vdds_mmc1 mcbsp1_fsx cam_d8

cam_d6

cam_d7

K

L

cap_vdd

_sram_core

vss

vdd_core

vss

cam_d9

pop_k22

_m26

vss

vdd_core

mcbsp2_dx

mmc1_cmd

vss

M

N

mcbsp2

_clkx

mmc1_dat2 mmc1_dat1 mmc1_dat0 mmc1_clk

vdd_core vdd_core

vdds_

mmc1a

vss

vdd_core mcbsp2_fsx

mmc1_dat5 mmc1_dat4 mmc1_dat3

P

Figure 2-7. CBB Pin Map [Quadrant B - Top View]

TERMINAL DESCRIPTION

15

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www.ti.com

gpmc_d11 gpmc_d12 gpmc_a6 vdds_mem

R

gpmc_ncs5

vdd_mpu

gpmc_d4 gpmc_d13 gpmc_a5 gpmc_clk

gpmc_ncs4

gpmc_ncs3

T

vdd_mpu

vss

vdd_mpu

vdds_mem

gpmc_d5

vss

gpmc_nbe1

U

NC

cap_vdd

_sram

_mpu

mcspi2

_cs1

gpmc_d6

gpmc_ncs2

uart1_cts

uart1_rx

vss

V

W

gpmc_d14 gpmc_d7

vss

vdd_mpu

vdds

vdd_mpu

vss

mcspi2

_somi

mcspi2

_cs0

mcspi2_

simo

gpmc_d15

vdd_mpu

Y

pop_aa1

_aa1

pop_aa2

_aa2

mcspi1

_somi

vdds_wkup

_bg

mcspi2_clk

mcspi1_clk

uart1_tx

uart1_rts jtag_emu1 jtag_emu0 jtag_rtck

jtag_tck

AA

AB

AC

AD

AE

AF

AG

mcspi1

_cs2

mcspi1

_cs3

mcspi1

_simo

mcbsp4

_fsx

mcspi1

_cs0

mcspi1_cs1 vdd_core

mcbsp4_dr mcbsp4_dx

vdds

mmc2_dat4 mcbsp3_fsx

mcbsp3

_clkx

etk_d10

etk_ctl

etk_clk

etk_d3

etk_d6

mcbsp4

_clkx

mmc2_clk mmc2_dat7

mcbsp3_dr

vdds

vdd_core

etk_d8

etk_d4

etk_d0

vss

sys_boot2

i2c3_scl

pop_ac8

_af1

pop_u2

_af2

mmc2_dat6 mmc2_dat3

mcbsp3_dx etk_d11

vdds

pop_ab1

_ag1

pop_ab8

_ag10

pop_ab9

_ag11

pop_ab11

_ag13

vss

mmc2_dat2 mmc2_cmd

vss

etk_d12

etk_d14

etk_d9

etk_d1

i2c3_sda

pop_ac2

_ah2

pop_ac13 pop_ac9

_ah11

pop_ac11

_ah13

pop_ac1

_ah1

mmc2_dat5 mmc2_dat1 mmc2_dat0 vdds_mem etk_d13

etk_d15

8

etk_d5

9

etk_d2

12

etk_d7

14

AH

_ah10

1

2

3

4

5

6

7

10

11

13

Figure 2-8. CBB Pin Map [Quadrant C - Top View]

16

TERMINAL DESCRIPTION

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SPRS505H –FEBRUARY 2008–REVISED OCTOBER 2013

mmc1_dat7

mcbsp2_dr

mcbsp_clks

vss

mmc1_dat6 hsusb0_dir

vss

R

vdd_core

vss

hsusb0_stp hsusb0_nxt hsusb0

_data0

hsusb0_clk

T

hsusb0

_data3

vdd_core

hsusb0

_data4

hsusb0

_data2

hsusb0

_data1

U

vdd_core

vss

mcbsp1_dr

mcbsp1_dx

vdd_core

vdda_dac

vss

hsusb0

_data7

hsusb0

_data6

hsusb0

_data5

V

mcbsp1

_clkx

tv_vref

tv_vfb2

tv_vfb1

tv_out2

tv_out1

vdd_mpu vdds_sram

vss

vdd_core

vss

vdd_core

W

Y

vss

vssa_dac

vdd_core

jtag_tdo

mcbsp1

_clkr

vdd_mpu

jtag_tms

_tmsc

jtag_tdi

vss

dss_data15

cap_vdd

_wkup

vdds_dpll

_per

jtag_ntrst

mcbsp1_fsr

uart2_tx

uart2_rts

dss_data14 AA

uart2_cts dss_data13 dss_data12

AB

AC

AD

AE

AF

AG

dss_data22 dss_data23

vss

uart2_rx

sys_32k

i2c4_scl dss_data11 dss_data10

i2c2_sda

i2c2_scl

vdds

vss

sys_xtalin vdd_core vdd_core

sys_xtalout sys_boot3 sys_boot4

vss

sys_boot5 sys_clkout2

vdds

vdd_core

i2c4_sda

vdds

pop_aa23

_ae28

sys_boot6

vdds

sys_off

_mode

sys

_nreswarm

sys_clkreq sys_nirq

pop_aa22

_af27

pop_h23

_af28

pop_ab13

_ag15

pop_ab23

_ag28

dss_data2

cam_d0

gpio_114 gpio_112

vdds

dss_data0

dss_data4 sys_clkout1 sys_boot1

vdds

pop_l1

_ah15

pop_ac22 pop_ac23

_ah28

sys

_nrespwron

dss_data3

23

pop_ac14

_ah16

cam_d1

17

gpio_115 gpio_113 cap_vdd_d

vss

21

dss_data1

22

dss_data5

24

sys_boot0

26

AH

_ah27

15

16

18

19

20

25

27

28

Figure 2-9. CBB Pin Map [Quadrant D - Top View]

TERMINAL DESCRIPTION

17

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1

2

3

4

5

6

7

8

9

10

11

12

13

A

pop_a1_a1

gpmc_ncs2

vss

NC

vss

gpmc_wait2 gpmc_ncs4 gpmc_ncs6 gpmc_ncs3

sys_boot2 gpmc_ncs5 gpmc_ncs7 gpmc_wait3

B

C

D

E

F

G

H

J

NC

vss

NC

vss

NC

vss

NC

i2c2_sda

i2c2_scl

vdds

gpmc_a9 gpmc_a10 sys_boot1 sys_boot6

vdd_mpu

NC

vdds

NC

gpmc_a7

gpmc_a5

gpmc_a8 sys_boot3 sys_boot4

gpmc_a6 sys_boot0

gpmc_a4 sys_boot5

NC

vdds

vss

NC

vss

NC

vss

vdd_core

NC

vdd_mpu

NC

vss

vdd_mpu

NC

vdd_mpu

gpmc_a2

gpmc_a3

uart1_rx

NC

vss

gpmc_nbe1 gpmc_a1

NC

vdd_mpu

vss

gpmc_nbe0 mmc2_dat7

_cle

vdds_dpll

K

L

NC

pop_j1_l1 gpmc_d14 mmc2_dat6 uart1_tx

vdd_mpu

vdds

gpmc_nwe gpmc_d15 mmc2_dat5

gpmc_clk gpmc_noe mcbsp3_dr

vdds

vss

vdd_mpu

vss

vdd_core

M

N

cap_vdd

_sram_mpu

vdd_mpu vdd_mpu

A. Top Views are provided to assist in hardware debugging efforts.

Figure 2-10. CBC Pin Map [Quadrant A - Top View]

18

TERMINAL DESCRIPTION

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SPRS505H –FEBRUARY 2008–REVISED OCTOBER 2013

14

15

16

17

18

19

20

21

22

23

24

25

26

pop_b16

_a20

pop_a20

_a25

pop_a21

_a26

cam_wen

NC

vdds

cam_d2

A

NC

pop_b21

_b26

cam_fld

cam_hs

cam_vs

NC

cam_d3

vss

NC

vss

NC

vss

NC

vss

NC

vss

B

C

D

E

F

G

H

J

cam_d5 cam_xclka cam_pclk

vdd_core

cam_d4

vdds

cam_d10 cam_strobe

cam_xclkb cam_d11

dss_data20 dss_acbias

dss_pclk dss_data6

dss_data7 dss_data8

i2c1_scl dss_data9

uart3_cts

_rctx

uart3_rts

_sd

uart3_tx

_irtx

vdd_core

vss

vdd_core

NC

vss

NC

vss

NC

vss

uart3_rx

_irrx

NC

hdq_sio

i2c1_sda

dss_hsync

vdds

vss

vdds

cap_vdd

_sram

_core

cap_vdd

_wkup

pop_h21

_k26

mmc1_dat2

mmc1_cmd

vss

NC

vss

K

L

dss_data16 dss_data17

vdds

vdd_core mmc1_dat1 mmc1_dat0 mmc1_dat4

dss_data18 dss_vsync dss_data19

NC

M

N

vss

mmc1_clk mmc1_dat3

vdds_mmc1 dss_data21 cam_d8

cam_d9

NC

Figure 2-11. CBC Pin Map [Quadrant B - Top View]

TERMINAL DESCRIPTION

19

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www.ti.com

mcspi1

_simo

mcspi1

_somi

vdd_mpu

mcspi1_clk

gpmc_d13

vss

NC

P

R

mcbsp3_dx

NC

vss

uart1_rts mcbsp4_dx

mcspi1_cs0 mcspi1_cs1 mcspi1_cs2 mmc2_cmd

gpmc_d10 pop_n2_t2 mcbsp4_fsx

vdds

vdd_core mcspi1_cs3 mmc2_dat1 mmc2_dat0

T

U

mcspi2

_somi

gpmc_d12 gpmc_d11

mcbsp3 mcbsp4_dr

_clkx

vdd_mpu

mcspi2_clk

vss

mmc2_dat3 mmc2_dat2 vdd_mpu vdds_sram vdd_mpu

mcbsp4

_clkx

sys_off

_mode

sys_

nrespwron

vdd_mpu

gpmc_d8

vss

etk_d9

mcspi2_cs0 mcspi2_cs1 mmc2_dat4

V

NC

mcspi2

_simo

uart1_cts mcbsp3_fsx

vss

mmc2_clk sys_clkout2

jtag_rtck

jtag_tdo

vdd_mpu

W

NC

gpmc_d9 pop_t2_y2

etk_d4

etk_d3

etk_ctl

etk_d0

etk_d2

etk_d6

vdd_core

vss

vdd_core

Y

vdds

vdd_mpu

gpmc_d1

etk_d5

gpmc_d0

etk_clk

etk_d8

AA

AB

AC

AD

AE

i2c3_scl

i2c3_sda

etk_d1

vss

gpmc_d3

gpmc_ncs1

NC

gpmc_d2

etk_d7

gpmc_d7 gpmc_nwp

gpmc_wait1

gpmc_ncs0

NC

vss

gpmc_wait0

vdds

NC

sys_

nreswarm

gpmc_nadv

_ale

gpmc_d6

gpmc_d4

gpmc_d5

etk_d12

NC

pop_w2

_ae2

etk_d10

vss

etk_d15

vdds

pop_aa1

_af1

pop_y2

_af4

pop_aa6

_af5

pop_y7

_af8

pop_y9

_af10

pop_aa10 pop_aa11

_af13

etk_d11

6

etk_d13

7

etk_d14

9

NC

2

NC

3

NC

11

AF

_af12

1

4

5

8

10

12

13

Figure 2-12. CBC Pin Map [Quadrant C - Top View]

20

TERMINAL DESCRIPTION

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SPRS505H –FEBRUARY 2008–REVISED OCTOBER 2013

vdds

_mmc1a

mmc1_dat5 mmc1_dat6 mmc1_dat7 mcbsp1_fsx

cam_d6

cam_d7

NC

P

R

mcbsp2

_clkx

vss

mcbsp2_dx vdd_core

NC

vss

mcbsp1

_clkx

mcbsp

mcbsp2_dr

mcbsp1_dr

_clks

vss

vdds

tv_vfb2

NC

T

U

vdds_dpll

_per

mcbsp2

_fsx

mcbsp1

hsusb0_stp

_clkr

pop_p21

_u26

jtag_ntrst

jtag_tdi mcbsp1_dx

NC

tv_vref

vss

jtag_tms

_tmsc

hsusb0

_data2

hsusb0

hsusb0_dir

jtag_tck

sys_nirq mcbsp1_fsr

hsusb0

_data4

vssa_dac vdda_dac

tv_out2

tv_out1

vss

V

_data0

vdds_wkup

_bg

hsusb0

_data3

sys_clkreq i2c4_sda

hsusb0_nxt hsusb0_clk

vdds

tv_vfb1

W

hsusb0

_data7

hsusb0

_data5

hsusb0

_data6

hsusb0

_data1

jtag_emu1 jtag_emu0

vss

uart2_cts dss_data13

NC

Y

uart2_rts dss_data12 dss_data14

AA

AB

AC

AD

AE

vss

dss_data23 dss_data15

dss_data22 dss_data10

vdds

vss

vdd_core

uart2_rx

NC

vss

vdds

NC

vdds

NC

i2c4_scl

gpio_113

cam_d0

gpio_112

gpio_115

vdds

uart2_tx

dss_data4 dss_data5

vss

dss_data11

vdds

pop_y20

_ae25

pop_y21

_ae26

sys_clkout1 cam_d1

gpio_114 cap_vdd_d sys_32k dss_data0 dss_data1 dss_data2 dss_data3

pop_aa12 pop_aa13 pop_aa14

_af14

pop_y14 pop_aa17

_af18

pop_y17

_af21

pop_aa19

_af22

pop_y19

_af24

pop_aa20 pop_aa21

_af25

sys_xtalin sys_xtalout

vss

23

AF

_af15

_af16

_af17

_af26

14

15

16

17

18

19

20

21

22

24

25

26

Figure 2-13. CBC Pin Map [Quadrant D - Top View]

TERMINAL DESCRIPTION

21

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1

2

3

4

5

6

7

8

9

10

11

12

A

NC

sdrc_a0

sdrc_dqs0

sdrc_dm2 sdrc_dqs2

sdrc_clk

sdrc_nclk

NC

sdrc_a4

sdrc_a3

sdrc_a1

sdrc_d3

sdrc_d1

sdrc_dm0

sdrc_d2

sdrc_a2

sdrc_d7

sdrc_d6

sdrc_d0

sdrc_a10

sdrc_a13

sdrc_a12

sdrc_d18

sdrc_d19

sdrc_d16

sdrc_d4

sdrc_a9

sdrc_d21

sdrc_d20

sdrc_d5

sdrc_a8

sdrc_d8

sdrc_d10

sdrc_d9

sdrc_d22

sdrc_d17

vdd_core

vss

B

C

D

E

F

G

H

J

NC

gpmc_wait0 gpmc_wait3 sdrc_a5

gpmc_ncs3 sdrc_a10

gpmc_nwp gpmc_ncs0 sdrc_a6

gpmc_ncs4

gpmc_nadv gpmc_noe gpmc_ncs6

_ale

sdrc_a7

sdrc_a14 vdd_mpu

vdd_mpu vdd_mpu

gpmc_a10 gpmc_nwe

gpmc_ncs7 gpmc_ncs5 sdrc_a11

gpmc_a8

vdd_mpu

gpmc_a9 gpmc_ncs1

vdd_mmc1a

vss

gpmc_a7

gpmc_a6

gpmc_a3

gpmc_a5

gpmc_a2

gpmc_a4

gpmc_a1

vdds_mem vdds_mem vdds_mem vdd_mpu vdd_mpu

gpmc_nbe0

_cle

vdds_mem vdds_mem vdds_mem

vss

K

L

gpmc_nbe1 gpmc_d0

gpmc_d1 gpmc_d2

vss

vdd_mpu

vss

vdd_mpu

gpmc_d4

mcspi2_cs1

mcspi2_cs0 vdd_mpu

vdd_mpu

vss

vdd_mpu

M

A. Top Views are provided to assist in hardware debugging efforts.

Figure 2-14. CUS Pin Map [Quadrant A - Top View]

22

TERMINAL DESCRIPTION

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Product Folder Links: OMAP3515 OMAP3503

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SPRS505H –FEBRUARY 2008–REVISED OCTOBER 2013

13

14

15

16

17

18

19

20

21

22

23

24

uart3_cts

_rctx

sdrc_dqs1 sdrc_d14

sdrc_dm1 sdrc_d13

sdrc_d12

sdrc_dm3 sdrc_dqs3

sdrc_ncs0 sdrc_nwe

cam_hs

hdq_sio

A

uart3_rts

_sd

uart3_rx

_irrx

sdrc_d15

sdrc_d26

sdrc_d27

sdrc_d28

sdrc_d30

sdrc_d31 sdrc_ncs1 sdrc_cke0

sdrc_ba0 sdrc_ncas sdrc_cke1

sdrc_ba1 sdrc_nras

cam_d5

cam_xclka

B

C

D

E

F

cam_xclkb uart3_tx

_irtx

sdrc_d11

sdrc_d25 sdrc_d29

sdrc_d24 vdds_mem

vdds_mem vdds_mem

dss_data20 dss_data6

sdrc_d23

cam_vs

dss_hsync dss_data7 dss_data8

cam_wen

cam_d3

cam_d2

cam_d10 dss_vsync dss_data9

vdd_core

vdds_dpll

_dll

dss_data17

dss_data19

cam_d4

cam_d11

dss_pclk

dss_data18

cam_fld

G

H

J

cap_vdd

_sram_core

vdd_core

vss

vdds_mem

vss

cam_pclk cam_strobe dss_acbias dss_data16 cam_d8

vdd_core

vss

vdd_core

vss

i2c1_scl

i2c1_sda dss_data21 cam_d9

cam_d7

vdd_core vdd_core

K

L

vss

mmc1_cmd cam_d6

vdd_core

vdds

vss

mmc1_dat2 mmc1_dat1 mmc1_dat0 mmc1_clk

M

Figure 2-15. CUS Pin Map [Quadrant B - Top View]

TERMINAL DESCRIPTION

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mcspi2

_somi

mcspi2

_somo

mcspi2

_clk

gpmc-d3

N

vdd_mpu

vss

gpmc_d5

gpmc_d7

gpmc_d6

gpmc_d8

P

R

mcspi1

_cs3

mcspi1

_simo

vdd_mpu

vss

gpmc_d11

vdd_mpu

mcspi1

_somi

mcspi1

_clk

mcspi1

_cs0

gpmc_d9 gpmc_d12

vss

T

cap_vdd

_sram_mpu

gpmc_d10 gpmc_d13

vdd_mpu

U

vdds

gpmc_d14 gpmc_d15 mmc2_dat3 mcbsp3_fsx mcbsp3_dr mcbsp3_dx uart1_rx

V

vdds

gpmc_clk mmc2_dat2 mcbsp3_

clkx

uart1_rts

uart1_tx

W

Y

sys_

nreswarm

mmc2_clk mmc2_dat6 mmc2_dat1

sys_clkout1

cap_vdd

_wkup

jtag_tms

_tmsc

sys_

nrespwron

mmc2_dat7 mmc2_dat5

sys_clkout2 jtag_rtck

vdds_sram

sys_boot0

i2c3_sda

AA

AB

AC

mmc2_dat4 mmc2_dat0

mmc2_cmd jtag_tck

jtag_ntrst

etk_d2

jtag_tdo

etk_d11

jtag_tdi

etk_clk

uart1_cts

etk_d10

etk_d8

etk_d4

etk_d1

etk_d6

etk_d12

etk_d14

etk_d5

2

etk_ctl

3

etk_d9

5

etk_d0

6

etk_d3

8

etk_d7

9

etk_d13

11

etk_d15

12

AD

NC

1

4

7

10

Figure 2-16. CUS Pin Map [Quadrant C - Top View]

24

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N

vss

mmc1_dat6 mmc1_dat5 mmc1_dat4 mmc1_dat3 vdds_mmc1

hsusb0_dir mmc1_dat7

vdds

vss

vdds

P

vss

mcbsp2_dx hsusb0_clk hsusb0_nxt hsusb0_stp

vdd_core

vdd_core vdd_core

R

mcbsp2

_clkx

hsusb0

_data7

hsusb0

_data1

hsusb0

_data0

vss

vdd_core

T

hsusb0

_data3

hsusb0

_data2

vss

vdds_dpll

_per

U

vdd_mpu

hsusb0

_data5

vss

mcbsp1 mcbsp2_dr mcbsp2 dss_data22 dss_data15

_fsx

V

vdd_mpu

_clkx

mcbsp1

_dx

mcbsp1

_clkr

hsusb0

_data6

hsusb0

_data4

vss

sys_nirq

i2c4_scl

dss_data23 dss_data14

W

Y

mcbsp1

_dr

sys_clkreq

i2c4_sda

dss_data13 tv_vfb2

tv_vref

vdds_wkup

_bg

mcbsp

_clks

mcbsp1

_fsx

sys_boot6 sys_32k

vssa_dac sys_boot5

tv_out2

AA

AB

mcbsp1

_fsr

vdda_dac

i2c3_scl

cam_d0

cam_d1

dss_data1

dss_data12 tv_vfb1

tv_out1

i2c2_sda

i2c2_scl

sys_boot1 sys_boot4

dss_data0 dss_data3 dss_data5 dss_data10 dss_data11

jtag_emu0 AC

sys_xtalout sys_xtalin

sys_boot2 sys_boot3

dss_data2 dss_data4

jtag_emu1

AD

sys_off_

mode

13

14

15

16

17

18

19

20

21

22

23

24

Figure 2-17. CUS Pin Map [Quadrant D - Top View]

TERMINAL DESCRIPTION

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2.3 Ball Characteristics

through describe the terminal characteristics and the signals multiplexed on each pin for the CBB, CBC,

and CUS packages, respectively. The following list describes the table column headers.

1. BALL BOTTOM: Ball number(s) on the bottom side associated with each signal(s) on the bottom.

2. BALL TOP: Ball number(s) on the top side associated with each signal(s) on the top.

3. PIN NAME: Names of signals multiplexed on each ball (also notice that the name of the pin is the

signal name in mode 0).

Note: through do not take into account subsystem pin multiplexing options. Subsystem pin multiplexing

options are described in Section 2.5, Signal Descriptions.

4. MODE: Multiplexing mode number.

(a) Mode 0 is the primary mode; this means that when mode 0 is set, the function mapped on the pin

corresponds to the name of the pin. There is always a function mapped on the primary mode.

Notice that primary mode is not necessarily the default mode.

Note: The default mode is the mode which is automatically configured on release of the internal

GLOBAL_PWRON reset; also see the RESET REL. MODE column.

(b) Modes 1 to 7 are possible modes for alternate functions. On each pin, some modes are effectively

used for alternate functions, while some modes are not used and do not correspond to a functional

configuration.

5. TYPE: Signal direction

–

I = Input

O = Output

I/O = Input/Output

D = Open drain

DS = Differential

A = Analog

Note: In the safe_mode, the buffer is configured in high-impedance.

6. BALL RESET STATE: The state of the terminal at reset (power up).

–

0: The buffer drives V_OL(pulldown/pullup resistor not activated)

0(PD): The buffer drives V_OLwith an active pulldown resistor.

1: The buffer drives V_OH(pulldown/pullup resistor not activated)

1(PU): The buffer drives V_OHwith an active pullup resistor.

Z: High-impedance

–

L: High-impedance with an active pulldown resistor

H : High-impedance with an active pullup resistor

7. BALL RESET REL. STATE: The state of the terminal at reset release.

–

0: The buffer drives V_OL(pulldown/pullup resistor not activated)

0(PD): The buffer drives V_OLwith an active pulldown resistor.

1: The buffer drives V_OH(pulldown/pullup resistor not activated)

1(PU): The buffer drives V_OHwith an active pullup resistor.

Z: High-impedance

–

L: High-impedance with an active pulldown resistor

H : High-impedance with an active pullup resistor

8. RESET REL. MODE: This mode is automatically configured on release of the internal

GLOBAL_PWRON reset.

9. POWER: The voltage supply that powers the terminal’s I/O buffers.

10. HYS: Indicates if the input buffer is with hysteresis.

11. BUFFER STRENGTH: Drive strength of the associated output buffer.

12. PULL U/D - TYPE: Denotes the presence of an internal pullup or pulldown resistor. Pullup and

pulldown resistors can be enabled or disabled via software.

26

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Note: The pullup/pulldown drive strength is equal to 100 μA except for CBB balls P27, P26, R27, and

R25 and CUS balls N22, N21, N20, and P24, which the pulldown drive strength is equal to 1.8 kΩ.

13. IO CELL: IO cell information.

Note: Configuring two pins to the same input signal is not supported as it can yield unexpected results.

This can be easily prevented with the proper software configuration.

Table 2-1. Ball Characteristics (CBB Pkg.)⁽¹⁾

BALL

BALL TOP PIN NAME

MODE [4]

TYPE [5]

BALL

RESET REL. POWER [9] HYS [10]

BUFFER

PULLUP

IO CELL [13]

BOTTOM [1] [2]

[3]

RESET

STATE [6]

RESET REL. MODE [8]

STATE [7]

STRENG TH /DOWN

(mA) [11]

TYPE [12]

D6

J2

sdrc_d0

sdrc_d1

sdrc_d2

sdrc_d3

sdrc_d4

sdrc_d5

sdrc_d6

sdrc_d7

sdrc_d8

sdrc_d9

sdrc_d10

sdrc_d11

sdrc_d12

sdrc_d13

sdrc_d14

sdrc_d15

sdrc_d16

sdrc_d17

sdrc_d18

sdrc_d19

sdrc_d20

sdrc_d21

sdrc_d22

sdrc_d23

sdrc_d24

sdrc_d25

sdrc_d26

sdrc_d27

sdrc_d28

sdrc_d29

sdrc_d30

sdrc_d31

sdrc_ba0

sdrc_ba1

sdrc_a0

sdrc_a1

sdrc_a2

sdrc_a3

sdrc_a4

sdrc_a5

sdrc_a6

sdrc_a7

sdrc_a8

sdrc_a9

sdrc_a10

sdrc_a11

0

IO

O

L

0

Z

0

vdds_ mem Yes

vdds_ mem No

4

PU/ PD

NA

LVCMOS

C6

J1

B6

G2

C8

G1

C9

F2

A7

F1

B9

D2

A9

D1

C14

B14

C15

B16

D17

C17

B17

D18

D11

B10

C11

D12

C12

A11

B13

D14

C18

A19

B19

B20

D20

A21

B21

C21

H9

B13

A13

B14

A14

B16

A16

B19

A19

B3

A3

B5

A5

B8

A8

B9

A9

B21

A21

D22

D23

E22

E23

G22

G23

AB21

AC21

N22

N23

P22

P23

R22

R23

T22

T23

U22

U23

V22

V23

H10

A4

O

NA

O

NA

B4

O

NA

B3

O

NA

C5

O

NA

C4

O

NA

D5

O

NA

C3

O

NA

C2

O

NA

C1

O

NA

D4

O

NA

D3

O

NA

D2

O

NA

(1) NA in this table stands for "Not Applicable".

TERMINAL DESCRIPTION

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IO CELL [13]

Table 2-1. Ball Characteristics (CBB Pkg.)⁽¹⁾(continued)

BALL

BALL TOP PIN NAME

MODE [4]

TYPE [5]

BALL

RESET REL. POWER [9] HYS [10]

BUFFER

PULLUP

BOTTOM [1] [2]

[3]

RESET

STATE [6]

RESET REL. MODE [8]

STATE [7]

STRENG TH /DOWN

(mA) [11]

TYPE [12]

D1

W22

sdrc_a12

sdrc_a13

sdrc_a14

sdrc_ncs0

sdrc_ncs1

sdrc_clk

0

7

0

7

0

4

7

0

4

7

0

4

7

0

4

7

0

4

7

0

4

7

0

4

7

0

4

7

0

1

O

IO

O

0

1

L

1

H

0

1

0

1

0

7

vdds_ mem No

vdds_ mem Yes

vdds_ mem No

vdds_ mem Yes

4

NA

LVCMOS

E2

W23

Y22

M22

M23

A11

B11

J22

NA

E1

NA

H11

H12

A13

A14

H16

NA

PU/ PD

NA

sdrc_nclk

sdrc_cke0

safe_mode

sdrc_cke1

safe_mode

sdrc_nras

sdrc_ncas

sdrc_nwe

sdrc_dm0

sdrc_dm1

sdrc_dm2

sdrc_dm3

sdrc_dqs0

sdrc_dqs1

sdrc_dqs2

sdrc_dqs3

gpmc_a1

gpio_34

PU/ PD

H17

J23

O

H

1

7

vdds_ mem Yes

4

PU/ PD

LVCMOS

H14

H13

H15

B7

L23

L22

K23

C1

O

1

0

L

1

0

Z

L

0

7

vdds_ mem No

vdds_ mem Yes

4

NA

LVCMOS

O

NA

O

NA

O

NA

A16

B11

C20

A6

A17

A6

O

NA

O

NA

A20

C2

O

NA

IO

O

PU/ PD

A17

A10

A20

N4

B17

B6

B20

AC15

IO

safe_mode

gpmc_a2

gpio_35

M4

L4

AB15

AC16

AB16

AC17

AB17

AC18

AB18

AC19

O

L

7

vdds_ mem Yes

4

PU/ PD

LVCMOS

IO

safe_mode

gpmc_a3

gpio_36

O

L

IO

safe_mode

gpmc_a4

gpio_37

K4

T3

R3

N3

M3

L3

O

L

IO

safe_mode

gpmc_a5

gpio_38

O

L

IO

safe_mode

gpmc_a6

gpio_39

O

H

IO

safe_mode

gpmc_a7

gpio_40

O

IO

safe_mode

gpmc_a8

gpio_41

O

IO

safe_mode

gpmc_a9

O

I

sys_

ndmareq2

gpio_42

4

7

0

1

IO

safe_mode

gpmc_a10

K3

AB19

O

I

H

7

vdds_ mem Yes

4

PU/ PD

LVCMOS

sys_

ndmareq3

gpio_43

4

IO

28

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BALL

SPRS505H –FEBRUARY 2008–REVISED OCTOBER 2013

Table 2-1. Ball Characteristics (CBB Pkg.)⁽¹⁾(continued)

BALL TOP PIN NAME

MODE [4]

TYPE [5]

BALL

RESET REL. POWER [9] HYS [10]

BUFFER

PULLUP

IO CELL [13]

BOTTOM [1] [2]

[3]

RESET

STATE [6]

RESET REL. MODE [8]

STATE [7]

STRENG TH /DOWN

(mA) [11]

TYPE [12]

safe_mode

gpmc_d0

gpmc_d1

gpmc_d2

gpmc_d3

gpmc_d4

gpmc_d5

gpmc_d6

gpmc_d7

gpmc_d8

gpio_44

7

0

4

7

0

4

7

0

4

7

0

4

7

0

4

7

0

4

7

0

4

7

0

4

7

0

4

7

0

4

7

0

1

K1

L1

M2

M1

N2

N1

R2

R1

T2

IO

H

0

vdds_ mem Yes

4

PU/ PD

LVCMOS

L2

P2

T1

V1

V2

W2

H2

T1

AB3

safe_mode

gpmc_d9

gpio_45

K2

P1

R1

R2

T2

W1

Y1

AC3

AB4

AC4

AB6

AC6

AB7

AC7

IO

H

0

vdds_ mem Yes

4

PU/ PD

LVCMOS

safe_mode

gpmc_d10

gpio_46

IO

safe_mode

gpmc_d11

gpio_47

IO

safe_mode

gpmc_d12

gpio_48

IO

safe_mode

gpmc_d13

gpio_49

IO

safe_mode

gpmc_d14

gpio_50

IO

safe_mode

gpmc_d15

gpio_51

IO

safe_mode

gpmc_ncs0

gpmc_ncs1

gpio_52

G4

H3

Y2

Y1

O

1

0

vdds_ mem No

vdds_ mem Yes

4

NA

LVCMOS

O

H

PU/ PD

IO

safe_mode

gpmc_ncs2

gpio_53

V8

U8

NA

O

H

7

vdds_ mem Yes

4

PU/ PD

LVCMOS

IO

safe_mode

gpmc_ncs3

O

I

sys_

ndmareq0

gpio_54

4

7

0

1

IO

safe_mode

gpmc_ncs4

T8

NA

O

I

H

7

vdds_ mem Yes

4

PU/ PD

LVCMOS

sys_

ndmareq1

mcbsp4_

clkx

2

3

IO

gpt9_pwm_e

vt

gpio_55

4

7

0

1

safe_mode

gpmc_ncs5

R8

NA

O

I

H

7

vdds_ mem Yes

4

PU/ PD

LVCMOS

sys_

ndmareq2

TERMINAL DESCRIPTION

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IO CELL [13]

Table 2-1. Ball Characteristics (CBB Pkg.)⁽¹⁾(continued)

BALL

BALL TOP PIN NAME

MODE [4]

TYPE [5]

BALL

RESET REL. POWER [9] HYS [10]

BUFFER

PULLUP

BOTTOM [1] [2]

[3]

RESET

STATE [6]

RESET REL. MODE [8]

STATE [7]

STRENG TH /DOWN

(mA) [11]

TYPE [12]

mcbsp4_dr

2

3

I

gpt10_pwm_

evt

IO

gpio_56

4

7

0

1

IO

safe_mode

gpmc_ncs6

P8

NA

O

I

H

7

vdds_ mem Yes

4

PU/ PD

LVCMOS

sys_

ndmareq3

mcbsp4_dx

2

3

IO

gpt11_pwm_

evt

gpio_57

4

7

0

1

2

3

IO

safe_mode

gpmc_ncs7

gpmc_io_dir

mcbsp4_fsx

N8

NA

O

H

7

vdds_ mem Yes

4

PU/ PD

LVCMOS

O

IO

gpt8_pwm_e

vt

gpio_58

4

7

0

4

7

0

IO

safe_mode

gpmc_clk

gpio_59

T4

F3

W2

W1

O

L

0

vdds_ mem Yes

vdds_ mem No

4

PU/ PD

NA

LVCMOS

IO

safe_mode

gpmc_nadv_

ale

O

G2

F4

G3

V2

gpmc_noe

gpmc_nwe

0

O

1

L

1

0

vdds_ mem No

vdds_ mem Yes

4

NA

LVCMOS

V1

NA

AC12

gpmc_nbe0_

cle

PU/ PD

gpio_60

4

7

0

4

7

0

4

7

0

4

7

0

4

7

0

1

IO

safe_mode

gpmc_nbe1

gpio_61

U3

H1

NA

O

L

0

7

0

vdds_ mem Yes

4

PU/ PD

LVCMOS

IO

safe_mode

gpmc_nwp

gpio_62

AB10

O

IO

safe_mode

gpmc_wait0

gpmc_wait1

gpio_63

M8

L8

AB12

AC10

I

H

0

7

vdds_ mem Yes

NA

4

PU/ PD

LVCMOS

I

IO

safe_mode

gpmc_wait2

gpio_64

K8

J8

NA

I

H

7

vdds_ mem Yes

4

PU/ PD

LVCMOS

IO

safe_mode

gpmc_wait3

I

sys_

ndmareq1

gpio_65

4

7

0

4

7

0

4

7

0

4

IO

safe_mode

dss_pclk

gpio_66

D28

D26

D27

NA

O

H

7

vdds

Yes

8

PU/ PD

LVCMOS

IO

safe_mode

dss_hsync

gpio_67

O

IO

safe_mode

dss_vsync

gpio_68

O

IO

30

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BALL

SPRS505H –FEBRUARY 2008–REVISED OCTOBER 2013

Table 2-1. Ball Characteristics (CBB Pkg.)⁽¹⁾(continued)

BALL TOP PIN NAME

MODE [4]

TYPE [5]

BALL

RESET REL. POWER [9] HYS [10]

BUFFER

PULLUP

IO CELL [13]

BOTTOM [1] [2]

[3]

RESET

STATE [6]

RESET REL. MODE [8]

STATE [7]

STRENG TH /DOWN

(mA) [11]

TYPE [12]

safe_mode

dss_acbias

gpio_69

7

0

4

7

0

2

4

7

0

2

4

7

0

4

7

0

4

7

0

2

4

7

0

2

4

7

0

2

4

7

0

2

4

7

0

4

7

0

4

7

0

4

7

0

4

7

0

4

7

0

4

7

0

4

7

E27

NA

O

L

7

vdds

Yes

8

PU/ PD

LVCMOS

IO

safe_mode

dss_data0

uart1_cts

gpio_70

AG22

IO

I

8

IO

safe_mode

dss_data1

uart1_rts

AH22

NA

IO

O

L

7

vdds

Yes

PU/ PD

LVCMOS

gpio_71

IO

safe_mode

dss_data2

gpio_72

AG23

AH23

AG24

NA

IO

L

7

vdds

Yes

8

PU/ PD

LVCMOS

safe_mode

dss_data3

gpio_73

IO

safe_mode

dss_data4

uart3_rx_ irrx

gpio_74

IO

I

IO

safe_mode

dss_data5

uart3_tx_ irtx

gpio_75

AH24

E26

NA

IO

O

L

7

vdds

Yes

8

PU/ PD

LVCMOS

IO

safe_mode

dss_data6

uart1_tx

IO

O

gpio_76

IO

safe_mode

dss_data7

uart1_rx

F28

IO

I

gpio_77

IO

safe_mode

dss_data8

gpio_78

F27

NA

IO

L

7

vdds

Yes

8

PU/ PD

LVCMOS

safe_mode

dss_data9

gpio_79

G26

IO

safe_mode

dss_data10

gpio_80

AD28

AD27

AB28

AB27

AA28

IO

safe_mode

dss_data11

gpio_81

IO

safe_mode

dss_data12

gpio_82

IO

safe_mode

dss_data13

gpio_83

IO

safe_mode

dss_data14

gpio_84

IO

safe_mode

TERMINAL DESCRIPTION

31

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Table 2-1. Ball Characteristics (CBB Pkg.)⁽¹⁾(continued)

BALL

BALL TOP PIN NAME

MODE [4]

TYPE [5]

BALL

RESET REL. POWER [9] HYS [10]

BUFFER

PULLUP

IO CELL [13]

BOTTOM [1] [2]

[3]

RESET

STATE [6]

RESET REL. MODE [8]

STATE [7]

STRENG TH /DOWN

(mA) [11]

TYPE [12]

AA27

G25

H27

H26

NA

dss_data15

gpio_85

0

4

7

0

4

7

0

4

7

0

2

3

4

7

0

2

IO

L

7

vdds

Yes

8

PU/ PD

LVCMOS

safe_mode

dss_data16

gpio_86

IO

8

LVCMOS

safe_mode

dss_data17

gpio_87

IO

safe_mode

dss_data18

mcspi3_clk

dss_data0

gpio_88

IO

safe_mode

dss_data19

H25

NA

IO

L

7

vdds

Yes

8

PU/ PD

LVCMOS

mcspi3_

simo

dss_data1

gpio_89

3

4

7

0

2

IO

safe_mode

dss_data20

E28

NA

O

H

7

vdds

Yes

8

PU/ PD

LVCMOS

mcspi3_

somi

IO

dss_data2

gpio_90

3

4

7

0

2

3

4

7

0

2

3

4

7

0

3

4

7

0

4

7

0

4

7

0

4

7

IO

safe_mode

dss_data21

mcspi3_cs0

dss_data3

gpio_91

J26

NA

O

L

7

vdds

Yes

8

PU/ PD

LVCMOS

IO

safe_mode

dss_data22

mcspi3_cs1

dss_data4

gpio_92

AC27

AC28

O

IO

safe_mode

dss_data23

dss_data5

gpio_93

O

IO

safe_mode

tv_out2

W28

Y28

Y27

W27

W26

A24

NA

O

Z

L

0

7

vdda_dac

vdds

NA⁽²⁾

4

NA

10-bit DAC

LVCMOS

tv_out1

O

0

NA

tv_vfb1

AO

IO

NA

L

NA

tv_vfb2

NA

tv_vref

NA

cam_hs

Yes

PU/ PD

gpio_94

safe_mode

cam_vs

A23

C25

NA

IO

L

7

vdds

4

PU/ PD

LVCMOS

gpio_95

safe_mode

cam_ xclka

gpio_96

O

IO

safe_mode

(2) The drive strength is fixed regardless of the load. The driver is designed to drive 75ohm for video applications.

32 TERMINAL DESCRIPTION

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BALL

SPRS505H –FEBRUARY 2008–REVISED OCTOBER 2013

Table 2-1. Ball Characteristics (CBB Pkg.)⁽¹⁾(continued)

BALL TOP PIN NAME

MODE [4]

TYPE [5]

BALL

RESET REL. POWER [9] HYS [10]

BUFFER

PULLUP

IO CELL [13]

BOTTOM [1] [2]

[3]

RESET

STATE [6]

RESET REL. MODE [8]

STATE [7]

STRENG TH /DOWN

(mA) [11]

TYPE [12]

C27

C23

NA

cam_pclk

gpio_97

0

4

7

0

I

L

7

vdds

Yes

4

PU/ PD

LVCMOS

IO

safe_mode

cam_fld

IO

4

PU/ PD

LVCMOS

cam_global_r 2

eset

gpio_98

4

7

0

4

7

0

4

7

0

4

7

0

4

7

0

4

7

0

4

7

0

4

7

0

4

7

0

4

7

0

4

7

0

4

7

0

4

7

0

4

7

0

2

4

7

0

4

7

4

IO

safe_mode

cam_d0

AG17

AH17

B24

C24

D24

A25

K28

L28

NA

I

L

7

vdds

Yes

NA

4

PU/PD

PU/ PD

PU/PD

PU/ PD

LVCMOS

gpio_99

safe_mode

cam_d1

I

gpio_100

safe_mode

cam_d2

I

gpio_101

safe_mode

cam_d3

IO

I

4

gpio_102

safe_mode

cam_d4

IO

I

4

gpio_103

safe_mode

cam_d5

IO

I

4

gpio_104

safe_mode

cam_d6

IO

I

NA

8

gpio_105

safe_mode

cam_d7

IO

NA

8

I

gpio_106

safe_mode

cam_d8

IO

NA

8

K27

L27

I

gpio_107

safe_mode

cam_d9

IO

NA

8

I

gpio_108

safe_mode

cam_d10

gpio_109

safe_mode

cam_d11

gpio_110

safe_mode

cam_ xclkb

gpio_111

safe_mode

cam_wen

cam_ shutter

gpio_167

safe_mode

cam_ strobe

gpio_126

safe_mode

gpio_112

IO

NA

4

B25

C26

B26

B23

I

IO

I

4

IO

O

IO

I

O

IO

D25

NA

O

L

7

vdds

Yes

4

PU/ PD

PU/PD

LVCMOS

IO

AG19

I

NA

TERMINAL DESCRIPTION

33

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IO CELL [13]

Table 2-1. Ball Characteristics (CBB Pkg.)⁽¹⁾(continued)

BALL

BALL TOP PIN NAME

MODE [4]

TYPE [5]

BALL

RESET REL. POWER [9] HYS [10]

BUFFER

PULLUP

BOTTOM [1] [2]

[3]

RESET

STATE [6]

RESET REL. MODE [8]

STATE [7]

STRENG TH /DOWN

(mA) [11]

NA

TYPE [12]

safe_mode

gpio_113

7

4

7

4

7

4

7

0

4

7

0

AH19

AG18

AH18

P21

NA

I

L

7

vdds

Yes

PU/PD

PU/ PD

LVCMOS

safe_mode

gpio_114

NA

safe_mode

gpio_115

NA

safe_mode

mcbsp2_fsx

gpio_116

IO

4⁽³⁾

safe_mode

N21

NA

mcbsp2_

clkx

IO

L

7

vdds

Yes

4⁽³⁾

PU/ PD

LVCMOS

gpio_117

4

7

0

4

7

0

4

7

0

4

7

0

4

7

0

4

7

0

4

7

0

4

7

0

4

7

0

4

7

0

4

7

0

4

7

0

4

7

safe_mode

mcbsp2_dr

gpio_118

R21

M21

N28

M27

N27

N26

N25

P28

P27

P26

R27

R25

NA

I

L

7

vdds

Yes

4⁽³⁾

4⁽⁴⁾

8

PU/ PD

LVCMOS

IO

safe_mode

mcbsp2_dx

gpio_119

IO

PU/ PD

safe_mode

mmc1_clk

gpio_120

O

vdds_mmc1 Yes

vdds_mmc1a No

PU/ PD⁽⁵⁾

IO

safe_mode

mmc1_cmd

gpio_121

IO

8

safe_mode

mmc1_dat0

gpio_122

IO

8

safe_mode

mmc1_dat1

gpio_123

IO

8

safe_mode

mmc1_dat2

gpio_124

(5)

IO

8

PU/ PD

PU/ PD⁽⁵⁾

PD⁽⁵⁾

safe_mode

mmc1_dat3

gpio_125

IO

8

safe_mode

mmc1_dat4

gpio_126

IO

8

safe_mode

mmc1_dat5

gpio_127

IO

8

PD⁽⁵⁾

safe_mode

mmc1_dat6

gpio_128

IO

8

PD⁽⁵⁾

safe_mode

mmc1_dat7

gpio_129

(5)

IO

8

PD

safe_mode

(3) The buffer strength of this IO cell is programmable (2, 4, 6, or 8 mA) according to the selected mode; the default value is described in

the above table.

(4) The buffer strength of this IO cell is programmable (2, 4, 6, or 8 mA) according to the selected mode; the default value is described in

the above table.

(5) The PU nominal drive strength of this IO cell is equal to 25 uA @ 1.8V and 41.6 uA @ 3.0V. The PD nominal drive strength of this IO

cell is equal to 1 mA @ 1.8V and 1.66 mA @ 3.0V.

34

TERMINAL DESCRIPTION

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BALL

SPRS505H –FEBRUARY 2008–REVISED OCTOBER 2013

Table 2-1. Ball Characteristics (CBB Pkg.)⁽¹⁾(continued)

BALL TOP PIN NAME

MODE [4]

TYPE [5]

BALL

RESET REL. POWER [9] HYS [10]

BUFFER

PULLUP

IO CELL [13]

BOTTOM [1] [2]

[3]

RESET

STATE [6]

RESET REL. MODE [8]

STATE [7]

STRENG TH /DOWN

(mA) [11]

TYPE [12]

AE2

NA

mmc2_clk

mcspi3_clk

gpio_130

0

1

4

7

0

1

O

L

7

vdds

Yes

4

PU/ PD

LVCMOS

IO

safe_mode

mmc2_ cmd

AG5

NA

IO

H

7

4

PU/ PD

LVCMOS

mcspi3_

simo

gpio_131

4

7

0

1

IO

safe_mode

mmc2_ dat0

AH5

NA

IO

H

7

vdds

Yes

PU/ PD

mcspi3_

somi

gpio_132

4

7

0

4

7

0

1

4

7

0

1

4

7

0

IO

safe_mode

mmc2_ dat1

gpio_133

AH4

AG4

NA

IO

H

7

vdds

Yes

4

PU/ PD

LVCMOS

safe_mode

mmc2_ dat2

mcspi3_cs1

gpio_134

IO

O

IO

safe_mode

mmc2_ dat3

mcspi3_cs0

gpio_135

AF4

AE4

NA

IO

H

L

H

L

7

vdds

Yes

4

PU/ PD

LVCMOS

safe_mode

mmc2_ dat4

IO

O

mmc2_dir_da 1

t0

mmc3_dat0

gpio_136

3

4

7

0

IO

safe_mode

mmc2_ dat5

AH3

NA

IO

O

L

7

vdds

Yes

4

PU/ PD

LVCMOS

mmc2_dir_da 1

t1

cam_global_r 2

eset

IO

mmc3_dat1

gpio_137

3

4

5

IO

hsusb3_tll_st

p

mm3_rxdp

safe_mode

mmc2_ dat6

6

7

0

1

IO

AF3

NA

IO

O

L

7

vdds

Yes

4

PU/ PD

LVCMOS

mmc2_dir_

cmd

cam_ shutter

mmc3_dat2

gpio_138

2

3

4

5

O

IO

hsusb3_tll_di

r

safe_mode

mmc2_ dat7

mmc2_ clkin

mmc3_dat3

gpio_139

7

0

1

3

4

5

AE3

NA

IO

I

L

7

vdds

Yes

4

PU/ PD

LVCMOS

IO

hsusb3_tll_n

xt

mm3_rxdm

6

IO

TERMINAL DESCRIPTION

35

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IO CELL [13]

LVCMOS

Table 2-1. Ball Characteristics (CBB Pkg.)⁽¹⁾(continued)

BALL

BALL TOP PIN NAME

MODE [4]

TYPE [5]

BALL

RESET

STATE [6]

BALL

RESET REL. POWER [9] HYS [10]

BUFFER

STRENG TH /DOWN

(mA) [11]

PULLUP

BOTTOM [1] [2]

[3]

RESET REL. MODE [8]

STATE [7]

TYPE [12]

safe_mode

mcbsp3_dx

uart2_cts

7

0

1

4

5

AF6

AE6

AF5

NA

IO

I

L

7

vdds

Yes

4

PU/ PD

gpio_140

IO

hsusb3_tll_

data4

safe_mode

mcbsp3_dr

uart2_rts

7

0

1

4

5

I

4

LVCMOS

O

IO

gpio_141

hsusb3_tll_

data5

safe_mode

7

0

mcbsp3_

clkx

IO

4

LVCMOS

uart2_tx

1

4

5

O

gpio_142

IO

hsusb3_tll_

data6

safe_mode

mcbsp3_fsx

uart2_rx

7

0

1

4

5

AE5

NA

IO

I

L

7

vdds

Yes

4

PU/ PD

LVCMOS

gpio_143

IO

hsusb3_tll_

data7

safe_mode

uart2_cts

7

0

1

2

AB26

AB25

AA25

I

H

mcbsp3_dx

IO

gpt9_pwm_e

vt

gpio_144

safe_mode

uart2_rts

4

7

0

1

2

IO

O

I

mcbsp3_dr

gpt10_pwm_

evt

IO

gpio_145

safe_mode

uart2_tx

4

7

0

1

IO

O

mcbsp3_

clkx

IO

gpt11_pwm

_evt

2

IO

gpio_146

safe_mode

uart2_rx

4

7

0

1

2

AD25

NA

I

H

7

vdds

Yes

4

PU/ PD

LVCMOS

mcbsp3_fsx

IO

gpt8_pwm_e

vt

gpio_147

safe_mode

uart1_tx

4

7

0

4

7

0

4

7

0

IO

AA8

AA9

NA

O

L

7

vdds

Yes

4

PU/ PD

LVCMOS

gpio_148

safe_mode

uart1_rts

gpio_149

safe_mode

uart1_cts

IO

O

IO

W8

I

36

TERMINAL DESCRIPTION

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BALL

SPRS505H –FEBRUARY 2008–REVISED OCTOBER 2013

Table 2-1. Ball Characteristics (CBB Pkg.)⁽¹⁾(continued)

BALL TOP PIN NAME

MODE [4]

TYPE [5]

BALL

RESET REL. POWER [9] HYS [10]

BUFFER

PULLUP

IO CELL [13]

BOTTOM [1] [2]

[3]

RESET

STATE [6]

RESET REL. MODE [8]

STATE [7]

STRENG TH /DOWN

(mA) [11]

TYPE [12]

gpio_150

4

5

IO

O

hsusb3_tll_cl

k

safe_mode

uart1_rx

7

0

2

3

4

7

0

Y8

NA

I

L

7

vdds

Yes

4

PU/ PD

LVCMOS

mcbsp1_ clkr

mcspi4_clk

gpio_151

IO

safe_mode

AE1

mcbsp4_

clkx

IO

4

PU/ PD

gpio_152

4

5

IO

hsusb3_tll_

data1

mm3_txse0

safe_mode

mcbsp4_dr

gpio_153

6

7

0

4

5

IO

AD1

AD2

AC1

NA

I

L

7

vdds

Yes

4

PU/ PD

LVCMOS

IO

hsusb3_tll_

data0

mm3_rxrcv

safe_mode

mcbsp4_dx

gpio_154

6

7

0

4

5

IO

hsusb3_tll_

data2

mm3_txdat

safe_mode

mcbsp4_fsx

gpio_155

6

7

0

4

5

IO

hsusb3_tll_

data3

mm3_txen_n

safe_mode

mcbsp1_ clkr

mcspi4_clk

gpio_156

6

7

0

1

4

7

0

IO

Y21

NA

IO

L

7

vdds

Yes

4

PU/ PD

LVCMOS

safe_mode

mcbsp1_fsr

AA21

IO

cam_global_r 2

eset

gpio_157

4

7

0

1

IO

safe_mode

mcbsp1_dx

V21

U21

T21

NA

IO

L

7

vdds

Yes

4

PU/ PD

LVCMOS

mcspi4_

simo

mcbsp3_dx

gpio_158

2

4

7

0

1

IO

safe_mode

mcbsp1_dr

I

mcspi4_

somi

IO

mcbsp3_dr

gpio_159

2

4

7

0

2

4

O

IO

safe_mode

mcbsp_clks

cam_ shutter

gpio_160

I

O

IO

TERMINAL DESCRIPTION

37

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IO CELL [13]

Table 2-1. Ball Characteristics (CBB Pkg.)⁽¹⁾(continued)

BALL

BALL TOP PIN NAME

MODE [4]

TYPE [5]

BALL

RESET REL. POWER [9] HYS [10]

BUFFER

PULLUP

BOTTOM [1] [2]

[3]

RESET

STATE [6]

RESET REL. MODE [8]

STATE [7]

STRENG TH /DOWN

(mA) [11]

TYPE [12]

uart1_cts

5

7

0

1

2

4

7

0

I

safe_mode

mcbsp1_fsx

mcspi4_cs0

mcbsp3_fsx

gpio_161

K26

NA

IO

L

7

vdds

Yes

4

PU/ PD

LVCMOS

safe_mode

W21

mcbsp1_

clkx

IO

4

PU/ PD

mcbsp3_

clkx

2

gpio_162

4

7

0

safe_mode

H18

NA

uart3_cts_

rctx

IO

H

7

vdds

Yes

PU/ PD

LVCMOS

gpio_163

4

7

0

4

7

0

4

7

0

4

7

0

4

7

0

4

7

0

4

7

0

4

7

0

safe_mode

uart3_rts_ sd

gpio_164

H19

H20

H21

T28

T25

R28

T26

T27

NA

O

H

L

H

L

7

vdds

Yes

4

PU/ PD

LVCMOS

IO

safe_mode

uart3_rx_ irrx

gpio_165

I

IO

safe_mode

uart3_tx_ irtx

gpio_166

O

IO

safe_mode

hsusb0_clk

gpio_120

I

IO

safe_mode

hsusb0_stp

gpio_121

O

H

L

H

L

IO

safe_mode

hsusb0_dir

gpio_122

I

IO

safe_mode

hsusb0_nxt

gpio_124

I

L

IO

safe_mode

hsusb0_

data0

IO

L

uart3_tx_ irtx

gpio_125

2

4

7

0

O

IO

safe_mode

U28

U27

U26

NA

hsusb0_

data1

IO

L

7

vdds

Yes

4

PU/ PD

LVCMOS

uart3_rx_ irrx

gpio_130

2

4

7

0

I

IO

safe_mode

hsusb0_

data2

IO

uart3_rts_ sd

gpio_131

2

4

7

0

O

IO

safe_mode

hsusb0_

data3

IO

uart3_cts_

rctx

2

4

gpio_169

38

TERMINAL DESCRIPTION

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BALL

SPRS505H –FEBRUARY 2008–REVISED OCTOBER 2013

Table 2-1. Ball Characteristics (CBB Pkg.)⁽¹⁾(continued)

BALL TOP PIN NAME

MODE [4]

TYPE [5]

BALL

RESET REL. POWER [9] HYS [10]

BUFFER

PULLUP

IO CELL [13]

BOTTOM [1] [2]

[3]

RESET

STATE [6]

RESET REL. MODE [8]

STATE [7]

STRENG TH /DOWN

(mA) [11]

TYPE [12]

safe_mode

7

0

U25

V28

V27

V26

NA

hsusb0_

data4

IO

L

7

vdds

Yes

4

PU/ PD

LVCMOS

gpio_188

4

7

0

safe_mode

hsusb0_

data5

IO

4

LVCMOS

gpio_189

4

7

0

safe_mode

hsusb0_

data6

IO

gpio_190

4

7

0

safe_mode

hsusb0_

data7

IO

gpio_191

safe_mode

i2c1_scl

4

7

0

4

7

0

4

7

0

4

7

0

4

7

0

1

K21

J21

NA

IOD

IO

H

0

7

vdds

Yes

4

PU/ PD

Open Drain

i2c1_sda

i2c2_scl

AF15

gpio_168

safe_mode

i2c2_sda

gpio_183

safe_mode

i2c3_scl

AE15

AF14

AG14

AD26

NA

IOD

IO

H

7

0

vdds

Yes

4

PU/ PD

Open Drain

IOD

IO

gpio_184

safe_mode

i2c3_sda

gpio_185

safe_mode

i2c4_scl

IOD

IO

IOD

O

sys_

nvmode1

safe_mode

i2c4_sda

7

0

1

AE26

J25

NA

IOD

O

H

0

7

vdds

Yes

4

PU/ PD

Open Drain

LVCMOS

sys_

nvmode2

safe_mode

hdq_sio

7

0

1

2

3

4

7

0

1

4

7

0

IOD

I

sys_altclk

i2c2_sccbe

i2c3_sccbe

gpio_170

O

IO

safe_mode

mcspi1_clk

mmc2_dat4

gpio_171

AB3

AB4

NA

IO

L

7

vdds

Yes

4⁽⁶⁾

PU/ PD

LVCMOS

safe_mode

mcspi1_

simo

IO

4⁽⁶⁾

mmc2_dat5

gpio_172

1

4

7

0

IO

safe_mode

AA4

NA

mcspi1_

somi

IO

L

7

vdds

Yes

4⁽⁶⁾

PU/ PD

LVCMOS

(6) The buffer strength of this IO cell is programmable (2, 4, 6, or 8 mA) according to the selected mode; the default value is described in

the above table.

TERMINAL DESCRIPTION

39

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IO CELL [13]

Table 2-1. Ball Characteristics (CBB Pkg.)⁽¹⁾(continued)

BALL

BALL TOP PIN NAME

MODE [4]

TYPE [5]

BALL

RESET REL. POWER [9] HYS [10]

BUFFER

PULLUP

BOTTOM [1] [2]

[3]

RESET

STATE [6]

RESET REL. MODE [8]

STATE [7]

STRENG TH /DOWN

(mA) [11]

TYPE [12]

mmc2_dat6

gpio_173

1

4

7

0

1

4

7

0

3

4

7

0

3

4

7

0

2

IO

safe_mode

mcspi1_cs0

mmc2_dat7

gpio_174

AC2

AC3

AB1

AB2

NA

IO

H

L

H

7

vdds

Yes

4⁽⁶⁾

PU/ PD

LVCMOS

safe_mode

mcspi1_cs1

mmc3_cmd

gpio_175

(6)

O

4

IO

safe_mode

mcspi1_cs2

mmc3_clk

gpio_176

O

L

4⁽⁶⁾

O

IO

safe_mode

mcspi1_cs3

O

H

4

hsusb2_tll_

data2

IO

hsusb2_

data2

3

IO

gpio_177

4

5

7

0

2

IO

mm2_txdat

safe_mode

mcspi2_clk

AA3

NA

IO

L

7

vdds

Yes

4

PU/ PD

LVCMOS

hsusb2_tll_

data7

hsusb2_

data7

3

O

gpio_178

4

7

0

IO

safe_mode

Y2

NA

mcspi2_

simo

IO

I

L

7

vdds

Yes

4

PU/ PD

LVCMOS

gpt9_pwm_e

vt

1

2

3

hsusb2_tll_

data4

hsusb2_

data4

gpio_179

4

7

0

IO

safe_mode

Y3

NA

mcspi2_

somi

IO

O

L

7

vdds

Yes

4

PU/ PD

LVCMOS

gpt10_pwm_

evt

1

2

3

hsusb2_tll_

data5

hsusb2_

data5

gpio_180

4

7

0

1

IO

safe_mode

mcspi2_cs0

Y4

NA

IO

H

7

vdds

Yes

4

PU/ PD

LVCMOS

gpt11_pwm_

evt

hsusb2_tll_

data6

2

3

IO

O

hsusb2_

data6

gpio_181

4

7

0

IO

safe_mode

mcspi2_cs1

V3

NA

O

L

7

vdds

Yes

4

PU/ PD

LVCMOS

40

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BALL

SPRS505H –FEBRUARY 2008–REVISED OCTOBER 2013

Table 2-1. Ball Characteristics (CBB Pkg.)⁽¹⁾(continued)

BALL TOP PIN NAME

MODE [4]

TYPE [5]

BALL

RESET REL. POWER [9] HYS [10]

BUFFER

PULLUP

IO CELL [13]

BOTTOM [1] [2]

[3]

RESET

STATE [6]

RESET REL. MODE [8]

STATE [7]

STRENG TH /DOWN

(mA) [11]

TYPE [12]

gpt8_pwm_e

vt

1

2

3

IO

hsusb2_tll_

data3

hsusb2_

data3

gpio_182

mm2_txen_n

safe_mode

sys_32k

4

5

7

0

4

7

0

4

7

0

IO

AE25

AE17

AF17

AF25

NA

I

Z

0

I

NA

0

vdds

Yes

NA

8

NA

LVCMOS

sys_xtalin

sys_xtalout

sys_clkreq

gpio_1

I

NA

O

IO

O

1

NA

Yes

PU/ PD

safe_mode

sys_nirq

AF26

NA

I

H

7

vdds

Yes

4

PU/ PD

LVCMOS

gpio_0

IO

safe_mode

AH25

AF24

NA

sys_

nrespwron

I

Z

0

I

NA

0

vdds

Yes

NA

8

NA

LVCMOS

Open Drain

sys_

nreswarm

0

IOD

IO

1 (PU)

PU/ PD

gpio_30

4

7

0

4

7

0

4

7

0

4

7

0

4

7

0

safe_mode

sys_boot0

gpio_2

AH26

AG26

AE14

AF18

AF19

NA

I

Z

0

vdds

Yes

4

PU/ PD

LVCMOS

IO

safe_mode

sys_boot1

gpio_3

I

IO

safe_mode

sys_boot2

gpio_4

I

IO

safe_mode

sys_boot3

gpio_5

I

IO

safe_mode

sys_boot4

I

mmc2_dir_da 1

t2

O

gpio_6

4

7

0

IO

safe_mode

sys_boot5

AE21

NA

I

Z

0

vdds

Yes

4

PU/ PD

LVCMOS

mmc2_dir_da 1

t3

O

gpio_7

4

7

0

4

7

0

IO

safe_mode

sys_boot6

gpio_8

AF21

AF22

NA

I

Z

0

Z

L

0

7

vdds

Yes

4

8

PU/ PD

LVCMOS

IO

safe_mode

sys_off_

mode

O

gpio_9

4

7

0

4

7

0

4

IO

safe_mode

sys_clkout1

gpio_10

AG25

AE22

NA

O

L

7

vdds

Yes

8

4

PU/ PD

LVCMOS

IO

safe_mode

sys_clkout2

gpio_186

O

IO

TERMINAL DESCRIPTION

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IO CELL [13]

Table 2-1. Ball Characteristics (CBB Pkg.)⁽¹⁾(continued)

BALL

BALL TOP PIN NAME

MODE [4]

TYPE [5]

BALL

RESET REL. POWER [9] HYS [10]

BUFFER

PULLUP

BOTTOM [1] [2]

[3]

RESET

STATE [6]

RESET REL. MODE [8]

STATE [7]

STRENG TH /DOWN

(mA) [11]

TYPE [12]

safe_mode

jtag_ntrst

jtag_tck

7

0

AA17

AA13

AA12

AA18

NA

I

L

H

L

0

H

0

vdds

Yes

NA

8

PU/ PD

LVCMOS

I

jtag_rtck

O

IO

jtag_tms_tms 0

c

8

AA20

AA19

AA11

NA

jtag_tdi

0

4

7

0

4

7

0

1

I

H

L

H

Z

0

vdds

Yes

NA

8

PU/ PD

LVCMOS

jtag_tdo

O

IO

jtag_emu0

gpio_11

H

8

safe_mode

jtag_emu1

gpio_31

AA10

AF10

NA

IO

H

0

4

vdds

Yes

8

4

PU/ PD

LVCMOS

safe_mode

etk_clk

O

mcbsp5_

clkx

IO

mmc3_clk

hsusb1_stp

gpio_12

2

3

4

5

6

O

IO

I

mm1_rxdp

hsusb1_tll_st

p

AE10

NA

etk_ctl

0

2

3

4

6

O

H

4

vdds

Yes

4

PU/ PD

LVCMOS

mmc3_cmd

hsusb1_clk

gpio_13

IO

O

IO

O

hsusb1_tll_cl

k

AF11

NA

etk_d0

0

1

O

H

4

vdds

Yes

4

PU/ PD

LVCMOS

mcspi3_

simo

IO

mmc3_dat4

2

3

IO

hsusb1_

data0

gpio_14

4

5

6

IO

mm1_rxrcv

hsusb1_tll_

data0

AG12

NA

etk_d1

0

1

O

H

4

vdds

Yes

4

PU/ PD

LVCMOS

mcspi3_

somi

IO

hsusb1_

data1

3

IO

gpio_15

4

5

6

IO

mm1_txse0

hsusb1_tll_

data1

AH12

NA

etk_d2

0

1

3

O

H

4

vdds

Yes

4

PU/ PD

LVCMOS

mcspi3_cs0

IO

hsusb1_

data2

gpio_16

4

5

6

IO

mm1_txdat

hsusb1_tll_d

ata2

AE13

NA

etk_d3

0

1

2

O

H

4

vdds

Yes

4

PU/ PD

LVCMOS

mcspi3_clk

mmc3_dat3

IO

42

TERMINAL DESCRIPTION

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BALL

SPRS505H –FEBRUARY 2008–REVISED OCTOBER 2013

Table 2-1. Ball Characteristics (CBB Pkg.)⁽¹⁾(continued)

BALL TOP PIN NAME

MODE [4]

TYPE [5]

BALL

RESET REL. POWER [9] HYS [10]

BUFFER

PULLUP

IO CELL [13]

BOTTOM [1] [2]

[3]

RESET

STATE [6]

RESET REL. MODE [8]

STATE [7]

STRENG TH /DOWN

(mA) [11]

TYPE [12]

hsusb1_

data7

3

IO

gpio_17

4

6

IO

hsusb1_tll_

data7

AE11

NA

etk_d4

0

1

2

3

O

I

L

4

vdds

Yes

4

PU/ PD

LVCMOS

mcbsp5_dr

mmc3_dat0

IO

hsusb1_

data4

gpio_18

4

6

IO

hsusb1_tll_

data4

AH9

etk_d5

0

1

2

3

O

4

LVCMOS

mcbsp5_fsx

mmc3_dat1

IO

hsusb1_

data5

gpio_19

4

6

IO

hsusb1_tll_

data5

AF13

etk_d6

0

1

2

3

O

mcbsp5_dx

mmc3_dat2

IO

hsusb1_

data6

gpio_20

4

6

IO

hsusb1_tll_

data6

AH14

etk_d7

0

1

2

3

O

mcspi3_cs1

mmc3_dat7

O

IO

hsusb1_

data3

gpio_21

4

5

6

IO

mm1_txen_n

hsusb1_tll_

data3

AF9

NA

etk_d8

0

1

O

I

L

4

vdds

Yes

4

PU/ PD

LVCMOS

sys_drm_

msecure

mmc3_dat6

hsusb1_dir

gpio_22

2

3

4

6

IO

I

IO

O

hsusb1_tll_di

r

AG9

NA

etk_d9

0

1

O

L

4

vdds

Yes

4

PU/ PD

LVCMOS

sys_secure_i

ndic ator

mmc3_dat5

hsusb1_nxt

gpio_23

2

3

4

5

6

IO

I

IO

O

mm1_rxdm

hsusb1_tll_n

xt

AE7

NA

etk_d10

0

2

3

4

O

I

L

4

vdds

Yes

4

PU/ PD

LVCMOS

uart1_rx

hsusb2_clk

gpio_24

O

IO

TERMINAL DESCRIPTION

43

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IO CELL [13]

Table 2-1. Ball Characteristics (CBB Pkg.)⁽¹⁾(continued)

BALL

BALL TOP PIN NAME

MODE [4]

TYPE [5]

BALL

RESET REL. POWER [9] HYS [10]

BUFFER

PULLUP

BOTTOM [1] [2]

[3]

RESET

STATE [6]

RESET REL. MODE [8]

STATE [7]

STRENG TH /DOWN

(mA) [11]

TYPE [12]

hsusb2_tll_cl

k

6

O

AF7

NA

etk_d11

0

3

4

5

6

O

IO

I

L

4

vdds

Yes

4

PU/ PD

LVCMOS

hsusb2_stp

gpio_25

mm2_rxdp

hsusb2_tll_st

p

AG7

AH7

NA

etk_d12

0

3

4

6

O

I

L

4

vdds

Yes

4

PU/ PD

LVCMOS

hsusb2_dir

gpio_26

IO

O

hsusb2_tll_di

r

etk_d13

0

3

4

5

6

O

I

hsusb2_nxt

gpio_27

IO

O

mm2_rxdm

hsusb2_tll_n

xt

AG8

NA

etk_d14

0

3

O

L

-

L

-

4

-

vdds

-

Yes

-

4

-

PU/ PD

-

LVCMOS

-

hsusb2_

data0

IO

gpio_28

4

5

6

IO

mm2_rxrcv

hsusb2_tll_

data0

AH8

NA

etk_d15

0

3

O

hsusb2_

data1

IO

gpio_29

4

5

6

IO

mm2_txse0

hsusb2_tll_

data1

AE9, AE18, NA

AE19, AE24,

AC4, Y16,

Y18, Y19,

vdd_core

0

PWR

Y20, W18,

W20, V20,

U19, U20,

T19, P20,

N19, N20,

M19, M25,

L25, K18,

K20, J4, J18,

J19, J20, H4,

E25, D8, D9,

D15, D22,

D23

Y9, Y10,

NA

vdd_mpu

0

PWR

-

Y11, Y14,

Y15, W9,

W11, W12,

W15, U10,

T9, T10, R9,

R10, N10,

M9, M10, L9,

L10, K11,

K14, K13, J9,

J10, J11,

J14, J15

AH6, U1, R4, NA

J1, J2, G28,

F1, F2, D16,

C16, C28,

vdds_mem

0

PWR

-

B5, B8, B12,

B18, B22,

A5, A8, A12,

A18, A22

44

TERMINAL DESCRIPTION

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BALL

SPRS505H –FEBRUARY 2008–REVISED OCTOBER 2013

Table 2-1. Ball Characteristics (CBB Pkg.)⁽¹⁾(continued)

BALL TOP PIN NAME

MODE [4]

TYPE [5]

BALL

RESET REL. POWER [9] HYS [10]

BUFFER

PULLUP

IO CELL [13]

BOTTOM [1] [2]

[3]

RESET

STATE [6]

RESET REL. MODE [8]

STATE [7]

STRENG TH /DOWN

(mA) [11]

TYPE [12]

AG20, AG21, NA

AG27, AF8,

AF16, AF23,

AE8, AE16,

AE23, AE27,

AD3, AD4,

vdds

0

PWR

-

W4, H28,

F25, F26

W16

K15

NA

vdds_sram

0

vdds_dpll_dll

PWR

-

AA16

vdds_dpll_pe

r

AA14

NA

vdds_wkup_

bg

0

PWR

-

K25, P25

vdds_mmc1,

vdds_mmc1a

V25

Y26

NA

vdda_dac

vssa_dac

vss

0

PWR

GND

-

AA26, AG2, NA

AG3, AG6,

AF12, AF20,

AE12, AE20,

AC25, AC26,

AG16, AH21,

Y12, Y13,

Y17, Y25,

W3, W10,

W13, W14,

W17, W19,

W25, V9,

V10, V19,

U2, U9, T20,

R19, R20,

R26, P3, P4,

P9, P10,

P19, N9,

M20, M28,

L19, L20,

L26, K9,

K10, K12,

K16, K17,

K19, J3, J12,

J13, J16,

J17, G27,

E3,E4, D7,

D10, D13,

D19, D21,

C7, C10,

C13, C19,

C22, B2,

B27, A3, A26

AH20, AA15, NA

V4, L21

cap_vdd_d,

cap_vdd_wk

up,

cap_vdd_sra

m_mpu ,

0

PWR

-

cap_vdd_sra

m_core

AH1, AH2,

A2, A12,

FeedThrough -

Pins⁽⁷⁾

-

AH10, AH11, A22, A23,

AH13, AH15, AA1, AA2,

AH16, AH27, AA22, AA23,

AH28, AG1, AB1, AB11,

AG10, AG11, AB13, AB23,

AG13, AG15, AB8, AB9,

AG28, AF1, AC1, AC11,

AF2, AF27, AC13, AC14,

AF28, AE28, AC2, AC22,

AA1, AA2,

AC23, AC8,

N1, N2, M1, AC9, B12,

M2, M26,

J27, J28,

B15, B28,

A2, A15,

A27, A28

B23, H22,

H23, K1, K2,

K22, L1, L2,

U1, U2, Y23

A1, B1, G1, A1, AB2,

No Connect

-

U4

AB22, B1,

B2, B22

(7) These signals are feed-through balls. For more information, see Section 2.5.10.

TERMINAL DESCRIPTION

45

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Table 2-2. Ball Characteristics (CBC Pkg.)⁽¹⁾

BALL

RESET

STATE [6]

BALL

RESET REL.

STATE [7]

BUFFER

HYS [10] STRENG TH

(mA) [11]

PULLUP

/DOWN

TYPE [12]

BALL

BOTTOM [1]

BALL TOP PIN NAME

RESET REL.

MODE [8]

MODE [4]

TYPE [5]

POWER [9]

IO CELL [13]

[2]

[3]

AE16

NA

cam_d0

0

I

L

7

vdds

Yes

4

PU100/

PD100

LVCMOS

gpio_99

safe_mode

cam_d1

4

7

0

I

-

I

AE15

NA

L

vdds

Yes

4

PU100/

PD100

LVCMOS

gpio_100

safe_mode

gpio_112

4

7

4

I

-

I

AD17

AE18

AD16

AE17

NA

L

7

vdds

Yes

4

PU100/

PD100

LVCMOS

safe_mode

gpio_114

7

4

-

I

PU100/

PD100

safe_mode

gpio_113

7

4

-

I

PU100/

PD100

safe_mode

gpio_115

7

4

-

I

PU100/

PD100

safe_mode

sdrc_a0

sdrc_a1

sdrc_a2

sdrc_a3

sdrc_a4

sdrc_a5

sdrc_a6

sdrc_a7

sdrc_a8

sdrc_a9

sdrc_a10

sdrc_a11

sdrc_a12

sdrc_a13

sdrc_a14

sdrc_ba0

sdrc_ba1

sdrc_cke0

7

0

-

NA

G20

K20

J20

O

0

H

0

1

0

7

vdds

No

Yes

4⁽²⁾

NA

LVCMOS

J21

U21

R20

M21

M20

N20

K21

Y16

N21

R21

AA15

Y12

AA18

V20

Y15

4⁽²⁾

(2)

4

4⁽²⁾

(2)

4

(2)

4

PU100/

PD100

safe_mode

sdrc_cke1

7

0

(2)

NA

Y13

O

H

1

7

vdds

Yes

4

PU100/

PD100

LVCMOS

safe_mode

sdrc_clk

7

0

NA

A12

D1

G1

G2

E1

IO

L

0

Z

0

vdds

Yes

4⁽²⁾

PU100/

PD100

LVCMOS

sdrc_d0

sdrc_d1

sdrc_d2

sdrc_d3

sdrc_d4

sdrc_d5

0

PU100/

PD100

PU100/

PD100

PU100/

PD100

PU100/

PD100

D2

E2

PU100/

PD100

PU100/

PD100

(1) NA in this table stands for Not Applicable.

(2) The drive strength is programmable vs the capacity load: load range = [2 pF to 6 pF] per default or [6 pF to 12 pF] according to the

selected mode.

46

TERMINAL DESCRIPTION

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SPRS505H –FEBRUARY 2008–REVISED OCTOBER 2013

Table 2-2. Ball Characteristics (CBC Pkg.)⁽¹⁾(continued)

BALL

RESET

STATE [6]

BALL

RESET REL.

STATE [7]

BUFFER

HYS [10] STRENG TH

(mA) [11]

PULLUP

/DOWN

TYPE [12]

BALL

BOTTOM [1]

BALL TOP PIN NAME

RESET REL.

MODE [8]

MODE [4]

TYPE [5]

IO

POWER [9]

vdds

IO CELL [13]

LVCMOS

[2]

[3]

NA

B3

sdrc_d6

0

L

Z

0

Yes

4⁽²⁾

PU100/

PD100

B4

A10

B11

A11

B12

A16

A17

B17

B18

B7

sdrc_d7

sdrc_d8

IO

PU100/

PD100

IO

PU100/

PD100

sdrc_d9

IO

PU100/

PD100

sdrc_d10

sdrc_d11

sdrc_d12

sdrc_d13

sdrc_d14

sdrc_d15

sdrc_d16

sdrc_d17

sdrc_d18

sdrc_d19

sdrc_d20

sdrc_d21

sdrc_d22

sdrc_d23

sdrc_d24

sdrc_d25

sdrc_d26

sdrc_d27

sdrc_d28

sdrc_d29

sdrc_d30

sdrc_d31

IO

4⁽²⁾

PU100/

PD100

(2)

IO

4

PU100/

PD100

IO

4⁽²⁾

PU100/

PD100

IO

PU100/

PD100

IO

PU100/

PD100

IO

4⁽²⁾

PU100/

PD100

(3)

IO

4

PU100/

PD100

A5

IO

4⁽³⁾

PU100/

PD100

B6

IO

PU100/

PD100

A6

IO

PU100/

PD100

A8

IO

PU100/

PD100

B9

IO

PU100/

PD100

A9

IO

PU100/

PD100

B10

C21

D20

B19

C20

D21

E20

E21

G21

IO

PU100/

PD100

IO

4⁽³⁾

PU100/

PD100

(3)

IO

4

PU100/

PD100

IO

4⁽³⁾

PU100/

PD100

IO

4⁽³⁾

PU100/

PD100

(3)

IO

4

PU100/

PD100

IO

4⁽³⁾

PU100/

PD100

IO

PU100/

PD100

IO

PU100/

PD100

NA

H1

A14

A4

sdrc_dm0

sdrc_dm1

sdrc_dm2

sdrc_dm3

sdrc_dqs0

0

O

0

L

0

Z

0

vdds

No

NA

LVCMOS

4⁽³⁾

(3)

O

No

4

A18

C2

O

No

4⁽³⁾

IO

Yes

PU100/

PD100

NA

B15

B8

sdrc_dqs1

sdrc_dqs2

sdrc_dqs3

0

IO

L

Z

0

vdds

Yes

4⁽³⁾

PU100/

PD100

LVCMOS

(3)

4

PU100/

PD100

A19

4⁽³⁾

PU100/

PD100

(3) The drive strength is programmable vs the capacity load: load range = [2 pF to 6 pF] per default or [6 pF to 12 pF] according to the

selected mode.

TERMINAL DESCRIPTION

47

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OMAP3515, OMAP3503

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www.ti.com

IO CELL [13]

Table 2-2. Ball Characteristics (CBC Pkg.)⁽¹⁾(continued)

BALL

RESET

STATE [6]

BALL

RESET REL.

STATE [7]

BUFFER

HYS [10] STRENG TH

(mA) [11]

PULLUP

/DOWN

TYPE [12]

BALL

BOTTOM [1]

BALL TOP PIN NAME

RESET REL.

MODE [8]

MODE [4]

TYPE [5]

POWER [9]

[2]

[3]

NA

U20

B13

T21

T20

V21

Y18

NA

sdrc_ncas

sdrc_nclk

sdrc_ncs0

sdrc_ncs1

sdrc_nras

sdrc_nwe

dss_data0

0

O

IO

1

L

1

L

0

7

vdds

No

4⁽³⁾

NA

LVCMOS

NA

4⁽³⁾

(3)

NA

4

NA

4⁽³⁾

AE21

4

PU100/

PD100

uart1_cts

gpio_70

2

4

7

0

I

IO

-

safe_mode

dss_data1

AE22

NA

IO

L

7

vdds

No

4

PU100/

PD100

LVCMOS

uart1_rts

gpio_71

2

4

7

0

O

IO

-

safe_mode

dss_data2

AE23

AE24

AD23

NA

IO

L

7

vdds

No

4

PU100/

PD100

LVCMOS

gpio_72

safe_mode

dss_data3

4

7

0

IO

-

IO

PU100/

PD100

gpio_73

safe_mode

dss_data4

4

7

0

IO

-

IO

PU100/

PD100

uart3_rx_irrx

gpio_74

2

4

7

0

I

IO

-

safe_mode

dss_data5

AD24

NA

IO

L

7

vdds

No

4

PU100/

PD100

LVCMOS

uart3_tx_irtx

gpio_75

2

4

7

0

O

IO

-

safe_mode

dss_data10

AC26

AD26

AA25

Y25

NA

IO

L

H

L

H

7

vdds

NA

Yes

4

PU100/

PD100

LVCMOS

gpio_80

4

7

0

IO

-

safe_mode

dss_data11

IO

PU100/

PD100

gpio_81

4

7

0

IO

-

safe_mode

dss_data12

IO

PU100/

PD100

gpio_82

4

7

0

IO

-

safe_mode

dss_data13

IO

PU100/

PD100

gpio_83

4

7

0

IO

-

safe_mode

dss_data14

AA26

AB26

F25

IO

PU100/

PD100

gpio_84

4

7

0

IO

-

safe_mode

dss_data15

IO

PU100/

PD100

gpio_85

4

7

0

IO

-

safe_mode

dss_data20

O

PU100/

PD100

48

TERMINAL DESCRIPTION

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Product Folder Links: OMAP3515 OMAP3503

OMAP3515, OMAP3503

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SPRS505H –FEBRUARY 2008–REVISED OCTOBER 2013

Table 2-2. Ball Characteristics (CBC Pkg.)⁽¹⁾(continued)

BALL

RESET

STATE [6]

BALL

RESET REL.

STATE [7]

BUFFER

HYS [10] STRENG TH

(mA) [11]

PULLUP

/DOWN

TYPE [12]

BALL

BOTTOM [1]

BALL TOP PIN NAME

RESET REL.

MODE [8]

MODE [4]

TYPE [5]

POWER [9]

IO CELL [13]

[2]

[3]

mcspi3_somi

dss_data2

gpio_90

2

3

4

7

0

IO

-

safe_mode

dss_data22

AC25

NA

O

L

7

vdds

NA

4

PU100/

PD100

LVCMOS

mcspi3_cs1

dss_data4

gpio_92

2

3

4

7

0

O

IO

-

safe_mode

dss_data23

AB25

G25

NA

O

L

7

vdds

NA

4

PU100/

PD100

LVCMOS

dss_data5

gpio_93

3

4

7

0

IO

-

safe_mode

dss_pclk

O

H

Yes

PU100/

PD100

gpio_66

hw_dbg12

safe_mode

gpmc_a1

4

5

7

0

IO

O

-

(4)

J2

H1

H2

G2

F1

F2

E1

E2

D1

NA

O

L

7

vdds

Yes

4

PU100/

PD100

LVCMOS

gpio_34

safe_mode

gpmc_a2

4

7

0

IO

-

O

4⁽⁴⁾

PU100/

PD100

gpio_35

safe_mode

gpmc_a3

4

7

0

IO

-

O

L

4⁽⁴⁾

PU100/

PD100

gpio_36

safe_mode

gpmc_a4

4

7

0

IO

-

(4)

O

L

4

PU100/

PD100

gpio_37

safe_mode

gpmc_a5

4

7

0

IO

-

O

L

4⁽⁴⁾

PU100/

PD100

gpio_38

safe_mode

gpmc_a6

4

7

0

IO

-

(4)

O

H

4

PU100/

PD100

gpio_39

safe_mode

gpmc_a7

4

7

0

IO

-

O

4⁽⁴⁾

PU100/

PD100

gpio_40

safe_mode

gpmc_a8

4

7

0

IO

-

O

PU100/

PD100

gpio_41

safe_mode

gpmc_a9

4

7

0

IO

-

O

PU100/

PD100

sys_ndmareq

2

1

I

gpio_42

4

7

IO

-

safe_mode

(4) The drive strength is programmable vs the capacity load: load range = [2 pF to 6 pF] per default or [6 pF to 12 pF] according to the

selected mode.

TERMINAL DESCRIPTION

49

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Product Folder Links: OMAP3515 OMAP3503

OMAP3515, OMAP3503

SPRS505H –FEBRUARY 2008–REVISED OCTOBER 2013

www.ti.com

Table 2-2. Ball Characteristics (CBC Pkg.)⁽¹⁾(continued)

BALL

RESET

STATE [6]

BALL

RESET REL.

STATE [7]

BUFFER

HYS [10] STRENG TH

(mA) [11]

PULLUP

/DOWN

TYPE [12]

BALL

BOTTOM [1]

BALL TOP PIN NAME

RESET REL.

MODE [8]

MODE [4]

TYPE [5]

POWER [9]

IO CELL [13]

[2]

[3]

D2

N1

NA

gpmc_a10

0

1

O

I

H

7

vdds

Yes

4⁽⁴⁾

PU100/

PD100

LVCMOS

sys_ndmareq

3

gpio_43

safe_mode

gpmc_clk

4

7

0

IO

-

L1

O

L

0

vdds

Yes

4⁽⁴⁾

PU100/

PD100

LVCMOS

gpio_59

safe_mode

gpmc_d0

4

7

0

IO

-

AA2

AA1

AC2

AC1

AE5

AD6

AD5

AC5

V1

U2

U1

IO

H

0

vdds

Yes

4⁽⁴⁾

4⁽⁵⁾

PU100/

PD100

LVCMOS

gpmc_d1

gpmc_d2

gpmc_d3

gpmc_d4

gpmc_d5

gpmc_d6

gpmc_d7

gpmc_d8

0

IO

PU100/

PD100

V2

PU100/

PD100

V1

PU100/

PD100

AA3

AA4

Y3

PU100/

PD100

PU100/

PD100

PU100/

PD100

Y4

4⁽⁵⁾

PU100/

PD100

(5)

R1

4

PU100/

PD100

gpio_44

safe_mode

gpmc_d9

4

7

0

IO

-

Y1

T1

N1

P2

IO

H

0

H

0

vdds

Yes

No

4⁽⁵⁾

PU100/

PD100

LVCMOS

gpio_45

safe_mode

gpmc_d10

4

7

0

IO

-

IO

PU100/

PD100

gpio_46

safe_mode

gpmc_d11

4

7

0

IO

-

U2

IO

PU100/

PD100

gpio_47

safe_mode

gpmc_d12

4

7

0

IO

-

U1

P1

IO

PU100/

PD100

gpio_48

safe_mode

gpmc_d13

4

7

0

IO

-

P1

M1

J2

IO

4⁽⁵⁾

PU100/

PD100

gpio_49

safe_mode

gpmc_d14

4

7

0

IO

-

(5)

L2

IO

4

PU100/

PD100

gpio_50

safe_mode

gpmc_d15

4

7

0

IO

-

M2

AD10

K2

IO

4⁽⁵⁾

PU100/

PD100

gpio_51

4

7

0

IO

-

safe_mode

(5)

AA9

gpmc_nadv_

ale

O

4

NA

(5) The drive strength is programmable vs the capacity load: load range = [2 pF to 6 pF] per default or [6 pF to 12 pF] according to the

selected mode.

50

TERMINAL DESCRIPTION

Submit Documentation Feedback

Product Folder Links: OMAP3515 OMAP3503

OMAP3515, OMAP3503

www.ti.com

SPRS505H –FEBRUARY 2008–REVISED OCTOBER 2013

Table 2-2. Ball Characteristics (CBC Pkg.)⁽¹⁾(continued)

BALL

RESET

STATE [6]

BALL

RESET REL.

STATE [7]

BUFFER

HYS [10] STRENG TH

(mA) [11]

PULLUP

/DOWN

TYPE [12]

BALL

BOTTOM [1]

BALL TOP PIN NAME

RESET REL.

MODE [8]

MODE [4]

TYPE [5]

POWER [9]

IO CELL [13]

[2]

[3]

K2

NA

gpmc_nbe0_

cle

0

O

L

0

vdds

Yes

4⁽⁵⁾

PU100/

PD100

LVCMOS

gpio_60

4

7

0

IO

-

safe_mode

gpmc_nbe1

(5)

J1

NA

O

L

7

vdds

Yes

4

PU100/

PD100

LVCMOS

gpio_61

4

7

0

IO

-

safe_mode

gpmc_ncs0

gpmc_ncs1

AD8

AD1

AA8

W1

O

1

0

vdds

No

4⁽⁵⁾

NA

LVCMOS

(5)

H

Yes

4

PU100/

PD100

gpio_52

4

7

0

IO

-

safe_mode

gpmc_ncs2

(5)

A3

B6

NA

O

H

7

vdds

Yes

4

PU100/

PD100

LVCMOS

gpio_53

4

7

0

IO

-

safe_mode

gpmc_ncs3

O

4⁽⁵⁾

PU100/

PD100

sys_ndmareq

0

1

I

gpio_54

4

7

0

IO

-

safe_mode

gpmc_ncs4

(6)

B4

C4

B5

NA

O

H

7

vdds

Yes

4

PU100/

PD100

LVCMOS

sys_ndmareq

1

I

mcbsp4_clkx

2

3

IO

gpt9_pwm_e

vt

gpio_55

4

7

0

IO

-

safe_mode

gpmc_ncs5

O

4⁽⁶⁾

PU100/

PD100

sys_ndmareq

2

1

I

mcbsp4_dr

2

3

I

gpt10_pwm_

evt

IO

gpio_56

4

7

0

IO

-

safe_mode

gpmc_ncs6

O

4⁽⁶⁾

PU100/

PD100

sys_ndmareq

3

1

I

mcbsp4_dx

2

3

IO

gpt11_pwm_

evt

gpio_57

4

7

0

IO

-

safe_mode

gpmc_ncs7

C5

NA

O

H

7

vdds

Yes

4⁽⁶⁾

PU100/

PD100

LVCMOS

gpmc_io_dir

mcbsp4_fsx

1

2

3

O

IO

gpt8_pwm_e

vt

gpio_58

safe_mode

gpmc_noe

4

7

0

IO

-

N2

L2

O

1

0

vdds

No

4⁽⁶⁾

NA

LVCMOS

(6) The drive strength is programmable vs the capacity load: load range = [2 pF to 6 pF] per default or [6 pF to 12 pF] according to the

selected mode.

TERMINAL DESCRIPTION

51

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Product Folder Links: OMAP3515 OMAP3503

OMAP3515, OMAP3503

SPRS505H –FEBRUARY 2008–REVISED OCTOBER 2013

www.ti.com

IO CELL [13]

Table 2-2. Ball Characteristics (CBC Pkg.)⁽¹⁾(continued)

BALL

RESET

STATE [6]

BALL

RESET REL.

STATE [7]

BUFFER

HYS [10] STRENG TH

(mA) [11]

PULLUP

/DOWN

TYPE [12]

BALL

BOTTOM [1]

BALL TOP PIN NAME

RESET REL.

MODE [8]

MODE [4]

TYPE [5]

POWER [9]

[2]

[3]

M1

K1

Y5

gpmc_nwe

gpmc_nwp

0

O

1

L

1

0

vdds

No

4⁽⁶⁾

NA

LVCMOS

(6)

AC6

Yes

4

PU100/

PD100

gpio_62

4

7

0

IO

-

safe_mode

gpmc_wait0

AC11

AC8

Y10

Y8

I

H

0

7

vdds

Yes

4⁽⁶⁾

PU100/

PD100

LVCMOS

gpmc_wait1

0

I

PU100/

PD100

gpio_63

4

7

0

IO

-

safe_mode

gpmc_wait2

B3

C6

NA

I

H

7

vdds

Yes

4⁽⁶⁾

PU100/

PD100

LVCMOS

gpio_64

4

7

0

IO

-

safe_mode

gpmc_wait3

I

4⁽⁶⁾

PU100/

PD100

sys_ndmareq

1

I

gpio_65

4

7

0

IO

-

safe_mode

hsusb0_clk

W19

V20

NA

I

L

7

vdds

Yes

4⁽⁷⁾

PU100/

PD100

LVCMOS

gpio_120

4

7

0

IO

-

safe_mode

(7)

hsusb0_data

0

IO

4

PU100/

PD100

uart3_tx_irtx

gpio_125

2

4

7

0

O

IO

-

safe_mode

(7)

Y20

V18

W20

NA

hsusb0_data

1

IO

L

7

vdds

Yes

4

PU100/

PD100

LVCMOS

uart3_rx_irrx

gpio_130

2

4

7

0

I

IO

-

safe_mode

hsusb0_data

2

IO

4⁽⁷⁾

PU100/

PD100

uart3_rts_sd

gpio_131

2

4

7

0

O

IO

-

safe_mode

hsusb0_data

3

IO

4⁽⁷⁾

PU100/

PD100

uart3_cts_rct

x

2

IO

gpio_169

4

7

0

IO

-

safe_mode

W17

Y18

Y19

Y17

NA

hsusb0_data

4

IO

L

7

vdds

Yes

4⁽⁷⁾

PU100/

PD100

LVCMOS

gpio_188

4

7

0

IO

-

safe_mode

(7)

hsusb0_data

5

IO

4

PU100/

PD100

gpio_189

4

7

0

IO

-

safe_mode

hsusb0_data

6

IO

4⁽⁷⁾

PU100/

PD100

gpio_190

4

7

0

IO

-

safe_mode

hsusb0_data

7

IO

4⁽⁷⁾

PU100/

PD100

(7) The capacity load range is [2 pf to 6 pF].

52 TERMINAL DESCRIPTION

Submit Documentation Feedback

Product Folder Links: OMAP3515 OMAP3503

OMAP3515, OMAP3503

www.ti.com

SPRS505H –FEBRUARY 2008–REVISED OCTOBER 2013

Table 2-2. Ball Characteristics (CBC Pkg.)⁽¹⁾(continued)

BALL

RESET

STATE [6]

BALL

RESET REL.

STATE [7]

BUFFER

HYS [10] STRENG TH

(mA) [11]

PULLUP

/DOWN

TYPE [12]

BALL

BOTTOM [1]

BALL TOP PIN NAME

RESET REL.

MODE [8]

MODE [4]

TYPE [5]

POWER [9]

IO CELL [13]

LVCMOS

[2]

[3]

gpio_191

safe_mode

hsusb0_dir

4

7

0

IO

-

(7)

V19

W18

U20

NA

I

L

7

vdds

Yes

4

PU100/

PD100

gpio_122

safe_mode

hsusb0_nxt

4

7

0

IO

-

NA

I

vdds

4⁽⁷⁾

PU100/

PD100

LVCMOS

gpio_124

safe_mode

hsusb0_stp

4

7

0

IO

-

O

H

vdds

4⁽⁷⁾

PU100/

PD100

LVCMOS

gpio_121

safe_mode

jtag_ntrst

4

7

0

IO

-

U15

W13

V14

U16

Y13

V15

N19

NA

I

L

0

7

vdds

Yes

NA

4

PU100/

PD100

LVCMOS

jtag_rtck

jtag_tck

jtag_tdi

jtag_tdo

0

O

I

PU100/

PD100

L

vdds

NA

4

PU100/

PD100

I

H

L

H

Z

H

L

vdds

PU100/

PD100

O

IO

O

vdds

PU100/

PD100

jtag_tms_tms

c

H

L

vdds

4

PU100/

PD100

mmc1_clk

vdds_mmc1

8

PU100/

PD100

gpio_120

safe_mode

mmc1_cmd

4

7

0

IO

-

L18

M19

M18

K18

N20

NA

IO

L

7

vdds_mmc1

Yes

8

PU100/

PD100

LVCMOS

gpio_121

safe_mode

mmc1_dat0

4

7

0

IO

-

IO

PU100/

PD100

gpio_122

safe_mode

mmc1_dat1

4

7

0

IO

-

IO

PU100/

PD100

gpio_123

safe_mode

mmc1_dat2

4

7

0

IO

-

IO

PU100/

PD100

gpio_124

safe_mode

mmc1_dat3

4

7

0

IO

-

IO

PU100/

PD100

gpio_125

safe_mode

mmc1_dat4

gpio_126

4

7

0

4

7

0

4

7

0

4

7

IO

-

M20

P17

P18

NA

IO

-

L

7

vdds_mmc1a

No

8

PU/PD⁽⁸⁾

LVCMOS

safe_mode

mmc1_dat5

gpio_127

IO

-

safe_mode

mmc1_dat6

gpio_128

IO

-

safe_mode

(8) The PU nominal drive strength of this IO cell is equal to 25 mA @ 1.8 V and 41.6 mA @ 3.0 V. The PD nominal drive strength of this IO

cell is equal to 1 mA @ 1.8 V and 1.66 mA @ 3.0 V.

TERMINAL DESCRIPTION

53

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Table 2-2. Ball Characteristics (CBC Pkg.)⁽¹⁾(continued)

BALL

RESET

STATE [6]

BALL

RESET REL.

STATE [7]

BUFFER

HYS [10] STRENG TH

(mA) [11]

PULLUP

/DOWN

TYPE [12]

BALL

BOTTOM [1]

BALL TOP PIN NAME

RESET REL.

MODE [8]

MODE [4]

TYPE [5]

POWER [9]

IO CELL [13]

[2]

[3]

P19

NA

mmc1_dat7

gpio_129

safe_mode

i2c1_scl

0

4

7

0

IO

-

L

7

vdds_mmc1a

No

8

PU/PD⁽⁸⁾

LVCMOS

J25

J24

C2

NA

IOD

H

0

7

vdds

Yes

3

PU100/

PD100

Open Drain

i2c1_sda

i2c2_scl

0

IOD

PU100/

PD100

PU100/

PD100

gpio_168

safe_mode

i2c2_sda

4

7

0

IO

-

4

3

C1

NA

IOD

H

L

H

L

7

vdds

Yes

PU100/

PD100

Open Drain

LVCMOS

gpio_183

safe_mode

i2c3_scl

4

7

0

IO

-

4

3

AB4

AC4

U19

IOD

PU100/

PD100

gpio_184

safe_mode

i2c3_sda

4

7

0

IO

-

4

3

IOD

PU100/

PD100

gpio_185

safe_mode

mcbsp1_clkr

4

7

0

IO

-

4

(9)

IO

4

PU100/

PD100

mcspi4_clk

gpio_156

1

4

7

0

IO

-

safe_mode

mcbsp1_clkx

(9)

T17

T20

NA

IO

L

7

vdds

Yes

PU100/

PD100

LVCMOS

mcbsp3_clkx

gpio_162

2

4

7

0

IO

-

safe_mode

mcbsp1_dr

I

4⁽⁹⁾

PU100/

PD100

mcspi4_somi

mcbsp3_dr

gpio_159

1

2

4

7

0

IO

I

IO

-

safe_mode

mcbsp1_dx

U17

NA

IO

L

7

vdds

Yes

4⁽⁹⁾

PU100/

PD100

LVCMOS

mcspi4_simo

mcbsp3_dx

gpio_158

1

2

4

7

0

IO

-

safe_mode

mcbsp1_fsr

(9)

V17

P20

NA

IO

L

7

vdds

Yes

4

PU100/

PD100

LVCMOS

cam_global_r

eset

2

IO

gpio_157

safe_mode

mcbsp1_fsx

4

7

0

IO

-

IO

4⁽⁹⁾

PU100/

PD100

mcspi4_cs0

mcbsp3_fsx

gpio_161

1

2

4

7

IO

-

safe_mode

(9) The capacity load range is [2 pf to 6 pF].

54 TERMINAL DESCRIPTION

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SPRS505H –FEBRUARY 2008–REVISED OCTOBER 2013

Table 2-2. Ball Characteristics (CBC Pkg.)⁽¹⁾(continued)

BALL

RESET

STATE [6]

BALL

RESET REL.

STATE [7]

BUFFER

HYS [10] STRENG TH

(mA) [11]

PULLUP

/DOWN

TYPE [12]

BALL

BOTTOM [1]

BALL TOP PIN NAME

RESET REL.

MODE [8]

MODE [4]

TYPE [5]

POWER [9]

IO CELL [13]

[2]

[3]

R18

T18

R19

U18

P9

NA

mcbsp2_clkx

0

IO

L

7

vdds

Yes

4⁽¹⁰⁾

PU100/

PD100

LVCMOS

gpio_117

safe_mode

mcbsp2_dr

4

7

0

IO

-

NA

I

vdds

PU100/

PD100

LVCMOS

gpio_118

safe_mode

mcbsp2_dx

4

7

0

IO

-

IO

PU100/

PD100

gpio_119

safe_mode

mcbsp2_fsx

4

7

0

IO

-

IO

PU100/

PD100

gpio_116

safe_mode

mcspi1_clk

4

7

0

IO

-

IO

PU100/

PD100

mmc2_dat4

gpio_171

1

4

7

0

IO

-

safe_mode

mcspi1_cs0

R7

R9

P8

P7

W7

NA

IO

H

L

H

L

7

vdds

Yes

4⁽¹¹⁾

PU100/

PD100

LVCMOS

mmc2_dat7

gpio_174

1

4

7

0

IO

-

safe_mode

mcspi1_cs2

O

4⁽¹¹⁾

PU100/

PD100

mmc3_clk

gpio_176

3

4

7

0

O

IO

-

safe_mode

mcspi1_simo

(11)

IO

4

PU100/

PD100

mmc2_dat5

gpio_172

1

4

7

0

IO

-

safe_mode

mcspi1_somi

IO

L

4⁽¹¹⁾

PU100/

PD100

mmc2_dat6

gpio_173

1

4

7

0

IO

-

safe_mode

mcspi2_clk

IO

L

4⁽¹²⁾

PU100/

PD100

hsusb2_tll_d

ata7

2

3

IO

O

hsusb2_data

7

gpio_178

safe_mode

mcspi2_cs0

4

7

0

IO

-

V8

NA

IO

H

7

vdds

Yes

4⁽¹²⁾

PU100/

PD100

LVCMOS

gpt11_pwm_

evt

1

2

IO

hsusb2_tll_d

ata6

(10) The buffer strength of this IO cell is programmable (2, 4, 6, or 8 mA) according to the selected mode; the default value is described in

the above table.

(11) The buffer strength of this IO cell is programmable (2, 4, 6, or 8 mA) according to the selected mode; the default value is described in

the above table.

(12) The capacity load range is [2 pf to 6 pF].

TERMINAL DESCRIPTION

55

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IO CELL [13]

Table 2-2. Ball Characteristics (CBC Pkg.)⁽¹⁾(continued)

BALL

RESET

STATE [6]

BALL

RESET REL.

STATE [7]

BUFFER

HYS [10] STRENG TH

(mA) [11]

PULLUP

/DOWN

TYPE [12]

BALL

BOTTOM [1]

BALL TOP PIN NAME

RESET REL.

MODE [8]

MODE [4]

TYPE [5]

POWER [9]

[2]

[3]

hsusb2_data

6

3

O

gpio_181

safe_mode

mcspi2_simo

4

7

0

IO

-

W8

NA

IO

L

7

vdds

Yes

4⁽¹²⁾

PU100/

PD100

LVCMOS

gpt9_pwm_e

vt

1

2

3

IO

I

hsusb2_tll_d

ata4

hsusb2_data

4

gpio_179

safe_mode

mcspi2_somi

4

7

0

IO

-

U8

NA

IO

L

7

vdds

Yes

4⁽¹²⁾

PU100/

PD100

LVCMOS

gpt10_pwm_

evt

1

2

3

IO

O

hsusb2_tll_d

ata5

hsusb2_data

5

gpio_180

safe_mode

mmc2_clk

4

7

0

IO

-

W10

R10

T10

NA

O

L

H

L

H

7

vdds

Yes

4⁽¹³⁾

PU100/

PD100

LVCMOS

mcspi3_clk

gpio_130

1

4

7

0

IO

-

safe_mode

mmc2_cmd

IO

PU100/

PD100

mcspi3_simo

gpio_131

1

4

7

0

IO

-

safe_mode

mmc2_dat0

IO

PU100/

PD100

mcspi3_somi

gpio_132

1

4

7

0

IO

-

safe_mode

mmc2_dat1

T9

NA

IO

H

7

vdds

Yes

4⁽¹³⁾

PU100/

PD100

LVCMOS

gpio_133

safe_mode

mmc2_dat2

4

7

0

IO

-

U10

IO

4⁽¹³⁾

PU100/

PD100

mcspi3_cs1

gpio_134

1

4

7

0

O

IO

-

safe_mode

mmc2_dat3

U9

NA

IO

H

L

H

L

7

vdds

Yes

4⁽¹³⁾

PU100/

PD100

LVCMOS

mcspi3_cs0

gpio_135

1

4

7

0

IO

-

safe_mode

mmc2_dat4

V10

IO

4⁽¹³⁾

PU100/

PD100

mmc2_dir_da

t0

1

O

mmc3_dat0

gpio_136

3

4

7

IO

-

safe_mode

(13) The capacity load range is [2 pf to 6 pF].

56 TERMINAL DESCRIPTION

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SPRS505H –FEBRUARY 2008–REVISED OCTOBER 2013

Table 2-2. Ball Characteristics (CBC Pkg.)⁽¹⁾(continued)

BALL

RESET

STATE [6]

BALL

RESET REL.

STATE [7]

BUFFER

HYS [10] STRENG TH

(mA) [11]

PULLUP

/DOWN

TYPE [12]

BALL

BOTTOM [1]

BALL TOP PIN NAME

RESET REL.

MODE [8]

MODE [4]

TYPE [5]

POWER [9]

IO CELL [13]

[2]

[3]

R2

NA

uart1_rts

0

O

L

7

vdds

Yes

4⁽¹³⁾

PU100/

PD100

LVCMOS

gpio_149

safe_mode

uart1_rx

4

7

0

IO

-

(13)

H3

NA

I

L

7

vdds

Yes

4

PU100/

PD100

LVCMOS

mcbsp1_clkr

mcspi4_clk

gpio_151

2

3

4

7

0

IO

-

safe_mode

uart1_tx

L4

NA

O

L

7

vdds

Yes

4⁽¹³⁾

PU100/

PD100

LVCMOS

gpio_148

safe_mode

uart2_cts

4

7

0

IO

-

Y24

I

H

4

PU100/

PD100

mcbsp3_dx

1

2

IO

gpt9_pwm_e

vt

gpio_144

safe_mode

uart2_rts

4

7

0

IO

-

AA24

AD21

AD22

NA

O

H

7

vdds

Yes

4

PU100/

PD100

LVCMOS

mcbsp3_dr

1

2

I

gpt10_pwm_

evt

IO

gpio_145

safe_mode

uart2_rx

4

7

0

IO

-

I

PU100/

PD100

mcbsp3_fsx

1

2

IO

gpt8_pwm_e

vt

gpio_147

safe_mode

uart2_tx

4

7

0

IO

-

O

PU100/

PD100

mcbsp3_clkx

1

2

IO

gpt11_pwm_

evt

gpio_146

4

7

0

IO

-

safe_mode

F23

F24

H24

G24

J23

NA

uart3_cts_rct

x

IO

H

7

vdds

Yes

4

PU100/

PD100

LVCMOS

gpio_163

safe_mode

uart3_rts_sd

4

7

0

IO

-

O

PU100/

PD100

gpio_164

safe_mode

uart3_rx_irrx

4

7

0

IO

-

I

PU100/

PD100

gpio_165

safe_mode

uart3_tx_irtx

4

7

0

IO

-

O

PU100/

PD100

gpio_166

safe_mode

hdq_sio

4

7

0

IO

-

IOD

PU100/

PD100

sys_altclk

1

I

TERMINAL DESCRIPTION

57

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IO CELL [13]

Table 2-2. Ball Characteristics (CBC Pkg.)⁽¹⁾(continued)

BALL

RESET

STATE [6]

BALL

RESET REL.

STATE [7]

BUFFER

HYS [10] STRENG TH

(mA) [11]

PULLUP

/DOWN

TYPE [12]

BALL

BOTTOM [1]

BALL TOP PIN NAME

RESET REL.

MODE [8]

MODE [4]

TYPE [5]

POWER [9]

[2]

[3]

i2c2_sccbe

i2c3_sccbe

gpio_170

2

3

4

7

0

O

IO

-

safe_mode

i2c4_scl

AD15

W16

NA

IOD

H

0

vdds

Yes

3

4

PU100/

PD100

Open Drain

sys_nvmode

1

O

safe_mode

i2c4_sda

7

0

-

4

3

IOD

PU100/

PD100

sys_nvmode

2

1

O

4

safe_mode

sys_boot0

7

0

-

I

4

F3

D3

C3

E3

E4

NA

Z

0

vdds

Yes

PU100/

PD100

LVCMOS

gpio_2

4

7

0

IO

-

safe_mode

sys_boot1

I

4

PU100/

PD100

gpio_3

4

7

0

IO

-

safe_mode

sys_boot2

I

PU100/

PD100

gpio_4

4

7

0

IO

-

safe_mode

sys_boot3

I

PU100/

PD100

gpio_5

4

7

0

IO

-

safe_mode

sys_boot4

I

PU100/

PD100

mmc2_dir_da

t2

1

O

gpio_6

4

7

0

IO

-

safe_mode

sys_boot5

G3

NA

I

Z

0

vdds

Yes

4

PU100/

PD100

LVCMOS

mmc2_dir_da

t3

1

O

gpio_7

4

7

0

IO

-

safe_mode

sys_boot6

D4

AE14

W11

W15

V16

NA

I

Z

L

0

H

Z

L

1

H

0

7

0

7

vdds

Yes

4

PU100/

PD100

LVCMOS

gpio_8

4

7

0

IO

-

safe_mode

sys_clkout1

O

PU100/

PD100

gpio_10

4

7

0

IO

-

safe_mode

sys_clkout2

O

4⁽¹⁴⁾

PU100/

PD100

gpio_186

safe_mode

sys_clkreq

4

7

0

IO

-

IO

4

PU100/

PD100

gpio_1

safe_mode

sys_nirq

4

7

0

IO

-

I

4

PU100/

PD100

(14) The capacity load range is [2 pf to 6 pF].

58 TERMINAL DESCRIPTION

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SPRS505H –FEBRUARY 2008–REVISED OCTOBER 2013

Table 2-2. Ball Characteristics (CBC Pkg.)⁽¹⁾(continued)

BALL

RESET

STATE [6]

BALL

RESET REL.

STATE [7]

BUFFER

HYS [10] STRENG TH

(mA) [11]

PULLUP

/DOWN

TYPE [12]

BALL

BOTTOM [1]

BALL TOP PIN NAME

RESET REL.

MODE [8]

MODE [4]

TYPE [5]

POWER [9]

IO CELL [13]

[2]

[3]

gpio_0

4

7

0

IO

-

safe_mode

V13

AD7

NA

sys_nrespwr

on

I

Z

0

I

NA

0

vdds

Yes

NA

4

NA

LVCMOS

AA5

sys_nreswar

m

0

IOD

1 (PU)

PU100/

PD100

gpio_30

4

7

0

IO

-

Open Drain

safe_mode

V12

NA

sys_off_mod

e

O

0

L

7

vdds

Yes

4

PU100/

PD100

LVCMOS

gpio_9

safe_mode

sys_xtalin

sys_xtalout

tv_out1

4

7

0

IO

-

AF19

AF20

W26

V26

NA

I

Z

L

I

O

NA

0

vdds

Yes

No

NA

8

NA

LVCMOS

10-bit DAC

LVCMOS

O

AO

O

I

0

vdda_dac

vdds

tv_out2

0

No

8

W25

U24

tv_vfb1

NA

I

0

No

2

tv_vfb2

0

No

2

V23

tv_vref

0

No

NA

4⁽¹⁵⁾

AE20

A24

sys_32k

cam_d2

I

NA

7

Yes

I

L

vdds

PU100/

PD100

gpio_101

hw_dbg4

safe_mode

cam_d3

4

5

7

0

IO

O

-

B24

D24

C24

D25

E26

B23

NA

I

L

7

vdds

Yes

4⁽¹⁵⁾

PU100/

PD100

LVCMOS

gpio_102

hw_dbg5

safe_mode

cam_d4

4

5

7

0

IO

O

-

I

4⁽¹⁵⁾

PU100/

PD100

gpio_103

hw_dbg6

safe_mode

cam_d5

4

5

7

0

IO

O

-

(15)

I

4

PU100/

PD100

gpio_104

hw_dbg7

safe_mode

cam_d10

4

5

7

0

IO

O

-

I

4⁽¹⁵⁾

PU100/

PD100

gpio_109

hw_dbg8

safe_mode

cam_d11

4

5

7

0

IO

O

-

I

PU100/

PD100

gpio_110

hw_dbg9

safe_mode

cam_fld

4

5

7

0

IO

O

-

IO

PU100/

PD100

cam_global_r

eset

2

IO

gpio_98

hw_dbg3

safe_mode

4

5

7

IO

O

-

(15) The capacity load range is [2 pf to 6 pF].

TERMINAL DESCRIPTION

59

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www.ti.com

Table 2-2. Ball Characteristics (CBC Pkg.)⁽¹⁾(continued)

BALL

RESET

STATE [6]

BALL

RESET REL.

STATE [7]

BUFFER

HYS [10] STRENG TH

(mA) [11]

PULLUP

/DOWN

TYPE [12]

BALL

BOTTOM [1]

BALL TOP PIN NAME

RESET REL.

MODE [8]

MODE [4]

TYPE [5]

POWER [9]

IO CELL [13]

[2]

[3]

C23

C26

D26

NA

cam_hs

0

IO

L

7

vdds

Yes

4⁽¹⁵⁾

PU100/

PD100

LVCMOS

gpio_94

hw_dbg0

safe_mode

cam_pclk

4

5

7

0

IO

O

-

NA

I

vdds

PU100/

PD100

LVCMOS

gpio_97

hw_dbg2

4

5

7

0

IO

O

-

safe_mode

cam_strobe

O

PU100/

PD100

gpio_126

hw_dbg11

safe_mode

cam_xclka

4

5

7

0

IO

O

-

C25

E25

P25

P26

N25

N26

D23

NA

O

L

7

vdds

Yes

NA

4⁽¹⁵⁾

4⁽¹⁶⁾

4

PU100/

PD100

LVCMOS

SubLVDS

LVCMOS

gpio_96

safe_mode

cam_xclkb

4

7

0

IO

-

O

PU100/

PD100

gpio_111

safe_mode

cam_d6

4

7

0

IO

-

I

PU100/

PD100

gpio_105

safe_mode

cam_d7

4

7

0

IO

-

I

NA

4

PU100/

PD100

gpio_106

safe_mode

cam_d8

4

7

0

IO

-

I

NA

4

PU100/

PD100

gpio_107

safe_mode

cam_d9

4

7

0

IO

-

I

NA

4

PU100/

PD100

gpio_108

safe_mode

cam_vs

4

7

0

IO

-

IO

Yes

4⁽¹⁶⁾

PU100/

PD100

gpio_95

hw_dbg1

safe_mode

cam_wen

4

5

7

0

IO

O

-

(16)

A23

NA

I

L

7

vdds

Yes

4

PU100/

PD100

LVCMOS

cam_shutter

gpio_167

2

4

5

7

0

O

IO

O

-

hw_dbg10

safe_mode

dss_acbias

F26

G26

NA

O

L

7

vdds

Yes

8

PU100/

PD100

LVCMOS

gpio_69

safe_mode

dss_data6

4

7

0

IO

-

IO

PU100/

PD100

uart1_tx

gpio_76

2

4

5

O

IO

O

hw_dbg14

(16) The capacity load range is [2 pf to 6 pF].

60 TERMINAL DESCRIPTION

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SPRS505H –FEBRUARY 2008–REVISED OCTOBER 2013

Table 2-2. Ball Characteristics (CBC Pkg.)⁽¹⁾(continued)

BALL

RESET

STATE [6]

BALL

RESET REL.

STATE [7]

BUFFER

HYS [10] STRENG TH

(mA) [11]

PULLUP

/DOWN

TYPE [12]

BALL

BOTTOM [1]

BALL TOP PIN NAME

RESET REL.

MODE [8]

MODE [4]

TYPE [5]

POWER [9]

IO CELL [13]

[2]

[3]

safe_mode

dss_data7

7

0

-

H25

NA

IO

L

7

vdds

Yes

8

PU100/

PD100

LVCMOS

uart1_rx

gpio_77

2

4

5

7

0

I

IO

O

-

hw_dbg15

safe_mode

dss_data8

H26

J26

NA

IO

L

7

vdds

Yes

8

PU100/

PD100

LVCMOS

gpio_78

hw_dbg16

safe_mode

dss_data9

4

5

7

0

IO

O

-

IO

PU100/

PD100

gpio_79

hw_dbg17

safe_mode

dss_data16

4

5

7

0

IO

O

-

L25

L26

M24

NA

IO

L

7

vdds

Yes

8

PU100/

PD100

LVCMOS

gpio_86

4

7

0

IO

-

safe_mode

dss_data17

IO

PU100/

PD100

gpio_87

4

7

0

IO

-

safe_mode

dss_data18

IO

PU100/

PD100

mcspi3_clk

dss_data0

gpio_88

2

3

4

7

0

IO

-

safe_mode

dss_data19

M26

N24

K24

NA

IO

L

7

vdds

Yes

8

4

PU100/

PD100

LVCMOS

mcspi3_simo

dss_data1

gpio_89

2

3

4

7

0

IO

-

safe_mode

dss_data21

O

L

PU100/

PD100

mcspi3_cs0

dss_data3

gpio_91

2

3

4

7

0

IO

-

safe_mode

dss_hsync

O

H

PU100/

PD100

gpio_67

hw_dbg13

safe_mode

dss_vsync

4

5

7

0

IO

O

-

M25

R8

NA

O

H

7

vdds

Yes

4

PU100/

PD100

LVCMOS

gpio_68

4

7

0

IO

-

safe_mode

mcspi1_cs1

O

4⁽¹⁷⁾

PU100/

PD100

mmc3_cmd

gpio_175

3

4

7

IO

-

safe_mode

(17) The buffer strength of this IO cell is programmable (2, 4, 6, or 8 mA) according to the selected mode; the default value is described in

the above table.

TERMINAL DESCRIPTION

61

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Table 2-2. Ball Characteristics (CBC Pkg.)⁽¹⁾(continued)

BALL

RESET

STATE [6]

BALL

RESET REL.

STATE [7]

BUFFER

HYS [10] STRENG TH

(mA) [11]

PULLUP

/DOWN

TYPE [12]

BALL

BOTTOM [1]

BALL TOP PIN NAME

RESET REL.

MODE [8]

MODE [4]

TYPE [5]

POWER [9]

IO CELL [13]

[2]

[3]

T8

NA

mcspi1_cs3

0

2

3

O

H

7

vdds

Yes

4⁽¹⁸⁾

PU100/

PD100

LVCMOS

hsusb2_tll_d

ata2

IO

hsusb2_data

2

gpio_177

mm2_txdat

safe_mode

mcspi2_cs1

4

5

7

0

IO

-

V9

NA

O

L

7

vdds

Yes

4⁽¹⁸⁾

PU100/

PD100

LVCMOS

gpt8_pwm_e

vt

1

2

3

IO

hsusb2_tll_d

ata3

hsusb2_data

3

gpio_182

mm2_txen_n

safe_mode

mcbsp_clks

4

5

7

0

IO

-

(19)

T19

NA

I

L

7

vdds

Yes

4

PU100/

PD100

LVCMOS

cam_shutter

gpio_160

uart1_cts

safe_mode

etk_clk

2

4

5

7

0

O

IO

I

-

AB2

NA

O

H

4

vdds

Yes

4⁽¹⁹⁾

PU100/

PD100

LVCMOS

mcbsp5_clkx

mmc3_clk

hsusb1_stp

gpio_12

1

2

3

4

5

6

IO

O

IO

I

mm1_rxdp

hsusb1_tll_st

p

hw_dbg0

etk_ctl

7

0

O

AB3

NA

H

4

vdds

Yes

4⁽¹⁹⁾

PU100/

PD100

LVCMOS

mmc3_cmd

hsusb1_clk

gpio_13

2

3

4

6

IO

O

IO

O

hsusb1_tll_cl

k

hw_dbg1

etk_d0

7

0

O

(19)

AC3

NA

H

4

vdds

Yes

4

PU100/

PD100

LVCMOS

mcspi3_simo

mmc3_dat4

1

2

3

IO

hsusb1_data

0

gpio_14

4

5

6

IO

mm1_rxrcv

hsusb1_tll_d

ata0

hw_dbg2

etk_d1

7

0

O

AD4

NA

H

4

vdds

Yes

4⁽¹⁹⁾

PU100/

PD100

LVCMOS

mcspi3_somi

1

IO

(18) The capacity load range is [2 pf to 6 pF].

(19) The capacity load range is [2 pf to 6 pF].

62

TERMINAL DESCRIPTION

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SPRS505H –FEBRUARY 2008–REVISED OCTOBER 2013

Table 2-2. Ball Characteristics (CBC Pkg.)⁽¹⁾(continued)

BALL

RESET

STATE [6]

BALL

RESET REL.

STATE [7]

BUFFER

HYS [10] STRENG TH

(mA) [11]

PULLUP

/DOWN

TYPE [12]

BALL

BOTTOM [1]

BALL TOP PIN NAME

RESET REL.

MODE [8]

MODE [4]

TYPE [5]

POWER [9]

IO CELL [13]

[2]

[3]

hsusb1_data

1

3

IO

gpio_15

4

5

6

IO

mm1_txse0

hsusb1_tll_d

ata1

hw_dbg3

etk_d2

7

0

O

AD3

AA3

Y3

NA

H

L

H

L

4

vdds

Yes

4⁽¹⁹⁾

4⁽²⁰⁾

PU100/

PD100

LVCMOS

mcspi3_cs0

1

3

IO

hsusb1_data

2

gpio_16

4

5

6

IO

mm1_txdat

hsusb1_tll_d

ata2

hw_dbg4

etk_d3

7

0

O

NA

vdds

PU100/

PD100

LVCMOS

mcspi3_clk

mmc3_dat3

1

2

3

IO

hsusb1_data

7

gpio_17

4

6

IO

hsusb1_tll_d

ata7

hw_dbg5

etk_d4

7

0

O

PU100/

PD100

mcbsp5_dr

mmc3_dat0

1

2

3

I

IO

hsusb1_data

4

gpio_18

4

6

IO

hsusb1_tll_d

ata4

hw_dbg6

etk_d5

7

0

O

AB1

AE3

AD2

4⁽²⁰⁾

PU100/

PD100

mcbsp5_fsx

mmc3_dat1

1

2

3

IO

hsusb1_data

5

gpio_19

4

6

IO

hsusb1_tll_d

ata5

hw_dbg7

etk_d6

7

0

O

(20)

4

PU100/

PD100

mcbsp5_dx

mmc3_dat2

1

2

3

IO

hsusb1_data

6

gpio_20

4

6

IO

hsusb1_tll_d

ata6

hw_dbg8

etk_d7

7

0

O

4⁽²⁰⁾

PU100/

PD100

mcspi3_cs1

1

O

(20) The capacity load range is [2 pf to 6 pF].

TERMINAL DESCRIPTION

63

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IO CELL [13]

Table 2-2. Ball Characteristics (CBC Pkg.)⁽¹⁾(continued)

BALL

RESET

STATE [6]

BALL

RESET REL.

STATE [7]

BUFFER

HYS [10] STRENG TH

(mA) [11]

PULLUP

/DOWN

TYPE [12]

BALL

BOTTOM [1]

BALL TOP PIN NAME

RESET REL.

MODE [8]

MODE [4]

TYPE [5]

POWER [9]

[2]

[3]

mmc3_dat7

2

3

IO

hsusb1_data

3

gpio_21

4

5

6

IO

mm1_txen_n

hsusb1_tll_d

ata3

hw_dbg9

etk_d8

7

0

O

AA4

NA

L

4

vdds

Yes

4⁽²⁰⁾

PU100/

PD100

LVCMOS

sys_drm_ms

ecure

1

O

mmc3_dat6

hsusb1_dir

gpio_22

2

3

4

6

IO

I

IO

O

hsusb1_tll_di

r

hw_dbg10

etk_d9

7

0

O

(21)

V2

NA

L

4

vdds

Yes

4

PU100/

PD100

LVCMOS

sys_secure_i

ndicator

1

O

mmc3_dat5

hsusb1_nxt

gpio_23

2

3

4

5

6

IO

I

IO

O

mm1_rxdm

hsusb1_tll_n

xt

hw_dbg11

etk_d10

7

0

O

AE4

NA

L

4

vdds

Yes

4⁽²¹⁾

PU100/

PD100

LVCMOS

uart1_rx

hsusb2_clk

gpio_24

2

3

4

6

I

O

IO

O

hsusb2_tll_cl

k

hw_dbg12

etk_d11

7

0

O

AF6

NA

L

4

vdds

Yes

4⁽²¹⁾

PU100/

PD100

LVCMOS

hsusb2_stp

gpio_25

3

4

5

6

O

IO

I

mm2_rxdp

hsusb2_tll_st

p

hw_dbg13

etk_d12

7

0

O

AE6

NA

L

4

vdds

Yes

4⁽²¹⁾

PU100/

PD100

LVCMOS

hsusb2_dir

gpio_26

3

4

6

I

IO

O

hsusb2_tll_di

r

hw_dbg14

etk_d13

7

0

O

AF7

NA

L

4

vdds

Yes

4⁽²¹⁾

PU100/

PD100

LVCMOS

hsusb2_nxt

gpio_27

3

4

5

6

I

IO

O

mm2_rxdm

hsusb2_tll_n

xt

hw_dbg15

7

O

(21) The capacity load range is [2 pf to 6 pF].

64 TERMINAL DESCRIPTION

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SPRS505H –FEBRUARY 2008–REVISED OCTOBER 2013

Table 2-2. Ball Characteristics (CBC Pkg.)⁽¹⁾(continued)

BALL

RESET

STATE [6]

BALL

RESET REL.

STATE [7]

BUFFER

HYS [10] STRENG TH

(mA) [11]

PULLUP

/DOWN

TYPE [12]

BALL

BOTTOM [1]

BALL TOP PIN NAME

RESET REL.

MODE [8]

MODE [4]

TYPE [5]

POWER [9]

IO CELL [13]

[2]

[3]

AF9

NA

etk_d14

0

3

O

L

4

vdds

Yes

4⁽²¹⁾

PU100/

PD100

LVCMOS

hsusb2_data

0

IO

gpio_28

4

5

6

IO

mm2_rxrcv

hsusb2_tll_d

ata0

hw_dbg16

etk_d15

7

0

O

AE9

NA

L

4

vdds

Yes

4⁽²¹⁾

PU100/

PD100

LVCMOS

hsusb2_data

1

3

IO

gpio_29

4

5

6

IO

mm2_txse0

hsusb2_tll_d

ata1

hw_dbg17

jtag_emu0

7

0

O

Y15

Y14

U3

NA

IO

H

L

H

L

0

7

vdds

Yes

4

PU100/

PD100

LVCMOS

gpio_11

safe_mode

jtag_emu1

4

7

0

IO

-

IO

PU100/

PD100

gpio_31

safe_mode

mcbsp3_clkx

4

7

0

IO

-

IO

4⁽²²⁾

PU100/

PD100

uart2_tx

1

4

5

O

gpio_142

IO

hsusb3_tll_d

ata6

safe_mode

mcbsp3_dr

7

0

-

I

N3

P3

W3

V3

NA

L

7

vdds

Yes

4⁽²²⁾

PU100/

PD100

LVCMOS

uart2_rts

gpio_141

1

4

5

O

IO

hsusb3_tll_d

ata5

safe_mode

mcbsp3_dx

7

0

-

IO

4⁽²²⁾

PU100/

PD100

uart2_cts

gpio_140

1

4

5

I

IO

hsusb3_tll_d

ata4

safe_mode

mcbsp3_fsx

7

0

-

IO

4⁽²²⁾

PU100/

PD100

uart2_rx

1

4

5

I

gpio_143

IO

hsusb3_tll_d

ata7

safe_mode

7

0

-

(22)

mcbsp4_clkx

IO

4

PU100/

PD100

gpio_152

4

5

IO

hsusb3_tll_d

ata1

mm3_txse0

6

IO

(22) The capacity load range is [2 pf to 6 pF].

TERMINAL DESCRIPTION

65

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Table 2-2. Ball Characteristics (CBC Pkg.)⁽¹⁾(continued)

BALL

RESET

STATE [6]

BALL

RESET REL.

STATE [7]

BUFFER

HYS [10] STRENG TH

(mA) [11]

PULLUP

/DOWN

TYPE [12]

BALL

BOTTOM [1]

BALL TOP PIN NAME

RESET REL.

MODE [8]

MODE [4]

TYPE [5]

POWER [9]

IO CELL [13]

[2]

[3]

safe_mode

mcbsp4_dr

7

0

-

I

(22)

U4

R3

T3

NA

L

7

vdds

Yes

4

PU100/

PD100

LVCMOS

gpio_153

4

5

IO

hsusb3_tll_d

ata0

mm3_rxrcv

safe_mode

mcbsp4_dx

6

7

0

IO

-

NA

IO

vdds

4⁽²²⁾

PU100/

PD100

LVCMOS

gpio_154

4

5

IO

hsusb3_tll_d

ata2

mm3_txdat

safe_mode

mcbsp4_fsx

6

7

0

IO

-

(22)

IO

4

PU100/

PD100

gpio_155

4

5

IO

hsusb3_tll_d

ata3

mm3_txen_n

safe_mode

mmc2_dat5

6

7

0

IO

-

M3

IO

4⁽²³⁾

PU100/

PD100

mmc2_dir_da

t1

1

2

O

cam_global_r

eset

IO

mmc3_dat1

gpio_137

3

4

5

IO

I

hsusb3_tll_st

p

mm3_rxdp

safe_mode

mmc2_dat6

6

7

0

IO

-

(23)

L3

NA

IO

L

7

vdds

Yes

4

PU100/

PD100

LVCMOS

mmc2_dir_c

md

1

O

cam_shutter

mmc3_dat2

gpio_138

2

3

4

5

O

IO

O

hsusb3_tll_di

r

safe_mode

mmc2_dat7

7

0

-

(23)

K3

NA

IO

L

7

vdds

Yes

4

PU100/

PD100

LVCMOS

mmc2_clkin

mmc3_dat3

gpio_139

1

3

4

5

I

IO

hsusb3_tll_n

xt

mm3_rxdm

safe_mode

uart1_cts

6

7

0

IO

-

W2

NA

I

L

7

vdds

Yes

4⁽²³⁾

PU100/

PD100

LVCMOS

gpio_150

4

5

IO

O

hsusb3_tll_cl

k

safe_mode

7

-

(23) The capacity load range is [2 pf to 6 pF].

66 TERMINAL DESCRIPTION

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SPRS505H –FEBRUARY 2008–REVISED OCTOBER 2013

Table 2-2. Ball Characteristics (CBC Pkg.)⁽¹⁾(continued)

BALL

RESET

STATE [6]

BALL

RESET REL.

STATE [7]

BUFFER

HYS [10] STRENG TH

(mA) [11]

PULLUP

/DOWN

TYPE [12]

BALL

BOTTOM [1]

BALL TOP PIN NAME

RESET REL.

MODE [8]

MODE [4]

TYPE [5]

POWER [9]

IO CELL [13]

[2]

[3]

AC21, D15,

G11, G18,

H20, M7,

NA

vdd_core

0

PWR

-

M17, R20,

T7, Y8, Y12

D13, G9,

G12, H7,

K11, L9, M9,

M10, N7, N8,

P10, U7,

U11, U13,

V7, V11, W9,

Y9, Y11

NA

vdd_mpu

0

PWR

-

A18, AC7,

AC15, AC18,

AC24, AD20,

AE10, C11,

D9, E24, G4,

J15, J18, L7,

L24, M4, T4,

T24, W24,

Y4, L20,

vdds

-

AB24, AD18,

AD19

U12

K13

U14

NA

vdds_sram

0

PWR

-

vdds_dpll_dll

vdds_dpll_pe

r

W14

NA

vdds_wkup_

bg

0

PWR

-

N23, P23

vdds_mmc1,

vdds_mmc1a

V25

V24

NA

vdda_dac

vssa_dac

vss

0

PWR

GND

-

A6, A8, A13,

AB5, AB22,

AC10, AC16,

AC19, AD14,

AD25,AE7,

AF23, B2,

B25, C12,

D7, D10,

D12, D14,

D18, D20,

E22, G1, G8,

G10, G20,

G23, H4, K1,

K15, K25,

L10, L17,

L19, L23, N4,

N10, N17,

R1, R4, R17,

T23, U25,

W1, W4,

W23, Y7,

Y10, Y16,

Y26

K14, K20,

N9, AE19

NA

cap_vdd_wk

up,

cap_vdd_sra

m_core,

cap_vdd_sra

m_mpu ,

cap_vdd_d

0

PWR

-

A1, L1, AF1, A1, J1, AA1, FeedThrough

T2, Y2, AE2, N2, T2, W2,

AF4, AF5, Y2, AA6, Y7,

-

Pins⁽²⁴⁾

AF8, AF10,

Y9, AA10,

AF12, AF13, AA11, AA12,

AF14, AF15, AA13, Y14,

AF17, AF16, AA14, B16,

A20, AF21, Y17, AA17,

AF18, AF24, Y19, AA19,

AF22, A25,

A20, Y20,

AE25, AF25, AA20, A21,

A26, B26,

K26, U26,

AE26, AF26

B21, H21,

P21, Y21,

AA21

(24) These signals are feed-through balls. For more information, refer to Section 2.5.10.

TERMINAL DESCRIPTION

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Table 2-2. Ball Characteristics (CBC Pkg.)⁽¹⁾(continued)

BALL

RESET

STATE [6]

BALL

RESET REL.

STATE [7]

BUFFER

HYS [10] STRENG TH

(mA) [11]

PULLUP

/DOWN

TYPE [12]

BALL

BOTTOM [1]

BALL TOP PIN NAME

RESET REL.

MODE [8]

MODE [4]

TYPE [5]

POWER [9]

IO CELL [13]

[2]

[3]

A2, A4, A5,

A7, A9, A10,

A11, A12,

A14, A15,

A16, A17,

A19, A21,

A22, AA23,

AB23, AC9,

AC12, AC13,

AC14, AC17,

AC20, AC22,

AC23, AD9,

AD11, AD12,

AD13, AE1,

AE8, AE11,

AE12, AE13,

AF2, AF3,

AF11, B1,

B7, B8, B9,

B10, B11,

B12, B13,

B14, B15,

B16, B17,

B18, B19,

B20, B21,

B22, C7, C8,

C9, C10,

-

No Connect

-

C13, C14,

C15, C16,

C17 C18,

C19, C20,

C21, C22,

D5, D6, D8,

D11, D16,

D17, D19,

D21, D22,

E23, F4, G7,

G13, G14,

G15, G16,

G17, G19,

H8, H9, H10,

H11, H12,

H13, H14,

H15, H16,

H17, H18,

H19, H23,

J3, J4, J7,

J8, J9, J10,

J11, J12,

J13, J14,

J16, J17,

J19, J20, K4,

K7, K8, K9,

K10, K12,

K16, K17,

K19, K23,

L8, M8, M23,

N18, P2, P4,

P24, R23,

R24, R25,

R26, T25,

T26, U23,

V4, W12,

Y23

Table 2-3. Ball Characteristics (CUS Pkg.)

BALL

BALL TOP [2] PIN NAME [3] MODE [4]

TYPE [5]

BALL RESET BALL RESET RESET REL. POWER [9]

HYS [10]

BUFFER

PULLUP

BOTTOM [1]

STATE [6]

REL. STATE MODE [8]

[7]

STRENG TH /DOWN TYPE

(mA) [11]

PU/ PD

[12]

D7

C5

C6

B5

sdrc_d0

sdrc_d1

sdrc_d2

sdrc_d3

sdrc_d4

sdrc_d5

sdrc_d6

sdrc_d7

sdrc_d8

0

IO

L

Z

0

vdds_ mem

Yes

4

LVCMOS

D9

D10

C7

B7

B11

68

TERMINAL DESCRIPTION

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SPRS505H –FEBRUARY 2008–REVISED OCTOBER 2013

Table 2-3. Ball Characteristics (CUS Pkg.) (continued)

BALL

BALL TOP [2] PIN NAME [3] MODE [4]

TYPE [5]

BALL RESET BALL RESET RESET REL. POWER [9]

HYS [10]

BUFFER

PULLUP

BOTTOM [1]

STATE [6]

REL. STATE MODE [8]

[7]

STRENG TH /DOWN TYPE

(mA) [11]

PU/ PD

NA

[12]

C12

B12

D13

C13

B14

A14

B15

C9

sdrc_d9

0

7

0

7

0

IO

O

L

0

1

L

1

H

Z

0

1

0

1

0

7

vdds_ mem

Yes

No

4

LVCMOS

sdrc_d10

sdrc_d11

sdrc_d12

sdrc_d13

sdrc_d14

sdrc_d15

sdrc_d16

sdrc_d17

sdrc_d18

sdrc_d19

sdrc_d20

sdrc_d21

sdrc_d22

sdrc_d23

sdrc_d24

sdrc_d25

sdrc_d26

sdrc_d27

sdrc_d28

sdrc_d29

sdrc_d30

sdrc_d31

sdrc_ba0

sdrc_ba1

sdrc_a0

E12

B8

B9

C10

B10

D12

E13

E15

D15

C15

B16

C16

D16

B17

B18

C18

D18

A4

O

No

NA

O

No

NA

B4

sdrc_a1

O

No

NA

D6

sdrc_a2

O

No

NA

B3

sdrc_a3

O

No

NA

B2

sdrc_a4

O

No

NA

C3

sdrc_a5

O

No

NA

E3

sdrc_a6

O

No

NA

F6

sdrc_a7

O

No

NA

E10

E9

sdrc_a8

O

No

NA

sdrc_a9

O

No

NA

E7

sdrc_a10

sdrc_a11

sdrc_a12

sdrc_a13

sdrc_a14

sdrc_ncs0

sdrc_ncs1

sdrc_clk

O

No

NA

G6

O

No

NA

G7

O

No

NA

F7

O

No

NA

F9

O

No

NA

A19

B19

A10

A11

B20

O

No

NA

O

No

NA

IO

O

Yes

No

PU/ PD

NA

sdrc_nclk

sdrc_cke0

safe_mode

sdrc_cke1

safe_mode

sdrc_nras

sdrc_ncas

sdrc_nwe

sdrc_dm0

sdrc_dm1

sdrc_dm2

sdrc_dm3

O

Yes

PU/ PD

C20

O

H

1

7

vdds_ mem

Yes

4

PU/ PD

LVCMOS

D19

C19

A20

B6

O

1

0

1

0

vdds_ mem

No

4

NA

LVCMOS

B13

A7

A16

TERMINAL DESCRIPTION

69

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PULLUP

Table 2-3. Ball Characteristics (CUS Pkg.) (continued)

BALL

BALL TOP [2] PIN NAME [3] MODE [4]

TYPE [5]

BALL RESET BALL RESET RESET REL. POWER [9]

HYS [10]

BUFFER

BOTTOM [1]

STATE [6]

REL. STATE MODE [8]

[7]

STRENG TH /DOWN TYPE

(mA) [11]

PU/ PD

[12]

A5

sdrc_dqs0

sdrc_dqs1

sdrc_dqs2

sdrc_dqs3

gpmc_a1

gpio_34

0

4

7

0

4

7

0

4

7

0

4

7

0

4

7

0

4

7

0

4

7

0

4

7

0

1

IO

O

L

Z

L

0

7

vdds_ mem

Yes

4

LVCMOS

A13

A8

A17

K4

IO

safe_mode

gpmc_a2

gpio_35

K3

K2

J4

J3

J2

J1

H1

H2

O

L

7

vdds_ mem

Yes

4

PU/ PD

LVCMOS

IO

safe_mode

gpmc_a3

gpio_36

O

L

IO

safe_mode

gpmc_a4

gpio_37

O

L

IO

safe_mode

gpmc_a5

gpio_38

O

L

IO

safe_mode

gpmc_a6

gpio_39

O

H

IO

safe_mode

gpmc_a7

gpio_40

O

IO

safe_mode

gpmc_a8

gpio_41

O

IO

safe_mode

gpmc_a9

O

I

sys_

ndmareq2

gpio_42

4

7

0

1

IO

safe_mode

gpmc_a10

G2

O

I

H

7

vdds_ mem

Yes

4

PU/ PD

LVCMOS

sys_

ndmareq3

gpio_43

4

7

0

4

7

0

4

7

0

4

7

IO

safe_mode

gpmc_d0

gpmc_d1

gpmc_d2

gpmc_d3

gpmc_d4

gpmc_d5

gpmc_d6

gpmc_d7

gpmc_d8

gpio_44

L2

IO

H

0

vdds_ mem

Yes

4

PU/ PD

LVCMOS

M1

M2

N2

M3

P1

P2

R1

R2

safe_mode

gpmc_d9

gpio_45

T2

U1

IO

H

0

vdds_ mem

Yes

4

PU/ PD

LVCMOS

safe_mode

gpmc_d10

gpio_46

IO

safe_mode

70

TERMINAL DESCRIPTION

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SPRS505H –FEBRUARY 2008–REVISED OCTOBER 2013

Table 2-3. Ball Characteristics (CUS Pkg.) (continued)

BALL

BALL TOP [2] PIN NAME [3] MODE [4]

TYPE [5]

BALL RESET BALL RESET RESET REL. POWER [9]

HYS [10]

BUFFER

PULLUP

BOTTOM [1]

STATE [6]

REL. STATE MODE [8]

[7]

STRENG TH /DOWN TYPE

(mA) [11]

[12]

R3

T3

U2

V1

V2

gpmc_d11

gpio_47

0

4

7

0

4

7

0

4

7

0

4

7

0

4

7

0

1

IO

H

0

vdds_ mem

Yes

4

PU/ PD

LVCMOS

safe_mode

gpmc_d12

gpio_48

IO

H

4

PU/ PD

LVCMOS

safe_mode

gpmc_d13

gpio_49

IO

safe_mode

gpmc_d14

gpio_50

IO

safe_mode

gpmc_d15

gpio_51

IO

safe_mode

gpmc_ncs0

gpmc_ncs3

E2

D2

O

I

1

0

7

vdds_ mem

No

4

NA

LVCMOS

H

Yes

PU/ PD

sys_

ndmareq0

gpio_54

4

7

0

1

IO

safe_mode

gpmc_ncs4

F4

O

I

H

7

vdds_ mem

Yes

4

PU/ PD

LVCMOS

sys_

ndmareq1

mcbsp4_ clkx

2

IO

gpt9_pwm_evt 3

gpio_55

4

7

0

1

safe_mode

gpmc_ncs5

G5

O

I

H

7

vdds_ mem

Yes

4

PU/ PD

LVCMOS

sys_

ndmareq2

mcbsp4_dr

2

3

I

gpt10_pwm_e

vt

IO

gpio_56

4

7

0

1

IO

safe_mode

gpmc_ncs6

F3

O

I

H

7

vdds_ mem

Yes

4

PU/ PD

LVCMOS

sys_

ndmareq3

mcbsp4_dx

2

3

IO

gpt11_pwm_e

vt

gpio_57

4

7

0

1

2

IO

safe_mode

gpmc_ncs7

gpmc_io_dir

mcbsp4_fsx

G4

O

H

7

vdds_ mem

Yes

4

PU/ PD

LVCMOS

O

IO

gpt8_pwm_evt 3

gpio_58

4

7

0

4

7

safe_mode

gpmc_clk

gpio_59

W2

F1

O

L

0

vdds_ mem

Yes

No

4

PU/ PD

NA

LVCMOS

IO

safe_mode

gpmc_nadv_al 0

e

O

F2

gpmc_noe

gpmc_nwe

0

O

1

0

vdds_ mem

No

4

NA

LVCMOS

G3

TERMINAL DESCRIPTION

71

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PULLUP

Table 2-3. Ball Characteristics (CUS Pkg.) (continued)

BALL

BALL TOP [2] PIN NAME [3] MODE [4]

TYPE [5]

BALL RESET BALL RESET RESET REL. POWER [9]

HYS [10]

BUFFER

BOTTOM [1]

STATE [6]

REL. STATE MODE [8]

[7]

STRENG TH /DOWN TYPE

(mA) [11]

[12]

K5

gpmc_nbe0_cl 0

e

O

L

0

vdds_ mem

Yes

4

PU/ PD

LVCMOS

gpio_60

4

7

0

4

7

0

4

7

0

1

IO

safe_mode

gpmc_nbe1

gpio_61

L1

E1

O

L

0

7

0

vdds_ mem

Yes

4

PU/ PD

LVCMOS

IO

safe_mode

gpmc_nwp

gpio_62

O

IO

safe_mode

gpmc_wait0

gpmc_wait3

C1

C2

I

H

0

7

vdds_ mem

Yes

NA

4

PU/ PD

LVCMOS

sys_

ndmareq1

gpio_65

4

7

0

4

7

0

4

7

0

4

7

0

4

7

0

2

4

7

0

2

4

7

0

4

7

0

4

7

0

2

4

7

0

2

4

7

0

2

4

7

0

IO

safe_mode

dss_pclk

G22

E22

F22

O

H

L

H

L

7

vdds

Yes

No

4

8

4

PU/ PD

LVCMOS

gpio_66

IO

safe_mode

dss_hsync

gpio_67

O

IO

safe_mode

dss_vsync

gpio_68

O

IO

safe_mode

dss_acbias

gpio_69

J21

O

IO

safe_mode

dss_data0

uart1_cts

gpio_70

AC19

IO

I

L

IO

safe_mode

dss_data1

uart1_rts

AB19

IO

O

L

7

vdds

No

4

PU/ PD

LVCMOS

gpio_71

IO

safe_mode

dss_data2

gpio_72

AD20

AC20

AD21

IO

L

7

vdds

No

4

PU/ PD

LVCMOS

safe_mode

dss_data3

gpio_73

IO

safe_mode

dss_data4

uart3_rx_ irrx

gpio_74

IO

I

IO

safe_mode

dss_data5

uart3_tx_ irtx

gpio_75

AC21

D24

IO

O

L

7

vdds

No

4

8

PU/ PD

LVCMOS

IO

safe_mode

dss_data6

uart1_tx

IO

O

Yes

gpio_76

IO

safe_mode

dss_data7

E23

IO

72

TERMINAL DESCRIPTION

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SPRS505H –FEBRUARY 2008–REVISED OCTOBER 2013

Table 2-3. Ball Characteristics (CUS Pkg.) (continued)

BALL

BALL TOP [2] PIN NAME [3] MODE [4]

TYPE [5]

BALL RESET BALL RESET RESET REL. POWER [9]

HYS [10]

BUFFER

PULLUP

BOTTOM [1]

STATE [6]

REL. STATE MODE [8]

[7]

STRENG TH /DOWN TYPE

(mA) [11]

[12]

uart1_rx

2

4

7

0

4

7

0

4

7

0

4

7

0

4

7

0

4

7

0

4

7

0

4

7

0

4

7

0

4

7

0

4

7

0

2

3

4

7

0

2

3

4

7

0

2

3

4

7

0

2

3

4

7

0

2

I

gpio_77

IO

safe_mode

dss_data8

gpio_78

E24

IO

L

7

vdds

Yes

NA

8

4

8

PU/ PD

LVCMOS

safe_mode

dss_data9

gpio_79

F23

IO

safe_mode

dss_data10

gpio_80

AC22

AC23

AB22

Y22

IO

safe_mode

dss_data11

gpio_81

IO

NA

safe_mode

dss_data12

gpio_82

IO

NA

safe_mode

dss_data13

gpio_83

IO

NA

safe_mode

dss_data14

gpio_84

W22

V22

IO

NA

safe_mode

dss_data15

gpio_85

IO

NA

safe_mode

dss_data16

gpio_86

J22

IO

Yes

safe_mode

dss_data17

gpio_87

G23

G24

IO

safe_mode

dss_data18

mcspi3_clk

dss_data0

gpio_88

IO

safe_mode

dss_data19

mcspi3_ simo

dss_data1

gpio_89

H23

D23

K22

V21

IO

L

H

L

H

L

7

vdds

Yes

NA

8

4

8

4

PU/ PD

LVCMOS

safe_mode

dss_data20

mcspi3_ somi

dss_data2

gpio_90

O

IO

safe_mode

dss_data21

mcspi3_cs0

dss_data3

gpio_91

O

IO

safe_mode

dss_data22

mcspi3_cs1

O

TERMINAL DESCRIPTION

73

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PULLUP

Table 2-3. Ball Characteristics (CUS Pkg.) (continued)

BALL

BALL TOP [2] PIN NAME [3] MODE [4]

TYPE [5]

BALL RESET BALL RESET RESET REL. POWER [9]

HYS [10]

BUFFER

BOTTOM [1]

STATE [6]

REL. STATE MODE [8]

[7]

STRENG TH /DOWN TYPE

(mA) [11]

[12]

dss_data4

gpio_92

3

4

7

0

3

4

7

0

4

7

0

4

7

0

4

7

0

4

7

0

IO

safe_mode

dss_data23

dss_data5

gpio_93

W21

O

L

7

vdds

NA

4

PU/ PD

LVCMOS

IO

safe_mode

tv_out2

AA23

AB24

AB23

Y23

O

I

Z

L

0

7

vdda_dac

vdds

8

NA

10-bit DAC

LVCMOS

tv_out1

0

NA

tv_vfb1

NA

L

NA

tv_vfb2

NA

Y24

tv_vref

NA

A22

cam_hs

IO

Yes

4

PU/ PD

gpio_94

safe_mode

cam_vs

E18

B22

J19

H24

IO

L

7

vdds

PU/ PD

LVCMOS

gpio_95

safe_mode

cam_ xclka

gpio_96

O

IO

safe_mode

cam_pclk

gpio_97

I

IO

safe_mode

cam_fld

IO

cam_global_re 2

set

gpio_98

4

7

0

4

7

0

4

7

0

4

7

0

4

7

0

4

7

0

4

7

0

4

7

0

4

7

0

4

IO

safe_mode

cam_d0

AB18

AC18

G19

F19

I

L

7

vdds

Yes

NA

4

PD

LVCMOS

gpio_99

safe_mode

cam_d1

I

PD

gpio_100

safe_mode

cam_d2

I

PU/ PD

PD

gpio_101

safe_mode

cam_d3

IO

I

gpio_102

safe_mode

cam_d4

IO

G20

B21

L24

I

gpio_103

safe_mode

cam_d5

IO

I

gpio_104

safe_mode

cam_d6

IO

I

gpio_105

safe_mode

cam_d7

IO

K24

J23

I

NA

PD

gpio_106

safe_mode

cam_d8

IO

I

NA

PD

gpio_107

IO

74

TERMINAL DESCRIPTION

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SPRS505H –FEBRUARY 2008–REVISED OCTOBER 2013

Table 2-3. Ball Characteristics (CUS Pkg.) (continued)

BALL

BALL TOP [2] PIN NAME [3] MODE [4]

TYPE [5]

BALL RESET BALL RESET RESET REL. POWER [9]

HYS [10]

BUFFER

PULLUP

BOTTOM [1]

STATE [6]

REL. STATE MODE [8]

[7]

STRENG TH /DOWN TYPE

(mA) [11]

[12]

safe_mode

cam_d9

7

0

4

7

0

4

7

0

4

7

0

4

7

0

2

4

7

0

4

7

0

4

7

0

4

7

0

4

7

0

4

7

0

4

7

0

4

7

0

4

7

0

4

7

0

4

7

0

4

7

0

4

7

0

K23

F21

G21

C22

F18

I

L

7

vdds

NA

4

PD

LVCMOS

gpio_108

IO

safe_mode

cam_d10

I

L

Yes

PU/ PD

LVCMOS

gpio_109

IO

safe_mode

cam_d11

I

gpio_110

IO

safe_mode

cam_ xclkb

gpio_111

O

IO

safe_mode

cam_wen

cam_ shutter

gpio_167

I

O

IO

safe_mode

cam_ strobe

gpio_126

J20

O

L

7

vdds

Yes

4

PU/ PD

PD

LVCMOS

IO

safe_mode

mcbsp2_fsx

gpio_116

V20

T21

V19

R20

M23

L23

M22

M21

M20

N23

N22

N21

IO

vdds

4⁽¹⁾

safe_mode

mcbsp2_ clkx

gpio_117

IO

vdds

4⁽¹⁾

safe_mode

mcbsp2_dr

gpio_118

(1)

I

vdds

4

IO

safe_mode

mcbsp2_dx

gpio_119

IO

vdds

4⁽¹⁾

safe_mode

mmc1_clk

gpio_120

O

vdds_mmc1

8

IO

safe_mode

mmc1_cmd

gpio_121

IO

8

safe_mode

mmc1_dat0

gpio_122

IO

8

safe_mode

mmc1_dat1

gpio_123

IO

8

safe_mode

mmc1_dat2

gpio_124

IO

8

safe_mode

mmc1_dat3

gpio_125

IO

8

safe_mode

mmc1_dat4

gpio_126

IO

vdds_mmc1a No

8

safe_mode

mmc1_dat5

IO

vdds_mmc1a No

8

PD

(1) The buffer strength of this IO cell is programmable (2, 4, 6, or 8 mA) according to the selected mode; the default value is described in

TERMINAL DESCRIPTION

75

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www.ti.com

PULLUP

Table 2-3. Ball Characteristics (CUS Pkg.) (continued)

BALL

BALL TOP [2] PIN NAME [3] MODE [4]

TYPE [5]

BALL RESET BALL RESET RESET REL. POWER [9]

HYS [10]

BUFFER

BOTTOM [1]

STATE [6]

REL. STATE MODE [8]

[7]

STRENG TH /DOWN TYPE

(mA) [11]

[12]

gpio_127

4

7

0

4

7

0

4

7

0

1

4

7

0

1

4

7

0

1

4

7

0

4

7

0

1

4

7

0

1

4

7

0

1

IO

safe_mode

mmc1_dat6

gpio_128

N20

P24

Y1

IO

L

7

vdds_mmc1a No

8

4

PD

LVCMOS

safe_mode

mmc1_dat7

gpio_129

IO

vdds_mmc1a No

PD

safe_mode

mmc2_clk

mcspi3_clk

gpio_130

O

vdds

Yes

PU/ PD

IO

safe_mode

mmc2_ cmd

mcspi3_ simo

gpio_131

AB5

AB3

IO

H

7

Yes

4

PU/ PD

LVCMOS

safe_mode

mmc2_ dat0

mcspi3_ somi

gpio_132

IO

safe_mode

mmc2_ dat1

gpio_133

Y3

IO

H

7

vdds

Yes

4

PU/ PD

LVCMOS

safe_mode

mmc2_ dat2

mcspi3_cs1

gpio_134

W3

IO

O

IO

safe_mode

mmc2_ dat3

mcspi3_cs0

gpio_135

V3

IO

H

L

H

L

7

vdds

Yes

4

PU/ PD

LVCMOS

safe_mode

mmc2_ dat4

AB2

IO

O

mmc2_dir_dat

0

mmc3_dat0

gpio_136

3

4

7

0

1

IO

safe_mode

mmc2_ dat5

AA2

IO

O

L

7

vdds

Yes

4

PU/ PD

LVCMOS

mmc2_dir_dat

1

cam_global_re 2

set

IO

mmc3_dat1

gpio_137

3

4

7

0

1

IO

safe_mode

mmc2_ dat6

Y2

IO

O

L

7

vdds

Yes

4

PU/ PD

LVCMOS

mmc2_dir_

cmd

cam_ shutter

mmc3_dat2

gpio_138

2

3

4

7

0

1

3

4

O

IO

safe_mode

mmc2_ dat7

mmc2_ clkin

mmc3_dat3

gpio_139

AA1

IO

I

L

7

vdds

Yes

4

PU/ PD

LVCMOS

IO

76

TERMINAL DESCRIPTION

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SPRS505H –FEBRUARY 2008–REVISED OCTOBER 2013

Table 2-3. Ball Characteristics (CUS Pkg.) (continued)

BALL

BALL TOP [2] PIN NAME [3] MODE [4]

TYPE [5]

BALL RESET BALL RESET RESET REL. POWER [9]

HYS [10]

BUFFER

PULLUP

BOTTOM [1]

STATE [6]

REL. STATE MODE [8]

[7]

STRENG TH /DOWN TYPE

(mA) [11]

[12]

safe_mode

mcbsp3_dx

uart2_cts

7

0

1

4

7

0

1

4

7

0

1

4

7

0

1

4

7

0

4

7

0

4

7

0

4

7

0

2

3

4

7

0

1

4

7

0

V6

V5

W4

V4

IO

I

L

7

vdds

Yes

4

PU/ PD

LVCMOS

gpio_140

IO

safe_mode

mcbsp3_dr

uart2_rts

I

L

4

PU/ PD

LVCMOS

O

IO

gpio_141

safe_mode

mcbsp3_ clkx

uart2_tx

IO

O

gpio_142

IO

safe_mode

mcbsp3_fsx

uart2_rx

IO

I

gpio_143

IO

safe_mode

uart1_tx

W7

W6

AC2

V7

O

L

7

vdds

Yes

4

PU/ PD

LVCMOS

gpio_148

IO

safe_mode

uart1_rts

O

gpio_149

IO

safe_mode

uart1_cts

I

gpio_150

IO

safe_mode

uart1_rx

I

mcbsp1_ clkr

mcspi4_clk

gpio_151

IO

safe_mode

mcbsp1_ clkr

mcspi4_clk

gpio_156

W19

IO

L

7

vdds

Yes

4

PU/ PD

LVCMOS

safe_mode

mcbsp1_fsr

AB20

IO

cam_global_re 2

set

gpio_157

4

7

0

1

2

4

7

0

1

2

4

7

0

2

4

5

7

IO

safe_mode

mcbsp1_dx

mcspi4_ simo

mcbsp3_dx

gpio_158

W18

IO

L

7

vdds

Yes

4

PU/ PD

LVCMOS

safe_mode

mcbsp1_dr

mcspi4_ somi

mcbsp3_dr

gpio_159

Y18

I

IO

O

IO

safe_mode

mcbsp_clks

cam_ shutter

gpio_160

AA18

I

O

IO

I

uart1_cts

safe_mode

TERMINAL DESCRIPTION

77

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PULLUP

Table 2-3. Ball Characteristics (CUS Pkg.) (continued)

BALL

BALL TOP [2] PIN NAME [3] MODE [4]

TYPE [5]

BALL RESET BALL RESET RESET REL. POWER [9]

HYS [10]

BUFFER

BOTTOM [1]

STATE [6]

REL. STATE MODE [8]

[7]

STRENG TH /DOWN TYPE

(mA) [11]

[12]

AA19

mcbsp1_fsx

mcspi4_cs0

mcbsp3_fsx

gpio_161

0

1

2

4

7

0

2

4

7

IO

L

7

vdds

Yes

4

PU/ PD

LVCMOS

safe_mode

mcbsp1_ clkx

mcbsp3_ clkx

gpio_162

V18

IO

L

7

vdds

Yes

4

PU/ PD

LVCMOS

safe_mode

A23

B23

B24

C23

R21

R23

P23

R22

T24

uart3_cts_ rctx 0

IO

H

L

H

L

7

vdds

Yes

4

PU/ PD

LVCMOS

gpio_163

4

7

0

4

7

0

4

7

0

4

7

0

4

7

0

4

7

0

4

7

0

4

7

safe_mode

uart3_rts_ sd

gpio_164

O

IO

safe_mode

uart3_rx_ irrx

gpio_165

I

IO

safe_mode

uart3_tx_ irtx

gpio_166

O

IO

safe_mode

hsusb0_clk

gpio_120

I

IO

safe_mode

hsusb0_stp

gpio_121

O

H

L

H

L

IO

safe_mode

hsusb0_dir

gpio_122

I

IO

safe_mode

hsusb0_nxt

gpio_124

I

L

IO

safe_mode

hsusb0_ data0 0

IO

O

L

uart3_tx_ irtx

gpio_125

2

4

7

IO

safe_mode

T23

U24

U23

hsusb0_ data1 0

IO

I

L

7

vdds

Yes

4

PU/ PD

LVCMOS

uart3_rx_ irrx

gpio_130

2

4

7

IO

safe_mode

hsusb0_ data2 0

IO

O

uart3_rts_ sd

gpio_131

2

4

7

IO

safe_mode

hsusb0_ data3 0

uart3_cts_ rctx 2

IO

gpio_169

4

7

safe_mode

W24

V23

hsusb0_ data4 0

IO

L

7

vdds

Yes

4

PU/ PD

LVCMOS

gpio_188

4

7

safe_mode

hsusb0_ data5 0

IO

gpio_189

4

7

safe_mode

78

TERMINAL DESCRIPTION

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SPRS505H –FEBRUARY 2008–REVISED OCTOBER 2013

Table 2-3. Ball Characteristics (CUS Pkg.) (continued)

BALL

BALL TOP [2] PIN NAME [3] MODE [4]

TYPE [5]

BALL RESET BALL RESET RESET REL. POWER [9]

HYS [10]

BUFFER

PULLUP

BOTTOM [1]

STATE [6]

REL. STATE MODE [8]

[7]

STRENG TH /DOWN TYPE

(mA) [11]

[12]

W23

T22

hsusb0_ data6 0

IO

L

7

vdds

Yes

4

PU/ PD

LVCMOS

gpio_190

4

7

safe_mode

hsusb0_ data7 0

IO

L

4

PU/ PD

LVCMOS

gpio_191

4

7

0

4

7

0

4

7

0

4

7

0

4

7

0

1

7

0

1

7

0

1

2

3

4

7

0

1

4

7

0

1

4

7

0

1

4

7

0

1

4

7

0

2

safe_mode

i2c1_scl

K20

IOD

IO

H

0

7

vdds

Yes

4

PU/ PD

Open Drain

K21

i2c1_sda

AC15

i2c2_scl

gpio_168

safe_mode

i2c2_sda

AC14

AC13

AC12

Y16

IOD

IO

H

7

0

7

vdds

Yes

4

PU/ PD

Open Drain

LVCMOS

gpio_183

safe_mode

i2c3_scl

IOD

IO

gpio_184

safe_mode

i2c3_sda

IOD

IO

gpio_185

safe_mode

i2c4_scl

IOD

O

sys_ nvmode1

safe_mode

i2c4_sda

Y15

IOD

O

sys_ nvmode2

safe_mode

hdq_sio

A24

IOD

I

sys_altclk

i2c2_sccbe

i2c3_sccbe

gpio_170

O

IO

safe_mode

mcspi1_clk

mmc2_dat4

gpio_171

T5

R4

T4

T6

R5

IO

L

7

vdds

Yes

4⁽²⁾

PU/ PD

LVCMOS

safe_mode

mcspi1_ simo

mmc2_dat5

gpio_172

IO

L

4⁽²⁾

safe_mode

mcspi1_ somi

mmc2_dat6

gpio_173

(2)

IO

L

4

safe_mode

mcspi1_cs0

mmc2_dat7

gpio_174

IO

H

4⁽²⁾

safe_mode

mcspi1_cs3

O

4

hsusb2_tll_

data2

IO

hsusb2_ data2 3

IO

gpio_177

4

5

mm2_txdat

(2) The buffer strength of this IO cell is programmable (2, 4, 6, or 8 mA) according to the selected mode; the default value is described in

TERMINAL DESCRIPTION

79

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PULLUP

Table 2-3. Ball Characteristics (CUS Pkg.) (continued)

BALL

BALL TOP [2] PIN NAME [3] MODE [4]

TYPE [5]

BALL RESET BALL RESET RESET REL. POWER [9]

HYS [10]

BUFFER

BOTTOM [1]

STATE [6]

REL. STATE MODE [8]

[7]

STRENG TH /DOWN TYPE

(mA) [11]

[12]

safe_mode

mcspi2_clk

7

0

2

N5

IO

L

7

vdds

Yes

4

PU/ PD

LVCMOS

hsusb2_tll_

data7

hsusb2_ data7 3

O

gpio_178

4

7

0

IO

safe_mode

mcspi2_ simo

N4

IO

L

7

vdds

Yes

4

PU/ PD

LVCMOS

gpt9_pwm_evt 1

hsusb2_tll_

data4

2

hsusb2_ data4 3

I

gpio_179

4

7

0

1

IO

safe_mode

mcspi2_ somi

N3

M5

M4

IO

L

7

vdds

Yes

4

PU/ PD

LVCMOS

gpt10_pwm_e

vt

hsusb2_tll_

data5

2

IO

hsusb2_ data5 3

O

gpio_180

4

7

0

1

IO

safe_mode

mcspi2_cs0

IO

H

4

PU/ PD

LVCMOS

gpt11_pwm_e

vt

hsusb2_tll_

data6

2

IO

hsusb2_ data6 3

O

gpio_181

4

7

0

IO

safe_mode

mcspi2_cs1

O

L

4

PU/ PD

LVCMOS

gpt8_pwm_evt 1

IO

hsusb2_tll_

data3

2

hsusb2_ data3 3

IO

gpio_182

mm2_txen_n

safe_mode

sys_32k

4

5

7

0

4

7

0

4

7

0

AA16

AD15

AD14

Y13

I

Z

0

I

NA

0

vdds

Yes

NA

4

NA

LVCMOS

sys_xtalin

sys_xtalout

sys_clkreq

gpio_1

I

NA

O

IO

O

1

NA

PU/ PD

safe_mode

sys_nirq

W16

I

H

7

vdds

Yes

4

PU/ PD

LVCMOS

gpio_0

IO

safe_mode

AA10

Y10

sys_

I

Z

0

I

NA

0

vdds

Yes

NA

4

NA

LVCMOS

nrespwron

sys_

nreswarm

0

IOD

IO

1 (PU)

PU/ PD

gpio_30

4

7

0

4

7

0

4

safe_mode

sys_boot0

gpio_2

AB12

AC16

I

Z

0

vdds

Yes

4

PU/ PD

LVCMOS

IO

safe_mode

sys_boot1

gpio_3

I

IO

80

TERMINAL DESCRIPTION

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SPRS505H –FEBRUARY 2008–REVISED OCTOBER 2013

Table 2-3. Ball Characteristics (CUS Pkg.) (continued)

BALL

BALL TOP [2] PIN NAME [3] MODE [4]

TYPE [5]

BALL RESET BALL RESET RESET REL. POWER [9]

HYS [10]

BUFFER

PULLUP

BOTTOM [1]

STATE [6]

REL. STATE MODE [8]

[7]

STRENG TH /DOWN TYPE

(mA) [11]

[12]

safe_mode

sys_boot2

gpio_4

7

0

4

7

0

4

7

0

1

AD17

AD18

AC17

I

Z

0

vdds

Yes

4

PU/ PD

LVCMOS

IO

safe_mode

sys_boot3

gpio_5

I

Z

PU/ PD

LVCMOS

IO

safe_mode

sys_boot4

I

mmc2_dir_dat

2

O

gpio_6

4

7

0

1

IO

safe_mode

sys_boot5

AB16

I

Z

0

vdds

Yes

4

PU/ PD

LVCMOS

mmc2_dir_dat

3

O

gpio_7

4

7

0

4

7

IO

safe_mode

sys_boot6

gpio_8

AA15

AD23

Y7

I

Z

0

L

Z

L

0

7

vdds

Yes

4

PU/ PD

LVCMOS

IO

safe_mode

sys_off_ mode 0

O

gpio_9

4

7

0

4

7

0

4

7

0

4

7

0

4

7

0

1

2

3

4

5

6

0

2

3

4

6

0

1

IO

safe_mode

sys_clkout1

gpio_10

O

IO

safe_mode

sys_clkout2

gpio_186

safe_mode

jtag_ntrst

jtag_tck

AA6

O

IO

AB7

AB6

AA7

AA9

AB10

AB9

AC24

I

L

0

vdds

Yes

NA

4

PU/ PD

LVCMOS

I

L

jtag_rtck

O

IO

I

L

0

jtag_tms_tmsc

jtag_tdi

H

L

H

Z

H

4

NA

4

jtag_tdo

O

IO

jtag_emu0

gpio_11

H

4

safe_mode

jtag_emu1

gpio_31

AD24

AC1

IO

H

0

4

vdds

Yes

4

PU/ PD

LVCMOS

safe_mode

etk_clk

O

mcbsp5_ clkx

mmc3_clk

hsusb1_stp

gpio_12

IO

O

IO

I

mm1_rxdp

hsusb1_tll_stp

etk_ctl

AD3

AD6

O

H

4

vdds

Yes

4

PU/ PD

LVCMOS

mmc3_cmd

hsusb1_clk

gpio_13

IO

O

IO

O

hsusb1_tll_clk

etk_d0

O

PU/ PD

mcspi3_ simo

IO

TERMINAL DESCRIPTION

81

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PULLUP

Table 2-3. Ball Characteristics (CUS Pkg.) (continued)

BALL

BALL TOP [2] PIN NAME [3] MODE [4]

TYPE [5]

BALL RESET BALL RESET RESET REL. POWER [9]

HYS [10]

BUFFER

BOTTOM [1]

STATE [6]

REL. STATE MODE [8]

[7]

STRENG TH /DOWN TYPE

(mA) [11]

PU/ PD

[12]

mmc3_dat4

2

IO

hsusb1_ data0 3

gpio_14

4

5

6

mm1_rxrcv

hsusb1_tll_

data0

AC6

AC7

AD8

AC5

AD2

AC8

AD9

etk_d1

0

1

O

H

L

H

L

4

vdds

Yes

4

LVCMOS

mcspi3_ somi

IO

hsusb1_ data1 3

gpio_15

4

5

6

mm1_txse0

hsusb1_tll_

data1

etk_d2

0

1

O

mcspi3_cs0

IO

hsusb1_ data2 3

gpio_16

4

5

6

mm1_txdat

hsusb1_tll_dat

a2

etk_d3

0

1

2

O

mcspi3_clk

mmc3_dat3

IO

hsusb1_ data7 3

gpio_17

4

6

hsusb1_tll_

data7

etk_d4

0

1

2

O

mcbsp5_dr

mmc3_dat0

I

IO

hsusb1_ data4 3

gpio_18

4

6

hsusb1_tll_

data4

etk_d5

0

1

2

O

L

mcbsp5_fsx

mmc3_dat1

IO

hsusb1_ data5 3

gpio_19

4

6

hsusb1_tll_

data5

etk_d6

0

1

2

O

L

mcbsp5_dx

mmc3_dat2

IO

hsusb1_ data6 3

gpio_20

4

6

hsusb1_tll_

data6

etk_d7

0

1

2

O

L

mcspi3_cs1

mmc3_dat7

O

IO

hsusb1_ data3 3

gpio_21

4

5

6

mm1_txen_n

hsusb1_tll_

data3

AC4

etk_d8

0

O

L

4

vdds

Yes

4

PU/ PD

LVCMOS

82

TERMINAL DESCRIPTION

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SPRS505H –FEBRUARY 2008–REVISED OCTOBER 2013

Table 2-3. Ball Characteristics (CUS Pkg.) (continued)

BALL

BALL TOP [2] PIN NAME [3] MODE [4]

TYPE [5]

BALL RESET BALL RESET RESET REL. POWER [9]

HYS [10]

BUFFER

PULLUP

BOTTOM [1]

STATE [6]

REL. STATE MODE [8]

[7]

STRENG TH /DOWN TYPE

(mA) [11]

[12]

sys_drm_

msecure

1

O

mmc3_dat6

hsusb1_dir

gpio_22

2

3

4

6

0

1

IO

I

IO

O

hsusb1_tll_dir

etk_d9

AD5

L

4

vdds

Yes

4

PU/ PD

LVCMOS

sys_secure_in

dic ator

mmc3_dat5

hsusb1_nxt

gpio_23

2

3

4

5

6

0

2

3

4

6

0

3

4

5

6

0

3

4

6

0

3

4

5

6

0

IO

I

IO

O

I

mm1_rxdm

hsusb1_tll_nxt

etk_d10

AC3

AC9

L

4

vdds

Yes

4

PU/ PD

LVCMOS

uart1_rx

hsusb2_clk

gpio_24

O

IO

O

IO

I

hsusb2_tll_clk

etk_d11

PU/ PD

hsusb2_stp

gpio_25

mm2_rxdp

hsusb2_tll_stp

etk_d12

AC10

AD11

O

I

L

4

vdds

Yes

4

PU/ PD

LVCMOS

hsusb2_dir

gpio_26

IO

O

I

hsusb2_tll_dir

etk_d13

hsusb2_nxt

gpio_27

IO

O

IO

mm2_rxdm

hsusb2_tll_nxt

etk_d14

AC11

L

4

vdds

Yes

4

PU/ PD

LVCMOS

hsusb2_ data0 3

gpio_28

4

5

6

mm2_rxrcv

hsusb2_tll_

data0

AD12

etk_d15

0

O

L

4

vdds

Yes

4

PU/ PD

LVCMOS

hsusb2_ data1 3

IO

gpio_29

4

5

6

mm2_txse0

hsusb2_tll_

data1

E16, F15,

F16, G15,

G16, H15, J6,

J7, J8, K6, K7,

K8

vdds_mem

0

PWR

-

F12, F13,

vdd_core

0

PWR

G12, G13,

H12, H13,

J17, J18, K17,

K18, K19,

L14, L15,

M14, M15,

R17, R18,

R19, T17,

T18, T19, T20

TERMINAL DESCRIPTION

83

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SPRS505H –FEBRUARY 2008–REVISED OCTOBER 2013

www.ti.com

PULLUP

Table 2-3. Ball Characteristics (CUS Pkg.) (continued)

BALL

BALL TOP [2] PIN NAME [3] MODE [4]

TYPE [5]

BALL RESET BALL RESET RESET REL. POWER [9]

HYS [10]

BUFFER

BOTTOM [1]

STATE [6]

REL. STATE MODE [8]

[7]

STRENG TH /DOWN TYPE

(mA) [11]

[12]

F10, G9, G10, vdd_mpu

H9, H10, J9,

J10, L11, L12,

M6, M7, M8,

M12, N6, N7,

N8, R6, R7,

0

PWR

-

R8, T7, T8,

U12, U13,

V12, V13,

W12, W13

H8

vdds_mmc1a

0

PWR

-

M17, M18,

vdds

M19, N17,

N18, N19,

U10, V9, V10,

W9, W10, Y9

N24

vdds_mmc1

0

PWR

-

Y12, U8, H17 cap_vdd_wku

p,

cap_vdd_sram

_mpu ,

cap_vdd_sram

_core

G18

vdds_dpll_dll

vdds_dpll_per

vdds_sram

0

PWR

-

U17

AA12

AA13

vdds_wkup_b

g

AB15

AB13

vssa_dac

vdda_dac

vss

0

GND

PWR

GND

-

H11, H14,

H16, J11, J12,

J13, J14, J15,

J16, K10,

K11, K14,

K15, L8, L10,

L13, L17, M9,

M10, M11,

M13, M16,

N9, N10, N11,

N12, N13,

N14, N15,

N16, P8, P10,

P11, P12,

P13, P14,

P15, P17,

R10, R11,

R14, R15, T9,

T10, T11,

T12, T13,

T14, T15,

T16, U9, U11,

U14, U15,

U16, V15,

V16, W15

AD1, A1, A2, No Connect

B1

-

84

TERMINAL DESCRIPTION

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2.4 Multiplexing Characteristics

Table 2-4 provides a description of the OMAP3515/03 multiplexing on the CBB, CBC, and CUS packages,

respectively.

Note: The following does not take into account subsystem pin multiplexing options. Subsystem pin

multiplexing options are described in Section 2.5, Signal Description.

Table 2-4. Multiplexing Characteristics

CBB

CBC

CUS

MODE 0

MODE 1

MODE 2

MODE 3

MODE 4

MODE 5

MODE 6

MODE 7

Bottom

Top

Bottom

NA

Top

D6

C6

B6

C8

C9

A7

B9

A9

J2

D1

D7

sdrc_d0

J1

NA

G1

C5

sdrc_d1

sdrc_d2

sdrc_d3

sdrc_d4

sdrc_d5

sdrc_d6

sdrc_d7

sdrc_d8

sdrc_d9

sdrc_d10

sdrc_d11

sdrc_d12

sdrc_d13

sdrc_d14

sdrc_d15

sdrc_d16

sdrc_d17

sdrc_d18

sdrc_d19

sdrc_d20

sdrc_d21

sdrc_d22

sdrc_d23

sdrc_d24

sdrc_d25

sdrc_d26

sdrc_d27

sdrc_d28

sdrc_d29

sdrc_d30

sdrc_d31

sdrc_ba0

sdrc_ba1

sdrc_a0

sdrc_a1

sdrc_a2

sdrc_a3

sdrc_a4

sdrc_a5

sdrc_a6

sdrc_a7

sdrc_a8

sdrc_a9

sdrc_a10

sdrc_a11

sdrc_a12

G2

G1

F2

F1

D2

D1

G2

C6

E1

B5

D2

D9

E2

D10

C7

B3

B4

B7

C14

B14

C15

B16

D17

C17

B17

D18

D11

B10

C11

D12

C12

A11

B13

D14

C18

A19

B19

B20

D20

A21

B21

C21

H9

B13

A10

B11

A11

B12

A16

A17

B17

B18

B7

B11

C12

B12

D13

C13

B14

A14

B15

C9

A13

B14

A14

B16

A16

B19

A19

B3

A3

A5

E12

B8

B5

B6

A5

A6

B9

B8

A8

C10

B10

D12

E13

E15

D15

C15

B16

C16

D16

B17

B18

C18

D18

A4

A8

B9

A9

B10

C21

D20

B19

C20

D21

E20

E21

G21

B21

A21

D22

D23

E22

E23

G22

G23

AB21

AC21

N22

N23

P22

P23

R22

R23

T22

AA18

V20

G20

K20

J20

H10

A4

B4

B3

D6

C5

J21

B3

C4

U21

R20

M21

M20

N20

K21

Y16

N21

R21

B2

D5

C3

E3

C2

T23

F6

C1

U22

U23

V22

V23

W22

E10

E9

D4

D3

E7

D2

G6

D1

G7

TERMINAL DESCRIPTION

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MODE 6 MODE 7

Table 2-4. Multiplexing Characteristics (continued)

CBB

CBC

CUS

MODE 0

MODE 1

MODE 2

MODE 3

MODE 4

MODE 5

Bottom

Top

Bottom

NA

Top

AA15

E2

E1

W23

F7

sdrc_a13

sdrc_a14

sdrc_ncs0

sdrc_ncs1

sdrc_clk

Y22

M22

M23

A11

B11

J22

J23

L23

L22

K23

C1

NA

J2

Y12

T21

T20

A12

B13

Y15

Y13

V21

U20

Y18

H1

F9

H11

H12

A13

A14

H16

H17

H14

H13

H15

B7

A19

B19

A10

A11

B20

C20

D19

C19

A20

B6

sdrc_nclk

sdrc_cke0

sdrc_cke1

sdrc_nras

sdrc_ncas

sdrc_nwe

sdrc_dm0

sdrc_dm1

sdrc_dm2

sdrc_dm3

sdrc_dqs0

sdrc_dqs1

sdrc_dqs2

sdrc_dqs3

gpmc_a1

gpmc_a2

gpmc_a3

gpmc_a4

gpmc_a5

gpmc_a6

gpmc_a7

gpmc_a8

gpmc_a9

safe_mode

A16

B11

C20

A6

A17

A6

A14

A4

B13

A7

A20

C2

A18

C2

A16

A5

A17

A10

A20

N4

B17

B6

B15

B8

A13

A8

B20

A19

NA

A17

K4

AC15

AB15

AC16

AB16

AC17

AB17

AC18

AB18

AC19

gpio_34

safe_mode

M4

H1

H2

G2

F1

NA

K3

gpio_35

gpio_36

gpio_37

gpio_38

gpio_39

gpio_40

gpio_41

gpio_42

L4

NA

K2

K4

NA

J4

T3

NA

J3

R3

F2

NA

J2

N3

E1

E2

D1

NA

J1

M3

NA

H1

L3

NA

H2

sys_ndmareq

2

K3

AB19

D2

NA

G2

gpmc_a10

sys_ndmareq

3

gpio_43

safe_mode

K1

L1

M2

AA2

AA1

AC2

AC1

AE5

AD6

AD5

AC5

V1

U2

U1

V2

L2

gpmc_d0

gpmc_d1

gpmc_d2

gpmc_d3

gpmc_d4

gpmc_d5

gpmc_d6

gpmc_d7

gpmc_d8

gpmc_d9

gpmc_d10

gpmc_d11

gpmc_d12

gpmc_d13

gpmc_d14

gpmc_d15

gpmc_ncs0

gpmc_ncs1

gpmc_ncs2

M1

M2

N2

M3

P1

P2

R1

R2

T2

U1

R3

T3

U2

V1

V2

E2

NA

D2

L2

N2

P2

T1

V1

V2

W2

H2

K2

P1

R1

R2

T2

W1

Y1

G4

H3

V8

U8

N1

V1

R2

AA3

AA4

Y3

R1

T2

T1

Y4

AB3

AC3

AB4

AC4

AB6

AC6

AB7

AC7

Y2

R1

T1

gpio_44

gpio_45

gpio_46

gpio_47

gpio_48

gpio_49

gpio_50

gpio_51

safe_mode

Y1

T1

N1

P2

U2

U1

P1

M1

J2

L2

M2

K2

AD8

AD1

A3

AA8

W1

NA

Y1

gpio_52

gpio_53

gpio_54

safe_mode

NA

B6

gpmc_ncs3 sys_ndmareq

0

T8

R8

NA

B4

C4

NA

F4

gpmc_ncs4 sys_ndmareq mcbsp4_clkx gpt9_pwm_e gpio_55

safe_mode

1

vt

G5

gpmc_ncs5 sys_ndmareq mcbsp4_dr

2

gpt10_pwm_ gpio_56

evt

86

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SPRS505H –FEBRUARY 2008–REVISED OCTOBER 2013

Table 2-4. Multiplexing Characteristics (continued)

CBB

CBC

CUS

MODE 0

MODE 1

MODE 2

MODE 3

MODE 4

MODE 5

MODE 6

MODE 7

Bottom

Top

Bottom

Top

P8

NA

B5

C5

N1

NA

F3

gpmc_ncs6 sys_ndmareq mcbsp4_dx gpt11_pwm_ gpio_57

evt

safe_mode

3

N8

NA

G4

gpmc_ncs7 gpmc_io_dir mcbsp4_fsx gpt8_pwm_e gpio_58

vt

T4

F3

W2

W1

L1

W2

F1

gpmc_clk

gpio_59

AD10

AA9

gpmc_nadv_

ale

G2

F4

G3

V2

V1

N2

M1

K2

L2

F2

G3

K5

gpmc_noe

gpmc_nwe

K1

AC12

FT⁽¹⁾

gpmc_nbe0_

cle

gpio_60

safe_mode

U3

H1

NA

J1

NA

Y5

L1

gpmc_nbe1

gpmc_nwp

gpmc_wait0

gpmc_wait1

gpmc_wait2

gpio_61

gpio_62

safe_mode

AB10

AB12

AC10

NA

AC6

AC11

AC8

B3

E1

C1

NA

C2

M8

L8

K8

J8

Y10

Y8

gpio_63

gpio_64

gpio_65

safe_mode

NA

C6

gpmc_wait3 sys_ndmareq

1

D28

D26

D27

E27

NA

G25

K24

M25

F26

NA

G22

E22

F22

J21

dss_pclk

gpio_66

gpio_67

gpio_68

gpio_69

hw_dbg12

hw_dbg13

safe_mode

dss_hsync

dss_vsync

dss_acbias

dss_data0

AG22

AE21

AC19

AB19

AD20

AC20

AD21

AC21

D24

uart1_cts

uart1_rts

dssvenc656_ gpio_70

data0

AH22

AG23

AH23

AG24

AH24

E26

NA

AE22

AE23

AE24

AD23

AD24

G26

NA

dss_data1

dss_data2

dss_data3

dss_data4

dss_data5

dss_data6

dss_data7

dssvenc656_ gpio_71

data1

safe_mode

dssvenc656_ gpio_72

data2

dssvenc656_ gpio_73

data3

uart3_rx_irrx dssvenc656_ gpio_74

data4

uart3_tx_irtx dssvenc656_ gpio_75

data5

uart1_tx

dssvenc656_ gpio_76

data6

hw_dbg14

hw_dbg15

F28

H25

E23

uart1_rx

dssvenc656_ gpio_77

data7

F27

NA

H26

NA

E24

dss_data8

dss_data9

dss_data10

dss_data11

dss_data12

dss_data13

dss_data14

dss_data15

dss_data16

dss_data17

dss_data18

dss_data19

dss_data20

dss_data21

dss_data22

dss_data23

tv_out2

gpio_78

gpio_79

gpio_80

gpio_81

gpio_82

gpio_83

gpio_84

gpio_85

gpio_86

gpio_87

hw_dbg16

hw_dbg17

safe_mode

G26

J26

F23

AD28

AD27

AB28

AB27

AA28

AA27

G25

AC26

AD26

AA25

Y25

AC22

AC23

AB22

Y22

AA26

AB26

L25

W22

V22

J22

H27

L26

G23

G24

H23

D23

K22

H26

M24

M26

F25

mcspi3_clk

dss_data0

gpio_88

gpio_89

gpio_90

gpio_91

gpio_92

gpio_93

H25

mcspi3_simo dss_data1

mcspi3_somi dss_data2

mcspi3_cs0 dss_data3

mcspi3_cs1 dss_data4

dss_data5

E28

J26

N24

AC27

AC28

W28

Y28

AC25

AB25

V26

V21

W21

AA23

AB24

AB23

Y23

W26

W25

U24

tv_out1

Y27

tv_vfb1

W27

W26

tv_vfb2

V23

Y24

tv_vref

(1) "FT" indicates Feed-Through. For more information, refer to Section 2.5.10.

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TERMINAL DESCRIPTION

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MODE 6 MODE 7

Table 2-4. Multiplexing Characteristics (continued)

CBB

CBC

CUS

MODE 0

MODE 1

MODE 2

MODE 3

MODE 4

MODE 5

Bottom

A24

Top

Bottom

C23

Top

NA

A22

E18

B22

J19

H24

cam_hs

gpio_94

hw_dbg0

hw_dbg1

safe_mode

A23

C25

C27

C23

NA

D23

C25

C26

B23

NA

cam_vs

gpio_95

gpio_96

gpio_97

gpio_98

cam_xclka

cam_pclk

cam_fld

hw_dbg2

hw_dbg3

cam_global_r

eset

AG17

AH17

B24

C24

D24

A25

K28

L28

NA

AE16

AE15

A24

B24

D24

C24

P25

P26

N25

N26

D25

E26

E25

A23

D26

AD17

AD16

AE18

AE17

U18

R18

T18

R19

N19

L18

NA

AB18

AC18

G19

F19

G20

B21

L24

K24

J23

K23

F21

G21

C22

F18

J20

NA

cam_d0

cam_d1

cam_d2

cam_d3

cam_d4

cam_d5

cam_d6

cam_d7

cam_d8

cam_d9

cam_d10

cam_d11

cam_xclkb

cam_wen

cam_strobe

gpio_99

safe_mode

gpio_100

gpio_101

gpio_102

gpio_103

gpio_104

gpio_105

gpio_106

gpio_107

gpio_108

gpio_109

gpio_110

gpio_111

gpio_167

gpio_126

gpio_112

gpio_113

gpio_114

gpio_115

gpio_116

gpio_117

gpio_118

gpio_119

gpio_120

gpio_121

gpio_122

gpio_123

gpio_124

gpio_125

gpio_126

gpio_127

gpio_128

gpio_129

gpio_130

gpio_131

gpio_132

gpio_133

gpio_134

gpio_135

hw_dbg4

hw_dbg5

hw_dbg6

hw_dbg7

K27

L27

B25

C26

B26

B23

D25

AG19

AH19

AG18

AH18

P21

N21

R21

M21

N28

M27

N27

N26

N25

P28

P27

P26

R27

R25

AE2

AG5

AH5

AH4

AG4

AF4

AE4

hw_dbg8

hw_dbg9

cam_shutter

hw_dbg10

hw_dbg11

NA

V20

T21

V19

R20

M23

L23

M22

M21

M20

N23

N22

N21

N20

P24

Y1

mcbsp2_fsx

mcbsp2_clkx

mcbsp2_dr

mcbsp2_dx

mmc1_clk

mmc1_cmd

mmc1_dat0

mmc1_dat1

mmc1_dat2

mmc1_dat3

mmc1_dat4

mmc1_dat5

mmc1_dat6

mmc1_dat7

mmc2_clk

M19

M18

K18

N20

M20

P17

P18

P19

W10

R10

T10

T9

mcspi3_clk

AB5

AB3

Y3

mmc2_cmd mcspi3_simo

mmc2_dat0 mcspi3_somi

mmc2_dat1

U10

U9

W3

mmc2_dat2 mcspi3_cs1

mmc2_dat3 mcspi3_cs0

V3

V10

AB2

mmc2_dat4 mmc2_dir_da

t0

mmc3_dat0 gpio_136

AH3

AF3

AE3

AF6

AE6

NA

M3

L3

NA

AA2

Y2

mmc2_dat5 mmc2_dir_da cam_global_r mmc3_dat1 gpio_137

t1 eset

hsusb3_tll_st mm3_rxdp

p

safe_mode

mmc2_dat6 mmc2_dir_c cam_shutter mmc3_dat2 gpio_138

md

hsusb3_tll_di

r

K3

P3

N3

AA1

V6

mmc2_dat7 mmc2_clkin

mmc3_dat3 gpio_139

hsusb3_tll_n mm3_rxdm safe_mode

xt

mcbsp3_dx uart2_cts

gpio_140

hsusb3_tll_d

ata4

safe_mode

V5

mcbsp3_dr

uart2_rts

gpio_141

hsusb3_tll_d

ata5

safe_mode

88

TERMINAL DESCRIPTION

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Table 2-4. Multiplexing Characteristics (continued)

CBB

CBC

CUS

MODE 0

MODE 1

MODE 2

MODE 3

MODE 4

MODE 5

MODE 6

MODE 7

Bottom

AF5

Top

Bottom

U3

Top

NA

W4

V4

mcbsp3_clkx uart2_tx

mcbsp3_fsx uart2_rx

gpio_142

gpio_143

gpio_144

gpio_145

gpio_146

gpio_147

hsusb3_tll_d

ata6

safe_mode

AE5

W3

NA

hsusb3_tll_d

ata7

AB26

AB25

AA25

AD25

Y24

NA

uart2_cts

uart2_rts

uart2_tx

uart2_rx

mcbsp3_dx gpt9_pwm_e

vt

AA24

AD22

AD21

mcbsp3_dr

gpt10_pwm_

evt

mcbsp3_clkx gpt11_pwm_

evt

mcbsp3_fsx gpt8_pwm_e

vt

AA8

AA9

W8

NA

L4

NA

W7

W6

AC2

uart1_tx

uart1_rts

uart1_cts

gpio_148

gpio_149

gpio_150

safe_mode

R2

W2

hsusb3_tll_cl

k

Y8

NA

H3

V3

NA

V7

uart1_rx

mcbsp1_clkr mcspi4_clk

gpio_151

gpio_152

safe_mode

AE1

NA

mcbsp4_clkx

hsusb3_tll_d mm3_txse0 safe_mode

ata1

AD1

AD2

AC1

NA

U4

R3

T3

NA

mcbsp4_dr

mcbsp4_dx

mcbsp4_fsx

gpio_153

gpio_154

gpio_155

hsusb3_tll_d mm3_rxrcv

ata0

safe_mode

NA

hsusb3_tll_d mm3_txdat

ata2

safe_mode

NA

hsusb3_tll_d mm3_txen_n safe_mode

ata3

Y21

NA

U19

V17

NA

W19

mcbsp1_clkr mcspi4_clk

mcbsp1_fsr

gpio_156

gpio_157

safe_mode

AA21

AB20

cam_global_r

eset

V21

U21

T21

K26

W21

H18

NA

U17

T20

T19

P20

T17

F23

NA

W18

Y18

mcbsp1_dx mcspi4_simo mcbsp3_dx

gpio_158

gpio_159

gpio_160

gpio_161

gpio_162

gpio_163

safe_mode

mcbsp1_dr

mcbsp_clks

mcspi4_somi mcbsp3_dr

cam_shutter

AA18

AA19

V18

uart1_cts

safe_mode

mcbsp1_fsx mcspi4_cs0 mcbsp3_fsx

mcbsp1_clkx

mcbsp3_clkx

A23

uart3_cts_rct

x

H19

H20

H21

T28

T25

R28

T26

T27

NA

F24

H24

G24

W19

U20

V19

W18

V20

NA

B23

B24

C23

R21

R23

P23

R22

T24

uart3_rts_sd

uart3_rx_irrx

uart3_tx_irtx

hsusb0_clk

hsusb0_stp

hsusb0_dir

hsusb0_nxt

gpio_164

gpio_165

gpio_166

gpio_120

gpio_121

gpio_122

gpio_124

gpio_125

safe_mode

hsusb0_data

0

uart3_tx_irtx

uart3_rx_irrx

uart3_rts_sd

U28

U27

U26

U25

V28

V27

V26

NA

Y20

V18

W20

W17

Y18

Y19

Y17

NA

T23

U24

U23

W24

V23

W23

T22

hsusb0_data

1

gpio_130

gpio_131

gpio_169

gpio_188

gpio_189

gpio_190

gpio_191

safe_mode

hsusb0_data

2

hsusb0_data

3

uart3_cts_rct

x

hsusb0_data

4

hsusb0_data

5

hsusb0_data

6

hsusb0_data

7

K21

NA

J25

J24

C2

NA

K20

i2c1_scl

i2c1_sda

i2c2_scl

i2c2_sda

i2c3_scl

J21

K21

AF15

AE15

AF14

AC15

AC14

AC13

gpio_168

gpio_183

gpio_184

safe_mode

C1

AB4

TERMINAL DESCRIPTION

89

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MODE 6 MODE 7

Table 2-4. Multiplexing Characteristics (continued)

CBB

CBC

CUS

MODE 0

MODE 1

MODE 2

MODE 3

MODE 4

MODE 5

Bottom

AG14

Top

Bottom

AC4

Top

NA

AC12

i2c3_sda

i2c4_scl

gpio_185

safe_mode

AD26

NA

AD15

NA

Y16

sys_nvmode

1

AE26

NA

W16

NA

Y15

i2c4_sda

sys_nvmode

2

safe_mode

J25

NA

J23

P9

P8

P7

R7

R8

R9

T8

NA

A24

T5

hdq_sio

sys_altclk

i2c2_sccbe i2c3_sccbe gpio_170

safe_mode

AB3

AB4

AA4

AC2

AC3

AB1

AB2

mcspi1_clk

mmc2_dat4

gpio_171

gpio_172

R4

T4

mcspi1_simo mmc2_dat5

mcspi1_somi mmc2_dat6

mcspi1_cs0 mmc2_dat7

mcspi1_cs1

gpio_173

T6

gpio_174

NA

R5

mmc3_cmd gpio_175

mcspi1_cs2

mmc3_clk

gpio_176

mcspi1_cs3

hsusb2_tll_d hsusb2_data gpio_177

mm2_txdat

ata2

2

AA3

Y2

NA

W7

W8

U8

V8

V9

NA

N5

N4

N3

M5

M4

mcspi2_clk

hsusb2_tll_d hsusb2_data gpio_178

safe_mode

ata7

7

mcspi2_simo gpt9_pwm_e hsusb2_tll_d hsusb2_data gpio_179

vt ata4

4

Y3

mcspi2_somi gpt10_pwm_ hsusb2_tll_d hsusb2_data gpio_180

evt ata5

5

Y4

mcspi2_cs0 gpt11_pwm_ hsusb2_tll_d hsusb2_data gpio_181

evt ata6

6

V3

mcspi2_cs1 gpt8_pwm_e hsusb2_tll_d hsusb2_data gpio_182

mm2_txen_n

vt

ata3

3

AE25

AE17

AF17

AF25

AF26

AH25

NA

AE20

AF19

AF20

W15

V16

NA

AA16

AD15

AD14

Y13

sys_32k

sys_xtalin

sys_xtalout

sys_clkreq

sys_nirq

gpio_1

gpio_0

safe_mode

W16

V13

AA10

sys_nrespwr

on

AF24

NA

AD7

NA

Y10

sys_nreswar

m

gpio_30

safe_mode

AH26

AG26

AE14

AF18

AF19

NA

F3

D3

C3

E3

E4

NA

AB12

AC16

AD17

AD18

AC17

sys_boot0

sys_boot1

sys_boot2

sys_boot3

sys_boot4

gpio_2

gpio_3

gpio_4

gpio_5

gpio_6

safe_mode

mmc2_dir_da

t2

AE21

NA

G3

NA

AB16

sys_boot5

sys_boot6

mmc2_dir_da

t3

gpio_7

safe_mode

AF21

AF22

NA

D4

NA

AA15

AD23

gpio_8

gpio_9

safe_mode

V12

sys_off_mod

e

AG25

AE22

AA17

AA13

AA12

AA18

NA

AE14

W11

U15

V14

NA

Y7

sys_clkout1

sys_clkout2

jtag_ntrst

jtag_tck

gpio_10

safe_mode

AA6

AB7

AB6

AA7

AA9

gpio_186

W13

V15

jtag_rtck

jtag_tms_tms

c

AA20

AA19

AA11

AA10

AF10

NA

U16

Y13

Y15

Y14

AB2

NA

AB10

AB9

jtag_tdi

jtag_tdo

jtag_emu0

jtag_emu1

etk_clk

AC24

AD24

AC1

gpio_11

gpio_31

safe_mode

mcbsp5_clkx mmc3_clk

hsusb1_stp gpio_12

mm1_rxdp

mm1_rxrcv

hsusb1_tll_st hw_dbg0

p

AE10

AF11

NA

AB3

AC3

NA

AD3

AD6

etk_ctl

etk_d0

mmc3_cmd hsusb1_clk gpio_13

hsusb1_tll_cl hw_dbg1

k

mcspi3_simo mmc3_dat4 hsusb1_data gpio_14

0

hsusb1_tll_d hw_dbg2

ata0

90

TERMINAL DESCRIPTION

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Table 2-4. Multiplexing Characteristics (continued)

CBB

CBC

CUS

MODE 0

MODE 1

MODE 2

MODE 3

MODE 4

MODE 5

MODE 6

MODE 7

Bottom

AG12

Top

Bottom

AD4

Top

NA

AC6

AC7

AD8

AC5

AD2

AC8

AD9

AC4

AD5

AC3

AC9

etk_d1

mcspi3_somi

mcspi3_cs0

mcspi3_clk

mcbsp5_dr

hsusb1_data gpio_15

1

mm1_txse0 hsusb1_tll_d hw_dbg3

ata1

AH12

AE13

AE11

AH9

AF13

AH14

AF9

AD3

AA3

Y3

NA

etk_d2

etk_d3

etk_d4

etk_d5

etk_d6

etk_d7

etk_d8

etk_d9

etk_d10

etk_d11

etk_d12

etk_d13

etk_d14

etk_d15

vdd_core

hsusb1_data gpio_16

2

mm1_txdat

hsusb1_tll_d hw_dbg4

ata2

mmc3_dat3 hsusb1_data gpio_17

7

hsusb1_tll_d hw_dbg5

ata7

mmc3_dat0 hsusb1_data gpio_18

4

hsusb1_tll_d hw_dbg6

ata4

AB1

AE3

AD2

AA4

V2

mcbsp5_fsx mmc3_dat1 hsusb1_data gpio_19

5

hsusb1_tll_d hw_dbg7

ata5

mcbsp5_dx mmc3_dat2 hsusb1_data gpio_20

6

hsusb1_tll_d hw_dbg8

ata6

mcspi3_cs1 mmc3_dat7 hsusb1_data gpio_21

3

mm1_txen_n hsusb1_tll_d hw_dbg9

ata3

sys_drm_ms mmc3_dat6 hsusb1_dir

ecure

gpio_22

hsusb1_tll_di hw_dbg10

r

AG9

AE7

sys_secure_i mmc3_dat5 hsusb1_nxt gpio_23

ndicator

mm1_rxdm hsusb1_tll_n hw_dbg11

xt

AE4

AF6

AE6

AF7

AF9

AE9

uart1_rx

hsusb2_clk gpio_24

hsusb2_tll_cl hw_dbg12

k

AF7

hsusb2_stp gpio_25

mm2_rxdp

hsusb2_tll_st hw_dbg13

p

AG7

AH7

AG8

AH8

AC10

AD11

AC11

AD12

hsusb2_dir

gpio_26

hsusb2_tll_di hw_dbg14

r

hsusb2_nxt gpio_27

mm2_rxdm hsusb2_tll_n hw_dbg15

xt

hsusb2_data gpio_28

0

mm2_rxrcv

hsusb2_tll_d hw_dbg16

ata0

hsusb2_data gpio_29

1

mm2_txse0 hsusb2_tll_d hw_dbg17

ata1

AC4, J4, H4, NA

D8, AE9, D9,

D15, Y16,

AE18, Y18,

W18, K18,

J18, AE19,

Y19, U19,

T19, N19,

AC21, D15, NA

G11, G18,

H20, M7,

M17, R20,

T7, Y8, Y12

F12, F13,

G12, G13,

H12, H13,

J17, J18,

K17, K18,

K19, L14,

L15, M14,

M15, R17,

R18, R19,

T17, T18,

T19, T20

M19, J19,

Y20, W20,

V20, U20,

P20, N20,

K20, J20,

D22, D23,

AE24, M25,

L25, E25

Y9, W9, T9, NA

R9, M9, L9,

J9, Y10,

D13, G9,

G12, H7,

NA

F10, G9,

G10, H9,

H10, J9, J10,

L11, L12,

M6, M7, M8,

M12, N6, N7,

N8, R6, R7,

R8, T7, T8,

U12, U13,

V12, V13,

vdd_mpu

K11, L9, M9,

M10, N7, N8,

P10, U7,

U11, U13,

V7, V11, W9,

Y9, Y11

U10, T10,

R10, N10,

M10, L10,

J10, Y11,

W11, K11,

J11, W12,

K13, Y14,

K14, J14,

Y15, W15,

J15

W12, W13

AA15

NA

K14

NA

Y12

cap_vdd_wk

up

K15

NA

K13

U12

NA

G18

vdds_dpll_dll

vdds_sram

vdds

W16

AA12

AD3, AD4,

W4, AF8,

AE8, AF16,

AE16, AF23,

AE23, F25,

F26, AG27

A18, AC7,

AC15, AC18,

AC24, AD20,

AE10, C11,

D9, E24, G4,

J15, J18, L7,

L24, M4, T4,

T24, W24,

Y4, L20,

M17, M18,

M19, N17,

N18, N19,

U10, V9,

V10, W9,

W10, Y9

AB24, AD18,

AD19

TERMINAL DESCRIPTION

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MODE 6 MODE 7

Table 2-4. Multiplexing Characteristics (continued)

CBB

CBC

CUS

MODE 0

MODE 1

MODE 2

MODE 3

MODE 4

MODE 5

Bottom

Top

Bottom

Top

U1, J1, F1,

J2, F2, R4,

NA

E16, F15,

F16, G15,

G16, H15,

J6, J7, J8,

K6, K7, K8

vdds_mem

B5, A5, AH6,

B8, A8, B12,

A12, D16,

C16, B18,

A18, B22,

A22, G28,

C28

AA16

NA

U14

W14

NA

U17

vdds_dpll_pe

r

AA14

AA13

vdds_wkup_

bg

AG2, U2, B2, NA

AG3, W3,

A6, A8, A13, NA

AB5, AB22,

AC10, AC16,

AC19, AD14,

AD25,AE7,

AF23, B2,

B25, C12,

D7, D10,

D12, D14,

D18, D20,

E22, G1, G8,

G10, G20,

G23, H4, K1,

K15, K25,

L10, L17,

H11, H14,

H16, J11,

J12, J13,

J14, J15,

J16, K10,

K11, K14,

K15, L8, L10,

L13, L17,

M9, M10,

M11, M13,

M16, N9,

N10, N11,

N12, N13,

N14, N15,

N16, P8,

P10, P11,

P12, P13,

P14, P15,

P17, R10,

R11, R14,

R15, T9,

vss

P3, J3, E3,

A3, P4, E4,

AG6, D7, C7,

V9, U9, P9,

N9, K9, W10,

V10, P10,

K10, D10,

C10, AF12,

AE12, Y12,

K12, J12,

Y13, W13,

J13, D13,

C13, W14,

K16, J16,

Y17, W17,

K17, J17,

W19, V19,

R19, P19,

L19, K19,

L19, L23, N4,

N10, N17,

R1, R4, R17,

T23, U25,

W1, W4,

W23, Y7,

D19, C19,

AF20, AE20,

T20, R2

Y10, Y16,

Y26

T10, T11,

T12, T13,

T14, T15,

T16, U9,

U11, U14,

U15, U16,

V15, V16,

W15

V25

NA

V25

V24

N23

P23

Y26

AB24

AD19

AE19

AC19

NA

AB13

AB15

N24

H8

vdda_dac

vssa_dac

vdds_mmc1

vdds_mmc1a

vss

Y26

K25

P25

AA26

AE27

AG21

AH20

AH21

AG16

AG20

M28

H28

NA

vdds

NA

vdds

NA

cap_vdd_d

vss

NA

vss

NA

vdds

L19

NA

vss

L20

NA

vdds

V4

N9

U8

cap_vdd_sra

m_mpu

L21

NA

K20

NA

H17

cap_vdd_sra

m_core

92

TERMINAL DESCRIPTION

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2.5 Signal Description

Many signals are available on multiple pins according to the software configuration of the pin multiplexing

options.

1. SIGNAL NAME: The signal name

2. DESCRIPTION: Description of the signal

3. TYPE: Type = Ball type for this specific function:

–

I = Input

O = Output

Z = High-impedance

D = Open Drain

DS = Differential

A = Analog

4. BALL BOTTOM: Associated ball(s) bottom

5. BALL TOP: Associated ball(s) top

6. SUBSYSTEM PIN MULTIPLEXING: Contains a list of the pin multiplexing options at the

module/subsystem level. The pin function is selected at the module/system level.

Note: The Subsystem Multiplexing Signals are not described in the following tables.

2.5.1 External Memory Interfaces

Table 2-5. External Memory Interfaces – GPMC Signals Description

SIGNAL NAME

[1]

DESCRIPTION [2]

TYPE

[3]

BALL

BOTTOM

(CBB

BALL

TOP

(CBB

BALL BOTTOM

(CBC Pkg.) [4]

BALL TOP

(CBC Pkg.) [5]

BALL

BOTTOM

(CUS

SUBSYSTEM

MULTIPLEXING

[6]

Pkg.) [4]

Pkg.) [5]

Pkg.) [4]

gpmc_a1

gpmc_a2

gpmc_a3

gpmc_a4

gpmc_a5

gpmc_a6

gpmc_a7

gpmc_a8

gpmc_a9

gpmc_a10

gpmc_a11

gpmc_a12

gpmc_a13

gpmc_a14

gpmc_a15

gpmc_a16

General-purpose memory address

bit 1

O

N4 / K1

M4 / L1

L4 / L2

K4 / P2

T3 / T1

R3 / V1

N3 / V2

M3 / W2

L3 / H2

K3 / K2

P1

AC15 / M2

AB15 / M1

AC16 / N2

AB16 / N1

AC17 / R2

AB17 / R1

AC18 / T2

AB18 / T1

J2 / AA2

H1 / AA1

H2 / AC2

G2 / AC1

F1 / AE5

F2 / AD6

E1 / AD5

E2 / AC5

D1 / V1

D2 / Y1

T1

NA / U2

NA / U1

NA / V2

NA / V1

NA / AA3

NA / AA4

NA / Y3

NA / Y4

NA / R1

T1

K4/ L2

K3/ M1

K2/ M2

J4/ N2

J3/ M3

J2/ P1

J1/ P2

H1/ R1

H2/ R2

G2/ T2

U1

/ gpmc_d0

General-purpose memory address

bit 2

gpmc_a18/

gpmc_d1

General-purpose memory address

bit 3

gpmc_a19/

gpmc_d2

General-purpose memory address

bit 4

gpmc_a20/

gpmc_d3

General-purpose memory address

bit 5

gpmc_a21/

gpmc_d4

General-purpose memory address

bit 6

gpmc_a22/

gpmc_d5

General-purpose memory address

bit 7

gpmc_a23/

gpmc_d6

General-purpose memory address

bit 8

gpmc_a24/

gpmc_d7

General-purpose memory address

bit 9

AC19 /

AB3

gpmc_a25/

gpmc_d8

General-purpose memory address

bit 10

AB19 /

AC3

gpmc_a26/

gpmc_d9

General-purpose memory address

bit 11

AB4

AC4

AB6

AC6

AB7

AC7

N1

gpmc_d10

gpmc_d11

gpmc_d12

gpmc_d13

gpmc_d14

gpmc_d15

General-purpose memory address

bit 12

R1

U2

P2

R3

General-purpose memory address

bit 13

R2

U1

P1

T3

General-purpose memory address

bit 14

T2

P1

M1

U2

General-purpose memory address

bit 15

W1

L2

J2

V1

General-purpose memory address

bit 16

Y1

M2

K2

V2

TERMINAL DESCRIPTION

93

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Table 2-5. External Memory Interfaces – GPMC Signals Description (continued)

SIGNAL NAME

[1]

DESCRIPTION [2]

TYPE

[3]

BALL

BOTTOM

(CBB

BALL

TOP

(CBB

BALL BOTTOM

(CBC Pkg.) [4]

BALL TOP

(CBC Pkg.) [5]

BALL

BOTTOM

(CUS

SUBSYSTEM

MULTIPLEXING

[6]

Pkg.) [4]

Pkg.) [5]

Pkg.) [4]

gpmc_a17

gpmc_a18

gpmc_a19

gpmc_a20

gpmc_a21

gpmc_a22

gpmc_a23

gpmc_a24

gpmc_a25

gpmc_a26

gpmc_d0

gpmc_d1

gpmc_d2

gpmc_d3

gpmc_d4

gpmc_d5

gpmc_d6

gpmc_d7

gpmc_d8

gpmc_d9

gpmc_d10

gpmc_d11

gpmc_d12

gpmc_d13

gpmc_d14

gpmc_d15

General-purpose memory address

bit 17

O

N4

M4

L4

AC15

AB15

AC16

AB16

AC17

AB17

AC18

AB18

AC19

AB19

M2

J2

H1

NA

U2

U1

V2

K4

K3

K2

J4

gpmc_a1

gpmc_a2

gpmc_a3

gpmc_a4

gpmc_a5

gpmc_a6

gpmc_a7

gpmc_a8

gpmc_a9

gpmc_a10

General-purpose memory address

bit 18

General-purpose memory address

bit 19

O

H2

General-purpose memory address

bit 20

O

K4

T3

R3

N3

M3

L3

G2

F1

General-purpose memory address

bit 21

O

J3

General-purpose memory address

bit 22

O

F2

J2

General-purpose memory address

bit 23

O

E1

J1

General-purpose memory address

bit 24

O

E2

H1

H2

G2

L2

General-purpose memory address

bit 25

O

D1

General-purpose memory address

bit 26

O

K3

K1

L1

D2

GPMC Data bit 0

GPMC Data bit 1

GPMC Data bit 2

GPMC Data bit 3

GPMC Data bit 4

GPMC Data bit 5

GPMC Data bit 6

GPMC Data bit 7

GPMC Data bit 8

GPMC Data bit 9

GPMC Data bit 10

GPMC Data bit 11

GPMC Data bit 12

GPMC Data bit 13

GPMC Data bit 14

GPMC Data bit 15

IO

AA2

AA1

AC2

AC1

AE5

AD6

AD5

AC5

V1

gpmc_a1/

gpmc_d0

M1

M2

N2

M3

P1

P2

R1

R2

T2

U1

R3

T3

U2

V1

V2

gpmc_a2/

gpmc_d1

L2

N2

gpmc_a3/

gpmc_d2

P2

T1

V1

V2

W2

H2

K2

P1

R1

R2

T2

W1

Y1

N1

V1

gpmc_a4/

gpmc_d3

R2

AA3

AA4

Y3

gpmc_a5/

gpmc_d4

R1

gpmc_a6/

gpmc_d5

T2

gpmc_a7

/gpmc_d6

T1

Y4

gpmc_a8/

gpmc_d7

AB3

AC3

AB4

AC4

AB6

AC6

AB7

AC7

R1

T1

gpmc_a9/

gpmc_d8

Y1

gpmc_a10/

gpmc_d9

T1

N1

P2

gpmc_a11/

gpmc_d10

U2

gpmc_a12/

gpmc_d11

U1

P1

gpmc_a13/

gpmc_d12

P1

M1

J2

gpmc_a14/

gpmc_d13

L2

gpmc_a15/

gpmc_d14

M2

K2

gpmc_a16/

gpmc_d15

gpmc_ncs0

gpmc_ncs1

gpmc_ncs2

gpmc_ncs3

gpmc_ncs4

gpmc_ncs5

GPMC Chip Select bit 0

GPMC Chip Select bit 1

GPMC Chip Select bit 2

GPMC Chip Select bit 3

GPMC Chip Select bit 4

GPMC Chip Select bit 5

O

G4

H3

V8

U8

T8

R8

Y2

Y1

AD8

AD1

A3

AA8

W1

NA

E2

NA

D2

F4

NA

B6

B4

C4

G5

94

TERMINAL DESCRIPTION

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Table 2-5. External Memory Interfaces – GPMC Signals Description (continued)

SIGNAL NAME

[1]

DESCRIPTION [2]

TYPE

[3]

BALL

BOTTOM

(CBB

BALL

TOP

(CBB

BALL BOTTOM

(CBC Pkg.) [4]

BALL TOP

(CBC Pkg.) [5]

BALL

BOTTOM

(CUS

SUBSYSTEM

MULTIPLEXING

[6]

Pkg.) [4]

Pkg.) [5]

Pkg.) [4]

gpmc_ncs6

gpmc_ncs7

gpmc_io_dir

GPMC Chip Select bit 6

GPMC Chip Select bit 7

O

P8

N8

NA

B5

C5

NA

F3

G4

NA

GPMC IO direction control for use

with external transceivers

gpmc_clk

GPMC clock

O

T4

F3

W2

W1

N1

L1

W2

F1

NA

gpmc_nadv_ale Address Valid or Address Latch

Enable

AD10

AA9

gpmc_noe

gpmc_nwe

Output Enable

Write Enable

O

G2

F4

G3

V2

V1

N2

M1

K2

L2

K1

FT⁽¹⁾

F2

G3

K5

NA

gpmc_nbe0_cle Lower Byte Enable. Also used for

Command Latch Enable

AC12

gpmc_nbe1

gpmc_nwp

gpmc_wait0

gpmc_wait1

gpmc_wait2

gpmc_wait3

Upper Byte Enable

O

I

U3

H1

M8

L8

NA

AB10

AB12

AC10

NA

J1

AC6

AC11

AC8

B3

NA

Y5

L1

E1

C1

NA

C2

NA

Flash Write Protect

External indication of wait

Y10

Y8

I

K8

J8

NA

I

NA

C6

(1) FT indicates "Feed-Through. For more information, refer to Section 2.5.10.

Table 2-6. External Memory Interfaces – SDRC Signals Description

SIGNAL

NAME

DESCRIPTION

TYPE⁽¹⁾

BALL

BOTTOM

(CBB Pkg.)

BALL TOP

(CBB Pkg.)

BALL BOTTOM

(CBC Pkg.)

BALL TOP

(CBC Pkg.)

BALL BOTTOM

(CUS Pkg.)

sdrc_d0

SDRAM data bit 0

SDRAM data bit 1

SDRAM data bit 2

SDRAM data bit 3

SDRAM data bit 4

SDRAM data bit 5

SDRAM data bit 6

SDRAM data bit 7

SDRAM data bit 8

SDRAM data bit 9

SDRAM data bit 10

SDRAM data bit 11

SDRAM data bit 12

SDRAM data bit 13

SDRAM data bit 14

SDRAM data bit 15

SDRAM data bit 16

SDRAM data bit 17

SDRAM data bit 18

SDRAM data bit 19

SDRAM data bit 20

SDRAM data bit 21

SDRAM data bit 22

SDRAM data bit 23

SDRAM data bit 24

SDRAM data bit 25

SDRAM data bit 26

IO

D6

C6

J2

J1

NA

D1

G1

D7

C5

sdrc_d1

sdrc_d2

B6

G2

G1

F2

G2

C6

sdrc_d3

C8

E1

B5

sdrc_d4

C9

D2

D9

sdrc_d5

A7

F1

E2

D10

C7

sdrc_d6

B9

D2

B3

sdrc_d7

A9

D1

B4

B7

sdrc_d8

C14

B14

C15

B16

D17

C17

B17

D18

D11

B10

C11

D12

C12

A11

B13

D14

C18

A19

B19

B13

A13

B14

A14

B16

A16

B19

A19

B3

A10

B11

A11

B12

A16

A17

B17

B18

B7

B11

C12

B12

D13

C13

B14

A14

B15

C9

sdrc_d9

sdrc_d10

sdrc_d11

sdrc_d12

sdrc_d13

sdrc_d14

sdrc_d15

sdrc_d16

sdrc_d17

sdrc_d18

sdrc_d19

sdrc_d20

sdrc_d21

sdrc_d22

sdrc_d23

sdrc_d24

sdrc_d25

sdrc_d26

A3

A5

E12

B8

B5

B6

A5

A6

B9

B8

A8

C10

B10

D12

E13

E15

D15

C15

A8

B9

A9

B10

C21

D20

B19

B21

A21

D22

(1) Type = Ball type for this specific function (I = Input, O = Output, Z = high-impedance, D = Open Drain, DS = Differential, A = Analog).

TERMINAL DESCRIPTION

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Table 2-6. External Memory Interfaces – SDRC Signals Description (continued)

SIGNAL

NAME

DESCRIPTION

TYPE⁽¹⁾

BALL

BOTTOM

(CBB Pkg.)

BALL TOP

(CBB Pkg.)

BALL BOTTOM

(CBC Pkg.)

BALL TOP

(CBC Pkg.)

BALL BOTTOM

(CUS Pkg.)

sdrc_d27

SDRAM data bit 27

SDRAM data bit 28

SDRAM data bit 29

SDRAM data bit 30

SDRAM data bit 31

SDRAM bank select 0

SDRAM bank select 1

SDRAM address bit 0

SDRAM address bit 1

SDRAM address bit 2

SDRAM address bit 3

SDRAM address bit 4

SDRAM address bit 5

SDRAM address bit 6

SDRAM address bit 7

SDRAM address bit 8

SDRAM address bit 9

SDRAM address bit 10

SDRAM address bit 11

SDRAM address bit 12

SDRAM address bit 13

SDRAM address bit 14

Chip select 0

IO

O

IO

O

B20

D20

A21

B21

C21

H9

D23

E22

E23

G22

G23

AB21

AC21

N22

N23

P22

P23

R22

R23

T22

T23

U22

U23

V22

V23

W22

W23

Y22

M22

M23

A11

B11

J22

NA

C20

D21

E20

E21

G21

AA18

V20

G20

K20

J20

B16

C16

D16

B17

B18

C18

D18

A4

sdrc_d28

sdrc_d29

sdrc_d30

sdrc_d31

sdrc_ba0

sdrc_ba1

sdrc_a0

H10

A4

sdrc_a1

B4

sdrc_a2

B3

D6

sdrc_a3

C5

J21

B3

sdrc_a4

C4

U21

R20

M21

M20

N20

K21

Y16

N21

R21

AA15

Y12

T21

T20

A12

B13

Y15

Y13

V21

U20

B2

sdrc_a5

D5

C3

sdrc_a6

C3

E3

sdrc_a7

C2

F6

sdrc_a8

C1

E10

E9

sdrc_a9

D4

sdrc_a10

sdrc_a11

sdrc_a12

sdrc_a13

sdrc_a14

sdrc_ncs0

sdrc_ncs1

sdrc_clk

sdrc_nclk

sdrc_cke0

sdrc_cke1

sdrc_nras

sdrc_ncas

D3

E7

D2

G6

D1

G7

E2

F7

E1

F9

H11

H12

A13

A14

H16

H17

H14

H13

A19

B19

A10

A11

B20

C20

D19

C19

Chip select 1

Clock

Clock Invert

Clock Enable 0

Clock Enable 1

J23

SDRAM Row Access

L23

SDRAM column

address strobe

L22

sdrc_nwe

sdrc_dm0

sdrc_dm1

sdrc_dm2

sdrc_dm3

sdrc_dqs0

sdrc_dqs1

sdrc_dqs2

sdrc_dqs3

SDRAM write enable

Data Mask 0

O

H15

B7

K23

C1

NA

Y18

H1

A20

B6

Data Mask 1

O

A16

B11

C20

A6

A17

A6

A14

A4

B13

A7

Data Mask 2

O

Data Mask 3

O

A20

C2

A18

C2

A16

A5

Data Strobe 0

Data Strobe 1

Data Strobe 2

Data Strobe 3

IO

A17

A10

A20

B17

B6

B15

B8

A13

A8

B20

A19

A17

96

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2.5.2 Video Interfaces

Table 2-7. Video Interfaces – CAM Signals Description

SIGNAL NAME

DESCRIPTION

TYPE⁽¹⁾

BALL BOTTOM

(CBB Pkg.)

BALL BOTTOM

(CBC Pkg.)

BALL BOTTOM

(CUS Pkg.)

cam_hs

Camera Horizontal Synchronization

Camera Vertical Synchronization

Camera Clock Output a

IO

O

I

A24

A23

C23

D23

A22

E18

cam_vs

cam_xclka

cam_xclkb

cam_d0

cam_d1

cam_d2

cam_d3

cam_d4

cam_d5

cam_d6

cam_d7

cam_d8

cam_d9

cam_d10

cam_d11

cam_fld

C25

B22

Camera Clock Output b

B26

E25

C22

Camera digital image data bit 0

Camera digital image data bit 1

Camera digital image data bit 2

Camera digital image data bit 3

Camera digital image data bit 4

Camera digital image data bit 5

Camera digital image data bit 6

Camera digital image data bit 7

Camera digital image data bit 8

Camera digital image data bit 9

Camera digital image data bit 10

Camera digital image data bit 11

Camera field identification

AG17

AH17

B24

AE16

AE15

A24

AB18

AC18

G19

I

C24

B24

F19

I

D24

G20

I

A25

C24

B21

I

K28

P25

L24

I

L28

P26

K24

I

K27

N25

J23

I

L27

N26

K23

I

B25

D25

F21

I

C26

E26

G21

IO

I

C23

B23

H24

cam_pclk

cam_wen

cam_strobe

Camera pixel clock

C27

C26

J19

Camera Write Enable

I

B23

A23

F18

Flash strobe control signal

O

IO

D25

D26

J20

cam_global_reset Global reset is used strobe

synchronization

C23 / AH3 / AA21

B23/M3/V17

H24/ AA2/ AB20

cam_shutter

Mechanical shutter control signal

O

B23 / AF3 / T21

A23 / T19

F18/ Y2/ AA18

(1) Type = Ball type for this specific function (I = Input, O = Output, Z = high-impedance, D = Open Drain, DS = Differential, A = Analog).

Table 2-8. Video Interfaces – DSS Signals Description

SIGNAL NAME

DESCRIPTION

TYPE⁽¹⁾

BALL BOTTOM

(CBB Pkg.)

BALL BOTTOM

(CBC Pkg.)

BALL BOTTOM

(CUS Pkg.)

dss_pclk

LCD Pixel Clock

O

D28

D26

G25

K24

G22

E22

dss_hsync

dss_vsync

dss_acbias

dss_data0

dss_data1

dss_data2

dss_data3

dss_data4

dss_data5

dss_data6

dss_data7

dss_data8

dss_data9

dss_data10

dss_data11

dss_data12

dss_data13

dss_data14

LCD Horizontal Synchronization

LCD Vertical Synchronization

AC bias control (STN) or pixel data enable (TFT) output

LCD Pixel Data bit 0

O

D27

M25

F22

O

E27

F26

J21

IO

AG22 / H26

AH22 / H25

AG23 / E28

AH23 / J26

AG24 / AC27

AH24 / AC28

E26

AE21 / M24

AE22 / M26

AE23 / F25

AE24 / N24

AD23 / AC25

AD24/ AB25

G26

AC19/G24

AB19/H23

AD20/D23

AC20/K22

AD21/V21

AC21/W21

D24

LCD Pixel Data bit 1

LCD Pixel Data bit 2

LCD Pixel Data bit 3

LCD Pixel Data bit 4

LCD Pixel Data bit 5

LCD Pixel Data bit 6

LCD Pixel Data bit 7

F28

H25

E23

LCD Pixel Data bit 8

F27

H26

E24

LCD Pixel Data bit 9

G26

J26

F23

LCD Pixel Data bit 10

AD28

AC26

AC22

LCD Pixel Data bit 11

AD27

AD26

AC23

LCD Pixel Data bit 12

AB28

AA25

AB22

LCD Pixel Data bit 13

AB27

Y25

Y22

LCD Pixel Data bit 14

AA28

AA26

W22

(1) Type = Ball type for this specific function (I = Input, O = Output, Z = high-impedance, D = Open Drain, DS = Differential, A = Analog).

TERMINAL DESCRIPTION

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Table 2-8. Video Interfaces – DSS Signals Description (continued)

SIGNAL NAME

DESCRIPTION

TYPE⁽¹⁾

BALL BOTTOM

(CBB Pkg.)

BALL BOTTOM

(CBC Pkg.)

BALL BOTTOM

(CUS Pkg.)

dss_data15

dss_data16

dss_data17

dss_data18

dss_data19

dss_data20

dss_data21

dss_data22

dss_data23

LCD Pixel Data bit 15

IO

O

AA27

G25

H27

AB26

L25

V22

J22

LCD Pixel Data bit 16

LCD Pixel Data bit 17

LCD Pixel Data bit 18

LCD Pixel Data bit 19

LCD Pixel Data bit 20

LCD Pixel Data bit 21

LCD Pixel Data bit 22

LCD Pixel Data bit 23

L26

G23

G24

H23

D23

K22

V21

W21

H26

M24

M26

F25

H25

E28

O

J26

N24

O

AC27

AC28

AC25

AB25

O

Table 2-9. Video Interfaces – RFBI Signals Description

SIGNAL

NAME

DESCRIPTION

TYPE⁽¹⁾

BALL BOTTOM

(CBB Pkg.)

BALL BOTTOM

(CBC Pkg.)

BALL BOTTOM

(CUS Pkg.)

SUBSYSTEM PIN

MULTIPLEXING⁽²⁾

rfbi_a0

RFBI command/data control

1st LCD chip select

RFBI data bus 0

O

E27

D26

F26

K24

J21

E22

dss_acbias

dss_hsync

dss_data0

dss_data1

dss_data2

dss_data3

dss_data4

dss_data5

dss_data6

dss_data7

dss_data8

dss_data9

dss_data10

dss_data11

dss_data12

dss_data13

dss_data14

dss_data15

dss_pclk

rfbi_cs0

rfbi_da0

rfbi_da1

rfbi_da2

rfbi_da3

rfbi_da4

rfbi_da5

rfbi_da6

rfbi_da7

rfbi_da8

rfbi_da9

rfbi_da10

rfbi_da11

rfbi_da12

rfbi_da13

rfbi_da14

rfbi_da15

rfbi_rd

IO

O

AG22

AH22

AG23

AH23

AG24

AH24

E26

AE21

AE22

AE23

AE24

AD23

AD24

G26

AC19

AB19

AD20

AC20

AD21

AC21

D24

RFBI data bus 1

RFBI data bus 2

RFBI data bus 3

RFBI data bus 4

RFBI data bus 5

RFBI data bus 6

RFBI data bus 7

F28

H25

E23

RFBI data bus 8

F27

H26

E24

RFBI data bus 9

G26

J26

F23

RFBI data bus 10

RFBI data bus 11

RFBI data bus 12

RFBI data bus 13

RFBI data bus 14

RFBI data bus 15

Read enable for RFBI

Write Enable for RFBI

AD28

AD27

AB28

AB27

AA28

AA27

D28

AC26

AD26

AA25

Y25

AC22

AC23

AB22

Y22

AA26

AB26

G25

W22

V22

G22

rfbi_wr

O

D27

M25

F22

dss_vsync

dss_data16

rfbi_te_vsync tearing effect removal and Vsync input

I

G25

L25

J22

0

from 1st LCD

rfbi_hsync0

Hsync for 1st LCD

I

H27

H26

L26

G23

G24

dss_data17

dss_data18

rfbi_te_vsync tearing effect removal and Vsync input

M24

1

from 2nd LCD

rfbi_hsync1

rfbi_cs1

Hsync for 2nd LCD

2nd LCD chip select

I

H25

E28

M26

F25

H23

D23

dss_data19

dss_data20

O

(1) Type = Ball type for this specific function (I = Input, O = Output, Z = high-impedance, D = Open Drain, DS = Differential, A = Analog).

(2) The subsystem pin multiplexing options are not described in and

98

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Table 2-10. Video Interfaces – TV Signals Description

SIGNAL NAME

DESCRIPTION

TYPE⁽¹⁾

BALL BOTTOM

(CBB Pkg.)

BALL BOTTOM

(CBC Pkg.)

BALL BOTTOM

(CUS Pkg.)

tv_out1

tv_out2

tv_vfb1

TV analog output Composite: tv_out1

TV analog output S-VIDEO: tv_out2

O

Y28

W28

Y27

W26

V26

AB24

AA23

AB23

tv_vfb1: Feedback through external

resistor to composite

AO

W25

tv_vfb2

tv_vref

tv_vfb2: Feedback through external

resistor to S-VIDEO

AO

W27

W26

U24

V23

Y23

Y24

External capacitor

(1) Type = Ball type for this specific function (I = Input, O = Output, Z = high-impedance, D = Open Drain, DS = Differential, A = Analog).

TERMINAL DESCRIPTION

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2.5.3 Serial Communication Interfaces

Table 2-11. Serial Communication Interfaces – HDQ/1-Wire Signals Description

SIGNAL

NAME

DESCRIPTION

TYPE⁽¹⁾

BALL BOTTOM

(CBB Pkg.)

BALL BOTTOM

(CBC Pkg.)

BALL BOTTOM

(CUS Pkg.)

hdq_sio

Bidirectional HDQ 1-Wire control and data

Interface. Output is open drain.

IOD

J25

J23

A24

(1) Type = Ball type for this specific function (I = Input, O = Output, Z = high-impedance, D = Open Drain, DS = Differential, A = Analog).

Table 2-12. Serial Communication Interfaces – I²C Signals Description

SIGNAL NAME

DESCRIPTION

TYPE⁽¹⁾

BALL BOTTOM

(CBB Pkg.)

BALL BOTTOM

(CBC Pkg.)

BALL BOTTOM

(CUS Pkg.)

INTER-INTEGRATED CIRCUIT INTERFACE (I2C1)

I²C Master Serial clock. Output is open

i2c1_scl

IOD

K21

J21

J25

J24

K20

K21

drain.

I²C Serial Bidirectional Data. Output is

i2c1_sda

open drain.

INTER-INTEGRATED CIRCUIT INTERFACE (I2C3)

I²C Master Serial clock. Output is open

i2c3_scl

IOD

O

AF14

AG14

J25

AB4

AC4

J23

AC13

AC12

A24

drain.

I²C Serial Bidirectional Data. Output is

i2c3_sda

open drain.

i2c3_sccbe

Serial Camera Control Bus Enable

INTER-INTEGRATED CIRCUIT INTERFACE (I2C2)

I²C Master Serial clock. Output is open

i2c2_scl

IOD

O

AF15

AE15

J25

C2

C1

AC15

AC14

A24

drain.

I²C Serial Bidirectional Data. Output is

i2c2_sda

open drain.

i2c2_sccbe

Serial Camera Control Bus Enable

J23

(1) Type = Ball type for this specific function (I = Input, O = Output, Z = high-impedance, D = Open Drain, DS = Differential, A = Analog).

Table 2-13. Serial Communication Interfaces – SmartReflex Signals Description⁽¹⁾

SIGNAL NAME

DESCRIPTION

TYPE⁽²⁾

BALL BOTTOM

(CBB Pkg.)

BALL BOTTOM

(CBC Pkg.)

BALL BOTTOM

(CUS Pkg.)

INTER-INTEGRATED CIRCUIT INTERFACE (I2C4)

I²C Master Serial clock. Output is open

i2c4_scl

IOD

AD26

AE26

AD15

W16

Y16

Y15

drain.

I²C Serial Bidirectional Data. Output is

i2c4_sda

open drain.

(1) For more information on SmartReflex voltage control, see the PRCM chapter of the OMAP35x Technical Reference Manual (TRM)

[literature number SPRUFA5].

(2) Type = Ball type for this specific function (I = Input, O = Output, Z = high-impedance, D = Open Drain, DS = Differential, A = Analog).

Table 2-14. Serial Communication Interfaces – McBSP LP Signals Description

SIGNAL NAME

DESCRIPTION

TYPE⁽¹⁾

BALL BOTTOM

(CBB Pkg.)

BALL BOTTOM

(CBC Pkg.)

BALL BOTTOM

(CUS Pkg.)

MULTICHANNEL SERIAL (McBSP LP 1)

mcbsp1_dr

mcbsp1_clkr

mcbsp1_fsr

mcbsp1_dx

mcbsp1_clkx

mcbsp1_fsx

mcbsp_clks

Received serial data

Receive Clock

I

U21

Y8 / Y21

AA21

V21

T20

U19 / H3

V17

Y18

V7 / W19

AB20

W18

IO

I

Receive frame synchronization

Transmitted serial data

Transmit clock

U17

W21

T17

V18

Transmit frame synchronization

K26

P20

AA19

AA18

External clock input (shared by McBSP1, 2,

3, 4, and 5)

T21

T19

MULTICHANNEL SERIAL (McBSP LP 2)

(1) Type = Ball type for this specific function (I = Input, O = Output, Z = high-impedance, D = Open Drain, DS = Differential, A = Analog)

100 TERMINAL DESCRIPTION

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Table 2-14. Serial Communication Interfaces – McBSP LP Signals Description (continued)

SIGNAL NAME

DESCRIPTION

TYPE⁽¹⁾

BALL BOTTOM

(CBB Pkg.)

BALL BOTTOM

(CBC Pkg.)

BALL BOTTOM

(CUS Pkg.)

mcbsp2_dr

mcbsp2_dx

mcbsp2_clkx

mcbsp2_fsx

Received serial data

I

R21

M21

N21

P21

T18

R19

R18

U18

V19

R20

T21

V20

Transmitted serial data

IO

Combined serial clock

Combined frame synchronization

MULTICHANNEL SERIAL (McBSP LP 3)

mcbsp3_dr

mcbsp3_dx

mcbsp3_clkx

mcbsp3_fsx

Received serial data

I

AE6 / AB25 / U21

AF6 / AB26 / V21

AF5 / AA25 / W21

AE5 / AD25 / K26

T20 / AA24 / N3

U17 / Y24 / P3

T17 / AD22 / U3

P20 / AD21 / W3

V5 / Y18

V6 / W18

W4 / V18

V4 / AA19

Transmitted serial data

Combined serial clock

IO

Combined frame synchronization

MULTICHANNEL SERIAL (McBSP LP 4)

mcbsp4_dr

mcbsp4_dx

mcbsp4_clkx

mcbsp4_fsx

Received serial data

I

R8 / AD1

P8 / AD2

T8 / AE1

N8 / AC1

C4 / U4

B5 / R3

B4 / V3

C5 / T3

G5

F3

F4

G4

Transmitted serial data

Combined serial clock

IO

Combined frame synchronization

MULTICHANNEL SERIAL (McBSP LP 5)

mcbsp5_dr

mcbsp5_dx

mcbsp5_clkx

mcbsp5_fsx

Received serial data

I

AE11

AF13

AF10

AH9

Y3

AC5

AC8

AC1

AD2

Transmitted serial data

Combined serial clock

IO

AE3

AB2

AB1

Combined frame synchronization

Table 2-15. Serial Communication Interfaces – McSPI Signals Description

SIGNAL NAME

DESCRIPTION

TYPE⁽¹⁾

BALL BOTTOM

(CBB Pkg.)

BALL BOTTOM

(CBC Pkg.)

BALL BOTTOM

(CUS Pkg.)

MULTICHANNEL SERIAL PORT INTERFACE (McSPI1)

mcspi1_clk

SPI Clock

IO

AB3

AB4

AA4

AC2

P9

P8

P7

R7

T5

R4

T4

T6

mcspi1_simo

mcspi1_somi

mcspi1_cs0

Slave data in, master data out

Slave data out, master data in

SPI Enable 0, polarity configured by

software

mcspi1_cs1

mcspi1_cs2

mcspi1_cs3

SPI Enable 1, polarity configured by

software

O

AC3

AB1

AB2

R8

R9

T8

NA

R5

SPI Enable 2, polarity configured by

software

SPI Enable 3, polarity configured by

software

MULTICHANNEL SERIAL PORT INTERFACE (McSPI2)

mcspi2_clk

SPI Clock

IO

AA3

Y2

W7

W8

U8

V8

N5

N4

N3

M5

mcspi2_simo

mcspi2_somi

mcspi2_cs0

Slave data in, master data out

Slave data out, master data in

Y3

SPI Enable 0, polarity configured by

software

Y4

mcspi2_cs1

SPI Enable 1, polarity configured by

software

O

V3

V9

M4

MULTICHANNEL SERIAL PORT INTERFACE (McSPI3)

mcspi3_clk

SPI Clock

IO

H26 / AE2 / AE13

H25 / AG5 / AF11

E28 / AH5 / AG12

J26 / AF4 / AH12

W10 / M24 / AA3

R10 / M26 / AC3

F25 / T10 / AD4

U9 / N24 / AD3

G24 / Y1 / AD8

H23 / AB5 / AD6

D23 / AB3 / AC6

K22 / V3 / AC7

mcspi3_simo

mcspi3_somi

mcspi3_cs0

Slave data in, master data out

Slave data out, master data in

SPI Enable 0, polarity configured by

software

mcspi3_cs1

SPI Enable 1, polarity configured by

software

O

AC27 / AG4 / AH14

AC25 / U10 / AD2

V21 / W3 / AD9

MULTICHANNEL SERIAL PORT INTERFACE (McSPI4)

(1) Type = Ball type for this specific function (I = Input, O = Output, Z = high-impedance, D = Open Drain, DS = Differential, A = Analog)

TERMINAL DESCRIPTION

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Table 2-15. Serial Communication Interfaces – McSPI Signals Description (continued)

SIGNAL NAME

DESCRIPTION

TYPE⁽¹⁾

BALL BOTTOM

(CBB Pkg.)

BALL BOTTOM

(CBC Pkg.)

BALL BOTTOM

(CUS Pkg.)

V7 / W19

W18

mcspi4_clk

SPI Clock

IO

Y8 / Y21

V21

U19 / H3

U17

mcspi4_simo

mcspi4_somi

mcspi4_cs0

Slave data in, master data out

Slave data out, master data in

U21

T20

Y18

SPI Enable 0, polarity configured by

software

K26

P20

AA19

Table 2-16. Serial Communication Interfaces – UARTs Signals Description

SIGNAL NAME

DESCRIPTION

TYPE⁽¹⁾

BALL BOTTOM

(CBB Pkg.)

BALL BOTTOM

(CBC Pkg.)

BALL BOTTOM

(CUS Pkg.)

UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER (UART1)

uart1_cts

uart1_rts

uart1_rx

uart1_tx

UART1 Clear To Send

UART1 Request To Send

UART1 Receive data

UART1 Transmit data

I

AG22 / W8 / T21

AH22 / AA9

AE21 / T19 / W2

AE22 / R2

AC19 / AC2 / AA18

W6 / AB19

O

I

F28 / Y8 / AE7

E26 / AA8

H3 / H25 / AE4

L4 / G26

E23 / V7 / AC3

D24 / W7

O

UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER (UART2)

uart2_cts

uart2_rts

uart2_rx

uart2_tx

UART2 Clear To Send

UART2 Request To Send

UART2 Receive data

UART2 Transmit data

I

AF6 / AB26

AE6 / AB25

AE5 / AD25

AF5 / AA25

N23/Y24

P3/AA24

W3/AD21

V3/AD22

V6

V5

V4

W4

O

I

O

UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER (UART3) / IrDA

uart3_cts_rctx

UART3 Clear To Send (input),

Remote TX (output)

IO

H18 / U26

W20 / F23

A23 / U23

uart3_rts_sd

uart3_rx_irrx

UART3 Request To Send, IR enable

O

I

H19 / U27

V18 / F24

B23 / U24

UART3 Receive data, IR and

Remote RX

AG24 / H20 / U28

AD23 / Y20 / H24

AD21 / B24 / T23

uart3_tx_irtx

UART3 Transmit data, IR TX

O

AH24 / H21 / T27

AD24 / V20 / G24

AC21 / C23 / T24

(1) Type = Ball type for this specific function (I = Input, O = Output, Z = high-impedance, D = Open Drain, DS = Differential, A = Analog)

Table 2-17. Serial Communication Interfaces – USB Signals Description

SIGNAL NAME

DESCRIPTION

TYPE⁽¹

BALL BOTTOM

(CBB Pkg.)

BALL BOTTOM

(CBC Pkg.)

BALL BOTTOM

(CUS Pkg.)

)

HIGH-SPEED UNIVERSAL SERIAL BUS INTERFACE (HSUSB0)

hsusb0_clk

hsusb0_stp

hsusb0_dir

Dedicated for external transceiver 60-MHz clock input to PHY

O

I

T28

T25

R28

W19

U20

V19

R21

R23

P23

Dedicated for external transceiver Stop signal

Dedicated for external transceiver Data direction control from

PHY

hsusb0_nxt

Dedicated for external transceiver Next signal from PHY

Dedicated for external transceiver Bidirectional data bus

I

T26

T27

U28

U27

U26

U25

W18

V20

Y20

V18

W20

W17

R22

T24

T23

U24

U23

W24

hsusb0_data0

hsusb0_data1

hsusb0_data2

hsusb0_data3

hsusb0_data4

IO

Dedicated for external transceiver Bidirectional data bus

additional signals for 12-pin ULPI operation

hsusb0_data5

hsusb0_data6

hsusb0_data7

Dedicated for external transceiver Bidirectional data bus

additional signals for 12-pin ULPI operation

IO

V28

V27

V26

Y18

Y19

Y17

V23

W23

T22

Dedicated for external transceiver Bidirectional data bus

additional signals for 12-pin ULPI operation

Dedicated for external transceiver Bidirectional data bus

additional signals for 12-pin ULPI operation

MM_FSUSB3

mm3_rxdm

Vminus receive data (not used in 3- or 4-pin configurations)

IO

AE3

K3

NA⁽²⁾

(1) Type = Ball type for this specific function (I = Input, O = Output, Z = high-impedance, D = Open Drain, DS = Differential, A = Analog)

(2) This pin is not available on the CUS package. For a list of pins not supported on a particular package, see Table 1-1.

102

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Table 2-17. Serial Communication Interfaces – USB Signals Description (continued)

SIGNAL NAME

DESCRIPTION

TYPE⁽¹

BALL BOTTOM

(CBB Pkg.)

BALL BOTTOM

(CBC Pkg.)

BALL BOTTOM

(CUS Pkg.)

)

mm3_rxdp

Vplus receive data (not used in 3- or 4-pin configurations)

Differential receiver signal input (not used in 3-pin mode)

Single-ended zero. Used as VM in 4-pin VP_VM mode.

USB data. Used as VP in 4-pin VP_VM mode.

Transmit enable

IO

AH3

AD1

AE1

AD2

AC1

M3

U4

V3

R3

T3

NA⁽²⁾

mm3_rxrcv

mm3_txse0

mm3_txdat

mm3_txen_n

MM_FSUSB2

mm2_rxdm

mm2_rxdp

NA

Vminus receive data (not used in 3- or 4-pin configurations)

Vplus receive data (not used in 3- or 4-pin configurations)

Differential receiver signal input (not used in 3-pin mode)

Single-ended zero. Used as VM in 4-pin VP_VM mode.

USB data. Used as VP in 4-pin VP_VM mode.

Transmit enable

IO

AH7

AF7

AG8

AH8

AB2

V3

AF7

AF6

AF9

AE9

T8

AD11

AC9

AC11

AD12

R5

mm2_rxrcv

mm2_txse0

mm2_txdat

mm2_txen_n

MM_FSUSB1

mm1_rxdm

mm1_rxdp

V9

M4

Vminus receive data (not used in 3- or 4-pin configurations)

Vplus receive data (not used in 3- or 4-pin configurations)

Differential receiver signal input (not used in 3-pin mode)

Single-ended zero. Used as VM in 4-pin VP_VM mode.

USB data. Used as VP in 4-pin VP_VM mode.

Transmit enable

IO

AG9

AF10

AF11

AG12

AH12

AH14

V2

AD5

AC1

AD6

AC6

AC7

AD9

AB2

AC3

AD4

AD3

AD2

mm1_rxrcv

mm1_txse0

mm1_txdat

mm1_txen_n

HSUSB3_TLL

hsusb3_tll_clk

hsusb3_tll_stp

hsusb3_tll_dir

Dedicated for external transceiver 60-MHz clock input to PHY

Dedicated for external transceiver Stop signal

O

I

W8

AH3

AF3

W2

M3

L3

NA

dedicated for external transceiver Data direction control from

PHY

O

hsusb3_tll_nxt

hsusb3_tll_data0

hsusb3_tll_data1

hsusb3_tll_data2

hsusb3_tll_data3

hsusb3_tll_data4

hsusb3_tll_data5

hsusb3_tll_data6

hsusb3_tll_data7

HSUSB2

Dedicated for external transceiver Next signal from PHY

Dedicated for external transceiver Bidirectional data bus

O

AE3

AD1

AE1

AD2

AC1

AF6

AE6

AF5

AE5

K3

U4

V3

R3

T3

P3

N3

V3

W3

NA

IO

hsusb2_clk

Dedicated for external transceiver 60-MHz clock input to PHY

Dedicated for external transceiver Stop signal

O

I

AE7

AF7

AG7

AE4

AF6

AE6

AC3

AC9

hsusb2_stp

hsusb2_dir

Dedicated for external transceiver Data direction control from

PHY

AC10

hsusb2_nxt

Dedicated for external transceiver Next signal from PHY

Dedicated for external transceiver Bidirectional data bus

I

AH7

AG8

AH8

AB2

V3

AF7

AF9

AE9

T8

AD11

AC11

AD12

R5

hsusb2_data0

hsusb2_data1

hsusb2_data2

hsusb2_data3

hsusb2_data4

IO

V9

M4

Dedicated for external transceiver Bidirectional data bus

additional signals for 12-pin ULPI operation

Y2

W8

N4

hsusb2_data5

hsusb2_data6

hsusb2_data7

Dedicated for external transceiver Bidirectional data bus

additional signals for 12-pin ULPI operation

IO

Y3

Y4

U8

V8

N3

M5

N5

Dedicated for external transceiver Bidirectional data bus

additional signals for 12-pin ULPI operation

Dedicated for external transceiver Bidirectional data bus

additional signals for 12-pin ULPI operation

AA3

W7

HSUSB2_TLL

hsusb2_tll_clk

Dedicated for external transceiver 60-MHz clock input to PHY

O

AE7

AE4

AC3

TERMINAL DESCRIPTION

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Table 2-17. Serial Communication Interfaces – USB Signals Description (continued)

SIGNAL NAME

DESCRIPTION

TYPE⁽¹

BALL BOTTOM

(CBB Pkg.)

BALL BOTTOM

(CBC Pkg.)

BALL BOTTOM

(CUS Pkg.)

)

hsusb2_tll_stp

hsusb2_tll_dir

Dedicated for external transceiver Stop signal

I

AF7

AG7

AF6

AE6

AC9

Dedicated for external transceiver data direction control from

PHY

O

AC10

hsusb2_tll_nxt

Dedicated for external transceiver Next signal from PHY

Dedicated for external transceiver Bidirectional data bus

O

AH7

AG8

AH8

AB2

V3

AF7

AF9

AE9

T8

AD11

AC11

AD12

R5

hsusb2_tll_data0

hsusb2_tll_data1

hsusb2_tll_data2

hsusb2_tll_data3

hsusb2_tll_data4

IO

V9

M4

Dedicated for external transceiver Bidirectional data bus

additional signals for 12-pin ULPI operation

Y2

W8

N4

hsusb2_tll_data5

hsusb2_tll_data6

hsusb2_tll_data7

Dedicated for external transceiver Bidirectional data bus

additional signals for 12-pin ULPI operation

IO

Y3

Y4

U8

V8

N3

M5

N5

Dedicated for external transceiver Bidirectional data bus

additional signals for 12-pin ULPI operation

Dedicated for external transceiver Bidirectional data bus

additional signals for 12-pin ULPI operation

AA3

W7

HSUSB1

hsusb1_clk

hsusb1_stp

hsusb1_dir

Dedicated for external transceiver 60-MHz clock input to PHY

Dedicated for external transceiver Stop signal

O

I

AE10

AF10

AF9

AB3

AB2

AA4

AD3

AC1

AC4

Dedicated for external transceiver data direction control from

PHY

hsusb1_nxt

Dedicated for external transceiver Next signal from PHY

Dedicated for external transceiver Bidirectional data bus

I

AG9

AF11

AG12

AH12

AH14

AE11

V2

AD5

AD6

AC6

AC7

AD9

AC5

hsusb1_data0

hsusb1_data1

hsusb1_data2

hsusb1_data3

hsusb1_data4

IO

AC3

AD4

AD3

AD2

Y3

Dedicated for external transceiver Bidirectional data bus

additional signals for 12-pin ULPI operation

hsusb1_data5

hsusb1_data6

hsusb1_data7

Dedicated for external transceiver Bidirectional data bus

additional signals for 12-pin ULPI operation

IO

AH9

AF13

AE13

AB1

AE3

AA3

AD2

AC8

AD8

Dedicated for external transceiver Bidirectional data bus

additional signals for 12-pin ULPI operation

Dedicated for external transceiver Bidirectional data bus

additional signals for 12-pin ULPI operation

HSUSB1_TLL

hsusb1_tll_clk

hsusb1_tll_stp

hsusb1_tll_dir

Dedicated for external transceiver 60-MHz clock input to PHY

Dedicated for external transceiver Stop signal

O

I

AE10

AF10

AF9

AB3

AB2

AA4

AD3

AC1

AC4

Dedicated for external transceiver data direction control from

PHY

O

hsusb1_tll_nxt

Dedicated for external transceiver Next signal from PHY

Dedicated for external transceiver Bidirectional data bus

O

AG9

AF11

AG12

AH12

AH14

AE11

V2

AD5

AD6

AC6

AC7

AD9

AC5

hsusb1_tll_data0

hsusb1_tll_data1

hsusb1_tll_data2

hsusb1_tll_data3

hsusb1_tll_data4

IO

AC3

AD4

AD3

AD2

Y3

Dedicated for external transceiver Bidirectional data bus

additional signals for 12-pin ULPI operation

hsusb1_tll_data5

hsusb1_tll_data6

hsusb1_tll_data7

Dedicated for external transceiver Bidirectional data bus

additional signals for 12-pin ULPI operation

IO

AH9

AF13

AE13

AB1

AE3

AA3

AD2

AC8

AD8

Dedicated for external transceiver Bidirectional data bus

additional signals for 12-pin ULPI operation

Dedicated for external transceiver Bidirectional data bus

additional signals for 12-pin ULPI operation

104

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2.5.4 Removable Media Interfaces

Table 2-18. Removable Media Interfaces – MMC/SDIO Signals Description

SIGNAL NAME

DESCRIPTION

TYPE⁽¹

BALL BOTTOM

(CBB Pkg.)

BALL BOTTOM

(CBC Pkg.)

BALL BOTTOM

(CUS Pkg.)

)

MULTIMEDIA MEMORY CARD (MMC1) / SECURE DIGITAL IO (SDIO1)

mmc1_clk

MMC/SD Output Clock

O

N28

M27

N27

N26

N25

P28

P27

P26

R27

R25

N19

L18

M19

M18

K18

N20

M20

P17

P18

P19

M23

L23

mmc1_cmd

mmc1_dat0

mmc1_dat1

mmc1_dat2

mmc1_dat3

mmc1_dat4

mmc1_dat5

mmc1_dat6

mmc1_dat7

MMC/SD command signal

MMC/SD Card Data bit 0 / SPI Serial Input

MMC/SD Card Data bit 1

MMC/SD Card Data bit 2

MMC/SD Card Data bit 3

MMC/SD Card Data bit 4

MMC/SD Card Data bit 5

MMC/SD Card Data bit 6

MMC/SD Card Data bit 7

IO

M22

M21

M20

N23

N22

N21

N20

P24

MULTIMEDIA MEMORY CARD (MMC2) / SECURE DIGITAL IO (SDIO2)

mmc2_clk

MMC/SD Output Clock

O

AE2

AE4

W10

V10

Y1

mmc2_dir_dat0

Direction control for DAT0 signal case an external

transceiver used

AB2

mmc2_dir_dat1

mmc2_dir_dat2

mmc2_dir_dat3

Direction control for DAT1 and DAT3 signals case an

external transceiver used

O

AH3

AF19

AE21

M3

E4

G3

AA2

AC17

AB16

Direction control for DAT2 signal case an external

transceiver used

Direction control for DAT4, DAT5, DAT6, and DAT7

signals case an external transceiver used

mmc2_clkin

mmc2_dat0

mmc2_dat1

mmc2_dat2

mmc2_dat3

mmc2_dat4

mmc2_dat5

mmc2_dat6

mmc2_dat7

mmc2_dir_cmd

MMC/SD input Clock

I

AE3

AH5

K3

T10

AA1

AB3

MMC/SD Card Data bit 0

MMC/SD Card Data bit 1

MMC/SD Card Data bit 2

MMC/SD Card Data bit 3

MMC/SD Card Data bit 4

MMC/SD Card Data bit 5

MMC/SD Card Data bit 6

MMC/SD Card Data bit 7

IO

O

AH4

T9

Y3

AG4

U10

W3

AF4

U9

V3

AE4 / AB3

AH3 / AB4

AF3 / AA4

AE3 / AC2

AF3

P9 / V10

M3/P8

L3/P7

K3/R7

L3

AB2 / T5

AA2 / R4

Y2 / T4

AA1 / T6

Y2

Direction control for CMD signal case an external

transceiver is used

mmc2_cmd

MMC/SD command signal

IO

AG5

R10

AB5

MULTIMEDIA MEMORY CARD (MMC3) / SECURE DIGITAL IO (SDIO3)

mmc3_clk

MMC/SD Output Clock

O

AB1 / AF10

AC3 / AE10

AE4 / AE11

AH3 / AH9

AF3 / AF13

AE3 / AE13

AF11

R9 / AB2

R8 / AB3

V10 / Y3

M3/AB1

L3/AE3

K3/AA3

AC3

AC1

AD3

mmc3_cmd

mmc3_dat0

mmc3_dat1

mmc3_dat2

mmc3_dat3

mmc3_dat4

mmc3_dat5

mmc3_dat6

mmc3_dat7

MMC/SD command signal

MMC/SD Card Data bit 0 / SPI Serial Input

MMC/SD Card Data bit 1

MMC/SD Card Data bit 2

MMC/SD Card Data bit 3

MMC/SD Card Data bit 4

MMC/SD Card Data bit 5

MMC/SD Card Data bit 6

MMC/SD Card Data bit 7

IO

AB2 / AC5

AA2 / AD2

Y2 / AC8

AA1 / AD8

AD6

AG9

V2

AD5

AF9

AA4

AC4

AH14

AD2

AD9

(1) Type = Ball type for this specific function (I = Input, O = Output, Z = high-impedance, D = Open Drain, DS = Differential, A = Analog)

TERMINAL DESCRIPTION

105

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2.5.5 Test Interfaces

Table 2-19. Test Interfaces – ETK Signals Description

SIGNAL NAME

DESCRIPTION

TYPE⁽¹⁾

BALL BOTTOM

(CBB Pkg.)

BALL BOTTOM

(CBC Pkg.)

BALL BOTTOM

(CUS Pkg.)

etk_ctl

etk_clk

etk_d0

etk_d1

etk_d2

etk_d3

etk_d4

etk_d5

etk_d6

etk_d7

etk_d8

etk_d9

etk_d10

etk_d11

etk_d12

etk_d13

etk_d14

etk_d15

ETK trace ctl

ETK trace clock

ETK data 0

ETK data 1

ETK data 2

ETK data 3

ETK data 4

ETK data 5

ETK data 6

ETK data 7

ETK data 8

ETK data 9

ETK data 10

ETK data 11

ETK data 12

ETK data 13

ETK data 14

ETK data 15

O

AE10

AF10

AF11

AG12

AH12

AE13

AE11

AH9

AB2

AB3

AC3

AD4

AD3

AA3

Y3

AD3

AC1

AD6

AC6

AC7

AD8

AC5

AB1

AE3

AD2

AA4

V2

AD2

AF13

AH14

AF9

AC8

AD9

AC4

AG9

AE7

AD5

AE4

AF6

AE6

AF7

AF9

AE9

AC3

AF7

AC9

AG7

AH7

AC10

AD11

AC11

AD12

AG8

AH8

(1) Type = Ball type for this specific function (I = Input, O = Output, Z = high-impedance, D = Open Drain, DS = Differential, A = Analog)

106

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Table 2-20. Test Interfaces – JTAG Signals Description

SIGNAL NAME

DESCRIPTION

TYPE⁽¹⁾

BALL BOTTOM

(CBB Pkg.)

BALL BOTTOM

(CBC Pkg.)

BALL BOTTOM

(CUS Pkg.)

jtag_ntrst

jtag_tck

jtag_rtck

Test Reset

Test Clock

I

AA17

AA13

AA12

U15

V14

W13

AB7

AB6

AA7

ARM Clock

Emulation

O

jtag_tms_tmsc

jtag_tdi

Test Mode Select

Test Data Input

Test Data Output

Test emulation 0

Test emulation 1

IO

I

AA18

AA20

AA19

AA11

AA10

V15

U16

Y13

Y15

Y14

AA9

AB10

AB9

jtag_tdo

O

IO

jtag_emu0

jtag_emu1

AC24

AD24

(1) Type = Ball type for this specific function (I = Input, O = Output, Z = high-impedance, D = Open Drain, DS = Differential, A = Analog)

Table 2-21. Test Interfaces – SDTI Signals Description

SIGNAL

NAME

DESCRIPTION

TYPE⁽¹⁾

BALL BOTTOM

(CBB Pkg.)

BALL BOTTOM

(CBC Pkg.)

BALL BOTTOM

(CUS Pkg.)

SUBSYSTEM

SIGNAL

MULTIPLEXING⁽²⁾

sdti_clk

sdti_txd0

sdti_txd1

sdti_txd2

sdti_txd3

Serial clock dual edge

O

AF7 / AA11 / AG8

AG7 / AA10 / AA11

AH7 / AA10

AG8

AF6 / Y15 / AF9

AE6 / Y14 / Y15

AF7 / Y14

AF9

AC9 / AC24 / AC11

etk_d11 / jtag_emu0 /

etk_d14

Serial data out (System Trace

messages)

AC10 / AD24 /

AC24

etk_d12 / jtag_emu1 /

jtag_emu0

Serial data out (System Trace

messages)

AD11 / AD24

etk_d13 / jtag_emu1

Serial data out (System Trace

messages)

AC11

etk_d14

Serial data out (System Trace

messages)

AH8

AE9

AD12

etk_d15

(1) Type = Ball type for this specific function (I = Input, O = Output, Z = high-impedance, D = Open Drain, DS = Differential, A = Analog)

(2) The subsystem pin multiplexing options are not described in and

Table 2-22. Test Interfaces – HWDBG Signals Description

SIGNAL NAME

DESCRIPTION

TYPE⁽¹⁾

BALL BOTTOM

(CBB Pkg.)

BALL BOTTOM

(CBC Pkg.)

BALL BOTTOM

(CUS Pkg.)

hw_dbg0

hw_dbg1

hw_dbg2

hw_dbg3

hw_dbg4

hw_dbg5

hw_dbg6

hw_dbg7

hw_dbg8

hw_dbg9

hw_dbg10

hw_dbg11

hw_dbg12

hw_dbg13

hw_dbg14

hw_dbg15

hw_dbg16

hw_dbg17

Debug signal 0

Debug signal 1

Debug signal 2

Debug signal 3

Debug signal 4

Debug signal 5

Debug signal 6

Debug signal 7

Debug signal 8

Debug signal 9

Debug signal 10

Debug signal 11

Debug signal 12

Debug signal 13

Debug signal 14

Debug signal 15

Debug signal 16

Debug signal 17

O

A24 / AF10

A23 / AE10

C27/ AF11

C23 / AG12

B24 / AH12

C24 / AE13

D24 / AE11

A25 / AH9

B25 / AF13

C26 / AH14

B23 / AF9

D25 / AG9

D28 / AE7

D26 / AF7

E26 / AG7

F28 / AH7

F27 / AG8

G26 / AH8

C23/AB2

D23/AB3

C26/AC3

B23/AD4

A24/AD3

B24/AA3

D24/Y3

AC1/A22

AD3/E18

AD6/J19

AC6/H24

AC7/G19

AD8/F19

AC5/G20

AD2/B21

AC8/F21

AD9/G21

AC4/F18

AD5/J20

AC3/G22

AC9/E22

AC10/D24

AD11/E23

AC11/E24

AD12/F23

C24/AB1

D25/AE3

E26/AD2

A23/AA4

D26/V2

G25/AE4

K24/AF6

G26/AE6

H25/AF7

H26/AF9

J26/AE9

(1) Type = Ball type for this specific function (I = Input, O = Output, Z = high-impedance, D = Open Drain, DS = Differential, A = Analog)

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2.5.6 Miscellaneous

Table 2-23. Miscellaneous – GP Timer Signals Description

SIGNAL NAME

gpt8_pwm_evt

gpt9_pwm_evt

gpt10_pwm_evt

gpt11_pwm_evt

DESCRIPTION

TYPE⁽¹⁾

BALL BOTTOM

(CBB Pkg.)

BALL BOTTOM

(CBC Pkg.)

BALL BOTTOM

(CUS Pkg.)

PWM or event for GP

timer 8

IO

N8 / AD25 / V3

T8 / AB26 / Y2

R8 / AB25 / Y3

P8 / AA25 / Y4

C5 / AD21/ V9

B4 / W8 / Y24

C4 / U8 / AA24

B5 / V8 / AD22

G4/ M4

PWM or event for GP

timer 9

IO

F4 / N4

G5 / N3

F3 / M5

PWM or event for GP

timer 10

IO

PWM or event for GP

timer 11

IO

(1) Type = Ball type for this specific function (I = Input, O = Output, Z = high-impedance, D = Open Drain, DS = Differential, A = Analog)

108

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2.5.7 General-Purpose IOs

Table 2-24. General-Purpose IOs Signals Description⁽¹⁾

SIGNAL NAME

DESCRIPTION

TYPE⁽²⁾

BALL BOTTOM

(CBB Pkg.)

BALL BOTTOM

(CBC Pkg.)

BALL BOTTOM

(CUS Pkg.)

gpio_0

gpio_1

General-purpose IO 0

General-purpose IO 1

General-purpose IO 2

General-purpose IO 3

General-purpose IO 4

General-purpose IO 5

General-purpose IO 6

General-purpose IO 7

General-purpose IO 8

General-purpose IO 9

General-purpose IO 10

General-purpose IO 11

General-purpose IO 12

General-purpose IO 13

General-purpose IO 14

General-purpose IO 15

General-purpose IO 16

General-purpose IO 17

General-purpose IO 18

General-purpose IO 19

General-purpose IO 20

General-purpose IO 21

General-purpose IO 22

General-purpose IO 23

General-purpose IO 24

General-purpose IO 25

General-purpose IO 26

General-purpose IO 27

General-purpose IO 28

General-purpose IO 29

General-purpose IO 30

General-purpose IO 31

General-purpose IO 34

General-purpose IO 35

General-purpose IO 36

General-purpose IO 37

General-purpose IO 38

General-purpose IO 39

General-purpose IO 40

General-purpose IO 41

General-purpose IO 42

General-purpose IO 43

General-purpose IO 44

General-purpose IO 45

General-purpose IO 46

General-purpose IO 47

General-purpose IO 48

IO

AF26

AF25

AH26

AG26

AE14

AF18

AF19

AE21

AF21

AF22

AG25

AA11

AF10

AE10

AF11

AG12

AH12

AE13

AE11

AH9

AF13

AH14

AF9

AG9

AE7

AF7

AG7

AH7

AG8

AH8

AF24

AA10

N4

V16

W15

F3

W16

Y13

AB12

AC16

AD17

AD18

AC17

AB16

AA15

AD23

Y7

gpio_2

gpio_3

D3

gpio_4

C3

gpio_5

E3

gpio_6

E4

gpio_7

G3

gpio_8

D4

gpio_9

V12

AE14

Y15

AB2

AB3

AC3

AD4

AD3

AA3

Y3

gpio_10

gpio_11

gpio_12

gpio_13

gpio_14

gpio_15

gpio_16

gpio_17

gpio_18

gpio_19

gpio_20

gpio_21

gpio_22

gpio_23

gpio_24

gpio_25

gpio_26

gpio_27

gpio_28

gpio_29

gpio_30

gpio_31

gpio_34

gpio_35

gpio_36

gpio_37

gpio_38

gpio_39

gpio_40

gpio_41

gpio_42

gpio_43

gpio_44

gpio_45

gpio_46

gpio_47

gpio_48

AC24

AC1

AD3

AD6

AC6

AC7

AD8

AC5

AD2

AC8

AD9

AC4

AD5

AC3

AC9

AC10

AD11

AC11

AD12

Y10

AD24

K4

AB1

AE3

AD2

AA4

V2

AE4

AF6

AE6

AF7

AF9

AE9

AD7

Y14

J2

M4

H1

K3

L4

H2

K2

K4

G2

J4

T3

F1

J3

R3

F2

J2

N3

E1

J1

M3

E2

H1

L3

D1

H2

K3

D2

G2

H2

V1

R2

K2

Y1

T2

P1

T1

U1

R1

U2

R3

R2

U1

T3

(1) NA in table stands for "Not Applicable".

(2) Type = Ball type for this specific function (I = Input, O = Output, Z = high-impedance, D = Open Drain, DS = Differential, A = Analog)

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Table 2-24. General-Purpose IOs Signals Description⁽¹⁾(continued)

SIGNAL NAME

DESCRIPTION

TYPE⁽²⁾

BALL BOTTOM

(CBB Pkg.)

BALL BOTTOM

(CBC Pkg.)

BALL BOTTOM

(CUS Pkg.)

gpio_49

gpio_50

gpio_51

gpio_52

gpio_53

gpio_54

gpio_55

gpio_56

gpio_57

gpio_58

gpio_59

gpio_60

gpio_61

gpio_62

gpio_63

gpio_64

gpio_65

gpio_66

gpio_67

gpio_68

gpio_69

gpio_70

gpio_71

gpio_72

gpio_73

gpio_74

gpio_75

gpio_76

gpio_77

gpio_78

gpio_79

gpio_80

gpio_81

gpio_82

gpio_83

gpio_84

gpio_85

gpio_86

gpio_87

gpio_88

gpio_89

gpio_90

gpio_91

gpio_92

gpio_93

gpio_94

gpio_95

gpio_96

gpio_97

gpio_98

gpio_99

General-purpose IO 49

General-purpose IO 50

General-purpose IO 51

General-purpose IO 52

General-purpose IO 53

General-purpose IO 54

General-purpose IO 55

General-purpose IO 56

General-purpose IO 57

General-purpose IO 58

General-purpose IO 59

General-purpose IO 60

General-purpose IO 61

General-purpose IO 62

General-purpose IO 63

General-purpose IO 64

General-purpose IO 65

General-purpose IO 66

General-purpose IO 67

General-purpose IO 68

General-purpose IO 69

General-purpose IO 70

General-purpose IO 71

General-purpose IO 72

General-purpose IO 73

General-purpose IO 74

General-purpose IO 75

General-purpose IO 76

General-purpose IO 77

General-purpose IO 78

General-purpose IO 79

General-purpose IO 80

General-purpose IO 81

General-purpose IO 82

General-purpose IO 83

General-purpose IO 84

General-purpose IO 85

General-purpose IO 86

General-purpose IO 87

General-purpose IO 88

General-purpose IO 89

General-purpose IO 90

General-purpose IO 91

General-purpose IO 92

General-purpose IO 93

General-purpose IO 94

General-purpose IO 95

General-purpose IO 96

General-purpose IO 97

General-purpose IO 98

General-purpose IO 99

IO

I

T2

W1

P1

L2

U2

V1

Y1

M2

V2

H3

AD1

A3

NA

V8

NA

U8

B6

D2

T8

B4

F4

R8

C4

G5

P8

B5

F3

N8

C5

G4

T4

N1

W2

G3

K2

K5

U3

J1

L1

H1

AC6

AC8

B3

E1

L8

NA

K8

NA

J8

C6

C2

D28

D26

D27

E27

AG22

AH22

AG23

AH23

AG24

AH24

E26

F28

F27

G26

AD28

AD27

AB28

AB27

AA28

AA27

G25

H27

H26

H25

E28

J26

G25

K24

M25

F26

AE21

AE22

AE23

AE24

AD23

AD24

G26

H25

H26

J26

G22

E22

F22

J21

AC19

AB19

AD20

AC20

AD21

AC21

D24

E23

E24

F23

AC22

AC23

AB22

Y22

W22

V22

J22

AC26

AD26

AA25

Y25

AA26

AB26

L25

L26

G23

G24

H23

D23

K22

V21

W21

A22

E18

B22

J19

M24

M26

F25

N24

AC25

AB25

C23

D23

C25

C26

B23

AE16

AC27

AC28

A24

A23

C25

C27

C23

AG17

H24

AB18

110

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Table 2-24. General-Purpose IOs Signals Description⁽¹⁾(continued)

SIGNAL NAME

DESCRIPTION

TYPE⁽²⁾

BALL BOTTOM

(CBB Pkg.)

BALL BOTTOM

(CBC Pkg.)

BALL BOTTOM

(CUS Pkg.)

gpio_100

gpio_101

gpio_102

gpio_103

gpio_104

gpio_105

gpio_106

gpio_107

gpio_108

gpio_109

gpio_110

gpio_111

gpio_112

gpio_113

gpio_114

gpio_115

gpio_116

gpio_117

gpio_118

gpio_119

gpio_120

gpio_121

gpio_122

gpio_123

gpio_124

gpio_125

gpio_126

gpio_127

gpio_128

gpio_129

gpio_130

gpio_131

gpio_132

gpio_133

gpio_134

gpio_135

gpio_136

gpio_137

gpio_138

gpio_139

gpio_140

gpio_141

gpio_142

gpio_143

gpio_144

gpio_145

gpio_146

gpio_147

gpio_148

gpio_149

gpio_150

General-purpose IO 100

General-purpose IO 101

General-purpose IO 102

General-purpose IO 103

General-purpose IO 104

General-purpose IO 105

General-purpose IO 106

General-purpose IO 107

General-purpose IO 108

General-purpose IO 109

General-purpose IO 110

General-purpose IO 111

General-purpose IO 112

General-purpose IO 113

General-purpose IO 114

General-purpose IO 115

General-purpose IO 116

General-purpose IO 117

General-purpose IO 118

General-purpose IO 119

General-purpose IO 120

General-purpose IO 121

General-purpose IO 122

General-purpose IO 123

General-purpose IO 124

General-purpose IO 125

General-purpose IO 126

General-purpose IO 127

General-purpose IO 128

General-purpose IO 129

General-purpose IO 130

General-purpose IO 131

General-purpose IO 132

General-purpose IO 133

General-purpose IO 134

General-purpose IO 135

General-purpose IO 136

General-purpose IO 137

General-purpose IO 138

General-purpose IO 139

General-purpose IO 140

General-purpose IO 141

General-purpose IO 142

General-purpose IO 143

General-purpose IO 144

General-purpose IO 145

General-purpose IO 146

General-purpose IO 147

General-purpose IO 148

General-purpose IO 149

General-purpose IO 150

I

AH17

B24

AE15

A24

AC18

G19

F19

IO

I

C24

B24

D24

G20

B21

A25

C24

K28

P25

L24

L28

P26

K24

K27

N25

J23

L27

N26

K23

B25

D25

F21

C26

E26

G21

C22

B26

E25

AG19

AH19

AG18

AH18

P21

AD17

AD16

AE18

AE17

U18

NA

I

NA

I

NA

I

NA

IO

V20

N21

R18

T21

R21

T18

V19

M21

R19

R20

N28 / T28

M27 / T25

N27 / R28

N26

W19 / N19

U20 / L18

V19 / M19

M18

M23 / R21

L23 / R23

M22 / P23

M21

M20/R22

N23/T24

J20 / N22

N21

N25 / T26

P28 / T27

D25 / P27

P26

W18 / K18

V20 / N20

M20 / D26

P17

R27

P18

N20

R25

P19

P24

AE2 / U28

AG5 / U27

AH5

Y20 / W10

V18 / R10

T10

Y1 / T23

AB5 / U24

AB3

Y3

AH4

T9

AG4

U10

W3

AF4

U9

V3

AE4

V10

AB2

AA2

Y2

AH3

M3

AF3

L3

AE3

K3

AA1

V6

AF6

N3

AE6

P3

V5

AF5

V3

W4

AE5

W3

V4

AB26

AB25

AA25

AD25

AA8

Y24

NA

AA24

AD22

AD21

L4

NA

W7

AA9

R2

W6

W8

W2

AC2

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Table 2-24. General-Purpose IOs Signals Description⁽¹⁾(continued)

SIGNAL NAME

DESCRIPTION

TYPE⁽²⁾

BALL BOTTOM

(CBB Pkg.)

BALL BOTTOM

(CBC Pkg.)

BALL BOTTOM

(CUS Pkg.)

gpio_151

gpio_152

gpio_153

gpio_154

gpio_155

gpio_156

gpio_157

gpio_158

gpio_159

gpio_160

gpio_161

gpio_162

gpio_163

gpio_164

gpio_165

gpio_166

gpio_167

gpio_168

gpio_169

gpio_170

gpio_171

gpio_172

gpio_173

gpio_174

gpio_175

gpio_176

gpio_177

gpio_178

gpio_179

gpio_180

gpio_181

gpio_182

gpio_183

gpio_184

gpio_185

gpio_186

gpio_188

gpio_189

gpio_190

gpio_191

General-purpose IO 151

General-purpose IO 152

General-purpose IO 153

General-purpose IO 154

General-purpose IO 155

General-purpose IO 156

General-purpose IO 157

General-purpose IO 158

General-purpose IO 159

General-purpose IO 160

General-purpose IO 161

General-purpose IO 162

General-purpose IO 163

General-purpose IO 164

General-purpose IO 165

General-purpose IO 166

General-purpose IO 167

General-purpose IO 168

General-purpose IO 169

General-purpose IO 170

General-purpose IO 171

General-purpose IO 172

General-purpose IO 173

General-purpose IO 174

General-purpose IO 175

General-purpose IO 176

General-purpose IO 177

General-purpose IO 178

General-purpose IO 179

General-purpose IO 180

General-purpose IO 181

General-purpose IO 182

General-purpose IO 183

General-purpose IO 184

General-purpose IO 185

General-purpose IO 186

General-purpose IO 188

General-purpose IO 189

General-purpose IO 190

General-purpose IO 191

IO

Y8

AE1

AD1

AD2

AC1

Y21

AA21

V21

U21

T21

K26

W21

H18

H19

H20

H21

B23

AF15

U26

J25

H3

V3

V7

NA

U4

NA

R3

NA

T3

NA

U19

V17

U17

T20

T19

P20

T17

F23

F24

H24

G24

A23

C2

W19

AB20

W18

Y18

AA18

AA19

V18

A23

B23

B24

C23

F18

AC15

U23

A24

T5

W20

J23

P9

AB3

AB4

AA4

AC2

AC3

AB1

AB2

AA3

Y2

P8

R4

P7

T4

R7

T6

R8

NA

R9

NA

T8

R5

W7

W8

U8

N5

N4

Y3

N3

Y4

V8

M5

V3

V9

M4

AE15

AF14

AG14

AE22

U25

V28

V27

V26

C1

AC14

AC13

AC12

AA6

W24

V23

W23

T22

AB4

AC4

W11

W17

Y18

Y19

Y17

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2.5.8 Power Supplies

Table 2-25. Power Supplies Signals Description⁽¹⁾

SIGNAL NAME

DESCRIPTION

BALL BOTTOM

(CBB Pkg.)

BALL TOP

(CBB Pkg.)

BALL BOTTOM

(CBC Pkg.)

BALL TOP

(CBC Pkg.)

BALL BOTTOM

(CUS Pkg.)

vdd_mpu

ARM power domain

Y9 / W9 / T9 / R9 /

M9 / L9 / J9 / Y10 /

U10 / T10 / R10 /

N10 / M10 / L10 /

J10 / Y11 / W11 /

K11 / J11 / W12 /

K13 / Y14 / K14 /

J14 / Y15 / W15 /

J15

NA

H7/ N7/ U7/ V7/ N8/

G9/ L9/ M9/ W9/ Y9/

M10/ P10/ K11/ U11/

V11/ Y11/ G12/ D13/

U13

NA

W13/ W12/ V13/

V12/ U13/ U12/ T8/

T7/ R8/ R7/ R6/ N8/

N7/ N6/ M12/ M8/

M7/ M6/ L12/ L11/

J10/ J9/ H10/ H9/

G10/ G9/F10

vdd_core

Core power domain

AC4 / J4 / H4 / D8 /

AE9 / D9 / D15 /

Y16 / AE18 / Y18 /

W18 / K18 / J18 /

AE19 / Y19 / U19 /

T19 / N19 / M19 /

J19 / Y20 / W20 /

V20 / U20 / P20 /

N20 / K20 / J20 /

D22 / D23 / AE24 /

M25 / L25 / E25

NA

M7/ T7/ Y8/ G11/ Y12/

D15/ M17/ G18/ H20/

R20/ AC21

NA

T20/ T19/ T18/ T17/

R19/ R18/ R17/

M15/ M14/ L15/

L14/ K19/ K18/ K17/

J18/ J17/ H13/ H12/

G13/ G12/ F13/ F12

cap_vdd_wkup

Wakeup/EMU/memor

y domains, connect

capacitor

AA15

NA

K14

NA

Y12

cap_vdd_d

Decoupling capacitor

AH20

K15

NA

AE19

K13

NA

vdds_dpll_dll

DLL IO power

G18

domain (1.8 V):

internal connection to

PLL_VDDS, power

supply for 3PLL (1.8

V)

vdda_dac

vssa_dac

vdds

Video DAC power

plane

V25

Y26

NA

V25

V24

NA

AB13

AB15

Video DAC ground

plane

IO power plane

AD3 / AD4 / W4 /

AF8 / AE8 / AF16 /

AE16 / AF23 /

AE23 / F25 / F26 /

AG27 / AE27/

G4/ M4/ T4/ Y4/ L7/

AC7/ D9/ AE10/ C11/

J15/ AC15/ A18/ J18/

AC18/ AD20/ E24/

Y9 / W10 / W9 /

V10 / V9 / U10 /

N19 / N18 / N17 /

M19 / M18 / M17

L24/ T24/ W24/ AC24

AG20/ H28/ AG21

vdds_mem

Memory IO power

plane

U1 / J1 / F1 / J2 /

F2 / R4 / B5 / A5 / / E1 / C23 / A4 / A7

AH6 / B8 / A8 / B12

/ A12 / D16 / C16 /

B18 / A18 / B22 /

A22 / G28 / C28

AC5 / P1 / H1 / F23

K8 / K7 / K6 / J8 /

J7 / J6 / H15 / G16

/ G15 / F16 / F15 /

E16

/ A10 / A15 / A18

vdds_dpll_per

vdds_wkup_bg

Peripheral DPLLs

power rail

AA16

NA

U14

NA

U17

For wakeup LDO and

VDDA (2 LDOs

AA14

W14

AA13

SRAM and BG)

(1) NA in this table stands for "Not applicable".

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Table 2-25. Power Supplies Signals Description⁽¹⁾(continued)

SIGNAL NAME

vss

DESCRIPTION

BALL BOTTOM

(CBB Pkg.)

BALL TOP

(CBB Pkg.)

BALL BOTTOM

(CBC Pkg.)

BALL TOP

(CBC Pkg.)

BALL BOTTOM

(CUS Pkg.)

Ground

AG2 / U2 / B2 /

H2 / B18 / AC20 /

G1/ K1/ R1/ W1/ B2/

C1/ F1/ H2/ M2/ R2/

Y6/AA7/ Y11/ AA16/

W20/P20/ L21/ H20/

F20/ B14/A13/ A7

W15/ V16/ V15/

U16/ U15/ U14/

U11/ U9/T16/ T15/

T14/ T13/ T12/ T11/

T10/ T9/ R15/ R14/

R11/ R10/ P17/

P15/ P14/ P13/P12/

P11/ P10/ P8/ N16/

N15/ N14/ N13/

N12/ N11/ N10/ N9/

M16/ M13/ M11/

AG3 / W3 / P3 / J3 / AB5 / AB14 / AB20 H4/ N4/ R4/ W4/ AB5/

E3 / A3 / P4 / E4 /

AG6 / D7 / C7 / V9 / C22 / B4 / B7 / B10

/ P2 / F22 / E2 /

A6/ D7/ Y7/AE7/ A8/

G8/ D10/ G10/ L10/

N10/ Y10/ AC10/ C12/

D12/A13/ D14/ AD14/

K15/ Y16/ L17/ N17/

R17/ D18/ D20/G20/

E22/ AB22/ G23/ L23/

T23/ W23/ AF23/ B25/

K25/U25/ AD25

U9 / P9 / N9 / K9 /

W10 / V10 / P10 /

K10 / D10 / C10 /

AF12 / AE12 / Y12 /

K12 / J12 / Y13 /

W13 / J13 / D13 /

C13 / W14 / K16 /

J16 / Y17 / W17 /

K17 / J17 / W19 /

V19 / R19 / P19 /

L19 / K19 / D19 /

C19 / AF20 / AE20 /

T20 / R20 / M20 /

L20 / D21 / C22 /

AC25 / Y25 / W25 /

AC26 / R26 / L26 /

A26 / G27 / B27 /

AA26/ M28/ AG16/

AH21

/ B15

M10/ M9/ L17/ L13/

L10/ L8/ K15/ K14/

K11/ K10/ J16/ J15/

J14/ J13/ J12/

J11/H16/ H14/ H11

vdds_sram

SRAM LDOs

W16

K25

NA

U12

N23

NA

AA12

N24

vdds_mmc1

MMC IO power

domain for CMD,

CLK, and DAT(0..3)

vdds_mmc1a

Power supply for

MMC DAT [4..7]

P25

V4

NA

P23

N9

NA

H8

U8

cap_vdd_sram_m SRAM LDO

pu

capacitance for

VDDRAM1

cap_vdd_sram_co SRAM LDO

L21

NA

K20

NA

H17

re

capacitance for

VDDRAM2

114

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2.5.9 System and Miscellaneous Terminals

Table 2-26. System and Miscellaneous Signals Description

SIGNAL NAME

DESCRIPTION

TYPE⁽¹

BALL

BOTTOM

(CBB Pkg.)

BALL TOP

(CBB Pkg.)

BALL

BOTTOM

(CBC Pkg.)

BALL TOP

(CBC Pkg.)

BALL

BOTTOM

(CUS Pkg.)

)

sys_32k

32-kHz clock input

I

AE25

AE17

NA

AE20

AF19

NA

AA16

AD15

sys_xtalin

Main input clock. Oscillator input or LVCMOS at

19.2, 13, or 12 MHz.

sys_xtalout

sys_altclk

Output of oscillator

O

I

AF17

J25

NA

AF20

J23

NA

AD14

A24

Alternate clock source selectable for GPTIMERs

(maximum 54 MHz), USB (48 MHz), or

NTSC/PAL (54 MHz)

sys_clkreq

Request from OMAP3515/03 device for system

clock (open source type)

IO

AF25

NA

W15

NA

Y13

sys_clkout1

sys_clkout2

sys_boot0

sys_boot1

sys_boot2

sys_boot3

sys_boot4

sys_boot5

sys_boot6

Configurable output clock1

Configurable output clock2

Boot configuration mode bit 0

Boot configuration mode bit 1

Boot configuration mode bit 2

Boot configuration mode bit 3

Boot configuration mode bit 4

Boot configuration mode bit 5

Boot configuration mode bit 6

O

AG25

AE22

AH26

AG26

AE14

AF18

AF19

AE21

AF21

AH25

AF24

AF26

AD26

AE26

AF22

U8

NA

AE14

W11

F3

NA

Y7

O

AA6

I

AB12

AC16

AD17

AD18

AC17

AB16

AA15

AA10

Y10

I

D3

I

C3

I

E3

I

E4

I

G3

I

D4

sys_nrespwron Power On Reset

V13

AD7

V16

AD15

W16

V12

B6

sys_nreswarm

sys_nirq

Warm Boot Reset (open drain output)

IOD

I

External FIQ input

W16

Y16

sys_nvmode1

sys_nvmode2

sys_off_mode

Indicates the voltage mode

O

I

Y15

AD23

D2

sys_ndmareq0 External DMA request 0 (system expansion).

Level (active low) or edge (falling) selectable.

sys_ndmareq1 External DMA request 1 (system expansion).

Level (active low) or edge (falling) selectable.

I

T8 / J8

L3 / R8

K3 / P8

AG9

NA

B4 / C6

D1 / C4

D2 / B5

V2

NA

F4 / C2

H2 / G5

G2 / F3

AD5

sys_ndmareq2 External DMA request 2 (system expansion).

Level (active low) or edge (falling) selectable.

sys_ndmareq3 External DMA request 3 (system expansion).

Level (active low) or edge (falling) selectable.

I

sys_secure_

indicator

MSECURE transactions indicator

O

sys_drm_

msecure

MSECURE output

AF9

AA4

AC4

(1) Type = Ball type for this specific function (I = Input, O = Output, Z = high-impedance, D = Open Drain, DS = Differential, A = Analog)

2.5.10 Feed-Through Balls (CBC and CBB Packages)

Feed-through pins represent a wire. That is, they do not connect to the silicon die, but rather just connect

from the bottom ball to the top ball. The purpose of these balls is to allow for different PoP packages.

Table 2-27 and Table 2-28 list the feed-through balls on the OMAP35x CBC and CBB packages,

respectively.

Table 2-27. CBC Package Feed-Through Balls

(1)

JEDEC 14x14mm, 0.65mm,

152ball

JEDEC DESCRIPTION

BALL TOP

BALL BOTTOM

FEED-THROUGH BALL

NAME

NC

No Connect

DDR Supply

No Connect

A1

pop_a1_a1

pop_j1_l1

d-vdd

NC

J1

L1

AA1

AF1

pop_aa1_af1

(1) For more details on the feedthrough pin connections, please refer to the PoP memory datasheet.

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Table 2-27. CBC Package Feed-Through Balls (continued)

f-vdd

NC

Flash Supply

No Connect

Flash Supply

N2

T2

pop_n2_t2

Y2

pop_t2_y2

W2

Y2

AE2

AF4

AF5

AF8

AF10

pop_w2_ae2

pop_y2_af4

pop_aa6_af5

pop_y7_af8

pop_y9_af10

NC

f-vdd

NC, Int

AA6

Y7

No Connect; Interrupt when

using OneNAND POP

Y9

f-nbe0, cle0

d-vdd

No Connect/CLE

AA10

AA11

AF12

AF13

pop_aa10_af12

pop_aa11_af13

DDR Supply/ POP FLASH

vpp supply

d-tq

No Connect/ DDR die

temperature sensor

AA12

AF14

pop_aa12_af14

vss

Shared Ground

DDR Supply

Shared Ground

DDR Supply

Shared Ground

DDR Supply

No Connect

DDR Supply

No Connect

AA13

Y14

AF15

AF17

AF16

A20

pop_aa13_af15

pop_y14_af17

pop_aa14_af16

pop_b16_a20

pop_y17_af21

pop_aa17_af18

pop_y19_af24

pop_aa19_af22

pop_a20_a25

pop_y20_ae25

pop_aa20_af25

pop_a21_a26

pop_b21_b26

pop_h21_k26

pop_p21_u26

pop_y21_ae26

pop_aa21_af26

d-vdd

d-vddq

d-vdd

vss

AA14

B16

Y17

AF21

AF18

AF24

AF22

A25

d-vdd

vss

AA17

Y19

d-vddq

NC

AA19

A20

NC

Y20

AE25

AF25

A26

NC

AA20

A21

NC

B21

B26

d-vdd

NC

H21

P21

K26

U26

Y21

AE26

AF26

NC

AA21

Table 2-28. CBB Package Feed-Through Balls

(1)

JEDEC 12x12, 0.5mm,

168ball

JEDEC DESCRIPTION

BALL TOP

BALL BOTTOM

FEED-THROUGH BALL

NAME

d-vdd

f-vdd

DDR Supply

Flash Supply

Flash vpp supply

A12

AA23

H23

K1

A15

pop_a12_a15

pop_aa23_ae28

pop_h23_af28

pop_k1_j28

AE28

AF28

J28

Y23

AA1

AC8

AC13

L1

M1

pop_y23_m1

pop_aa1_aa1

pop_ac8_af1

pop_ac13_ah10

pop_l1_ah15

pop_u1_n1

AA1

AF1

f-vdd

AH10

AH15

N1

f-vdd

U1

f-vpp

AC11

AB9

AH13

AG11

pop_ac11_ah13

pop_ab9_ag11

NC, int0

No Connect/PoP OneNAND

interrupt

NC, int1

No Connect/PoP OneNAND

interrupt

AC9

AH11

pop_ac9_ah11

NC

No Connect

A1

pop_a1_a1

A2

pop_a2_a2

A22

A23

A27

A28

pop_a22_a27

pop_a23_a28

(1) For more details on the feedthrough pin connections, please refer to the PoP memory datasheet.

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Table 2-28. CBB Package Feed-Through Balls (continued)

NC

No Connect

AB1

AB2

AB22

AB23

AC1

AC2

AC22

AC23

B1

AG1

NA

pop_ab1_ag1

NA

NC

No Connect

NC

No Connect

NA

NC

No Connect

AG28

AH1

AH2

AH27

AH28

B1

pop_ab23_ag28

pop_ac1_ah1

pop_ac2_ah2

pop_ac22_ah27

pop_ac23_ah28

pop_b1_b1

NA

NC

No Connect

NC

No Connect

NC

No Connect

NC

No Connect

NC

No Connect

NC

No Connect

B2

NA

NC

No Connect

B22

B23

AB11

AC14

AA2

U2

NA

NC

No Connect

B28

AG13

AH16

AA2

AF2

AF27

AG10

AG15

B15

J27

pop_b23_b28

pop_ab11_ag13

pop_ac14_ah16

pop_aa2_aa2

pop_u2_af2

pop_aa22_af27

pop_ab8_ag10

pop_ab13_ag15

pop_b12_b15

pop_h22_j27

pop_k2_m2

pop_k22_m26

pop_l2_n2

f-rst#, rp#

d-tq

vss

Flash reset

DDR temperature alert

Shared Ground

AA22

AB8

AB13

B12

H22

K2

M2

K22

L2

M26

N2

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3 ELECTRICAL CHARACTERISTICS

3.1 Power Domains

The OMAP3515/03 device integrates enhanced features that dynamically adapt energy consumption

according to application needs and performance requirements.

The OMAP3515/03 device includes an enhanced power-management scheme based on:

•

Nine independent functional voltage domains on chip partitioning

Multiple voltage domains

Voltage scaling support

Enhanced memory retention support

Optimized device off mode

Centralized management of power, reset, and clock

The external power supplies of OMAP3515/03 are:

•

vdd_mpu for the ARM

vdd_core for macros

vdds for IO macros

vdds_mem for memory macros

vdds_sram for SRAM LDOs

vdds_dpll_dll for DLL IO

vdds_dpll_per for peripheral DPLLs

vdds_wkup_bg for wakeup LDO and VDDA (2 LDOs: SRAM and BandGap)

vdda_dac for video DAC

vdds_mmc1 and vdds_mmc1a for MMC IO

The supply voltages are detailed in Table 3-3.

Figure 3-1 illustrates the power domains:

118

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vdd_mpu

vdds_dpll_dll

DLL/DCDL

BandGap

vdds_wkup_bg

LDO3

1.0 V/1.2 V

SRAM1

ARRAY

WKUP

EMU

LDO

in 1.8 V

out 1.2 V

cap_vdd_wkup

vdds_mem

MPU

BCK

MEM

cap_vdd_sram_mpu

DPLL_MPU

SRAM 1 LDO

0 V/1.0 V/1.2 V

vdds

vdd_mpu domain

vdds_sram

vpp

eFUSE

LDO

in 1.8 V

out 1.2 V

SRAM2

ARRAY

SRAM 2 LDO

0 V/1.0 V/1.2 V

vdd_core

vdds_mmc1

vdds_mmc1a

Core

cap_vdd_sram_core

DPLL_CORE

MMC1

LDO

in 1.8 V

out 1.2 V

LDO

tv_ref

(for capacitor)

HSDIVIDER

Periph1

DPLL4

vdds_dpll_per

vdda_dac

LDO

HSDIVIDER

Dual Video DAC

LDO

in 1.8 V

out 1.2 V

Periph2

DPLL5

vdd_core domain

vss

vssa_dac

OMAP Device

030-003

Figure 3-1. OMAP3515/03 Power Domains

This power domain segmentation switches off (or places in retention state) domains that are unused while

keeping others active. This implementation is based on internal switches that independently control each

power domain.

A power domain regular logic is attached to one of the device V_DDsupplies through a primary domain

switch. When the primary switch is open, most of the logic supply is off, resulting in a low-leakage state of

the domain. Embedded switches are implemented for all power domains except the wake-up domain. This

allows the domain to be powered off, if not being used, to give maximum power savings. For more

information, see the PRCM chapter of the OMAP35x Technical Reference Manual (TRM) [literature

number SPRUFA5].

All domain output signals at the interface between power domains are connected through isolation latch

cells. These cells ensure a proper electrical isolation between the domains and an appropriate interface

state at the domain boundaries.

ELECTRICAL CHARACTERISTICS

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3.2 Absolute Maximum Ratings

The following table specifies the absolute maximum ratings over the operating junction temperature range

of OMAP commercial and extended temperature devices. Stresses beyond those listed under absolute

maximum ratings may cause permanent damage to the device. These are stress ratings only and

functional operation of the device at these or any other conditions beyond those indicated under

recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for

extended periods may affect device reliability.

Notes:

•

Logic functions and parameter values are not assured out of the range specified in the recommended

operating conditions.

•

The OMAP3515/03 device adheres to EIA/JESD22−A114, Electrostatic Discharge (ESD) Sensitivity

Testing Human Body Model (HBM). Minimum pass level for HBM is ±1 kV.

Table 3-1. Absolute Maximum Ratings Over Operating Junction Temperature Range

PARAMETER

MIN

MAX

UNIT

vdd_mpu

vdd_core

Supply voltage range for core macros

–0.5

1.6

V

vdds

vdds_mem

Second supply voltage range for 1.8-V I/O macros

–0.5

2.25

V

vdds_mmc1

Supply voltage range for MMC1 CMD,

CLK and DAT[3:0] and for memory stick

I/Os

1.8-V mode

–0.5

-0.5

2.45

3.50

3.0-V mode

vdds_

vdds_mmc1a

Second supply voltage range for MMC1

DAT[7:4]

1.8-V mode

3.0-V mode

–0.5

-0.5

–0.5

2.45

3.50

2.10

V

vdds_dpll_dll

vdds_dpll_per

Supply voltage for DLL DPLL

Supply voltage for Per DPLL

V

vdds_sram

Supply voltage for SRAM LDOs

–0.5

2.25

vdds_wkup_bg Supply voltage for wakeup LDO and VDDA (2 LDOs SRAM and BG)

V_PAD

Voltage range MMC1, MS (Balls N28,

Supply voltage range for 1.8-V IOs

Supply voltage range for 3.0-V IOs

–0.54⁽¹⁾

–0.45⁽²⁾

2.34⁽¹⁾

3.45⁽²⁾

at PAD

M27, N27, N26, N25,

P28)

MMC1 (Balls P27, P26,

R27, R25)

I2C1, I2C2, I2C3, I2C4 (Balls K21, J21, AF15, AE15, AF14,

AG14, AD26, AE26)

–0.63⁽¹⁾

2.73⁽¹⁾

Crystal (xtalin/xtalout) (Balls AE17, AF17)

Other balls

–0.5

2.71

vddsx⁽³⁾+ 0.5

2.43

vdda_dac

V_ESD

Supply voltage range for analog macros

V

ESD stress

voltage⁽⁴⁾

HBM (human body

model)⁽⁵⁾

vdds_ MMC1a,

500

mmc1_dat[7-4] (CBB pkg only)⁽⁶⁾

Other pins

1000

300

500

200

20

(6)

CDM (charged device

model)⁽⁷⁾

MMC1 signals (CBB pkg only)

Other pins

I_IOI

Current-pulse injection on each I/O pin⁽⁸⁾

Clamp current for an input or output

Storage temperature range⁽⁹⁾

mA

°C

I_clamp

T_stg

–20

–65

150

(1) For a maximum time of 30% time period.

(2) For a maximum time of 15% time period.

(3) Depending on ball, vddsx can be vdds_mem or vdds.

(4) Electrostatic discharge (ESD) to measure device sensitivity/immunity to damage caused by electrostatic discharges into the device.

(5) JEDEC JESD22–A114F

(6) Corresponding signals: mmc1_dat0, mmc1_dat1, mmc1_dat2, mmc1_dat3, mmc1_dat4, mmc1_dat5, mmc1_dat6, mmc1_dat7,

mmc1_clk, mmc1_cmd and vdds_mmc1 (CBB pkg only).

(7) JEDEC JESD22−C101D

(8) Each device is tested with I/O pin injection of 200 mA with a stress voltage of 1.5 times maximum vdd at room temperature.

(9) These temperatures extreme do not simulate actual operating conditions but exaggerate any faults that might exist.

120

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This section includes the maximum power consumption for each power domain (core, etc.). Table 3-2

summarizes the power consumption at the ball level.

Table 3-2. Estimated Maximum Power Consumption At Ball Level

PARAMETER

MAX

UNIT

( T = 90°C) ( T = 105°C)

Signal

Description

vdd_mpu

Processors⁽¹⁾

OMAP3515/03 (SmartReflex™ Enabled)

639

808

439

539

353

438

65

695

889

489

609

403

507

65

mA

OMAP3515/03 (SmartReflex™ Disabled)

OMAP3515 (SmartReflex™ Enabled)

OMAP3515 (SmartReflex™ Disabled)

OMAP3503 (SmartReflex™ Enabled)

OMAP3503 (SmartReflex™ Disabled)

vdd_core

Core

vdda_dac

Video DAC

vdss_dpll_dll

vdds_dpll_per

vdds_sram

vdds_wkup_bg

vdds_mem

vdds

DLL + DPLL MPU, and core

25

DPLL peripheral 1 and peripheral 2

Processors and core LDO (LDO1 and LDO2)

Bandgap, wakeup + LDO, EMU off

Standard I/Os (SDRC+GPMC)

Standard I/Os (all excluding SDRC and GPMC)

MMC I/O⁽²⁾

15

41

6

37

63

vdds_mmc1

vdds_mmc1a

vpp

20

Power supply for MMC IO [DAT4 – DAT7]

eFuse

2

50

(1) OPP6 is only supported on high-speed grade OMAP3530 devices.

(2) MMC card and I/O card are not included.

ELECTRICAL CHARACTERISTICS

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3.3 Recommended Operating Conditions

All OMAP3515/03 modules are used under the operating conditions contained in Table 3-3. The

information in the notes below is provided solely for convenience and does not extend or modify the

warranty provided under TI's standard terms and conditions for TI semiconductor products.

Note (POH Limitations):

To avoid significant device degradation for commercial temperature OMAP3515/OMAP3503 devices (0°C

≤ T_j≤ 90°C), the device power-on hours (POH) must be limited to one of the following:

•

100K total POH when operating across all OPPs and keeping the time spent at OPP5-OPP6 to less

than 23K POH.

•

50K total POH when operating at OPP5 - OPP6.

44K total POH with no restrictions to the proportion of these POH at operating points OPP1 - OPP6.

To avoid significant device degradation for extended temperature OMAP3515A/OMAP3503A devices (-

40°C ≤ T_j≤ 105°C), the following restrictions apply:

•

OPP5 and OPP6 are not supported.*

The total device POH must be limited to less than 50K.*

*If an extended temperature device is operated such that T_jnever exceeds 90C (-40°C ≤T_j≤ 90°C) then

the OPP POH limits for commercial devices indicated above apply.

Note: Logic functions and parameter values are not guaranteed out of the range specified in the

recommended operating conditions. The above notations cannot be deemed a warranty or deemed to

extend or modify the warranty under TI's standard terms and conditions for TI semiconductor products.

Table 3-3. Recommended Operating Conditions

PARAMETER

DESCRIPTION

MIN

NOM

MAX

UNIT

(1)

V_DD1

OMAP processor logic supply

OPP6: Overdrive

OPP5: Overdrive

V_DD1NOM

-

1.35

V_DD1NOM

+

V

(vdd_mpu ),

SmartReflex

Disabled

(0.05*V_DD1NOM

V_DD1NOM

(0.05*V_DD1NOM

V_DD1NOM

(0.05*V_DD1NOM

V_DD1NOM

(0.05*V_DD1NOM

V_DD1NOM

(0.05*V_DD1NOM

V_DD1NOM

(0.05*V_DD1NOM

V_DD2NOM

(0.05*V_DD2NOM

V_DD2NOM

(0.05*V_DD2NOM

V_DD2NOM

)

(0.05*V_DD1NOM

V_DD1NOM

(0.05*V_DD1NOM

V_DD1NOM

(0.05*V_DD1NOM

V_DD1NOM

(0.05*V_DD1NOM

V_DD1NOM

(0.05*V_DD1NOM

V_DD1NOM

(0.05*V_DD1NOM

V_DD2NOM

(0.05*V_DD2NOM

V_DD2NOM

(0.05*V_DD2NOM

V_DD2NOM

)

-

1.35

1.27

1.20

1.06

0.985

1.15

1.06

0.985

1.8

+

V

OPP4: Mid-Overdrive

OPP3: Nominal

-

+

-

+

OPP2: Low-Power

-

+

OPP1: Ultra Low-

Power⁽²⁾

-

+

V_DD2(vdd_core) OMAP core logic supply⁽³⁾

SmartReflex

Disabled

OPP3: Nominal

-

+

OPP2: Low-Power

-

+

OPP1: Ultra Low-

Power⁽²⁾

-

+

(0.05*V_DD2NOM

vdds

Supply voltage for I/O macros

Noise (peak-peak)

1.71

1.91

90

V

mVpp

V

vdds_mem

vdds_mmc1

Supply voltage for memory I/O macros

Noise (peak-peak)

1.71

1.8

1.89

90

mVpp

V

Supply voltage range for MMC1

CMD, CLK and DAT[3:0] and for

memory stick I/Os

1.8-V mode

3.0-V mode

1.71

2.7

1.8

3.0

1.89

3.3

V

(1) OPP6 is only supported on high-speed grade OMAP3530/25 devices.

(2) Cannot boot in OPP1. If OPP1 is desired, boot in higher OPP then switch to OPP1.

(3) Core logic includes interconnect, graphics processor, and peripherals.

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Table 3-3. Recommended Operating Conditions (continued)

PARAMETER

DESCRIPTION

MIN

1.71

NOM

1.8

MAX

1.89

3.3

UNIT

vdds_mmc1a

Second supply voltage range for

MMC1 DAT[7:4]

1.8-V mode

3.0-V mode

V

2.7

3.0

1.8

vdds_wkup_bg Wakeup LDO

Noise (peak-peak)

1.71

1.89

50

V

mVpp

V

vdda_dac

Analog supply voltage for video DAC

Noise (peak-peak)

1.71

1.8

1.89

30

For a frequency of 0 to

100 kHz

mVpp

(For a frequency < 100

kHz, decreases 20dB /

sec)

vdds_sram

SRAM LDOs

1.71

1.8

1.89

50

V

mVpp

V

Noise (peak-peak)

vdds_dpll_per

vdds_dpll_dll

Peripherals DPLLs power supply

Noise (peak-peak)

1.89

36

mVpp

V

Supply voltage for DPLLs I/Os

Noise (peak-peak)

1.89

30

mVpp

V

vpp⁽⁴⁾

vss

eFuse programming

Ground

0

–

0

V

vssa_dac

T_a

Dedicated ground for DAC

V

Operating free air temperature

range

Commercial

Temperature

70

°C

Extended Temperature

-40

0

-

85

90

T_j

Operating junction temperature⁽⁵⁾

Commercial

Temperature

–

°C

Extended Temperature

-40

-

105

(4) It is recommended not to connect this pin. It is just used for eFuse programming on package unit.

(5) For proper device operation, Tj must be within the specified range.

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3.4 DC Electrical Characteristics

Table 3-4 summarizes the dc electrical characteristics.

Table 3-4. DC Electrical Characteristics

PARAMETER

MIN

NOM

MAX

UNIT

LVCMOS Pin Buffers - CBB: N28, M27, N27, N26, N25, P28,P27, P26, R27, R25/ CBC: N19, L18, M19, M18, K18, N20, M20, P17, P18,

P19/ CUS: M23, L23, M22, M21, M20, N23

V_IH

High-level input voltage

vdds⁽¹⁾= 1.8 V

vdds⁽¹⁾= 3.0 V

0.65 × vdds⁽¹⁾

vdds + 0.3

V

0.625 ×

vdds⁽¹⁾

V_IL

V_OH

V_OL

Low-level input voltage

vdds⁽¹⁾= 1.8 V

vdds⁽¹⁾= 3.0 V

vdds⁽¹⁾= 1.8 V

vdds⁽¹⁾= 3.0 V

vdds⁽¹⁾= 1.8 V

vdds⁽¹⁾= 3.0 V

–0.3

vdds⁽¹⁾– 0.2

0.75 × vdds⁽¹⁾

0.35 × vdds

0.25 × vdds

V

High-level output voltage⁽²⁾

Low-level output voltage⁽²⁾

0.2

0.125 ×

vdds⁽¹⁾

t_T

Input transition time (rise time, t_Ror fall time, Normal Mode

10

3

ns

t_Fevaluated between 10% and 90% at PAD)

High-Speed

Mode

LVDS/CMOS Pin Buffers - CBB: AG19, AH19, AG18, AH18, AG17, AH17/ CBC: AE16, AE15, AD17, AE18, AD16, AE17/ CUS: AB18,

AC18

Low-Power Receiver (LP-RX)

V_IL

V_IH

Low-level input threshold

High-level input threshold

Input hysteresis

500

mV

800

25

V_HYS

Ultralow-Power Receiver (ULP-RX)

V_IL-ULPMLow-level input threshold, ULPM

300

mV

V_IH

High-level input threshold

880

70

High-Speed Receiver (HS-RX)

V_IDTH

V_IDTL

Differential input high threshold

Differential input low threshold

Maximum differential input voltage

Single-ended input low voltage

Single-ended input high voltage

mV

–70

270

V_IDMAX

V_ILHS

–40

70

V_IHHS

460

330

V_CMRXDCCommon-mode voltage

LVDS/CMOS Pin Buffers - CBB: K28, L28, K27, L27/ CBC: P25, P26, N25, N26 / CUS: L24, K24, J23, K23

V_CM

Vos

Vid

t_T

Input common mode voltage range

Receiver Input dc offset

600

–20

70

900

1200

20

mV

mV⁽³⁾

Receiver input differential amplitude

100

200

533

Input transition time (rise time, t_Ror fall time, t_Fevaluated

between 10% and 90% at PAD)

267

ps

LVDS/CMOS Pin Buffers - CBB: AG22, AH22, AG23, AH23, AG24, AH24/ CBC: AE21, AE22, AE23, AE24, AD23, AD24 / CUS: AC19,

AB19, AD20, AC20, AD21, AC21

High-Speed Transceiver (HS-TX)

V_OHHS

|V_OD

V_CMTX

HS output high voltage

360

270

250

mV

|

HS transmit differential voltage

HS transmit static common mode voltage

140

150

200

Low-Power Transceiver (LP-TX)

(1) This global value may be overridden on a per interface basis if another value is explicitly defined for that interface (for example, I²C).

(2) With 100 μA sink / source current at vddsxmin.

(3) Corresponds to peak-to-peak values: minimum = 140 mV_pp; nominal = 200 mV_pp; maximum = 400 mV_pp

.

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Table 3-4. DC Electrical Characteristics (continued)

PARAMETER

Thevenin output low level

MIN

–50

1.1

NOM

MAX

50

UNIT

mV

V

V_OL

V_OH

Thevenin output high level

1.2

1.3

Low-Power Receiver (LP-RX)

V_IL

V_IH

Low-level input threshold

High-level input threshold

Input hysteresis

550

300

mV

880

25

V_HYST

Ultralow-Power Receiver (ULP-RX)

V_IL-ULPSLow-level input threshold, ULPM

V_IHHigh-level input threshold

mV

880

subLVDS/CMOS Pin Buffers - CBB: AA27, AA28, AB27, AB28, AD27, AD28, AC28, AC27/ CBC: AC26, AD26, AA25, Y25, AA26,

AB26, AC25, AB25/ CUS: V22, W22, Y22, AB22, AC23, AC22, W21, V21

Vod

Vocm

t_T

Differential voltage range @ R_L= 100 Ω

100

0.8

150

0.9

200

1

mV

V

Common mode voltage range

Input transition time (Vod rise time, t_Ror Vod fall time, t_F

evaluated between 20% and 80% at PAD)

200

500

ps

Standard LVCMOS Pin Buffers

(4)

V_IH

High-level input voltage (Standard LVCMOS)

Low-level input voltage (Standard LVCMOS)

Hysteresis voltage at an input⁽⁵⁾

0.65 × vdds

- 0.3

vdds + 0.3

V

(4)

V_IL

0.35 × vdds

V_HYS

V_OH

0.1

High-level output voltage, driver enabled,

pullup or pulldown disabled

I_O= I_OHor

I_O= –2 mA

vdds – 0.45

vdds – 0.40

I_O= I_OH< |–2|

mA

V_OL

Low-level output voltage with , driver enabled, I_O= I_OLor

0.45

V

pullup or pulldown disabled

I_O= 2 mA

I_O= I_OL< 2 mA

0.40

10⁽⁶⁾

t_T

Input transition time (rise time, t_Ror fall time, t_Fevaluated

between 10% and 90% at PAD)

0

ns

I_I

Input current with V _I= V_Imax

–1

1

μA

I_OZ

Off-state output current for output in high impedance with driver

only, driver disabled

–20

20

Off-state output current for output in high impedance with

driver/receiver/pullup only, driver disabled, pullup not inhibited

–100

100

Off-state output current for output in high impedance with

driver/receiver/pulldown only, driver disabled, pulldown not

inhibited

I_Z

Total leakage current through the PAD connection of a

driver/receiver combination that may include a pullup or pulldown.

The driver output is disabled and the pullup or pulldown is

inhibited.

– 20

20

μA

LVCMOS Open-Drain Pin Buffers Dedicated to I2C IOs - CBB: K21, J21, AF14, AG14, AF15, AE15, AD26, AE26/ CBC: J25, J24, C2,

C1, AB4, AC4, AD15, W16, A21, C21/ CUS: K20, K21, AC13, AC12, AC15, AC14, Y16, Y15

V_IH

V_IL

V_OL

I_I

High level input voltage

0.7 x vdds

vdds + 0.5

0.3 x vdds

0.2 x vdds

10

V

Low level input voltage

- 0.5

0

Low-level output voltage open-drain at 3-mA sink current

V

Input current at each I/O pin with an input voltage between 0.1 x

vdds to 0.9 x vdds

- 10

μA

C_I

Capacitance for each I/O pin

10

pF

(4) V_IH/V_IL(Standard LVCMOS) parameters are applicable for sys_altclk input clocks.

(5) V_hysis the magnitude of the difference between the positive-going threshold voltage V_T+and the negative-going voltage V_T-

(6) This global value may be overridden on a per interface basis if another value is explicitly defined for that interface (for example, I²C).

.

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Table 3-4. DC Electrical Characteristics (continued)

PARAMETER

MIN

NOM

MAX

250

40

UNIT

T_OF

Output fall time from V_IHminto V_ILmaxwith a

bus capacitance C_Bfrom 10 pF to 400 pF

Fast mode

20 + 0.1C_B

ns

Standard mode

Output fall time with a capacitive load from 10 High-speed mode

pF to 100 pF at 3-mA sink current

10

20

Output fall time with a capacitive load of 400

pF at 3-mA sink current

80

20

Output fall time with a capacitive load of 40

pF (for CBUS compatibility)

LVCMOS Open-Drain Pin Buffers Dedicated in GPIO mode - CBB: AF15, AE15, AF14, AG14, AD26, AE26 / CBC: C2, C1, AB4, AC4,

AD15, W16, A21, C21/ CUS: AC15, AC14, AC13, AC12, Y16, Y15

V_IH

V_IL

High-level input voltage

0.7 x vdds

- 0.5

vdds + 0.5

0.3 x vdds

V

Low-level input voltage

V_OH

V_OL

High-level output voltage at 4-mA sink current

Low-level output voltage at 4-mA sink current

vdds - 0.45

0.45

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3.5 Core Voltage Decoupling

For module performance, decoupling capacitors are required to suppress the switching noise generated

by high frequency and to stabilize the supply voltage. A decoupling capacitor is most effective when it is

close to the device because this minimizes the inductance of the circuit board wiring and interconnects.

Table 3-5 summarizes the power supplies decoupling characteristics.

Table 3-5. Core Voltage Decoupling Characteristics

PARAMETER

MIN

50

TYP

100

1.0

MAX

120

UNIT

nF

μF

nF

(1)

Cvdd_mpu

Cvdd_core⁽¹⁾

50

120

Cvdds_sram

Ccap_vdd_sram_mpu

Ccap_vdd_sram_core

Ccap_vdd_wkup

Cvdds_wkup_bg

Cvdds_dpll_dll

Cvdds_dpll_per

Cvdda_dac

0.7

1.3

1.0

100

Ccap_vdd_d

100

200

Cvdds_mmc1

Cvdds_mmc1a

Cvdds

100

Cvdds_mem

(1) 1 capacitor per 2 to 4 balls

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Figure 3-2 illustrates an example of power supply decoupling.

OMAP Device

vdds_sram

Cvdds_sram

vdds_sram

vdda_dac

cap_vdd_sram_mpu

Ccap_vdd_sram_mpu

Ccap_vdd_sram_core

Cvdda_dac

SRAM_LDO1

Video DAC

vssa_dac

cap_vdd_sram_core

vdds_wkup_bg

SRAM_LDO2

BG

vdds_wkup_bg

Cvdds_wkup_bg

WKUP_LDO

DPLL_MPU

vdds_mmc1

cap_vdd_wkup

MMC IOs

Ccap_vdd_wkup

Cvdds_mmc1

vdds_dpll_dll

vdds_mem

vdds_dpll_dll

vdds_mem

vdds

Cvdds

IOs and Memory

Cvdds_dpll_dll

Cvdds_mem

DPLL_CORE

DPLL5

vdds_dpll_per

Cvdds_dpll_per

DPLL4

Core

Vdd_core

vdd_mpu

Cvdd_mpu

vdd_mpu

vdd_core

VSS

MPU

Cvdd_core

030-004

A. Signals "vdds" and "vdds_mem" are combined with "vdds" on the CBC package.

B. Signals "vdds" and "vdds_mem" are separate on the CBB and CUS packages.

Figure 3-2. Power Supply Decoupling

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3.6 Power-up and Power-down

This section provides the timing requirements for the OMAP3515/03 hardware signals.

3.6.1 Power-up Sequence

The following steps give an example of power-up sequence supported by the OMAP3515/03 device.

1. vdds and vdds_mem are ramped ensuring a level on the IO domain and sys_nrespwron must be low.

At the same time, vdds_sram and vdds_wkup_bg can also be ramped.

2. Once vdds_wkup_bg rail is stabilized, vdd_core can be ramped.

3. Once vdd_core is stabilized, then vdd_mpu can be ramped.

4. vdds_dpll_dll and vdds_dpll_per rails can be ramped at any time during the above sequence.

5. sys_nrespwron can be released as soon as the vdds_pll_dll rail is stabilized, and sys_xtalin and

sys_32k clocks are stabilized.

6. During the whole sequence above, sys_nreswarm is held low by OMAP3515/03. sys_nreswarm is

released after the eFuse check has been performed; that is, after sys_nrespwron is released.

7. The other power supplies can then be turned on upon software request.

shows the power-up sequence.

Notes:

•

If an external square clock is provided, it could be started after sys_nrespwron release provided it is

clean: no glitch, stable frequency, and duty cycle.

•

Higher voltage can be used. OPP voltage values may change following the silicon characterization

result.

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1.8 V

vdds_wkup_bg

1.8 V

vdds_mem,vdds,

vdds_sram

ldo3 (internal)

(2)

vdd_core

vdd_mpu

(2)

1.8 V

vdds_dpll_dll

vdds_dpll_per

1.8 V

sys_32k

sys_nrespwron

sys_xtalin

EFUSE.RSTPWRON(internal)

sys_nreswarm

vdds_mmc1,vdds_mmc1a,

vdda_dac⁽¹⁾, vpp

030-005

Figure 3-3. Power-up Sequence

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3.6.2 Power-down Sequence

The following steps give an example of the power-down sequence supported by the OMAP3515/03

device.

1. Reset OMAP3515/03 device.

2. Stop all signals driven to OMAP3515/03 balls.

3. Option 1: Power down all domains simutaneously.

4. Option 2: If all domains cannot be powered down simultaneously, follow the below sequence:

(a) Power off all complex I/O domains (vdds_mmc1, vdds_mmc1a, vdda_dac)

(b) Power off all core domains (vdd_core, vdd_mpu )

(c) Power off all PLL domains (vdds_dpll_dll, vdds_dpll_per)

(d) Power off all SRAM LDOs (vdds_sram)

(e) Power off all reference domains (vdds_wkup_bg)

(f) Power off all standard I/O domains (vdds, vdds_mem)

The OMAP3515/03 device proceeds with the power-down sequence shown in Figure 3-4 .

Note: Another possible power-down sequence:

•

vdd_mpu shuts down before vdd_core.

vdds_sram, vdds_wkup_bg, vdds, and vdds_mem shut down simultaneously.

vdds_dpll_dll and vdds_dpll_per shut down anytime between all complex IO domains shut down and

vdds_sram shuts down.

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sys_nrespwron

vdds_mmc1,

vdda_dac

vdds_wkup_bg

vdd_mpu

vdd_core

vdds_mem, vdds,

vdds_sram

vdds_dpll_dll,

vdds_dpll_per

sys_32kin

sys.clk

030-006

Figure 3-4. Power-down Sequence

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4 CLOCK SPECIFICATIONS

The OMAP3515/03 device has three external input clocks, a low frequency (sys_32k), a high frequency

(sys_xtalin), and an optional (sys_altclk). The OMAP3515/03 device has two configurable output clocks,

sys_clkout1 and sys_clkout2.

Figure 4-1 shows the interface to the external clock sources and clock outputs.

OMAP

sys_32k

Power IC

Alternate Clock Source Selectable (54, 48 MHz or other [up

to 59 MHz])

sys_altclk

To Peripherals (From OSC_CLK: 12, 13,16.8, 19.2, 26, or

38.4 MHz)

sys_clkout1

sys_clkout2

sys_xtalout

To Peripherals (From OSC_CLK: 12,13, 16.8, 19.2, 26, or

38.4 MHz, core_clk [DPLL, up to 332 MHz], DPLL-96 MHz

or DPLL-54 MHz outputs with a divider of 1, 2, 4, 8, or 16)

To Quartz (Oscillator output) or Unconnected

sys_xtalin

sys_clkreq

sys_xtalout

sys_xtalin

To Quartz (Oscillator input) or Square Clock

Clock Request. To Square Clock Source or from Peripherals

sys_xtalout

Unconnected

Oscillator

is Bypassed

Oscillator

is Used

sys_xtalin

Square

Clock

Source

sys_clkreq

GPin

030-007

Figure 4-1. Clock Interface

The OMAP3515/03 device operation requires the following three input clocks:

•

The 32-kHz frequency is used for low frequency operation. It supplies the wake-up domain for

operation in lowest power mode (off mode). This clock is provided through the sys_32k pin.

The system alternative clock can be used (through the sys_altclk pin) to provide alternative 48 or 54

MHz or other clock source (up to 59 MHz).

The system clock input (12, 13, 16.8, 19.2, 26, or 38.4 MHz) is used to generate the main source clock

of the OMAP3515/03 device. It supplies the DPLLs as well as several OMAP modules. The system

clock input can be connected to either:

–

A crystal oscillator clock managed by sys_xtalin and sys_xtalout. In this case, the sys_clkreq is

used as an input (GPIN).

–

A CMOS digital clock through the sys_xtalin pin. In this case, the sys_clkreq is used as an output to

request the external system clock.

The OMAP3515/03 outputs externally two clocks:

•

sys_clkout1 can output the oscillator clock (12, 13, 16.8, 19.2, 26, or 38.4 MHz) at any time. It can be

controlled by software or externally using sys_clkreq control. When the device is in the off state, the

sys_clkreq can be asserted to enable the oscillator and activate the sys_clkout1 without waking up the

device. The off state polarity of sys_clkout1 is programmable.

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•

sys_clkout2 can output the oscillator clock (12, 13, 16.8, 19.2, 26, or 38.4 MHz), core_clk (core DPLL

output), 96 MHz or 54 MHz. It can be divided by 2, 4, 8, or 16 and its off state polarity is

programmable. This output is active only when the core power domain is active.

For more information on the OMAP3515/03 Applications Processor clocking structure, see the Power,

Reset, and Clock management (PRCM) chapter of the OMAP35x Applications Processor TRM (literature

number SPRUFA5).

4.1 Input Clock Specifications

The clock system accepts three input clock sources:

•

32-kHz digital CMOS clock

Crystal oscillator clock or CMOS digital clock (12, 13, 16.8, 19.2, 26, or 38.4 MHz)

Alternate clock (48 or 54 MHz, or other up to 59 MHz)

4.1.1 Clock Source Requirements

Table 4-1 illustrates the requirements to supply a clock to the OMAP3515/03 device.

Table 4-1. Clock Source Requirements

PAD

CLOCK FREQUENCY

STABILITY

± 25 ppm

± 50 ppm

DUTY CYCLE

na

JITTER

na

TRANSITION

na

sys_xtalout

sys_xtalin

12, 13, 16.8, or 19.2 MHz

Crystal

12, 13, 16.8, 19.2, 26, or 38.4 MHz Square

48,54 or up to 59 MHz

45% to 55%

40% to 60%

< 1%

< 3.6 ns

< 5 ns

sys_altclk

4.1.2 External Crystal Description

To supply a 12-, 13-, 16.8-, or 19.2-MHz clock to the OMAP3515/03, an external crystal can be connected

to the sys_xtalin and sys_xtalout pins. Figure 4-2 describes the crystal implementation.

OMAP Device

sys_xtalin

sys_xtalout

Optional R_bias

Optional R_d

C_f2

C_f1

Crystal

030-008

Figure 4-2. Crystal Implementation(1) (2) (3) (4)

(1) On the PCB, the oscillator components (crystal, foot capacitors, optional R_biasand R_d) must be located close to the package. All these

components must be routed first with the lowest possible number of board vias.

(2) An optional resistor R_dcan be added in series with the crystal to debug or filter the harmonics; a footprint must be reserved on the PCB

for use with 10-MHz crystals and feature low-drive levels.

(3) A 120-kΩ internal bias resistor R_biasis used. The feedback resistor R_biasprovides negative feedback to the oscillator to put it in the

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linear operating region; thus oscillation begins when power is applied.

(4) C_f1and C_f2represent the total capacitance of the PCB and components excluding the power IC and crystal. Their values in fact depend

on the crystal datasheet. In the datasheet of the crystal, the frequency is specified at a specific load capacitor value which is the

equivalent capacitor of the two capacitors C_f1and C_f2connected to sys_xtalin and sys_xtalout. The frequency of the oscillations

depends on the value of the capacitors (10 pF corresponds to a load capacitor of 5 pF for the crystal).

The crystal must be in the fundamental mode of operation and parallel resonant. Table 4-2 summarizes

the required electrical constraints.

Table 4-2. Crystal Electrical Characteristics

NAME

DESCRIPTION

Parallel resonance crystal frequency⁽¹⁾

Load capacitance for crystal parallel resonance

Crystal ESR (12 and 13 MHz)⁽¹⁾

MIN

TYP

MAX

UNIT

MHz

pF

f_p

12, 13, 16.8, or 19.2

C_L

5

20

80

ESR12&13

Ω

ESR16.8&19.2 Crystal ESR (16.8 and 19.2 MHz)⁽²⁾

50

Ω

C_o

Crystal shunt capacitance

Crystal motional inductance for f_p= 12 MHz

Crystal motional capacitance

Crystal drive level

1

5

7

pF

L_m

35

mH

fF

C_m

DL

R_bias

100

0.5

300

mW

kΩ

Internal bias resistor

30

120

(1) Measured with the load capacitance specified by the crystal manufacturer. This load is defined by the foot capacitances tied in series. If

C_L= 20 pF, then both foot capacitors will be C_f1= C_f2= 40 pF. Parasitic capacitance from package and board must also be taken in

account.

(2) Measured with the load capacitance specified by the crystal manufacturer. This load is defined by the foot capacitances tied in series. If

C_L= 20 pF, then both foot capacitors will be C_f1= C_f2= 40 pF. Parasitic capacitance from package and board must also be taken in

account.

2

C

0

ESR=R 1+

m

C

L

When selecting a crystal, the system design must take into account the temperature and aging

characteristics of a crystal versus the user environment and expected lifetime of the system. Table 4-3

details the switching characteristics of the oscillator and the input requirements of the 12-, 13-, 16.8-, or

19.2-MHz input clock.

Table 4-3. Base Oscillator Switching Characteristics

NAME

f_p

t_sX

DESCRIPTION

MIN

TYP

MAX

UNIT

MHz

ms

Oscillation frequency

Start-up time^{(1) (2)}

12, 13, 16.8, or 19.2

8

(1) Start-up time defined as time interval between oscillator control signal release and sys_xtalin amplitude at 50% of its final value (vdd and

vdds supplies ramped and stable). The start-up time can be performed in function of the crystal characteristics. 8-ms minimum only

when using the internal oscillator; it is programmable after reset for wake-up. At power-on reset, the time is adjustable using the pin

itself. The reset must be released when the oscillator or clock source is stable. Before the processor boots up and the oscillator is set to

bypass mode, there is a start-up time when the internal oscillator is in application mode and receives a square wave. The start-up time

in this case is about 100 μs.

(2) For f_p= 12 or 13 MHz: C_L= 13.5 pF and L_m= 35 mH

For f_p= 16.8 or 19.2 MHz: C_L= 9 pF and L_m= 15 mH

4.1.3 Clock Squarer Input Description

A 1.8-V CMOS clock squarer is another source that can supply a 12-, 13-, 16.8-, 19.2-, 26-, or 38.4-MHz

clock to the OMAP3515/03. An analog clock squarer function converts a low-amplitude sinusoidal clock

into a low-jitter digital signal. It can be connected to input pin sys_xtalin (sys_xtalout unconnected).

Figure 4-3 illustrates the effective connections.

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OMAP Device

Oscillator

In Bypass Mode

sys_clkreq

sys_xtalin

sys_xtalout

Clock Squarer Source

030-010

Figure 4-3. Clock Squarer Source Connection

To connect a digital clock source, the oscillator is configured in bypass mode. The sys_clkreq pin is an

OMAP3515/03 output which can be used to switch the clock source on or off.

1. Pin sys_xtalout is not used in this mode. It must be left unconnected.

2. Once the system is powered up, the clock squarer source or crystal oscillator source can be applied;

however, this affects the performance. The input source must be configured after power up to attain

the desired system requirements.

Table 4-4 summarizes the electrical constraints required by the clock squarer used in the fundamental

mode of operation.

Note: There is an internal pulldown resistor of 5k Ω (max.) on sys_xtalin when the oscillator is disabled.

Table 4-4. Base Oscillator Electrical Characteristics (in Bypass Mode)

NAME

DESCRIPTION

MIN

TYP

MAX

UNIT

MHz

ms

f

Frequency⁽¹⁾

Start-up time

12, 13, 16.8, 19.2, 26, or 38.4

(2)

t_sX

I_DDQ

Current consumption on VDDS when sys_xtalin = 0 and in power-

down mode

1

μA

(1) Measured with the load capacitance specified by the manufacturer. Parasitic capacitance from package and board must also be taken in

account.

(2) Before the processor boots up and the oscillator is set to bypass mode, there is a start-up time when the internal oscillator is in

application mode and receives a square wave. The start-up time in this case is about 100 μs.

Table 4-5 details the input requirements of the 12-, 13-, 16.8-, 19.2-, 26-, or 38.4-MHz input clock.

Table 4-5. 12-, 13-, 16.8-, 19.2-, 26-, or 38.4-MHz Input Clock Squarer Timing Requirements

NAME

OCS0

DESCRIPTION

MIN

TYP

MAX

UNIT

MHz

ns

1 / t_c(xtalin)

t_w(xtalin)

t_J(xtalin)

Frequency, sys_xtalin

12, 13, 16.8, 19.2, 26, or 38.4

OCS1

OCS2

OCS3

OCS4

OCS5

Pulse duration, sys_xtalin low or high

Peak-to-peak jitter⁽¹⁾, sys_xtalin

Rise time, sys_xtalin

0.45 * t_c(xtalin)

–1%

0.55 * t_c(xtalin)

1%

3.6

±25

t_R(xtalin)

t_F(xtalin)

t_J(xtalin)

ns

Fall time, sys_xtalin

Frequency stability, sys_xtalin

ppm

(1) Peak-to-peak jitter is defined as the difference between the maximum and the minimum output periods on a statistical population of 300

period samples. The sinusoidal noise is added on top of the vdds supply voltage.

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OCS0

OCS1

sys.xtalin

030-011

Figure 4-4. Crystal Oscillator in Bypass Mode

4.1.4 External 32-kHz CMOS Input Clock

A 32.768-kHz clock signal (often abbreviated to 32-kHz) can be supplied by an external 1.8-V CMOS

signal on pin sys_32k.

Table 4-6 summarizes the electrical constraints imposed to the clock source.

Table 4-6. 32-kHz Input Clock Source Electrical Characteristics

NAME

DESCRIPTION

Frequency

MIN

TYP

MAX

UNIT

kHz

pF

f

32.768

C_I

R_I

Input capacitance

Input resistance

0.44

0.25

10⁶

GΩ

Table 4-7 details the input requirements of the 32-kHz input clock.

Table 4-7. 32-kHz Input Clock Source Timing Requirements⁽¹⁾

NAME

DESCRIPTION

Frequency, sys_32k

MIN

TYP

MAX

UNIT

CK0

CK3

CK4

CK5

1 / t_c(32k)

t_R(32k)

t_F(32k)

32.768

kHz

ns

Rise time, sys_32k

20

Fall time, sys_32k

ns

t_J(32k)

Frequency stability, sys_32k

±200

ppm

(1) See Table 3-4, Electrical Characteristics, Standard LVCMOS IOs part for sys_32k V_IH/V_ILparameters.

CK0

CK1

sys_32k

030-012

Figure 4-5. 32-kHz CMOS Clock

4.1.5 External sys_altclk CMOS Input Clock

A 48-, 54-, or up to 59- MHz clock signal can be supplied by an external 1.8-V CMOS signal on pin

sys_altclk.

Table 4-8 summarizes the electrical constraints imposed by the clock source.

Table 4-8. 48-, 54-, or up to 59- MHz Input Clock Source Electrical Characteristics

NAME

DESCRIPTION

Frequency , sys_altclk

Input capacitance

MIN

TYP

48-, 54-, or up to 59- MHz

0.74

MAX

UNIT

MHz

pF

f

C_I

R_I

Input resistance

0.25

10⁶

GΩ

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Table 4-9 details the input requirements of the input clock.

Table 4-9. 48- or 54-MHz Input Clock Source Timing Requirements^{(1) (2)}

NAME

ALT0

DESCRIPTION

MIN

TYP

MAX

UNIT

1 / t_c(altclk)

t_w(altclk)

Frequency, sys_altclk

48-, 54-, or up to 59- MHz

MHz

ns

ALT1

Pulse duration, sys_altclk low or

high

0.40 * t_c(altclk)

0.60 * t_c(altclk)

ALT2

ALT3

ALT4

ALT5

t_J(altclk)

t_R(altclk)

t_F(altclk)

t_J(altclk)

Peak-to-peak jitter⁽¹⁾, sys_altclk

–1%

1%

10

Rise time, sys_altclk

ns

Fall time, sys_altclk

10

Frequency stability, sys_altclk

± 50

ppm

(1) Peak-to-peak jitter is defined as the difference between the maximum and the minimum output periods on a statistical population of 300

period samples. The sinusoidal noise is added on top of the vdds supply voltage.

(2) See Table 3-4, Electrical Characteristics, for sys_altclk V_IH/V_ILparameters.

ALT0

ALT1

sys_altclk

030-013

Figure 4-6. Alternate CMOS Clock

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4.2 Output Clock Specifications

Two output clocks (pin sys_clkout1 and pin sys_clkout2) are available:

•

sys_clkout1 can output the oscillator clock (12, 13, 16.8, 19.2, 26, or 38.4 MHz) at any time. It can be

controlled by software or externally using sys_clkreq control. When the device is in the off state, the

sys_clkreq can be asserted to enable the oscillator and activate the sys_clkout1 without waking up the

device. The off state polarity of sys_clkout1 is programmable.

•

sys_clkout2 can output sys_clk (12, 13, 16.8, 19.2, 26, or 38.4 MHz), CORE_CLK (core DPLL output,

332 MHz maximum), APLL-96 MHz, or APLL-54 MHz. It can be divided by 2, 4, 8, or 16 and its off

state polarity is programmable. This output is active only when the core domain is active.

Table 4-10 summarizes the sys_clkout1 output clock electrical characteristics.

Table 4-10. sys_clkout1 Output Clock Electrical Characteristics

NAME

DESCRIPTION

MIN

TYP

MAX

UNIT

MHz

pF

f

Frequency

Load capacitance⁽¹⁾

12, 13, 16.8, 19.2, 26, or 38.4

C_I

f(max) = 38.4 MHz

f(max) = 26 MHz

37

50

(1) The load capacitance is adapted to a frequency.

Table 4-11 details the sys_clkout1 output clock timing characteristics.

Table 4-11. sys_clkout1 Output Clock Switching Characteristics

NAME

DESCRIPTION

Frequency

MIN

TYP

12, 13, 16.8, 19.2, 26, or 38.4

0.60 *

t_c(CLKOUT1)

5.5

MAX

UNIT

MHz

ns

f

1 / CO0

CO1

t_w(CLKOUT1)

Pulse duration, sys_clkout1 low or high

0.40 *

t_c(CLKOUT1)

CO2

CO3

t_R(CLKOUT1)

t_F(CLKOUT1)

Rise time, sys_clkout1⁽¹⁾

Fall time, sys_clkout1⁽¹⁾

ns

5.5

(1) With a load capacitance of 50 pF.

CO0

CO1

sys_clkout

030-014

Figure 4-7. sys_clkout1 System Output Clock

Table 4-12 summarizes the sys_clkout2 output clock electrical characteristics.

Table 4-12. sys_clkout2 Output Clock Electrical Characteristics

NAME

DESCRIPTION

Frequency, sys_clkout2

Load capacitance⁽¹⁾

MIN

TYP

MAX

322

12

UNIT

MHz

pF

f

C_L

f(max) = 166 MHz

2

8

(1) The load capacitance is adapted to a frequency.

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Table 4-13 details the sys_clkout2 output clock timing characteristics.

Table 4-13. sys_clkout2 Output Clock Switching Characteristics

NAME

DESCRIPTION

Frequency

MIN

TYP

MAX

UNIT

MHz

ns

f

1 / CO0

322

CO1

CO2

CO3

t_w(CLKOUT2)

t_R(CLKOUT2)

t_F(CLKOUT2)

Pulse duration, sys_clkout2 low or high

Rise time, sys_clkout2⁽¹⁾

Fall time, sys_clkout2⁽¹⁾

0.40 * t_c(CLKOUT2)

0.60 * t_c(CLKOUT2)

3.7

4.3

ns

(1) With a load capacitance of 12 pF.

CO0

CO1

sys_clkout

030-015

Figure 4-8. sys_clkout2 System Output Clock

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4.3 DPLL and DLL Specifications

The OMAP3515/03 integrates seven DPLLs and a DLL. The PRM and CM drive five of them, while the

sixth ( not supported) and the seventh ( not supported) are controlled by the display subsystem.

The five main DPLLs are:

•

DPLL1 (MPU)

DPLL2 ( not supported on OMAP3515/03 devices)

DPLL3 (Core)

DPLL4 (Peripherals)

DPLL5 (Second Peripherals DPLL)

Figure 4-9 illustrates the DLL and DPLL implementation.

OMAP

vdds_dpll_dll

Power Rail

DPLL1

DPLL2

DPLL3

DPLL4

DLL

DPLL5

vdds_dpll_per

030-016

(1) DPLL2 is not supported on OMAP3515/03 devices.

Figure 4-9. DPLL and DLL Implementation

For more information on the OMAP3530/25 Applications Processor DPLLs and clocking structure, see the

Power, Reset, and Clock management (PRCM) chapter of the OMAP35x Applications Processor TRM

(literature number SPRUFA5).

4.3.1 Digital Phase-Locked Loop (DPLL)

The DPLL provides all interface clocks and some functional clocks (such as the processor clocks) of the

OMAP3515/03 device.

DPLL1 and DPLL2 get an always-on clock used to produce the synthesized clock. They get a high-speed

bypass clock used to switch the DPLL output clock on this high-speed clock during bypass mode.

The high-speed bypass clock is an L3 divided clock (programmable by 1 or 2) that saves DPLL processor

power consumption when the processor does not need to run faster than the L3 clock speed, or optimizes

performance during frequency scaling.

Each DPLL synthesized frequency is set by programming M (multiplier) and N (divider) factors. In addition,

all DPLL outputs can be controlled by an independent divider (M2 to M6).

The clock generating DPLLs of the OMAP3515/03 device have following features:

•

Independent power domain per DPLL

Controlled by clock-manager (CM)

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•

Fed with always-on system clock with independent gating control per DPLL

Analog part supplied through dedicated power supply (1.8 V) and an embedded LDO to get rid of 1-

MHz noise

•

Up to five independent output dividers for simultaneous generation of multiple clock frequencies

4.3.1.1 DPLL1 (MPU)

DPLL1 is located in the MPU subsystem and supplies all clocks of the subsystem. All MPU subsystem

clocks are internally generated in the subsystem. When the core domain is on, it can use the DPLL3

(CORE DPLL) output as a high-frequency bypass input clock.

4.3.1.2 DPLL3 (CORE)

DPLL3 supplies all interface clocks and also a few module functional clocks. It can be also source of the

emulation trace clock. It is located in the core domain area. All interface clocks and a few module

functional clocks are generated in the CM. When the core domain is on, it can be used as a bypass input

to DPLL1 and DPLL2.

4.3.1.3 DPLL4 (Peripherals)

DPLL4 generates clocks for the peripherals. It supplies five clock sources: 96-MHz functional clocks to

subsystems and peripherals, 54 MHz to TV DAC, display functional clock, camera sensor clock, and

emulation trace clock. It is located in the core domain area. All interface clocks and few module functional

clocks are generated in the CM. Its outputs to the DSS, PER, and EMU domains are propagated with

always-on clock trees.

4.3.1.4 DPLL5 (Second peripherals DPLL)

DPLL5 supplies the 120-MHz functional clock to the CM.

4.3.2 Delay-Locked Loops (DLL)

The SDRC includes analog-controlled delay technology for interfacing high-speed mobile DDR memory

components. For more information, see the SDRC-GPMC chapter of the OMAP35x Technical Reference

Manual (TRM) [literature number SPRUF98 ]. A DLL is a calibration module used on dynamic track of

voltage and temperature variations, as well as to compensate the silicon process dispersion.

The SDRC DLL has four modes of operation:

1. APPLICATION MODE 0: used to generate 72° delay

2. APPLICATION MODE 1: used to generate 90° delay

3. MODEMAXDELAY: used for low frequency operation where we do not have the requirement of

accurate 72° or 90° phase shift

4. IDLE MODE: a low-power state that allows the DLL to gain lock quickly on exit from this mode

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4.3.3 DPLLs and DLL Characteristics

Several specifications characterize the seven DPLLs.

Table 4-14 summarizes the DPLL characteristics and assumes testing over recommended operating

conditions.

Table 4-14. DPLL Characteristics

NAME

vdds_dpll_per

vdds_dpll_dll

T_J

PARAMETER

MIN

1.71

–40

TYP

1.8

25

MAX

1.89

105

UNIT

V

COMMENTS⁽¹⁾

At ball level (+5%, +10%)

V

Junction temperature

°C

Will not unlock after lock over this range for

slow temperature drifts

f_input

Input reference frequency⁽²⁾

Internal reference frequency

0.75

7.5

25

65

2.1

MHz

FINP

f_internal

FREQSEL3 = 0; FINT = FINP/(N+1)

FREQSEL3 = 1; FINT = FINP/(N+1)

21

f_output

CLKOUT output frequency

900

1800

f_output*2

CLKOUTx2 output

frequency

50

t_lock

Frequency lock time⁽³⁾

71.4

37.1

166.7

46.7

4.8

200

104

μs

150 FINT cycles; FREQSEL3 = 0

780 FINT cycles; FREQSEL3 = 1

350 FINT cycles; FREQSEL3 = 0

980 FINT cycles; FREQSEL3 = 1

10 FINT cycles

p_lock

Phase lock time

466.7

130.7

13.3

t_relock

Relock time – frequency

lock⁽⁴⁾

Lowcurrstby = 0; FREQSEL3 = 0

100 FINT cycles

4.8

19

13.3

53.3

200

μs

Lowcurrstby = 0; FREQSEL3 = 1

40 FINT cycles

Lowcurrstby = 1; FREQSEL3 = 0

400 FINT cycles

19

Lowcurrstby = 1; FREQSEL3 = 1

150 FINT cycles

p_relock

Relock time – Phase lock⁽⁴⁾

71.4

11.9

95.2

26.7

Lowcurrstby = 0; FREQSEL3 = 0

250 FINT cycles

33.3

266.7

74.7

Lowcurrstby = 0; FREQSEL3 = 1

200 FINT cycles

Lowcurrstby = 1; FREQSEL3 = 0

560 FINT cycles

Lowcurrstby = 1; FREQSEL3 = 1

(1) f_reqselneeds to be programmed accordingly to reference clock and DPLL divider (register setting), Lowcurrstdby depends on the targeted

DPLL power state (dynamic).

Lowcurrstdby = 0 then DPLL is in normal mode

Lowcurrstdby = 1 then DPLL is in low-power mode

(2) Input frequencies below 0.75 MHz are possible with performance penalty.

(3) Maximum frequency for nominal conditions. Speed binning possible above fmax.

(4) Relock time assumes typical operating conditions, 4°C maximum temperature drift (see the Functional Specification for more detailed

information).

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show s the DPLL1 clock frequency ranges.

Note: The DPLL1 clock frequency ranges depend on the V_DD1(vdd_mpu ) operating point.

Table 4-15. DPLL1 Clock Frequency Ranges

Clock Signal

Description

Max

720

600

550

500

250

125

Unit

MHz

OPP6⁽¹⁾

OPP5

OPP4

ARM_CLK

DPLL1 output clock.

OPP3

OPP2

OPP1⁽²⁾

(1) OPP6 frequency range is only supported on high-speed grade OMAP3530/25 devices.

(2) Cannot boot in OPP1. If OPP1 is desired, boot in higher OPP then switch to OPP1.

Table 4-16 through Table 4-18 show the DPLL3 clock frequency ranges.

Note: The DPLL3 clock frequency ranges depend on the VDD2 (vdd_core) operating point and the L3

clock speed configuration.

Table 4-16. DPLL3 Clock Frequency Ranges, VDD2 OPP3

Config 1

Config 2

(166 MHz)

(133 MHz)

Unit

Clock Signal

CM: CORE_CLK

Description

Min

Max

Min

Max

Output of clock manager (CM), generated

directly from DPLL3.

-

332

-

266

MHz

Output of clock manager (CM), generated

using DPLL3.

CM: L3_ICLK

CM: L4_ICLK

166

83

133

Output of clock manager (CM), generated

using CM L3_ICLK and divider.

66.5

SGX

SGX input clock, taken from CM CORE_CLK.

SDRC input clock, taken from CM L3_ICLK.

GPMC input clock, taken from CM L3_ICLK.

-

110.67

166

-

88.67

133

MHz

SDRC

GPMC

83

66.5

Table 4-17. DPLL3 Clock Frequency Ranges, VDD2 OPP2

Config 1

(83 MHz)

Config 2

(100 MHz)

Unit

Clock Signal

Description

Min

Max

Min

Max

Output of clock manager (CM), generated

directly from DPLL3.

CM: CORE_CLK

CM: L3_ICLK

CM: L4_ICLK

-

166

-

200

MHz

Output of clock manager (CM), generated using

DPLL3.

-

83

-

100

50

Output of clock manager (CM), generated using

CM L3_ICLK and divider.

41.5

SGX

SGX input clock, taken from CM CORE_CLK.

SDRC input clock, taken from CM L3_ICLK.

GPMC input clock, taken from CM L3_ICLK.

-

55.53

83

-

66.67

100

50

MHz

SDRC

GPMC

41.5

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Table 4-18. DPLL3 Clock Frequency Ranges, VDD2 OPP1⁽¹⁾

Config 1

(40 MHz)

Config 2

(50 MHz)

Unit

Clock Signal

Description

Min

Max

Min

Max

Output of clock manager (CM), generated directly

from DPLL3.

CM: CORE_CLK

CM: L3_ICLK

CM: L4_ICLK

-

83

-

100

MHz

Output of clock manager (CM), generated using

DPLL3.

41.5

50

25

Output of clock manager (CM), generated using CM

L3_ICLK and divider.

20.75

SGX

SGX input clock, taken from CM CORE_CLK.

SDRC input clock, taken from CM L3_ICLK.

GPMC input clock, taken from CM L3_ICLK.

-

N/A

41.5

-

N/A

50

MHz

SDRC

GPMC

25

(1) Cannot boot in OPP1. If OPP1 is desired, boot in higher OPP then switch to OPP1.

Table 4-19 summarizes the DLL characteristics.

Table 4-19. DLL Characteristics

PARAMETER

Supply voltage vdds_dpll_dll

Junction operating temperature

Input clock frequency

MIN

1.71

–40

66

NOM

1.8

MAX

1.89

105

133

166

15

UNIT

V

COMMENTS

25

°C

120

MHz

APPLICATION MODE 0

APPLICATION MODE 1

83

Input load⁽¹⁾

Lock time⁽²⁾

fF

Clocks

ns

500

372

2

Relock time

IDLE to MODEMAXDELAY

(Mode transitions through idle mode)

150

1

Clocks

μs

IDLE to APPLICATION MODE 1 or 0

IDLE to APPLICATION MODE @133 MHz

IDLE to APPLICATION MODE @166 MHz

1

1.5

μs

(1) This parameter is design goal and is not tested on silicon.

(2) Lock signal would go high from power down within 500 clocks. Lock signal switches to low state when the input clock is switched off

after 3 μs.

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4.3.4 DPLL and DLL Noise Isolation

The DPLL and DLL require dedicated power supply pins to isolate the core analog circuit from the

switching noise generated by the core logic that can cause jitter on the clock output signal. Guard rings

are added to the cell to isolate it from substrate noise injection.

The vdd supplies are the most sensitive to noise; decoupling capacitance is recommended below the

supply rails. The maximum input noise level allowed is 30 mV_PPfor frequencies below 1 MHz.

Figure 4-10 illustrates an example of a noise filter.

OMAP Device

Noise Filter

vdds_dpll_dll

C

DPLL_MPU

DPLL_CORE

DPLL2

DLL

Noise Filter

vdds_dpll_per

C

DPLL5

DPLL4

030-017

(1) DPLL2 is not supported on OMAP3515/03 devices.

Figure 4-10. DPLL and DLL Noise Filter

Table 4-20 specifies the noise filter requirements.

Table 4-20. DPLL and DLL Noise Filter Requirements

NAME

MIN

TYP

MAX

UNIT

Filtering capacitor

100

nF

(1) The capacitors must be inserted between power and ground as close as possible.

(2) This circuit is provided only as an example.

(3) The filter must be located as close as possible to the device.

(4) No filtering required if noise is below 10 mV_PP

.

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5 VIDEO DAC SPECIFICATIONS

A dual-display interface equips the OMAP3515/03 processor. This display subsystem provides the

necessary control signals to interface the memory frame buffer directly to the external displays (TV-set).

Two (one per channel) 10-bit current steering DACs are inserted between the DSS and the TV set to

generate the video analog signal. One of the video DACs also includes TV detection and power-down

mode. Figure 5-1 illustrates the OMAP3515/03 DAC architecture. For more information, see the DSS

chapter of the OMAP35x Technical Reference Manual (TRM) [literature number SPRUF98].

OMAP Device

TV DCT

tv_vfb1

DIN1[9:0]

TVOUT

BUFFER

Video DAC 1

tv_out1

DSS

tv_vfb2

DIN2[9:0]

TVOUT

BUFFER

Video DAC 2

tv_out2

V_ref

vdda_dac

vssa_dac

tv_vref

CBG

030-018

Figure 5-1. Video DAC Architecture

The following paragraphs detail the 10-bit DAC interface pinout, static and dynamic specifications, and

noise requirements. The operating conditions and absolute maximum ratings are detailed in Table 5-2 and

Table 5-4.

5.1 Interface Description

Table 5-1 summarizes the external pins of the video DAC.

Table 5-1. External Pins of 10-bit Video DAC

PIN NAME

I/O

DESCRIPTION

tv_out1

O

TV analog output composite

DAC1 video output. An external resistor is connected between this

node and tv_vfb1. The nominal value of ROUT1 is 1650 Ω. Finally,

note that this is the output node that drives the load (75 Ω).

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Table 5-1. External Pins of 10-bit Video DAC (continued)

PIN NAME

I/O

DESCRIPTION

tv_out2

O

TV analog output S-VIDEO

DAC2 video output. An external resistor is connected between this

node and tv_vfb2. The nominal value of ROUT2 is 1650 Ω. Finally,

note that this is the output node that drives the load (75 Ω).

tv_vref

tv_vfb1

tv_vfb2

I

Reference output voltage from internal

bandgap

A decoupling capacitor (CBG) needs to be connected for optimum

performance.

O

Amplifier feedback node

Amplifier feedback node. An external resistor is connected between

this node and tv_out1. The nominal value of ROUT1 is 1650 Ω (1%).

Amplifier feedback node

Amplifier feedback node. An external resistor is connected between

this node and tv_out2. The nominal value of ROUT2 is 1650 Ω (1%).

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5.2 Electrical Specifications Over Recommended Operating Conditions

(T_MINto T_MAX, vdda_dac = 1.8 V, R_OUT1/2= 1650 Ω, R_LOAD= 75 Ω, unless otherwise noted)

Table 5-2. DAC – Static Electrical Specification

PARAMETER

Resolution

DC ACCURACY

CONDITIONS/ASSUMPTIONS

MIN

TYP

MAX

UNIT

R

10

Bits

INL⁽¹⁾

DNL⁽²⁾

Integral nonlinearity

–1

1

LSB

Differential nonlinearity

ANALOG OUTPUT

-

Full-scale output voltage

R_LOAD= 75 Ω

0,7

0.88

50

1

V

mV

-

Output offset voltage

Output offset voltage drift

Gain error

-

20

mV/°C

% FS

Ω

-

–17

19

R_VOUT

Output impedance

67.5

75

82.5

REFERENCE

V_REF

-

Reference voltage range

Reference noise density

0.525

3700

0.55

129

0.575

4200

V

100-kHz reference noise

bandwidth

R_SET

P_SRR

Full-scale current adjust resistor

Reference PSRR⁽³⁾(Up to 6 MHz)

4000

40

Ω

dB

POWER CONSUMPTION

I_vdda-up

Analog Supply Current⁽⁴⁾

-

2 channels, no load

2 channels

8

mA

Analog supply driving a 75-Ω load

50

(RMS)

I_vdda-up(peak) Peak analog supply current:

Lasts less than 1 ns

60

2

mA

I_vdd-up

Digital supply current⁽⁵⁾

Measured at f_CLK= 54 MHz, f_OUT

= 2 MHz sine wave, vdd = 1.3 V

I_{vdd-up (peak)}

I_vdda-down

I_vdd-down

Peak digital supply current⁽⁶⁾

Analog power at power-down

Digital power at power-down

Lasts less than 1 ns

T = 30°C, vdda = 1.8 V

T = 30°C, vdd = 1.3 V

2.5

1.5

1

mA

(1) The INL is measured at the output of the DAC (accessible at an external pin during bypass mode).

(2) The DNL is measured at the output of the DAC (accessible at an external pin during bypass mode).

(3) Assuming a capacitor of 0.1 μF at the tv_ref node.

(4) The analog supply current I_vddais directly proportional to the full-scale output current IFS and is insensitive to f_CLK

(5) The digital supply current I_VDDis dependent on the digital input waveform, the DAC update rate f_CLK, and the digital supply VDD.

(6) The peak digital supply current occurs at full-scale transition for duration less than 1 ns.

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(T_MINto T_MAX, vdda_dac = 1.8 V, R_OUT1/2= 1650 Ω, R_LOAD= 75 Ω, unless otherwise noted)

Table 5-3. Video DAC – Dynamic Electrical Specification

PARAMETER

Output update rate

Clock jitter

CONDITIONS/ASSUMPTIONS

MIN

TYP

MAX

UNIT

MHz

ps

(1)

f_CLK

Equal to input clock frequency

54

rms clock jitter required in order to assure 10-

bit accuracy

40

Attenuation at 5.1 MHz

Attenuation at 54 MHz⁽¹⁾

Output settling time

Corner frequency for signal

Image frequency

0.1

25

0.5

30

85

1.5

33

dB

ns

t_ST

Time from the start of the output transition to

output within ± 1 LSB of final value.

t_Rout

t_Fout

BW

Output rise time

Output fall time

Measured from 10% to 90% of full-scale

transition

25

ns

Measured from 10% to 90% of full-scale

transition

Signal bandwidth

Differential gain⁽²⁾

Differential phase⁽²⁾

Within bandwidth

6

1.5%

1

MHz

deg.

dB

SFDR

SNR

f_CLK= 54 MHz, f_OUT= 1 MHz

45

55⁽³⁾

Signal-to-noise ratio

dB

1 kHz to 6 MHz bandwidth

PSRR

Power supply rejection ratio Up to 6 MHz

20⁽⁴⁾

–50

dB

Crosstalk Between the two video

channels

–40

(1) For internal input clock information, For more information, see the DSS chapter of the OMAP35x Technical Reference Manual (TRM)

[literature number SPRUF98].

(2) The differential gain and phase value is for dc coupling. Note that there is degradation for the ac coupling.

(3) The SNR value is for dc coupling. Note that there is a 6-dB degradation for ac coupling.

(4) The PSSR value is for dc coupling. Note that there is a 10-dB degradation for ac coupling.

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5.3 Analog Supply (vdda_dac) Noise Requirements

In order to assure 10-bit accuracy of the DAC analog output, the analog supply vdda_dac has to meet the

noise requirements stated in this section.

The DAC Power Supply Rejection Ratio is defined as the relative variation of the full-scale output current

divided by the supply variation. Thus, it is expressed in percentage of Full-Scale Range (FSR) per volt of

DI_OUT

100×

I_OUTFS

% FSR

PSRR_DAC

=

V

V_AC

supply variation as shown in the following equation:

Depending on frequency, the PSRR is defined in Table 5-4.

Table 5-4. Video DAC – Power Supply Rejection Ratio

Supply Noise Frequency

PSRR % FSR/V

0 to 100 kHz

> 100 kHz

1

The rejection decreases 20 dB/dec.

Example: at 1 MHz the PSRR is 10% of FSR/V

A graphic representation is shown in Figure 5-2.

PSRR (% FSR/V)

First pole of

DAC output load

10

1

f

1 MHz

100 kHz

030-019

Figure 5-2. Video DAC – Power Supply Rejection Ratio

To ensure that the DAC SFDR specification is met, the PSRR values and the clock jitter requirements

translate to the following limits on vdda_dac (for the Video DAC).

The maximum peak-to-peak noise on vdda (ripple) is defined in Table 5-5:

Table 5-5. Video DAC – Maximum Peak-to-Peak Noise on vdda_dac

Tone Frequency

0 to 100 kHz

> 100 kHz

Maximum Peak-to-Peak Noise on vdda_dac

< 30 mVpp

Decreases 20 dB/dec.

Example: at 1 MHz the maximum is 3 mVpp

The maximum noise spectral density (white noise) is defined in Table 5-6:

Table 5-6. Video DAC – Maximum Noise Spectral Density

Supply Noise Bandwidth

0 to 100 kHz

Maximum Supply Noise Density

< 20 μV / √Hz

> 100 kHz

Decreases 20 dB/dec.

Example: at 1 MHz the maximum noise density is 2 μ / √Hz

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Because the DAC PSRR deteriorates at a rate of 20 dB/dec after 100 kHz, it is highly recommended to

have vdda_dac low pass filtered (proper decoupling) (see the illustrated application: Section 5.4, External

Component Value Choice).

5.4 External Component Value Choice

The full-scale output voltage V_OUTMAXis regulated by the reference amplifier, and is set by an internal

resistor R_SET. I_OUTMAXcan be expressed as:

I_OUTMAX= I_REF/8 * (63 + 15/16)

(1)

Where:

V_REF= 0.55V

(2)

(3)

I_REF= V_REF/ (2* R_SET

)

The output current I_OUTappearing at DAC output is a function of both the input code and I_OUTMAXand can

be expressed as:

I_OUT= (DAC_CODE/1023) * I_OUTMAX

(4)

(5)

(6)

Where:

DAC_CODE = 0 to 1023 is the DAC input code in decimal.

The output voltage is:

V_OUT= I_OUT*N* R_CABLE

Where:

(N = amplifier gain = 21)

R_CABLE= 75 Ω (cable typical impedance)

(7)

(8)

The TV-out buffer requires a per channel external resistors: R_OUT1/2. The equation below can be used to

select different resistor values (if necessary):

R_OUT= (N+1) R_CABLE= 1650 Ω

(9)

Recommended parameter values are:

Table 5-7. Video DAC – Recommended External Components Values

Recommended Value

UNIT

nF

C_BG

100

R_OUT1/2

1650

Ω

In order to limit the reference noise bandwidth and to suppress transients on V_REF, it is necessary to

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6 TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS

6.1 Timing Test Conditions

All timing requirements and switching characteristics are valid over the recommended operating conditions

of , unless otherwise specified.

6.2 Interface Clock Specifications

6.2.1 Interface Clock Terminology

The Interface clock is used at the system level to sequence the data and/or control transfers accordingly

with the interface protocol.

6.2.2 Interface Clock Frequency

The two interface clock characteristics are:

•

The maximum clock frequency

The maximum operating frequency

The interface clock frequency documented in this document is the maximum clock frequency, which

corresponds to the maximum frequency programmable on this output clock. This frequency defines the

maximum limit supported by the OMAP3515/03 IC and doesn’t take into account any system consideration

(PCB, peripherals).

The system designer will have to consider these system considerations and OMAP3515/03 IC timings

characteristics as well, to define properly the maximum operating frequency, which corresponds to the

maximum frequency supported to transfer the data on this interface.

6.2.3 Clock Jitter Specifications

Jitter is a phase noise, which may alter different characteristics of a clock signal. The jitter specified in this

document is the time difference between the typical cycle period and the actual cycle period affected by

noise sources on the clock. The cycle (or period) jitter terminology identifies this type of jitter.

Cycle (or Period) Jitter

T_n-1

T_n

T_n+1

Max. Cycle Jitter = Max (T_i)

Min. Cycle Jitter = Min (T_i)

Jitter Standard Deviation (or rms Jitter) = Standard Deviation (T_i)

030-020

Figure 6-1. Cycle (or Period) Jitter

6.2.4 Clock Duty Cycle Error

The duty cycle error is the ratio between either the high-level pulse duration or the low-level pulse duration

and the cycle time of a clock signal.

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6.3 Timing Parameters

The timing parameter symbols used in the timing requirement and switching characteristic tables are

created in accordance with JEDEC Standard 100. To shorten the symbols, some pin names and other

related terminologies have been abbreviated as follows:

Table 6-1. Timing Parameters

LOWERCASE SUBSCRIPTS

Symbols

Parameter

Cycle time (period)

Delay time

c

d

dis

en

h

Disable time

Enable time

Hold time

su

START

t

Setup time

Start bit

Transition time

Valid time

v

w

Pulse duration (width)

Unknown, changing, or don’t care level

High

X

H

L

Low

V

Valid

IV

AE

FE

LE

Z

Invalid

Active Edge

First Edge

Last Edge

High impedance

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6.4 External Memory Interfaces

The OMAP3515/03 processor includes the following external memory interfaces:

•

General-purpose memory controller (GPMC)

SDRAM controller (SDRC)

6.4.1 General-Purpose Memory Controller (GPMC)

The GPMC is the OMAP3515/03 unified memory controller used to interface external memory devices

such as:

•

Asynchronous SRAM-like memories and ASIC devices

Asynchronous page mode and synchronous burst NOR flash

NAND flash

6.4.1.1 GPMC/NOR Flash Interface Synchronous Timing

Table 6-3 and Table 6-4 assume testing over the recommended operating conditions (see Figure 6-2

through Figure 6-5) and electrical characteristic conditions.

Table 6-2. GPMC/NOR Flash Synchronous Mode Timing Conditions

TIMING CONDITION PARAMETER

Input Conditions

VALUE

UNIT

t_R

Input signal rise time

Input signal fall time

1.8

ns

t_F

Output Conditions

C_LOAD

Output load capacitance

15.94

pF

Table 6-3. GPMC/NOR Flash Interface Timing Requirements – Synchronous Mode⁽¹⁾

NO.

PARAMETER

OPP3

OPP2

OPP1⁽²⁾

MIN MAX

UNIT

MIN

MAX

MIN

MAX

F12 t_su(DV-CLKH)

F13 t_h(CLKH-DV)

F21 t_{su(WAITV-CLKH)}

F22 t_{h(CLKH-WAITV)}

Setup time, read gpmc_d[15:0]

valid before gpmc_clk high

1.9

3.2

1.9

3.2

2.5

ns

Hold time, read gpmc_d[15:0]

valid after gpmc_clk high

Setup time, gpmc_waitx⁽³⁾valid

before gpmc_clk high

Hold Time, gpmc_waitx⁽³⁾valid

after gpmc_clk high

1.9

2.5

1.9

2.5

(1) For VDD2 (vdd_core) OPP voltages, see Section 3.3, Recommended Operating Conditions.

(2) Cannot boot in OPP1. If OPP1 is desired, boot in higher OPP then switch to OPP1.

(3) Wait monitoring support is limited to a WaitMonitoringTime value > 0. For a full description of wait monitoring feature, see the OMAP35x

Technical Reference Manual (literature number ).

Table 6-4. GPMC/NOR Flash Interface Switching Characteristics – Synchronous Mode

NO.

PARAMETER

1.15 V

1.0 V

0.9 V

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

F0

F1

t_c(CLK)

Cycle time(15), output

clock gpmc_clk period

10

12.05

25

ns

t_w(CLKH)

Typical pulse duration,

output clock gpmc_clk

high

0.5 P(12)

F1

t_w(CLKL)

t_dc(CLK)

Typical pulse duration,

output clock gpmc_clk low

0.5 P(12)

–500

0.5 P(12)

500

0.5 P(12)

–602

0.5 P(12)

602

0.5 P(12)

–1250

0.5 P(12)

1250

ns

ps

Duty cycle error, output

clk gpmc_clk

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Table 6-4. GPMC/NOR Flash Interface Switching Characteristics – Synchronous Mode (continued)

NO.

PARAMETER

1.15 V

1.0 V

0.9 V

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

t_j(CLK)

Jitter standard

33.3

ps

deviation(16), output clock

gpmc_clk

t_R(CLK)

t_F(CLK)

Rise time, output clock

gpmc_clk

1.6

2

ns

Fall time, output clock

gpmc_clk

t_R(DO)

Rise time, output data

Fall time, output data

2

ns

t_F(DO)

F2

F3

F4

F5

F6

t_d(CLKH-nCSV)

Delay time, gpmc_clk

rising edge to

gpmc_ncsx(11) transition

F(6) – 1.9 F(6) + 3.3 F(6) – 1.8 F(6) + 4.1 F(6) – 2.6 F(6) + 4.9

E(5) – 1.9 E(5) + 3.3 E(5) – 1.8 E(5) + 4.1 E(5) – 2.6 E(5) + 4.9

B(2) – 4.1 B(2) + 2.1 B(2) – 4.1 B(2) + 2.1 B(2) – 4.9 B(2) + 2.6

t_{d(CLKH-nCSIV)}

t_d(ADDV-CLK)

t_{d(CLKH-ADDIV)}

t_d(nBEV-CLK)

Delay time, gpmc_clk

rising edge to

gpmc_ncsx(11) invalid

ns

Delay time, address bus

valid to gpmc_clk first

edge

Delay time, gpmc_clk

rising edge to

gpmc_a[16:1] invalid

–2.1

–2.6

Delay time,

B(2) – 1.1 B(2) + 2.1 B(2) – 0.9 B(2) + 1.9 B(2) – 2.6 B(2) + 2.6

D(4) – 2.1 D(4) + 1.1 D(4) – 1.9 D(4) + 0.9 D(4) – 2.6 D(4) + 2.6

gpmc_nbe0_cle,

gpmc_nbe1 valid to

gpmc_clk first edge

F7

t_{d(CLKH-nBEIV)}

Delay time, gpmc_clk

rising edge to

ns

gpmc_nbe0_cle,

gpmc_nbe1 invalid

F8

t_d(CLKH-nADV)

Delay time, gpmc_clk

rising edge to

gpmc_nadv_ale transition

G(7) – 1.9 G(7) + 4.1 G(7) – 2.1 G(7) + 4.1 G(7) – 2.6 G(7) + 4.9

D(4) – 1.9 D(4) + 4.1 D(4) – 2.1 D(4) + 4.1 D(4) – 2.6 D(4) + 4.9

H(8) – 2.1 H(8) + 2.1 H(8) – 2.1 H(8) + 2.1 H(8) – 2.6 H(8) + 4.9

E(5) – 2.1 E(5) + 2.1 E(5) – 2.1 E(5) + 2.1 E(5) – 2.6 E(5) + 4.9

ns

F9

t_{d(CLKH-nADVIV)}Delay time, gpmc_clk

rising edge to

gpmc_nadv_ale invalid

F10

t_d(CLKH-nOE)

Delay time, gpmc_clk

rising edge to gpmc_noe

transition

F11

F14

t_{d(CLKH-nOEIV)}

t_d(CLKH-nWE)

Delay time, gpcm rising

edge to gpmc_noe invalid

ns

Delay time, gpmc_clk

rising edge to gpmc_nwe

transition

I(9) – 1.9

I(9) + 4.1

I(9) – 2.1

I(9) + 4.1

I(9) – 2.6

I(9) + 4.9

F15

F17

F18

F19

F20

t_d(CLKH-Data)

t_d(CLKH-nBE)

t_W(nCSV)

Delay time, gpmc_clk

rising edge to data bus

transition

J(10) – 2.1 J(10) + 1.1 J(10) – 1.9 J(10) + 0.9 J(10) – 2.6 J(10) + 2.6

ns

Delay time, gpmc_clk

rising edge to

gpmc_nbex_cle transition

Pulse duration, Read

A(1)

ns

gpmc_ncsx(11)

Write

low

t_W(nBEV)

Pulse duration, Read

C(3)

ns

gpmc_nbe0_cle,

gpmc_nbe1 low

Write

t_W(nADVV)

Pulse duration, Read

K(13)

ns

gpmc_nadv_ale

Write

low

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Table 6-4. GPMC/NOR Flash Interface Switching Characteristics – Synchronous Mode (continued)

NO.

PARAMETER

1.15 V

1.0 V

0.9 V

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

F23

t_{d(CLKH-IODIR)}

Delay time, gpmc_clk

rising edge to gpmc_io_dir

high (IN direction)

H(8) – 2.1 H(8) + 4.1 H(8) – 2.1 H(8) + 4.1 H(8) – 2.6 H(8) + 4.9

ns

F24

t_{d(CLKH-IODIV)}

Delay time, gpmc_clk

rising edge to gpmc_io_dir

low (OUT direction)

M(17) –

2.1

M(17) +

4.1

M(17) –

2.1

M(17) +

4.1

M(17) –

2.6

M(17) +

4.9

ns

(1) For single read: A = (CSRdOffTime – CSOnTime) * (TimeParaGranularity + 1) * GPMC_FCLK period

For burst read: A = (CSRdOffTime – CSOnTime + (n – 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK period

For burst write: A = (CSWrOffTime – CSOnTime + (n – 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK period

with n being the page burst access number.

(2) B = ClkActivationTime * GPMC_FCLK

(3) For single read: C = RdCycleTime * (TimeParaGranularity + 1) * GPMC_FCLK

For burst read: C = (RdCycleTime + (n – 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK

For burst write: C = (WrCycleTime + (n – 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK with n being the

page burst access number.

(4) For single read: D = (RdCycleTime – AccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK

For burst read: D = (RdCycleTime – AccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK

For burst write: D = (WrCycleTime – AccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK

(5) For single read: E = (CSRdOffTime – AccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK

For burst read: E = (CSRdOffTime – AccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK

For burst write: E = (CSWrOffTime – AccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK

(6) For nCS falling edge (CS activated):

–

Case GpmcFCLKDivider = 0:

F = 0.5 * CSExtraDelay * GPMC_FCLK

Case GpmcFCLKDivider = 1:

–

F = 0.5 * CSExtraDelay * GPMC_FCLK if (ClkActivationTime and CSOnTime are odd) or (ClkActivationTime and CSOnTime

are even)

–

F = (1 + 0.5 * CSExtraDelay) * GPMC_FCLK otherwise

–

Case GpmcFCLKDivider = 2:

–

F = 0.5 * CSExtraDelay * GPMC_FCLK if ((CSOnTime – ClkActivationTime) is a multiple of 3)

F = (1 + 0.5 * CSExtraDelay) * GPMC_FCLK if ((CSOnTime – ClkActivationTime – 1) is a multiple of 3)

F = (2 + 0.5 * CSExtraDelay) * GPMC_FCLK if ((CSOnTime – ClkActivationTime – 2) is a multiple of 3)

(7) For ADV falling edge (ADV activated):

–

Case GpmcFCLKDivider = 0:

G = 0.5 * ADVExtraDelay * GPMC_FCLK

Case GpmcFCLKDivider = 1:

–

G = 0.5 * ADVExtraDelay * GPMC_FCLK if (ClkActivationTime and ADVOnTime are odd) or (ClkActivationTime and

ADVOnTime are even)

–

G = (1 + 0.5 * ADVExtraDelay) * GPMC_FCLK otherwise

–

Case GpmcFCLKDivider = 2:

–

G = 0.5 * ADVExtraDelay * GPMC_FCLK if ((ADVOnTime – ClkActivationTime) is a multiple of 3)

G = (1 + 0.5 * ADVExtraDelay) * GPMC_FCLK if ((ADVOnTime – ClkActivationTime – 1) is a multiple of 3)

G = (2 + 0.5 * ADVExtraDelay) * GPMC_FCLK if ((ADVOnTime – ClkActivationTime – 2) is a multiple of 3)

For ADV rising edge (ADV deactivated) in Reading mode:

–

Case GpmcFCLKDivider = 0:

G = 0.5 * ADVExtraDelay * GPMC_FCLK

Case GpmcFCLKDivider = 1:

–

G = 0.5 * ADVExtraDelay * GPMC_FCLK if (ClkActivationTime and ADVRdOffTime are odd) or (ClkActivationTime and

ADVRdOffTime are even)

–

G = (1 + 0.5 * ADVExtraDelay) * GPMC_FCLK otherwise

–

Case GpmcFCLKDivider = 2:

–

G = 0.5 * ADVExtraDelay * GPMC_FCLK if ((ADVRdOffTime – ClkActivationTime) is a multiple of 3)

G = (1 + 0.5 * ADVExtraDelay) * GPMC_FCLK if ((ADVRdOffTime – ClkActivationTime – 1) is a multiple of 3)

G = (2 + 0.5 * ADVExtraDelay) * GPMC_FCLK if ((ADVRdOffTime – ClkActivationTime – 2) is a multiple of 3)

For ADV rising edge (ADV deactivated) in Writing mode:

–

Case GpmcFCLKDivider = 0:

G = 0.5 * ADVExtraDelay * GPMC_FCLK

Case GpmcFCLKDivider = 1:

–

G = 0.5 * ADVExtraDelay * GPMC_FCLK if (ClkActivationTime and ADVWrOffTime are odd) or (ClkActivationTime and

ADVWrOffTime are even)

–

G = (1 + 0.5 * ADVExtraDelay) * GPMC_FCLK otherwise

–

Case GpmcFCLKDivider = 2:

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–

G = 0.5 * ADVExtraDelay * GPMC_FCLK if ((ADVWrOffTime – ClkActivationTime) is a multiple of 3)

G = (1 + 0.5 * ADVExtraDelay) * GPMC_FCLK if ((ADVWrOffTime – ClkActivationTime – 1) is a multiple of 3)

G = (2 + 0.5 * ADVExtraDelay) * GPMC_FCLK if ((ADVWrOffTime – ClkActivationTime – 2) is a multiple of 3)

(8) For OE falling edge (OE activated) / IO DIR rising edge (Data Bus input direction):

–

Case GpmcFCLKDivider = 0:

H = 0.5 * OEExtraDelay * GPMC_FCLK

Case GpmcFCLKDivider = 1:

–

H = 0.5 * OEExtraDelay * GPMC_FCLK if (ClkActivationTime and OEOnTime are odd) or (ClkActivationTime and OEOnTime

are even)

–

H = (1 + 0.5 * OEExtraDelay) * GPMC_FCLK otherwise

–

Case GpmcFCLKDivider = 2:

–

H = 0.5 * OEExtraDelay * GPMC_FCLK if ((OEOnTime – ClkActivationTime) is a multiple of 3)

H = (1 + 0.5 * OEExtraDelay) * GPMC_FCLK if ((OEOnTime – ClkActivationTime – 1) is a multiple of 3)

H = (2 + 0.5 * OEExtraDelay) * GPMC_FCLK if ((OEOnTime – ClkActivationTime – 2) is a multiple of 3)

For OE rising edge (OE deactivated):

–

GpmcFCLKDivider = 0:

H = 0.5 * OEExtraDelay * GPMC_FCLK

Case GpmcFCLKDivider = 1:

–

H = 0.5 * OEExtraDelay * GPMC_FC if (ClkActivationTime and OEOffTime are odd) or (ClkActivationTime and OEOffTime are

even)

–

H = (1 + 0.5 * OEExtraDelay) * GPMC_FCLK otherwise

–

Case GpmcFCLKDivider = 2:

–

H = 0.5 * OEExtraDelay * GPMC_FCLK if ((OEOffTime – ClkActivationTime) is a multiple of 3)

H = (1 + 0.5 * OEExtraDelay) * GPMC_FCLK if ((OEOffTime – ClkActivationTime – 1) is a multiple of 3)

H = (2 + 0.5 * OEExtraDelay) * GPMC_FCLK if ((OEOffTime – ClkActivationTime – 2) is a multiple of 3)

(9) For WE falling edge (WE activated):

–

Case GpmcFCLKDivider = 0:

I = 0.5 * WEExtraDelay * GPMC_FCLK

Case GpmcFCLKDivider = 1:

–

I = 0.5 * WEExtraDelay * GPMC_FCLK if (ClkActivationTime and WEOnTime are odd) or (ClkActivationTime and WEOnTime

are even)

–

I = (1 + 0.5 * WEExtraDelay) * GPMC_FCLK otherwise

–

Case GpmcFCLKDivider = 2:

–

I = 0.5 * WEExtraDelay * GPMC_FCLK if ((WEOnTime – ClkActivationTime) is a multiple of 3)

I = (1 + 0.5 * WEExtraDelay) * GPMC_FCLK if ((WEOnTime – ClkActivationTime – 1) is a multiple of 3)

I = (2 + 0.5 * WEExtraDelay) * GPMC_FCLK if ((WEOnTime – ClkActivationTime – 2) is a multiple of 3)

For WE rising edge (WE deactivated):

–

Case GpmcFCLKDivider = 0:

I = 0.5 * WEExtraDelay * GPMC_FCLK

Case GpmcFCLKDivider = 1:

–

I = 0.5 * WEExtraDelay * GPMC_FCLK if (ClkActivationTime and WEOffTime are odd) or (ClkActivationTime and WEOffTime

are even)

–

I = (1 + 0.5 * WEExtraDelay) * GPMC_FCLK otherwise

–

Case GpmcFCLKDivider = 2:

–

I = 0.5 * WEExtraDelay * GPMC_FCLK if ((WEOffTime – ClkActivationTime) is a multiple of 3)

I = (1 + 0.5 * WEExtraDelay) * GPMC_FCLK if ((WEOffTime – ClkActivationTime – 1) is a multiple of 3)

I = (2 + 0.5 * WEExtraDelay) * GPMC_FCLK if ((WEOffTime – ClkActivationTime – 2) is a multiple of 3)

(10) J = GPMC_FCLK period

(11) In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. In gpmc_waitx, x is equal to 0, 1, 2, or 3.

(12) P = gpmc_clk period

(13) For read: K = (ADVRdOffTime – ADVOnTime) * (TimeParaGranularity + 1) * GPMC_FCLK

For write: K = (ADVWrOffTime – ADVOnTime) * (TimeParaGranularity + 1) * GPMC_FCLK

(14) GPMC_FCLK is General-Purpose Memory Controller internal functional clock.

(15) Related to the gpmc_clk output clock maximum and minimum frequencies programmable in the I/F module by setting the

GPMC_CONFIG1_CSx configuration register bit field GpmcFCLKDivider.

(16) The jitter probability density can be approximated by a Gaussian function.

(17) M = (RdCycleTime - AccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK

Above M parameter expression is given as one example of GPMC programming. IO DIR signal will go from IN to OUT after both

RdCycleTime and BusTurnAround completion. Behavior of IO direction signal does depend on kind of successive Read/Write accesses

performed to Memory and multiplexed or non-multiplexed memory addressing scheme, bus keeping feature enabled or not. IO DIR

behavior is automatically handled by GPMC controller. For a full description of the gpmc_io_dir feature, see the OMAP35x Technical

Reference Manual (TRM) [literature number SPRUF98].

158

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F1

F0

F1

gpmc_clk

F2

F3

F18

gpmc_ncsx

F4

F6

gpmc_a[10:1]

Valid Address

F19

F7

gpmc_nbe0_cle

gpmc_nbe1

F19

F6

F8

F20

F9

gpmc_nadv_ale

gpmc_noe

F10

F11

F13

F12

D 0

gpmc_d[15:0]

gpmc_waitx

gpmc_io_dir

F23

F24

OUT

IN

OUT

030-021

In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. In gpmc_waitx, x is equal to 0, 1, 2, or 3.

Figure 6-2. GPMC/NOR Flash – Synchronous Single Read – (GpmcFCLKDivider = 0)

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F1

F0

F1

gpmc_clk

F2

F3

gpmc_ncsx

F4

gpmc_a[10:1]

Valid Address

F6

F7

gpmc_nbe0_cle

F7

F9

gpmc_nbe1

F6

F8

gpmc_nadv_ale

gpmc_noe

F10

F11

F13

F12

D 0

F22

F12

D 3

gpmc_d[15:0]

gpmc_waitx

gpmc_io_dir

D 1

D 2

F21

F23

F24

OUT

IN

OUT

030-022

In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. In gpmc_waitx, x is equal to 0, 1, 2, or 3.

Figure 6-3. GPMC/NOR Flash – Synchronous Burst Read – 4x16-bit (GpmcFCLKDivider = 0)

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F1

F0

gpmc_clk

F2

F3

gpmc_ncsx

F4

F6

gpmc_a[10:1]

Valid Address

F17

gpmc_nbe0_cle

F17

gpmc_nbe1

gpmc_nadv_ale

gpmc_nwe

F6

F8

F9

F14

F15

D 1

F15

D 2

F15

gpmc_d[15:0]

gpmc_waitx

D 0

D 3

gpmc_io_dir

OUT

030-023

In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. In gpmc_waitx, x is equal to 0, 1, 2, or 3.

Figure 6-4. GPMC/NOR Flash – Synchronous Burst Write – (GpmcFCLKDivider = 0)

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F1

F0

F1

gpmc_clk

F2

F3

gpmc_ncsx

F6

F7

gpmc_nbe0_cle

Valid

F6

F7

gpmc_nbe1

Valid

F4

gpmc_a[26:17]

Address (MSB)

F5

F12

F13

D1 D2

F4

F12

gpmc_a[16:1]_d[15:0]

Address (LSB)

F8

D0

D3

F8

F9

gpmc_nadv_ale

gpmc_noe

F10

F11

gpmc_waitx

gpmc_io_dir

F24

F23

OUT

IN

OUT

030-024

In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. In gpmc_waitx, x is equal to 0, 1, 2, or 3.

Figure 6-5. GPMC/Multiplexed NOR Flash – Synchronous Burst Read

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F1

F0

gpmc_clk

F2

F3

gpmc_ncsx

F4

F6

gpmc_a[26:17]

gpmc_nbe0_cle

Address (MSB)

F17

gpmc_nbe1

gpmc_nadv_ale

gpmc_nwe

F6

F8

F9

F14

F15

D 1

F15

D 2

F15

gpmc_d[15:0]

gpmc_waitx

Address (LSB)

D 0

D 3

gpmc_io_dir

OUT

030-025

In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. In gpmc_waitx, x is equal to 0, 1, 2, or 3.

Figure 6-6. GPMC/Multiplexed NOR Flash – Synchronous Burst Write

6.4.1.2 GPMC/NOR Flash Interface Asynchronous Timing

Table 6-7 and Table 6-8 assume testing over the recommended operating conditions (see Figure 6-7

through Figure 6-12) and electrical characteristic conditions.

Table 6-5. GPMC/NOR Flash Asynchronous Mode Timing Conditions

TIMING CONDITION PARAMETER

Input Conditions

VALUE

UNIT

t_R

Input signal rise time

Input signal fall time

1.8

ns

t_F

Output Conditions

C_LOAD

Output load capacitance

15.94

pF

Table 6-6. GPMC/NOR Flash Interface Asynchronous Timing – Internal Parameters^{(1) (2)}

NO.

PARAMETER

1.15 V

MAX

1.0 V

0.9 V

UNIT

MIN

MAX

MIN

MAX

FI1

FI2

FI3

FI4

Maximum output data generation delay from internal

functional clock

6.5

9.1

13.7

ns

Maximum input data capture delay by internal

functional clock

4

5.6

9.1

8.1

Maximum device select generation delay from internal

functional clock

6.5

13.7

Maximum address generation delay from internal

functional clock

(1) The internal parameters table must be used to calculate Data Access Time stored in the corresponding CS register bit field.

(2) Internal parameters are referred to the GPMC functional internal clock which is not provided externally.

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Table 6-6. GPMC/NOR Flash Interface Asynchronous Timing – Internal Parameters^{(1) (2)}(continued)

NO.

PARAMETER

1.15 V

MAX

1.0 V

0.9 V

UNIT

MIN

MAX

MIN

MAX

FI5

FI6

FI7

FI8

FI9

Maximum address valid generation delay from internal

functional clock

6.5

100

9.1

13.7

ns

ps

Maximum byte enable generation delay from internal

functional clock

9.1

170

13.7

200

Maximum output enable generation delay from internal

functional clock

Maximum write enable generation delay from internal

functional clock

Maximum functional clock skew

Table 6-7. GPMC/NOR Flash Interface Timing Requirements – Asynchronous Mode

NO.

PARAMETER

1.15 V

MIN MAX

1.0 V

0.9 V

UNIT

MIN

MAX

MIN

MAX

FA5⁽¹⁾

t_acc(DAT)

Data maximum access

time

H⁽²⁾

GPMC_FCLK cycles

FA20⁽³⁾t_{acc1-pgmode(DAT)}Page mode successive

P⁽⁴⁾

data maximum access

time

FA21⁽⁵⁾t_{acc2-pgmode(DAT)}Page mode first data

maximum access time

H⁽²⁾

GPMC_FCLK cycles

(1) The FA5 parameter illustrates the amount of time required to internally sample input Data. It is expressed in number of GPMC functional

clock cycles. From start of read cycle and after FA5 functional clock cycles, input Data is internally sampled by active functional clock

edge. FA5 value must be stored inside the AccessTime register bit field.

(2) H = AccessTime * (TimeParaGranularity + 1)

(3) The FA20 parameter illustrates amount of time required to internally sample successive input Page Data. It is expressed in number of

GPMC functional clock cycles. After each access to input Page Data, next input Page Data is internally sampled by active functional

clock edge after FA20 functional clock cycles. The FA20 value must be stored in the PageBurstAccessTime register bit field.

(4) P = PageBurstAccessTime * (TimeParaGranularity + 1)

(5) The FA21 parameter illustrates amount of time required to internally sample first input Page Data. It is expressed in number of GPMC

functional clock cycles. From start of read cycle and after FA21 functional clock cycles, First input Page Data is internally sampled by

active functional clock edge. FA21 value must be stored inside the AccessTime register bit field.

Table 6-8. GPMC/NOR Flash Interface Switching Characteristics – Asynchronous Mode

NO.

PARAMETER

1.15 V

1.0 V

0.9 V

UNIT

MIN

MAX

2.0

MIN

MAX

2.0

MIN

MAX

2.0

t_R(DO)

Rise time, output data

ns

t_F(DO)

Fall time, output data

Pulse duration, Read

2.0

FA0

t_W(nBEV)

N(12)

gpmc_nbe0_cl

e, gpmc_nbe1

Write

valid time

FA1

FA3

t_W(nCSV)

Pulse duration, Read

A(1)

ns

gpmc_ncsx(13)

v low

Write

t_{d(nCSV-nADVIV)}

Delay time,

gpmc_ncsx(13)

valid to

Read

Write

B(2) – 0.2 B(2) + 2.0 B(2) – 0.2 B(2) + 2.6 B(2) – 0.2 B(2) + 3.7

ns

gpmc_nadv_al

e invalid

FA4

FA9

t_{d(nCSV-nOEIV)}

Delay time,

C(3) – 0.2 C(3) + 2.0 C(3) – 0.2 C(3) + 2.6 C(3) – 0.2 C(3) + 3.7

J(9) – 0.2 J(9) + 2.0 J(9) – 0.2 J(9) + 2.6 J(9) – 0.2 J(9) + 3.7

ns

gpmc_ncsx(13) valid to

gpmc_noe invalid

(Single read)

t_d(AV-nCSV)

Delay time, address

bus valid to

gpmc_ncsx(13) valid

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Table 6-8. GPMC/NOR Flash Interface Switching Characteristics – Asynchronous Mode (continued)

NO.

PARAMETER

1.15 V

1.0 V

0.9 V

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

FA10 t_d(nBEV-nCSV)

Delay time,

J(9) – 0.2 J(9) + 2.0 J(9) – 0.2 J(9) + 2.6 J(9) – 0.2 J(9) + 3.7

ns

gpmc_nbe0_cle,

gpmc_nbe1 valid to

gpmc_ncsx(13) valid

FA12 t_{d(nCSV-nADVV)}

FA13 t_d(nCSV-nOEV)

FA14 t_{d(nCSV-IODIR)}

FA15 t_{d(nCSV-IODIR)}

FA16 t_w(AIV)

Delay time,

gpmc_ncsx(13) valid to

gpmc_nadv_ale valid

K(10) –

0.2

K(10) +

2.0

K(10) –

0.2

K(10) +

2.6

K(10) –

0.2

K(10) +

3.7

ns

Delay time,

gpmc_ncsx(13) valid to

gpmc_noe valid

L(11) – 0.2 L(11) + 2.0 L(11) – 0.2 L(11) + 2.6 L(11) – 0.2 L(11) + 3.7

Delay time,

gpmc_ncsx(13) valid to

gpmc_io_dir high

Delay time,

gpmc_ncsx(13) valid to

gpmc_io_dir low

M(14) –

0.2

M(14) +

2.0

M(14) –

0.2

M(14) +

2.6

M(14) –

0.2

M(14) +

3.7

Address invalid

duration between 2

successive R/W

accesses

G(7)

FA18 t_{d(nCSV-nOEIV)}

Delay time,

I(8) – 0.2

I(8) + 2.0

I(8) – 0.2

I(8) + 2.6

I(8) – 0.2

I(8) + 3.7

ns

gpmc_ncsx(13) valid to

gpmc_noe invalid

(Burst read)

FA20 t_w(AV)

Pulse duration, address

valid – 2nd, 3rd, and

4th accesses

D(4)

ns

FA25 t_d(nCSV-nWEV)

Delay time,

gpmc_ncsx(13) valid to

gpmc_nwe valid

E(5) – 0.2 E(5) + 2.0 E(5) – 0.2 E(5) + 2.6 E(5) – 0.2 E(5) + 3.7

F(6) – 0.2 F(6) + 2.0 F(6) – 0.2 F(6) + 2.6 F(6) – 0.2 F(6) + 3.7

FA27 t_{d(nCSV-nWEIV)}

Delay time,

gpmc_ncsx(13) valid to

gpmc_nwe invalid

FA28 t_d(nWEV-DV)

FA29 t_d(DV-nCSV)

Delay time, gpmc_ new

valid to data bus valid

2.0

2.6

3.7

ns

Delay time, data bus

valid to gpmc_ncsx(13)

valid

J(9) – 0.2 J(9) + 2.0 J(9) – 0.2 J(9) + 2.6 J(9) – 0.2 J(9) + 3.7

FA37 t_d(nOEV-AIV)

Delay time, gpmc_noe

valid to

2.0

2.6

3.7

ns

gpmc_a[16:1]_d[15:0]

address phase end

(1) For single read: A = (CSRdOffTime – CSOnTime) * (TimeParaGranularity + 1) * GPMC_FCLK

For single write: A = (CSWrOffTime – CSOnTime) * (TimeParaGranularity + 1) * GPMC_FCLK

For burst read: A = (CSRdOffTime – CSOnTime + (n – 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK

For burst write: A = (CSWrOffTime – CSOnTime + (n – 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK with n

being the page burst access number

(2) For reading: B = ((ADVRdOffTime – CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (ADVExtraDelay – CSExtraDelay)) * GPMC_FCLK

For writing: B = ((ADVWrOffTime – CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (ADVExtraDelay – CSExtraDelay)) * GPMC_FCLK

(3) C = ((OEOffTime – CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (OEExtraDelay – CSExtraDelay)) * GPMC_FCLK

(4) D = PageBurstAccessTime * (TimeParaGranularity + 1) * GPMC_FCLK

(5) E = ((WEOnTime – CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (WEExtraDelay – CSExtraDelay)) * GPMC_FCLK

(6) F = ((WEOffTime – CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (WEExtraDelay – CSExtraDelay)) * GPMC_FCLK

(7) G = Cycle2CycleDelay * GPMC_FCLK

(8) I = ((OEOffTime + (n – 1) * PageBurstAccessTime – CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (OEExtraDelay – CSExtraDelay)) *

GPMC_FCLK

(9) J = (CSOnTime * (TimeParaGranularity + 1) + 0.5 * CSExtraDelay) * GPMC_FCLK

(10) K = ((ADVOnTime – CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (ADVExtraDelay – CSExtraDelay)) * GPMC_FCLK

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(11) L = ((OEOnTime – CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (OEExtraDelay – CSExtraDelay)) * GPMC_FCLK

(12) For single read: N = RdCycleTime * (TimeParaGranularity + 1) * GPMC_FCLK

For single write: N = WrCycleTime * (TimeParaGranularity + 1) * GPMC_FCLK

For burst read: N = (RdCycleTime + (n – 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK

For burst write: N = (WrCycleTime + (n – 1) * PageBurstAccessTime) * (TimeParaGranularity + 1) * GPMC_FCLK

(13) In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7.

(14) M = ((RdCycleTime - CSOnTime) * (TimeParaGranularity + 1) - 0.5 * CSExtraDelay) * GPMC_FCLK

Above M parameter expression is given as one example of GPMC programming. IO DIR signal will go from IN to OUT after both

RdCycleTime and BusTurnAround completion. Behavior of IO direction signal does depend on kind of successive Read/Write accesses

performed to Memory and multiplexed or non-multiplexed memory addressing scheme, bus keeping feature enabled or not. IO DIR

behavior is automatically handled by GPMC controller. For a full description of the gpmc_io_dir feature, see the OMAP35x Technical

Reference Manual (TRM) [literature number SPRUF98].

GPMC_FCLK

gpmc_clk

FA5

FA1

gpmc_ncsx

FA9

gpmc_a[10:1]

Valid Address

FA0

FA10

gpmc_nbe0_cle

gpmc_nbe1

Valid

FA0

Valid

FA10

FA3

FA12

gpmc_nadv_ale

FA4

FA13

gpmc_noe

gpmc_d[15:0]

Data IN 0

gpmc_waitx

gpmc_io_dir

FA15

FA14

OUT

IN

OUT

030-026

Figure 6-7. GPMC/NOR Flash – Asynchronous Read – Single Word Timing(1) (2) (3)

(1) In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. In gpmc_waitx, x is equal to 0, 1, 2, or 3.

(2) FA5 parameter illustrates amount of time required to internally sample input data. It is expressed in number of GPMC functional clock

cycles. From start of read cycle and after FA5 functional clock cycles, input data is internally sampled by active functional clock edge.

FA5 value must be stored inside AccessTime register bit field.

(3) GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.

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GPMC_FCLK

gpmc_clk

FA5

FA1

gpmc_ncsx

FA16

FA9

gpmc_a[10:1]

Address 0

FA0

Address 1

FA0

FA10

gpmc_nbe0_cle

gpmc_nbe1

Valid

FA0

Valid

FA0

Valid

FA10

FA3

FA12

FA3

FA12

gpmc_nadv_ale

FA4

FA13

gpmc_noe

Data Upper

gpmc_d[15:0]

gpmc_waitx

gpmc_io_dir

FA15

FA14

OUT

FA14

OUT

IN

030-027

Figure 6-8. GPMC/NOR Flash – Asynchronous Read – 32-bit Timing(1) (2) (3)

(1) In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. In gpmc_waitx, x is equal to 0, 1, 2, or 3.

(2) FA5 parameter illustrates amount of time required to internally sample input data. It is expressed in number of GPMC functional clock

cycles. From start of read cycle and after FA5 functional clock cycles, input data is internally sampled by active functional clock edge.

FA5 value must be stored inside AccessTime register bit field.

(3) GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.

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gpmc_clk

FA21

FA20

Add1

FA20

Add3

FA20

FA1

gpmc_ncsx

FA9

gpmc_a[10:1]

Add0

Add2

Add4

FA0

FA10

gpmc_nbe0_cle

FA0

FA10

gpmc_nbe1

FA12

gpmc_nadv_ale

FA18

FA13

gpmc_noe

D3

gpmc_d[15:0]

D0

D1

D2

D3

gpmc_waitx

FA15

FA14

OUT

gpmc_io_dir

OUT

IN

030-028

Figure 6-9. GPMC/NOR Flash – Asynchronous Read – Page Mode 4x16-bit Timing(1) (2) (3) (4)

(1) In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. In gpmc_waitx, x is equal to 0, 1, 2, or 3.

(2) FA21 parameter illustrates amount of time required to internally sample first input page data. It is expressed in number of GPMC

functional clock cycles. From start of read cycle and after FA21 functional clock cycles, first input page data is internally sampled by

active functional clock edge. FA21 value must be stored inside AccessTime register bit field.

(3) FA20 parameter illustrates amount of time required to internally sample successive input page data. It is expressed in number of GPMC

functional clock cycles. After each access to input page data, next input page data is internally sampled by active functional clock edge

after FA20 functional clock cycles. FA20 is also the duration of address phases for successive input page data (excluding first input

page data). FA20 value must be stored in PageBurstAccessTime register bit field.

(4) GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.

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gpmc_fclk

gpmc_clk

FA1

gpmc_ncsx

FA9

gpmc_a[10:1]

gpmc_nbe0_cle

gpmc_nbe1

Valid Address

FA0

FA10

FA0

FA3

FA12

gpmc_nadv_ale

FA27

FA25

gpmc_nwe

gpmc_d[15:0]

gpmc_waitx

gpmc_io_dir

FA29

Data OUT

OUT

030-029

In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. In gpmc_waitx, x is equal to 0, 1, 2, or 3.

Figure 6-10. GPMC/NOR Flash – Asynchronous Write – Single Word Timing

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GPMC_FCLK

gpmc_clk

FA1

FA5

gpmc_ncsx

FA9

gpmc_a[26:17]

Address (MSB)

FA0

FA10

gpmc_nbe0_cle

Valid

FA0

FA10

gpmc_nbe1

Valid

FA3

FA12

gpmc_nadv_ale

FA4

FA13

gpmc_noe

gpmc_a[16:1]_d[15:0]

gpmc_io_dir

FA29

FA37

Data IN

Address (LSB)

FA15

FA14

OUT

IN

gpmc_waitx

030-030

Figure 6-11. GPMC/Multiplexed NOR Flash – Asynchronous Read – Single Word Timing(1) (2) (3)

(1) In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. In gpmc_waitx, x is equal to 0, 1, 2, or 3.

(2) FA5 parameter illustrates amount of time required to internally sample input data. It is expressed in number of GPMC functional clock

cycles. From start of read cycle and after FA5 functional clock cycles, input data is internally sampled by active functional clock edge.

FA5 value must be stored inside AccessTime register bit field.

(3) GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.

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gpmc_fclk

gpmc_clk

FA1

gpmc_ncsx

FA9

gpmc_a[26:17]

gpmc_nbe0_cle

gpmc_nbe1

Address (MSB)

FA0

FA10

FA0

FA3

FA12

gpmc_nadv_ale

FA27

FA25

gpmc_nwe

gpmc_a[16:1]_d[15:0]

gpmc_waitx

FA29

FA28

Valid Address (LSB)

Data OUT

gpmc_io_dir

OUT

030-031

In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. In gpmc_waitx, x is equal to 0, 1, 2, or 3.

Figure 6-12. GPMC/Multiplexed NOR Flash – Asynchronous Write – Single Word Timing

6.4.1.3 GPMC/NAND Flash Interface Timing

Table 6-10 through Table 6-12 assume testing over the recommended operating conditions (see Figure 6-

13 through Figure 6-16) and electrical characteristic conditions.

Table 6-9. GPMC/NAND Flash Asynchronous Mode Timing Conditions

TIMING CONDITION PARAMETER

Input Conditions

VALUE

UNIT

t_R

Input signal rise time

Input signal fall time

1.8

ns

t_F

Output Conditions

C_LOAD

Output load capacitance

15.94

pF

Table 6-10. GPMC/NAND Flash Interface Asynchronous Timing – Internal Parameters^{(1) (2)}

NO.

PARAMETER

1.15 V

1.0 V

0.9 V

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

GNFI1

GNFI2

Maximum output data generation delay from

internal functional clock

6.5

9.1

13.7

ns

Maximum input data capture delay by internal

functional clock

4

5.6

8.1

(1) Internal parameters table must be used to calculate data access time stored in the corresponding CS register bit field.

(2) Internal parameters are referred to the GPMC functional internal clock which is not provided externally.

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Table 6-10. GPMC/NAND Flash Interface Asynchronous Timing – Internal Parameters^{(1) (2)}(continued)

NO.

PARAMETER

1.15 V

1.0 V

0.9 V

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

GNFI3

GNFI4

GNFI5

GNFI6

GNFI7

GNFI8

Maximum device select generation delay from

internal functional clock

6.5

9.1

13.7

ns

ps

Maximum address latch enable generation delay

from internal functional clock

6.5

100

9.1

170

13.7

200

Maximum command latch enable generation

delay from internal functional clock

Maximum output enable generation delay from

internal functional clock

Maximum write enable generation delay from

internal functional clock

Maximum functional clock skew

Table 6-11. GPMC/NAND Flash Interface Timing Requirements

NO.

PARAMETER

1.15 V

1.0 V

0.9 V

UNIT

MIN

MAX

J⁽²⁾

MIN

MAX

J⁽²⁾

MIN

MAX

J⁽²⁾

GNF12⁽¹⁾t_acc(DAT)

Data maximum access time

GPMC_FCLK

cycles

(1) The GNF12 parameter illustrates the amount of time required to internally sample input data. It is expressed in number of GPMC

functional clock cycles. From start of the read cycle and after GNF12 functional clock cycles, input data is internally sampled by the

active functional clock edge. The GNF12 value must be stored inside AccessTime register bit field.

(2) J = AccessTime * (TimeParaGranularity + 1)

Table 6-12. GPMC/NAND Flash Interface Switching Characteristics

NO.

PARAMETER

1.15 V

1.0 V

0.9 V

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

t_R(DO)

Rise time, output

data

2.0

ns

t_F(DO)

Fall time, output

data

2.0

GNF0

GNF1

t_w(nWEV)

Pulse duration,

gpmc_nwe valid

time

A(1)

t_d(nCSV-nWEV)

t_w(CLEH-nWEV)

t_w(nWEV-DV)

Delay time,

gpmc_ncsx(13)

valid to

B(2) – 0.2 B(2) + 2.0

C(3) – 0.2 C(3) + 2.0

D(4) – 0.2 D(4) + 2.0

E(5) – 0.2 E(5) + 2.0

F(6) – 0.2 F(6) + 2.0

B(2) – 0.2

C(3) – 0.2

D(4) – 0.2

E(5) – 0.2

F(6) – 0.2

B(2) + 2.6 B(2) – 0.2 B(2) + 3.7

C(3) + 2.6 C(3) – 0.2 C(3) + 3.7

D(4) + 2.6 D(4) – 0.2 D(4) + 3.7

E(5) + 2.6 E(5) – 0.2 E(5) + 3.7

F(6) + 2.6 F(6) – 0.2 F(6) + 3.7

ns

gpmc_nwe valid

GNF2

GNF3

GNF4

GNF5

Delay time,

gpmc_nbe0_cle

high to gpmc_nwe

valid

Delay time,

gpmc_d[15:0]

valid to

gpmc_nwe valid

t_w(nWEIV-DIV)

Delay time,

gpmc_nwe invalid

to gpmc_d[15:0]

invalid

t_{w(nWEIV-CLEIV)}

Delay time,

gpmc_nwe invalid

to

gpmc_nbe0_cle

invalid

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Table 6-12. GPMC/NAND Flash Interface Switching Characteristics (continued)

NO.

PARAMETER

1.15 V

1.0 V

0.9 V

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

GNF6

t_{w(nWEIV-nCSIV)}

t_w(ALEH-nWEV)

t_{w(nWEIV-ALEIV)}

Delay time,

G(7) – 0.2 G(7) + 2.0 G(7) – 0.2 G(7) + 2.6 G(7) – 0.2 G(7) + 3.7

ns

gpmc_nwe invalid

to gpmc_ncsx(13)

invalid

GNF7

GNF8

Delay time,

gpmc_nadv_ale

High to

C(3) – 0.2 C(3) + 2.0

F(6) – 0.2 F(6) + 2.0

C(3) – 0.2

F(6) – 0.2

C(3) + 2.6 C(3) – 0.2 C(3) + 3.7

F(6) + 2.6 F(6) – 0.2 F(6) + 3.7

ns

gpmc_nwe valid

Delay time,

gpmc_nwe invalid

to

gpmc_nadv_ale

invalid

GNF9

t_c(nWE)

Cycle time, Write

cycle time

H(8)

I(9) – 0.2

H(8)

ns

GNF10

t_d(nCSV-nOEV)

Delay time,

gpmc_ncsx(13)

valid to gpmc_noe

valid

I(9) – 0.2

I(9) + 2.0

I(9) + 2.6

I(9) – 0.2

I(9) + 3.7

GNF13

t_w(nOEV)

Pulse duration,

gpmc_noe valid

time

K(10)

ns

GNF14

GNF15

t_c(nOE)

Cycle time, Read

cycle time

L(11)

M(12) – 0.2

L(11)

ns

t_{w(nOEIV-nCSIV)}

Delay time,

M(12) –

0.2

M(12) +

2.0

M(12) +

2.6

M(12) –

0.2

M(12) +

3.7

gpmc_noe invalid

to gpmc_ncsx(13)

invalid

(1) A = (WEOffTime – WEOnTime) * (TimeParaGranularity + 1) * GPMC_FCLK

(2) B = ((WEOnTime – CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (WEExtraDelay – CSExtraDelay)) * GPMC_FCLK

(3) C = ((WEOnTime – ADVOnTime) * (TimeParaGranularity + 1) + 0.5 * (WEExtraDelay – ADVExtraDelay)) * GPMC_FCLK

(4) D = (WEOnTime * (TimeParaGranularity + 1) + 0.5 * WEExtraDelay ) * GPMC_FCLK

(5) E = ((WrCycleTime – WEOffTime) * (TimeParaGranularity + 1) – 0.5 * WEExtraDelay ) * GPMC_FCLK

(6) F = ((ADVWrOffTime – WEOffTime) * (TimeParaGranularity + 1) + 0.5 * (ADVExtraDelay – WEExtraDelay )) * GPMC_FCLK

(7) G = ((CSWrOffTime – WEOffTime) * (TimeParaGranularity + 1) + 0.5 * (CSExtraDelay – WEExtraDelay )) * GPMC_FCLK

(8) H = WrCycleTime * (1 + TimeParaGranularity) * GPMC_FCLK

(9) I = ((OEOnTime – CSOnTime) * (TimeParaGranularity + 1) + 0.5 * (OEExtraDelay – CSExtraDelay)) * GPMC_FCLK

(10) K = (OEOffTime – OEOnTime) * (1 + TimeParaGranularity) * GPMC_FCLK

(11) L = RdCycleTime * (1 + TimeParaGranularity) * GPMC_FCLK

(12) M = ((CSRdOffTime – OEOffTime) * (TimeParaGranularity + 1) + 0.5 * (CSExtraDelay – OEExtraDelay )) * GPMC_FCLK

(13) In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7.

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GNF1

GNF2

GNF6

GNF5

gpmc_ncsx

gpmc_nbe0_cle

gpmc_nadv_ale

gpmc_noe

GNF0

gpmc_nwe

GNF3

GNF4

gpmc_a[16:1]_d[15:0]

Command

030-032

In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7.

Figure 6-13. GPMC/NAND Flash – Command Latch Cycle Timing

GPMC_FCLK

gpmc_ncsx

GNF1

GNF7

GNF6

GNF8

gpmc_nbe0_cle

gpmc_nadv_ale

gpmc_noe

GNF9

GNF0

gpmc_nwe

GNF3

GNF4

gpmc_a[16:1]_d[15:0]

Address

030-033

In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7.

Figure 6-14. GPMC/NAND Flash – Address Latch Cycle Timing

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GPMC_FCLK

GNF12

GNF10

GNF15

gpmc_ncsx

gpmc_nbe0_cle

gpmc_nadv_ale

GNF14

GNF13

gpmc_noe

gpmc_a[16:1]_d[15:0]

DATA

gpmc_waitx

030-034

Figure 6-15. GPMC/NAND Flash – Data Read Cycle Timing(1) (2) (3)

(1) The GNF12 parameter illustrates amount of time required to internally sample input data. It is expressed in number of GPMC functional

clock cycles. From start of read cycle and after GNF12 functional clock cycles, input data is internally sampled by active functional clock

edge. The GNF12 value must be stored inside AccessTime register bit field.

(2) GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.

(3) In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. In gpmc_waitx, x is equal to 0 ,1, 2, or 3.

GPMC_FCLK

GNF1

GNF6

gpmc_ncsx

gpmc_nbe0_cle

gpmc_nadv_ale

gpmc_noe

GNF9

GNF0

gpmc_nwe

GNF3

GNF4

gpmc_a[16:1]_d[15:0]

DATA

030-035

In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. In gpmc_waitx, x is equal to 0 or 1.

Figure 6-16. GPMC/NAND Flash – Data Write Cycle Timing

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6.4.2 SDRAM Controller Subsystem (SDRC)

The SDRAM controller subsystem (SDRC) module provides connectivity between the OMAP35x

Applications Processor and external DRAM memory components. The SDRC module only supports low-

power double-data-rate (LPDDR) SDRAM devices. Memory devices can be interfaced to the SDRC using

a stacked-memory approach or through the printed circuit board (PCB). The stacked-memory approach

uses the package on package interface pins (available on CBB & CBC package).

6.4.2.1 SDRAM Controller Subsystem Device-Specific Information

The approach to specifying interface timing for the SDRC memory bus is different than on other interfaces

such as the general-purpose memory controller (GPMC) and the multi-channel buffered serial ports

(McBSPs). For these other interfaces the device timing was specified in terms of data manual

specifications and I/O buffer information specification (IBIS) models.

For the SDRC memory bus, the approach is to specify compatible memory devices and provide the

printed circuit board (PCB) solution and guidelines directly to the user. Texas Instruments (TI) has

performed the simulation and system characterization to ensure all interface timings in this solution are

met.

6.4.2.2 LPDDR Interface

The LPDDR interface is balled out on the bottom side of all OMAP35x packages and on the top side of

OMAP35x POP packages. The LPDDR interface on the top of the POP package has been designed for

compatibility any POP LPDDR device with a matching footprint and compliance with the JEDEC LPDDR-

266 specification.

This section provides the timing specification for the bottom-side LPDDR interface as a PCB design and

manufacturing specification. The design rules constrain PCB trace length, PCB trace skew, signal

integrity, cross-talk, and signal timing. These rules, when followed, result in a reliable LPDDR memory

system without the need for a complex timing closure process. For more information regarding guidelines

for using this LPDDR specification, see the Understanding TI's PCB Routing Rule-Based DDR Timing

Specification Application Report (literature number SPRAAV0).

6.4.2.2.1 LPDDR Interface Schematic

Figure 6-17 and Figure 6-18 show the LPDDR interface schematics for a LPDDR memory system. The 1

x16 LPDDR system schematic is identical to Figure 6-17 except that the high word LPDDR device is

deleted.

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sdrc_d0

LPDDR

T

DQ0

T

sdrc_d7

sdrc_dm0

sdrc_dqs0

sdrc_d8

DQ7

LDM

LDQS

DQ8

T

sdrc_d15

sdrc_dm1

sdrc_dqs1

DQ15

UDM

UDQS

LPDDR

DQ0

T

sdrc_d16

T

sdrc_d23

sdrc_dm2

sdrc_dqs2

sdrc_d24

DQ7

LDM

LDQS

DQ8

T

sdrc_d31

sdrc_dm3

sdrc_dqs3

sdrc_ba0

sdrc_ba1

sdrc_a0

DQ15

UDM

UDQS

BA0

BA1

A0

T

BA0

BA1

A0

T

sdrc_a14

sdrc_ncs0

sdrc_ncs1

sdrc_ncas

sdrc_nras

sdrc_nwe

sdrc_cke0

sdrc_cke1

sdrc_clk

A14

CS

A14

CS

N/C

T

CAS

RAS

WE

CAS

RAS

WE

CKE

N/C

T

CK

T

sdrc_nclk

Figure 6-17. OMAP35x LPDDR High Level Schematic (x16 memories)

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sdrc_d0

LPDDR

DQ0

T

sdrc_d7

sdrc_dm0

sdrc_dqs0

sdrc_d8

DQ7

DM0

DQS0

DQ8

T

sdrc_d15

sdrc_dm1

sdrc_dqs1

DQ15

DM1

DQS1

T

sdrc_d16

DQ16

T

sdrc_d23

sdrc_dm2

sdrc_dqs2

sdrc_d24

DQ23

DM2

DQS2

DQ24

T

sdrc_d31

sdrc_dm3

sdrc_dqs3

sdrc_ba0

sdrc_ba1

sdrc_a0

DQ31

DM3

DQS3

BA0

BA1

A0

T

sdrc_a14

sdrc_ncs0

sdrc_ncs1

sdrc_ncas

sdrc_nras

sdrc_nwe

sdrc_cke0

sdrc_cke1

sdrc_clk

A14

CS

N/C

T

CAS

RAS

WE

CKE

T

CK

sdrc_nclk

Figure 6-18. OMAP35x LPDDR High Level Schematic (x32 memory)

6.4.2.2.2 Compatible JEDEC LPDDR Devices

Table 6-13 shows the parameters of the JEDEC LPDDR devices that are compatible with this interface.

Generally, the LPDDR interface is compatible with x16 and x32 LPDDR266 and LPDDR333 speed grade

LPDDR devices.

Table 6-13. Compatible JEDEC LPDDR Devices

NO.

PARAMETER

MIN

MAX

UNIT

NOTES

JEDEC LPDDR Device Speed

Grade

(1)

(2)

1

LPDDR-266

See Note

2

3

JEDEC LPDDR Device Bit Width

JEDEC LPDDR Device Count

16

1

32

2

Bits

Devices

See Note

JEDEC LPDDR Device Ball

Count

4

60

90

Balls

(1) Higher LPDDR speed grades are supported due to inherent JEDEC LPDDR backwards compatibility.

(2) 1 x16 LPDDR device is used for 16 bit LPDDR memory system. 1x32 or 2x16 LPDDR devices are used for a 32-bit LPDDR memory

system.

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6.4.2.2.3 PCB Stackup

The minimum stackup required for routing the OMAP35x is a six layer stack as shown in Table 6-14.

Additional layers may be added to the PCB stack up to accommodate other circuity or to reduce the size

of the PCB footprint.

Table 6-14. OMAP35x Minimum PCB Stack Up

LAYER

TYPE

Signal

Plane

Signal

Plane

Signal

DESCRIPTION

Top Routing Mostly Horizontal

Ground

1

2

3

4

5

6

Power

Internal Routing

Ground

Bottom Routing Mostly Vertical

Table 6-15. PCB Stack Up Specifications

NO.

1

PARAMETER

MIN

6

TYP

MAX

UNIT

NOTES

PCB Routing/Plane Layers

Signal Routing Layers

2

3

Full ground layers under LPDDR routing region

2

4

Number of ground plane cuts allowed within LPDDR routing region

0

Number of ground reference planes required for each LPDDR routing 1

layer

5

6

1

Number of layers between LPDDR routing layer and reference ground 0

plane

7

PCB Routing Feature Size

PCB Trace Width w

4

Mils

8

9

PCB BGA escape via pad size

PCB BGA escape via hole size

Device BGA Pad Size

18

8

10

11

12

13

14

See Note⁽¹⁾

See Note⁽²⁾

LPDDR Device BGA Pad Size

Single Ended Impedance, ZO

Impedance Control

50

75

Ω

Z-5

Z

Z + 5

See Note⁽³⁾

(1) Please see the Flip Chip Ball Grid Array Package Reference Guide (literature number SPRU811) for device BGA pad size.

(2) Please see the LPDDR device manufacturer documentation for the LPDDR device BGA pad size.

(3) Z is the nominal singled ended impedance selected for the PCB specified by item 12.

6.4.2.3 Placement

Figure 6-19 shows the required placement for the OMAP35x device as well as the LPDDR devices. The

dimensions for Figure 6-19 are defined in Table 6-16. The placement does not restrict the side of the PCB

that the devices are mounted on. The ultimate purpose of the placement is to limit the maximum trace

lengths and allow for proper routing space. For 1x16 and 1x32 LPDDR memory systems, the second

LPDDR device is omitted from the placement.

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X

A1

Y

OFFSET

LPDDR

Device

Y

OMAP

OFFSET

A1

Recommended LPDDR Device

Orientation

Figure 6-19. OMAP35x and LPDDR Device Placement

Table 6-16. Placement Specifications

NO.

1

PARAMETER

MIN

MAX

1440

1030

525

UNIT

Mils

NOTES

See Notes⁽¹⁾

(2)

X

,

2

Y

3

Y Offset

See Notes^{(1) (2) (3)}

, ,

4

LPDDR Keepout Region

See Note⁽⁴⁾

Clearance from non-LPDDR signal to LPDDR

Keepout Region

5

4

w

See Note⁽⁵⁾

(1) See Figure 6-17 for dimension definitions.

(2) Measurements from center of device to center of LPDDR device.

(3) For 16 bit memory systems it is recommended that Y Offset be as small as possible.

(4) LPDDR keepout region to encompass entire LPDDR routing area.

(5) Non-LPDDR signals allowed within LPDDR keepout region provided they are separated from LPDDR routing layers by a ground plane.

6.4.2.4 LPDDR Keep Out Region

The region of the PCB used for the LPDDR circuitry must be isolated from other signals. The LPDDR

keep out region is defined for this purpose and is shown in Figure 6-20. The size of this region varies with

the placement and LPDDR routing. Additional clearances required for the keep out region are shown in

Table 6-16.

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A1

LPDDR Device

A1

Region should encompass all LPDDR circuitry and varies depending

on placement. Non-LPDDR signals should not be routed on the

LPDDR signal layers within the LPDDR keep out region. Non-LPDDR

signals may be routed in the region provided they are routed on

layers separated from LPDDR signal layers by a ground layer. No

breaks should be allowed in the reference ground layers in this

region. In addition, the 1.8 V power plane should cover the entire keep

out region.

Figure 6-20. LPDDR Keepout Region

6.4.2.5 Net Classes

Table 6-17 lists the clock net classes for the LPDDR interface. Table 6-18 lists the signal net classes, and

associated clock net classes, for the signals in the LPDDR interface. These net classes are used for the

termination and routing rules that follow.

Table 6-17. Clock Net Class Definitions

CLOCK NET CLASS

OMAP PIN NAMES

sdrc_clk/sdrc_nclk

sdrc_dqs0

CK

DQS0

DQS1

DQS2

DQS3

sdrc_dqs1

sdrc_dqs2

sdrc_dqs3

Table 6-18. Signal Net Class Definitions

CLOCK NET CLASS

ASSOCIATED CLOCK NET CLASS

OMAP PIN NAMES

sdrc_ba, sdrc_a, sdrc_ncs0, sdrc_ncas,

sdrc_nras, sdrc_nwe, sdrc_cke0

ADDR_CTRL

CK

DQ0

DQ1

DQ2

DQ3

DQS0

DQS1

DQS2

DQS3

sdrc_d, sdrc_dm0

sdrc_d, sdrc_dm1

sdrc_d, sdrc_dm2

sdrc_d, sdrc_dm3

6.4.2.6 LPDDR Signal Termination

No terminations of any kind are required in order to meet signal integrity and overshoot requirements.

Serial terminators are permitted, if desired, to reduce EMI risk; however, serial terminations are the only

type permitted. Table 6-19 shows the specifications for the series terminators.

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Table 6-19. LPDDR Signal Terminations

NO.

1

PARAMETER

CK Net Class

MIN

0

TYP

MAX

10

UNIT

Ω

NOTES

See Note⁽¹⁾

2

ADDR_CTRL Net Class

0

22

Zo

Ω

See Notes^{(1) (2) (3)}

,

Data Byte Net Classes

(DQS0-DQS3, DQ0-DQ3)

3

0

Zo

Ω

See Notes^{(1) (2) (3)}

, ,

(1) Only series termination is permitted, parallel or SST specifically disallowed.

(2) Terminator values larger than typical only recommended to address EMI issues.

(3) Termination value should be uniform across net class.

6.4.2.7 LPDDR CK and ADDR_CTRL Routing

Figure 6-21 shows the topology of the routing for the CK and ADDR_CTRL net classes. The route is a

balanced T as it is intended that the length of segments B and C be equal. In addition, the length of A

should be maximized.

A1

T

A

OMAP

A1

Figure 6-21. CK and ADDR_CTRL Routing and Topology

Table 6-20. CK and ADDR_CTRL Routing Specification

NO.

1

PARAMETER

MIN

TYP

MAX

2w

UNIT

NOTES

Center to Center CK-CK spacing

CK A to B/A to C Skew Length Mismatch

CK B to C Skew Length Mismatch

2

25

Mils

See Note⁽¹⁾

3

25

Center to Center CK to other

LPDDR trace spacing

4

4w

See Note⁽²⁾

See Note⁽³⁾

5

6

CK/ADDR_CTRL nominal trace length

CACLM-50

CACLM

CACLM+50

100

Mils

ADDR_CTRL to CK Skew Length Mismatch

ADDR_CTRL to ADDR_CTRL

Skew Length Mismatch

7

8

9

100

Mils

Center to Center ADDR_CTRL to other

LPDDR trace 4w spacing

4w

3w

See Note⁽²⁾

See Note⁽¹⁾

Center to Center ADDR_CTRL to other

ADDR_CTRL 3w trace spacing

ADDR_CTRL A to B/A to C Skew Length

Mismatch

10

11

100

Mils

ADDR_CTRL B to C Skew Length Mismatch

(1) Series terminator, if used, should be located closest to device.

(2) Center to center spacing is allowed to fall to minimum (w) for up to 500 mils of routed length to accommodate BGA escape and routing

congestion.

(3) CACLM is the longest Manhattan distance of the CK and ADDR_CTRL net classes.

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Figure 6-22 shows the topology and routing for the DQS and DQ net classes; the routes are point to point.

Skew matching across bytes is not needed nor recommended.

T

E0

A1

T

E1

OMAP

T

E2

A1

T

E3

Figure 6-22. DQS and DQ Routing and Topology

Table 6-21. DQS and DQ Routing Specification⁽¹⁾

NO.

PARAMETER

MIN

TYP

MAX

UNIT

NOTES

2

DQS E Skew Length Mismatch

25

Mils

Center to Center DQS to other LPDDR

trace spacing

3

4w

See Note⁽²⁾

See Note⁽³⁾

4

5

6

DQS/DQ nominal trace length

DQ to DQS Skew Length Mismatch

DQ to DQ Skew Length Mismatch

DQLM - 50

DQLM

DQLM + 50

100

Mils

100

Center to Center DQ to other LPDDR

trace spacing

7

4w

3w

See Note⁽²⁾

Center to Center DQ to other DQ trace

spacing

8

9

See Note^{(2) (4)}

,

DQ E Skew Length Mismatch

100

Mils

(1) Series terminator, if used, should be located closest to LPDDR.

(2) Center to center spacing is allowed to fall to minimum (w) for up to 500 mils of routed length to accommodate BGA escape and routing

congestion.

(3) Center to center spacing is allowed to fall to minimum (w) for up to 500 mils of routed length to accommodate BGA escape and routing

congestion.

(4) DQLM is the longest Manhattan distance of the DQS and DQ net classes.

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6.5 Video Interfaces

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6.5.1 Camera Interface

The camera subsystem provides the system interfaces and the processing capability to connect supported

YCbCr Interfaces to the OMAP3515/03 device. The camera subsystem supports up to two simultaneous

pixel flows but only one of them can use supported video processing hardware:

•

PARALLEL : the parallel interface data must go through the video processing hardware.

6.5.1.1 Parallel Camera Interface Timing

The parallel camera interface is a 12-bit interface which can be used in two modes:

1. SYNC mode: progressive and interlaced image sensor modules for 8-, 10-, 11-, and 12-bit data. The

pixel clock can be up to 75 MHz in 12-bit mode. The pixel clock can be up to 130 MHz in 8-bit packed

mode.

2. ITU mode provides an ITU-R BT 656 compatible data stream with progressive image sensor modules

only in 8- and 10-bit configurations. The pixel clock can be up to 75 MHz.

6.5.1.1.1 SYNC Normal Mode

6.5.1.1.1.1 12-Bit SYNC Normal – Progressive Mode

Table 6-23 and Table 6-24 assume testing over the recommended operating conditions and electrical

chaDSI Timing Conditionsracteristic conditions (see Figure 6-23).

Table 6-22. ISP Timing Conditions – 12-Bit SYNC Normal – Progressive Mode

TIMING CONDITION PARAMETER

Input Conditions

VALUE

UNIT

t_R

Input signal rise time

Input signal fall time

2.7

ns

t_F

Output Condition

C_LOAD

Output load capacitance

8.6

pF

Table 6-23. ISP Timing Requirements – 12-Bit SYNC Normal – Progressive Mode⁽¹⁾

NO.

PARAMETER

1.15 V

MAX

1.0 V

UNIT

MIN

MAX

ISP17

ISP18

t_c(pclk)

Cycle time⁽²⁾, cam_pclk period

Typical pulse duration, cam_pclk high

Typical pulse duration, cam_pclk low

Duty cycle error, cam_pclk

13.3

22.2

ns

ps

ns

t_W(pclkH)

t_W(pclkL)

t_dc(pclk)

t_j(pclk)

0.5*P⁽³⁾

667

133

1111

200

Cycle jitter⁽⁴⁾, cam_pclk

ISP19

ISP20

ISP21

t_su(dV-pclkH)

Setup time, cam_d[11:0] valid before cam_pclk rising

edge

1.82

3.25

t_h(pclkH-dV)

t_su(dV-vsH)

Hold time, cam_d[11:0] valid after cam_pclk rising

edge

ns

Setup time, cam_vs valid before cam_pclk rising

edge

ISP22

ISP23

t_h(pclkH-vsV)

t_su(dV-hsH)

Hold time, cam_vs valid after cam_pclk rising edge

1.82

3.25

ns

Setup time, cam_hs valid before cam_pclk rising

edge

(1) The timing requirements are assured for the cycle jitter and duty cycle error conditions specified.

(2) Related with the input maximum frequency supported by the ISP module.

(3) P = cam_pclk period in ns

(4) Maximum cycle jitter supported by cam_pclk input clock.

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Table 6-23. ISP Timing Requirements – 12-Bit SYNC Normal – Progressive Mode⁽¹⁾(continued)

NO.

PARAMETER

1.15 V

MAX

1.0 V

UNIT

MIN

1.82

MIN

3.25

MAX

ISP24

ISP25

t_h(pclkH-hsV)

t_su(dV-hsH)

Hold time, cam_hs valid after cam_pclk rising edge

ns

Setup time, cam_wen valid before cam_pclk rising

edge

ISP26

t_h(pclkH-hsV)

Hold time, cam_wen valid after cam_pclk rising edge

1.82

3.25

ns

Table 6-24. ISP Switching Characteristics – 12-Bit SYNC Normal – Progressive Mode

NO.

PARAMETER

1.15 V

1.0 V

UNIT

MIN

MAX

MIN

MAX

ISP15

ISP16

t_c(xclk)

Cycle time⁽¹⁾, cam_xclk period

Typical pulse duration, cam_xclk high

Typical pulse duration, cam_xclk low

Duty cycle error, cam_xclk

4.6

ns

ps

ns

t_W(xclkH)

t_W(xclkL)

t_dc(xclk)

t_j(xclk)

0.5*PO⁽²⁾

231

Jitter standard deviation⁽³⁾, cam_xclk

33

t_R(xclk)

t_F(xclk)

Rise time, cam_xclk

0.93

Fall time, cam_xclk

(1) Related with the cam_xclk maximum and minimum frequencies programmable in the ISP module.

Warning: The camera sensor or the camera module must be disabled to change the frequency configuration. For more information, see

the OMAP35x Technical Reference Manual (TRM) [literature number SPRUF98]

(2) PO = cam_xclk period in ns

(3) The jitter probability density can be approximated by a Gaussian function.

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ISP16

ISP15

ISP16

cam_xclki

ISP17

ISP18

cam_pclk

cam_vs

ISP19

ISP20

ISP22

ISP21

cam_hs

ISP23

D(n-1)

ISP24

D(1)

cam_d[11:0]

D(0)

D(n-3) D(n-2)

D(0)

D(n-1)

ISP25

ISP26

cam_wen

cam_fld

030-056

Figure 6-23. ISP – 12-Bit SYNC Normal – Progressive Mode(1) (2) (3) (4) (5) (6) (7) (8)

(1) The polarity of cam_pclk, cam_fld, cam_vs, and cam_hs are configurable. If the cam_hs, cam_vs, and cam_fld signals are output, the

signal length can be set.

(2) The parallel camera in SYNC mode supports progressive image sensor modules and 8-, 10-, 11-, or 12-bit data.

(3) When the image sensor has fewer than 12 data lines, it must be connected to the lower data lines and the unused lines must be

grounded.

(4) However, it is possible to shift the data to 0, 2, or 4 data internal lanes.

(5) The bit configurations are: cam_d[11:4] or cam_d[7:0] in 8-bit mode, cam_d[11:2] or cam_d[9:0] in 10-bit mode, cam_d[10:0] in 11-bit

mode, and cam_d[11:0] in 12-bit mode.

(6) Optionally, the data write to memory can be qualified by the external cam_wen signal.

(7) The cam_wen signal can be used as a external memory write-enable signal. The data is stored to memory only if cam_hs, cam_vs, and

cam_wen signals are asserted.

(8) In cam_xclki; I is equal to a or b.

6.5.1.1.1.2 8-bit Packed SYNC – Progressive Mode

Table 6-26 and Table 6-27 assume testing over the recommended operating conditions and electrical

characteristic conditions (see Figure 6-24).

Table 6-25. ISP Timing Conditions – 8-bit Packed SYNC – Progressive Mode

TIMING CONDITION PARAMETER

Input Conditions

VALUE

UNIT

t_R

t_F

Input signal rise time

Input signal fall time

2.5

ns

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Table 6-25. ISP Timing Conditions – 8-bit Packed SYNC – Progressive Mode (continued)

TIMING CONDITION PARAMETER

VALUE

UNIT

Output Conditions

C_LOAD

Output load capacitance

8.6

pF

Table 6-26. ISP Timing Requirements – 8-bit Packed SYNC – Progressive Mode⁽¹⁾

NO.

PARAMETER

1.15 V

MAX

1.0 V

UNIT

MIN

MAX

ISP3

ISP4

t_c(pclk)

Cycle time⁽²⁾, cam_pclk period

Typical pulse duration, cam_pclk high

Typical pulse duration, cam_pclk low

Duty cycle error, cam_pclk

7.7

15.4

ns

ps

ns

t_W(pclkH)

t_W(pclkL)

t_dc(pclk)

t_j(pclk)

0.5*P⁽³⁾

385

83

769

167

Cycle jitter⁽⁴⁾, cam_pclk

ISP5

ISP6

ISP7

t_su(dV-pclkH)

Setup time, cam_d[11:0] valid before cam_pclk

rising edge

1.08

2.27

t_h(pclkH-dV)

t_su(dV-vsH)

Hold time, cam_d[11:0] valid after cam_pclk rising

edge

ns

Setup time, cam_vs valid before cam_pclk rising

edge

ISP8

ISP9

t_h(pclkH-vsV)

t_su(dV-hsH)

Hold time, cam_vs valid after cam_pclk rising edge

1.08

2.27

ns

Setup time, cam_hs valid before cam_pclk rising

edge

ISP10

ISP11

t_h(pclkH-hsV)

t_su(dV-hsH)

Hold time, cam_hs valid after cam_pclk rising edge

1.08

2.27

ns

Setup time, cam_wen valid before cam_pclk rising

edge

ISP12

t_h(pclkH-hsV)

Hold time, cam_wen valid after cam_pclk rising edge

1.08

2.27

ns

(1) The timing requirements are assured for the cycle jitter and duty cycle error conditions specified.

(2) Related with the input maximum frequency supported by the ISP module.

(3) P = cam_pclk period in ns.

(4) Maximum cycle jitter supported by cam_pclk input clock.

Table 6-27. ISP Switching Characteristics – 8-bit packed SYNC – Progressive Mode

NO.

PARAMETER

1.15 V

1.0 V

UNIT

MIN

MAX

MIN

MAX

ISP1

ISP2

t_c(xclk)

Cycle time⁽¹⁾, cam_xclk period

Typical pulse duration, cam_xclk high

Typical pulse duration, cam_xclk low

Duty cycle error, cam_xclk

4.6

ns

ps

ns

t_W(xclkH)

t_W(xclkL)

t_dc(xclk)

t_j(xclk)

0.5*PO⁽²⁾

231

67

Jitter standard deviation⁽³⁾, cam_xclk

67

t_R(xclk)

t_F(xclk)

Rise time, cam_xclk

0.93

Fall time, cam_xclk

(1) Related with the cam_xclk maximum and minimum frequencies programmable in the ISP module.

Warning: You must disable the camera sensor or the camera module to change the frequency configuration. For more information, see

the OMAP35x Technical Reference Manual (TRM) [literature number SPRUF98]

(2) PO = cam_xclk period in ns

(3) The jitter probability density can be approximated by a Gaussian function.

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ISP1

ISP2

cam_xclki

ISP4

ISP3

ISP4

cam_pclk

cam_vs

ISP5

ISP6

ISP8

ISP7

cam_hs

ISP9

D(n-1)

ISP10

D(1)

cam_d[7:0]

D(0)

D(n-3) D(n-2)

D(0)

D(n-1)

ISP12

ISP11

cam_wen

cam_fld

030-059

Figure 6-24. ISP – 8-bit Packed SYNC – Progressive Mode(1) (2) (3) (4) (5)

(1) The polarity of cam_pclk, cam_fld, cam_vs, and cam_hs are configurable.

(2) The image sensor must be connected to the lower data lines and the unused lines must be grounded. However, it is possible to shift the

data to 0, 2, or 4 data internal lanes. The bit configurations are: cam_d[11:4] or cam_d[7:0] in 8-bit packed mode.

(3) Optionally, the data write to memory can be qualified by the external cam_wen signal. The cam_wen signal can be used as a external

memory write-enable signal. The data is stored to memory only if cam_hs, cam_vs, and cam_wen signals are asserted. The polarity of

cam_fld is programmable.

(4) The camera module can pack 8-bit data into 16 bits. It doubles the maximum pixel clock. This mode can be particularly useful to transfer

a YCbCr data stream or compressed stream to memory at very high speed.

(5) In cam_xclki; I is equal to a or b.

6.5.1.1.1.3 12-Bit SYNC Normal – Interlaced Mode

Table 6-29 and Table 6-30 assume testing over the recommended operating conditions and electrical

characteristic conditions (see Figure 6-25).

Table 6-28. ISP Timing Conditions – 12-Bit SYNC Normal – Interlaced Mode

TIMING CONDITION PARAMETER

Input Conditions

VALUE

UNIT

t_R

t_F

Input signal rise time

Input signal fall time

2.7

ns

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Table 6-28. ISP Timing Conditions – 12-Bit SYNC Normal – Interlaced Mode (continued)

TIMING CONDITION PARAMETER

VALUE

UNIT

Output Conditions

C_LOAD

Output load capacitance

8.6

pF

Table 6-29. ISP Timing Requirements – 12-Bit SYNC Normal – Interlaced Mode⁽¹⁾

NO.

PARAMETER

1.15 V

1.0 V

UNIT

MIN

MAX

MIN

MAX

ISP17

ISP18

t_c(pclk)

Cycle time⁽²⁾, cam_pclk period

Typical pulse duration, cam_pclk high

Typical pulse duration, cam_pclk low

Duty cycle error, cam_pclk

13.3

22.2

ns

ps

ns

t_W(pclkH)

t_W(pclkL)

t_dc(pclk)

t_j(pclk)

0.5*P⁽³⁾

667

133

1111

200

Cycle jitter⁽⁴⁾, cam_pclk

ISP19

ISP20

ISP21

t_su(dV-pclkH)

Setup time, cam_d[11:0] valid before cam_pclk

rising edge

1.82

3.25

t_h(pclkH-dV)

t_su(dV-vsH)

Hold time, cam_d[11:0] valid after cam_pclk rising

edge

3.25

ns

Setup time, cam_vs valid before cam_pclk rising

edge

ISP22

ISP23

t_h(pclkH-vsV)

t_su(dV-hsH)

Hold time, cam_vs valid after cam_pclk rising edge

1.82

3.25

ns

Setup time, cam_hs valid before cam_pclk rising

edge

ISP24

ISP25

t_h(pclkH-hsV)

t_su(dV-hsH)

Hold time, cam_hs valid after cam_pclk rising edge

1.82

3.25

ns

Setup time, cam_wen valid before cam_pclk rising

edge

ISP26

ISP27

ISP28

t_h(pclkH-hsV)

t_su(dV-fldH)

t_{h(pclkH-fldV)}

Hold time, cam_wen valid after cam_pclk rising

edge

1.82

3.25

ns

Setup time, cam_fld valid before cam_pclk rising

edge

Hold time, cam_fld valid after cam_pclk rising edge

(1) The timing requirements are assured for the cycle jitter and duty cycle error conditions specified.

(2) Related with the input maximum frequency supported by the ISP module.

(3) P = cam_lclk period in ns.

(4) Maximum cycle jitter supported by cam_pclk input clock.

Table 6-30. ISP Switching Characteristics – 12-Bit SYNC Normal – Interlaced Mode

NO.

PARAMETER

1.15 V

1.0 V

UNIT

MIN

MAX

MIN

MAX

ISP15

ISP16

t_c(xclk)

Cycle time⁽¹⁾, cam_xclk period

Typical pulse duration, cam_xclk high

Typical pulse duration, cam_xclk low

Duty cycle error, cam_xclk

4.6

ns

ps

ns

t_W(xclkH)

t_W(xclkL)

t_dc(xclk)

t_j(xclk)

0.5*PO⁽²⁾

231

Jitter standard deviation⁽³⁾, cam_xclk

33

t_R(xclk)

t_F(xclk)

Rise time, cam_xclk

0.93

Fall time, cam_xclk

(1) Related with the cam_xclk maximum and minimum frequencies programmable in the ISP module.

Warning: You must disable the camera sensor or the camera module to change the frequency configuration. For more information, see

the OMAP35x Technical Reference Manual (TRM) [literature number SPRUF98]

(2) PO = cam_xclk period in ns.

(3) The jitter probability density can be approximated by a Gaussian function.

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ISP16

ISP15

ISP16

cam_xclki

cam_pclk

ISP18

ISP17

ISP20

ISP19

cam_vs

cam_hs

FRAME(0)

ISP21

ISP22

L(0)

L(n-1)

L(0)

ISP23

D(1)

ISP24

D(n-1)

cam_d[11:0]

cam_wen

D(0)

D(n-3) D(n-2)

D(n-1)

D(0)

D(2)

ISP25

ISP26

ISP28

ISP27

cam_fld

PAIR

IMPAIR

030-057

Figure 6-25. ISP – 12-Bit SYNC Normal – Interlaced Mode(1) (2) (3) (4) (5) (6) (7) (8)

(1) The polarity of cam_pclk, cam_fld, cam_vs, and cam_hs are configurable. If the cam_hs, cam_vs, and cam_fld signals are output, the

signal length can be set.

(2) The parallel camera in SYNC mode supports interlaced image sensor modules and 8-, 10-, 11-, or 12-bit data.

(3) When the image sensor has fewer than 12 data lines, it must be connected to the lower data lines and the unused lines must be

grounded.

(4) It is possible to shift the data to 0, 2, or 4 data internal lanes.

(5) The bit configurations are: cam_d[11:4] or cam_d[7:0] in 8-bit mode, cam_d[11:2] or cam_d[9:0] in 10-bit mode, cam_d[10:0] in 11-bit

mode, and cam_d[11:0] in 12-bit mode.

(6) Optionally, the data write to memory can be qualified by the external cam_wen signal.

(7) The cam_wen signal can be used as a external memory write-enable signal. The data is stored to memory only if cam_hs, cam_vs, and

cam_wen signals are asserted.

(8) In cam_xclki; I is equal to a or b.

6.5.1.1.1.4 8-bit Packed SYNC – Interlaced Mode

Table 6-32 and Table 6-33 assume testing over the recommended operating conditions and electrical

characteristic conditions (see Figure 6-26).

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Table 6-31. ISP Timing Conditions – 8-bit Packed SYNC – Interlaced Mode

TIMING CONDITION PARAMETER

VALUE

UNIT

Input Conditions

t_R

Input signal rise time

Input signal fall time

2.5

ns

t_F

Output Conditions

C_LOAD

Output load capacitance

8.6

pF

Table 6-32. ISP Timing Requirements – 8-bit Packed SYNC – Interlaced Mode⁽¹⁾

NO.

PARAMETER

1.15 V

1.0 V

UNIT

MIN

MAX

MIN

MAX

ISP3

ISP4

t_c(pclk)

Cycle time⁽²⁾, cam_pclk period

Typical pulse duration, cam_pclk high

Typical pulse duration, cam_pclk low

Duty cycle error, cam_pclk

7.7

15.4

ns

ps

ns

t_W(pclkH)

t_W(pclkL)

t_dc(pclk)

t_j(pclk)

0.5*P⁽³⁾

385

83

769

167

Cycle jitter⁽⁴⁾, cam_pclk

ISP5

ISP6

ISP7

t_su(dV-pclkH)

Setup time, cam_d[11:0] valid before cam_pclk

rising edge

1.08

2.27

t_h(pclkH-dV)

t_su(dV-vsH)

Hold time, cam_d[11:0] valid after cam_pclk rising

edge

ns

Setup time, cam_vs valid before cam_pclk rising

edge

ISP8

ISP9

t_h(pclkH-vsV)

t_su(dV-hsH)

Hold time, cam_vs valid after cam_pclk rising edge

1.08

2.27

ns

Setup time, cam_hs valid before cam_pclk rising

edge

ISP10 t_h(pclkH-hsV)

ISP11 t_su(dV-hsH)

Hold time, cam_hs valid after cam_pclk rising edge

1.08

2.27

ns

Setup time, cam_wen valid before cam_pclk rising

edge

ISP12 t_h(pclkH-hsV)

ISP13 t_su(dV-fldH)

Hold time, cam_wen valid after cam_pclk rising edge

1.08

2.27

ns

Setup time, cam_fld valid before cam_pclk rising

edge

ISP14 t_{h(pclkH-fldV)}

Hold time, cam_fld valid after cam_pclk rising edge

1.08

2.27

ns

(1) The timing requirements are assured for the cycle jitter and duty cycle error conditions specified.

(2) Related with the input maximum frequency supported by the ISP module.

(3) P = cam_lclk period in ns.

(4) Maximum cycle jitter supported by cam_pclk input clock.

Table 6-33. ISP Switching Characteristics – 8-bit Packed SYNC – Interlaced Mode

NO.

PARAMETER

1.15 V

1.0 V

UNIT

MIN

MAX

MIN

MAX

ISP16

ISP2

t_c(xclk)

Cycle time⁽¹⁾, cam_xclk period

Typical pulse duration, cam_xclk high

Typical pulse duration, cam_xclk low

Duty cycle error, cam_xclk

4.6

ns

ps

ns

t_W(xclkH)

t_W(xclkL)

t_dc(xclk)

t_j(xclk)

0.5*PO⁽²⁾

231

Jitter standard deviation⁽³⁾, cam_xclk

67

t_R(xclk)

t_F(xclk)

Rise time, cam_xclk

0.93

Fall time, cam_xclk

(1) Related with the cam_xclk maximum and minimum frequencies programmable in the ISP module.

Warning: You must disable the camera sensor or the camera module to change the frequency configuration. For more information, see

the OMAP35x Technical Reference Manual (TRM) [literature number SPRUF98]

(2) PO = cam_xclk period in ns.

(3) The jitter probability density can be approximated by a Gaussian function.

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ISP2

ISP1

ISP2

cam_xclki

ISP4

ISP3

ISP4

cam_pclk

ISP6

ISP5

cam_vs

cam_hs

FRAME(0)

ISP7

ISP8

L(0)

L(n-1)

L(0)

ISP9

D(1)

ISP10

D(n-1)

cam_d[7:0]

cam_wen

D(0)

D(n-3)

D(n-2)

D(n-1)

D(0)

D(2)

ISP11

ISP12

ISP14

ISP13

cam_fld

PAIR

IMPAIR

030-060

Figure 6-26. ISP – 8-bit Packed SYNC – Interlaced Mode(1) (2) (3) (4) (10)

(1) The polarity of cam_pclk, cam_fld, cam_vs, and cam_hs are configurable.

(2) The image sensor must be connected to the lower data lines and the unused lines must be grounded. However, it is possible to shift the

data to 0, 2, or 4 data internal lanes. The bit configurations are: cam_d[11:4] or cam_d[7:0] in 8-bit packed mode.

(3) Optionally, the data write to memory can be qualified by the external cam_wen signal. The cam_wen signal can be used as a external

memory write-enable signal. The data is stored to memory only if cam_hs, cam_vs, and cam_wen signals are asserted.

(4) The camera module can pack 8-bit data into 16 bits. It doubles the maximum pixel clock. This mode can be particularly useful to transfer

a YCbCr data stream or compressed stream to memory at very high speed.

(5) In cam_xclki; I is equal to a or b.

6.5.1.1.2 ITU Mode

Table 6-35 and Table 6-36 assume testing over the recommended operating conditions and electrical

characteristic conditions (see Figure 6-27).

Table 6-34. ISP Timing Conditions – ITU Mode

TIMING CONDITION PARAMETER

Input Conditions

VALUE

UNIT

t_R

Input signal rise time

2.7

ns

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Table 6-34. ISP Timing Conditions – ITU Mode (continued)

TIMING CONDITION PARAMETER

VALUE

UNIT

t_F

Input signal fall time

2.7

ns

Output Conditions

C_LOAD

Output load capacitance

8.6

pF

Table 6-35. ISP Timing Requirements – ITU Mode⁽¹⁾

NO.

PARAMETER

1.15 V

1.0 V

UNIT

MIN

MAX

MIN

MAX

ISP17

ISP18

t_c(pclk)

Cycle time⁽²⁾, cam_pclk period

Typical pulse duration, cam_pclk high

Typical pulse duration, cam_pclk low

Duty cycle error, cam_pclk

13.3

22.2

ns

ps

ns

t_W(pclkH)

t_W(pclkL)

t_dc(pclk)

t_j(pclk)

0.5*P⁽³⁾

667

133

1111

200

Cycle jitter⁽⁴⁾, cam_pclk

ISP23

ISP24

t_su(dV-pclkH)

Setup time, cam_d[9:0] valid before cam_pclk

rising edge

1.82

3.25

t_h(pclkH-dV)

Hold time, cam_d[9:0] valid after cam_pclk rising

edge

ns

(1) The timing requirements are assured for the cycle jitter and duty cycle error conditions specified.

(2) Related with the input maximum frequency supported by the ISP module.

(3) P = cam_lclk period in ns.

(4) Maximum cycle jitter supported by cam_lclk input clock.

Table 6-36. ISP Switching Characteristics – ITU Mode

NO.

PARAMETER

1.15 V

1.0 V

UNIT

MIN

MAX

MIN

MAX

ISP15

ISP16

t_c(xclk)

Cycle time⁽¹⁾, cam_xclk period

Typical pulse duration, cam_xclk high

Typical pulse duration, cam_xclk low

Duty cycle error, cam_xclk

4.6

ns

ps

ns

t_W(xclkH)

t_W(xclkL)

t_dc(xclk)

t_j(xclk)

0.5*PO⁽²⁾

231

Jitter standard deviation⁽³⁾, cam_xclk

33

t_R(xclk)

t_F(xclk)

Rise time, cam_xclk

0.93

Fall time, cam_xclk

(1) Related with the cam_xclk maximum and minimum frequencies programmable in the ISP module.

Warning: The camera sensor or the camera module must be disabled to change the frequency configuration. For more information, see

the OMAP35x Technical Reference Manual (TRM) [literature number SPRUF98]

(2) PO = cam_xclk period in ns

(3) The jitter probability density can be approximated by a Gaussian function.

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ISP16

ISP15

ISP16

cam_xclki

cam_pclk

ISP17

ISP18

ISP23

D (0)

ISP24

D(0)

D(n-1)

cam_d[9:0]

SOF

EOF

SOF

EOF

030-058

Figure 6-27. ISP – ITU Mode(1) (2)

(1) The unused lines must be grounded and the data bus must be connected to the lower data lines. It is possible to shift the data to 0, 2, or

4 data internal lanes. The different configurations are: cam_d[11:4] or cam_d[7:0] in 8-bit mode and cam_d[11:2] or cam_d[9:0] in 10-bit

mode.

(2) The parallel camera in ITU mode supports progressive camera modules.

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6.5.2 Display Subsystem (DSS)

The display subsystem (DSS) provides the logic to display the video frame from external (SDRAM) or

internal (SRAM) memory on an LCD panel or a TV set. The DSS integrates a display controller, a remote

frame buffer module (RFBI), and a TV-out module. It can be used in two configurations:

•

LCD display in:

–

Bypass mode (RFBI module bypassed)

RFBI mode (through RFBI module)

•

TV display (not discussed in this document because of its analog IO signals)

The two displays can be active at the same time.

NOTE

For more information, see Display Subsystem / Display Subsystem Functional Description

section of the OMAP35x Technical Reference Manual (TRM) [literature number SPRUF98].

6.5.2.1 LCD Display in Bypass Mode

Two types of LCD panel are supported:

•

Thin film transistor (TFT) or active matrix technology

Supertwisted nematic (STN) or passive matrix technology

Both configurations are discussed in the following paragraphs.

6.5.2.1.1 LCD Display in TFT Mode

6.5.2.1.1.1 LCD Display in TFT Mode – HDTV Application

Table 6-37 assumes testing over the recommended operating conditions (see Figure 6-28).

Table 6-37. LCD Display Switching Characteristics in TFT Mode – HDTV Application^{(3) (4)}

NO.

PARAMETER

OPP3

OPP2

UNIT

MIN

MAX

MIN

MAX

DL0

DL1

DL2

DL3

t_{d(PCLKA-HSYNCT)}Delay time, dss_pclk active edge to dss_hsync

transition

–4.2

4.2

–4.7

4.7

ns

t_{d(PCLKA-VSYNCT)}Delay time, dss_pclk active edge to dss_vsync

transition

–4.2

4.2

–4.7

4.7

t_{d(PCLKA-ACBIASA)}Delay time, dss_pclk active edge to

dss_acbias active level

t_{d(PCLKA-DATAV)}

Delay time, dss_pclk active edge to dss_data

bus valid

–4.2

–4.7

DL4

DL5

t_c(PCLK)

t_w(PCLK)

Cycle time⁽²⁾, dss_pclk

13.468

0.45*P⁽¹⁾

15.152

0.45*P⁽¹⁾

ns

Pulse duration, dss_pclk low or high

0.55*P⁽¹⁾

(1) P = dss_pclk period.

(2) The pixel clock frequency is software programmable via the pixel clock divider configuration from 1 to 255 division range in the

DISPC_DIVISOR register.

(3) The capacitive load is equivalent to 25 pF at 1.15 V and 30 pF at 1.0 V.

(4) For more information, see the DSS chapter in the OMAP35x Technical Reference Manual (TRM) [literature number SPRUF98].

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DL5

DL4

dss_pclk

DL1

dss_vsync

DL0

dss_hsync

DL2

dss_acbias

DL3

dss_data[23:0]

030-061

Figure 6-28. LCD Display in TFT Mode – HDTV Application(1) (2) (3) (4)

(1) The pixel data bus depends on the use of 8-, 9-, 12-, 16-, 18-, or 24-bit per pixel data output pins.

(2) The pixel clock frequency is programmable.

(3) All timings not illustrated in the waveform are programmable by software, control signal polarity, and driven edge of dss_pclk.

(4) For more information, see the DSS chapter in the OMAP35x Technical Reference Manual (TRM) [literature number SPRUF98].

6.5.2.1.2 LCD Display in STN Mode

Table 6-38 assumes testing over the recommended operating conditions (see Figure 6-29).

Table 6-38. LCD Display Switching Characteristics in STN Mode^{(3) (4) (5)}

NO.

PARAMETER

OPP3

OPP2

UNIT

MIN

MAX

MIN

MAX

DL3

t_{d(PCLKA-DATAV)}

Delay time, dss_pclk active edge to dss_data

bus valid

–6.9

6.9

–6.9

6.9

ns

DL4

DL5

t_c(PCLK)

t_w(PCLK)

Cycle time⁽²⁾, dss_pclk

22.727

ns

Pulse duration, dss_pclk low or high

0.45*P⁽¹⁾0.55*P⁽¹⁾0.45*P⁽¹⁾0.55*P⁽¹⁾

(1) P = dss_pclk period.

(2) The pixel clock frequency is software programmable via the pixel clock divider configuration from 1 to 255 division range in the

DISPC_DIVISOR register.

(3) The DSS in STN mode is used with 4 or 8 pins only; unused pixel data bits always remain low.

(4) The capacitive load is equivalent to 40 pF.

(5) For more information, see the DSS chapter in the OMAP35x Technical Reference Manual (TRM) [literature number SPRUF98].

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DL5

DL4

dss_pclk

dss_vsync

dss_hsync

dss_acbias

DL3

dss_data[23:0]

030-062

Figure 6-29. LCD Display in STN Mode(1) (2) (3) (4) (5)

(1) The pixel data bus depends on the use 4-, 8-, 12-, 16-, 18-, or 24-bit per pixel data output pins.

(2) All timings not illustrated in the waveform are programmable by software, control signal polarity, and driven edge of dss_pclk.

(3) dss_vsync width must be programmed to be as small as possible.

(4) The pixel clock frequency is programmable.

(5) For more information, see the DSS chapter in the OMAP35x Technical Reference Manual (TRM) [literature number SPRUF98].

6.5.2.2 LCD Display in RFBI Mode

Table 6-40 and Table 6-41 assume testing over the recommended operating conditions (see Figure 6-30

through Figure 6-32).

Table 6-39. LCD Timing Conditions – RFBI Mode

TIMING CONDITION PARAMETER

VALUE

UNIT

MIN

MAX

Input Conditions

t_R

t_F

Input signal rise time

Input signal fall time

15

ns

Output Conditions

C_LOAD

Output load capacitance

30

pF

Table 6-40. LCD Display Timing Requirements in RFBI Mode

NO.

PARAMETER

OPP3

MAX

OPP2

MAX

OPP1⁽¹⁾

MIN MAX

UNIT

MIN

DR0

DR1

t_su(DAV-RDH)

t_h(RDH-DAIV)

Setup time, rfbi_da[15:0] valid to rfbi_rd

high

7.0

9.0

ns

Hold time, rfbi_rd high to rfbi_da[15:0]

invalid

5.0

t_{d(Data sampled)}rfbi_da[15:0] are sampled at the end off

the access time

N⁽²⁾

(1) Cannot boot in OPP1. If OPP1 is desired, boot in higher OPP then switch to OPP1.

(2) N = (AccessTime) * (TimeParaGranularity + 1) * L4CLK

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UNIT

Table 6-41. LCD Display Switching Characteristics in RFBI Mode

PARAMETER

OPP3

OPP2

OPP1⁽¹⁾

MIN MAX

MIN

MAX

MIN

MAX

t_{w(rfbi_wrH)}

Pulse duration, rfbi_wr high

Pulse duration, rfbi_wr low

A⁽²⁾

B⁽³⁾

C⁽⁴⁾

A⁽²⁾

B⁽³⁾

C⁽⁴⁾

ns

t_{w(rfbi_wrL)}

t_{d(rfbi_a0-rfbi_wrL)}

Delay time, rfbi_a0 transition to rfbi_wr

low

t_{d(rfbi_wrH-rfbi_a0)}

Delay time, rfbi_wr high to rfbi_a0

transition

D⁽⁵⁾

ns

t_{d(rfbi_csx-rfbi_wrL)}

t_{d(rfbi_wrH-rfbi_csxH)}

Delay time, rfbi_csx⁽¹⁵⁾low to rfbi_wr low

Delay time, rfbi_wr high to rfbi_csx⁽¹⁵⁾

high

E⁽⁶⁾

F⁽⁷⁾

E⁽⁶⁾

F⁽⁷⁾

ns

t_d(dataV)

rfbi_da[15:0] valid

G⁽⁸⁾

H⁽⁹⁾

I⁽¹⁰⁾

G⁽⁸⁾

H⁽⁹⁾

I⁽¹⁰⁾

ns

t_{d(rfbi_a0H-rfbi_rdL)}

t_{d(rfbi_rdlH-rfbi_a0)}

Delay time, rfbi_a0 high to rfbi_rd low

Delay time, rfbi_rd high to rfbi_a0

transition

t_{w(rfbi_rdH)}

Pulse duration, rfbi_rd high

J⁽¹¹⁾

K⁽¹²⁾

L⁽¹³⁾

M⁽¹⁴⁾

J⁽¹¹⁾

K⁽¹²⁾

L⁽¹³⁾

M⁽¹⁴⁾

ns

t_{w(rfbi_rdL)}

Pulse duration, rfbi_rd low

Delay time, rfbi_rd low to rfbi_csx⁽¹⁵⁾low

Delay time, rfbi_rd high to rfbi_csx⁽¹⁵⁾

high

t_{d(rfbi_rdL-rfbi_csxL)}

t_{d(rfbi_rdH-rfbi_csxH)}

t_{R(rfbi_wr)}

Rise time, rfbi_wr

Fall time, rfbi_wr

10

ns

t_{F(rfbi_wr)}

t_{R(rfbi_a0)}

t_{F(rfbi_a0)}

Rise time, rfbi_a0

Fall time, rfbi_a0

t_{R(rfbi_csx)}

t_{F(rfbi_csx)}

t_{R(rfbi_da[15:0])}

t_{F(rfbi_da[15:0])}

t_{R(rfbi_rd)}

Rise time, rfbi_csx⁽¹⁵⁾

Fall time, rfbi_csx⁽¹⁵⁾

Rise time, rfbi_da[15:0]

Fall time, rfbi_da[15:0]

Rise time, rfbi_rd

t_{F(rfbi_rd)}

Fall time, rfbi_rd

(1) Cannot boot in OPP1. If OPP1 is desired, boot in higher OPP then switch to OPP1.

(2) A = (WECycleTime – WEOffTime) * (TimeParaGranularity + 1) * L4CLK

(3) B = (WEOffTime – WEOntime) * (TimeParaGranularity + 1) * L4CLK

(4) C = WEOnTime * (TimeParaGranularity + 1) * L4CLK

(5) D = (WECycleTime + CSPulseWidth – WEOffTime) * (TimeParaGranularity + 1) * L4CLK

if mode Write to Read or Read to Write is enabled

(6) E = (WEOnTime – CSOnTime) * (TimeParaGranularity + 1) * L4CLK

(7) F = (CSOffTime – WEOffTime) * (TimeParaGranularity + 1) * L4CLK

(8) G = (WECycleTime) * (TimeParaGranularity + 1) * L4CLK

(9) H = (REOnTime) * (TimeParaGranularity + 1) * L4CLK

(10) I = (RECycleTime + CSPulseWidth – REOffTime) * (TimeParaGranularity + 1) * L4CLK

if mode Write to Read or Read to Write is enabled

(11) J = (RECycleTime – REOffTime) * (TimeParaGranularity + 1) * L4CLK

(12) K = (REOffTime – REOntime) * (TimeParaGranularity + 1) * L4CLK

(13) L = (REOnTime – CSOnTime) * (TimeParaGranularity + 1) * L4CLK

(14) M = (CSOffTime – REOffTime) * (TimeParaGranularity + 1) * L4CLK

(15) In rfbi_csx, x stands for 0 or 1.

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CsPulseWidth

WeCycleTime

CsOffTime

rfbi_a0

CsOffTime

CsOnTime

rfbi_csx

WeOffTime

WeOnTime

WeOffTime

WeOnTime

rfbi_wr

rfbi_da[15:0]

rfbi_rd

DATA0

DATA1

034-002

Figure 6-30. LCD Display in RFBI Mode – Command / Data Write Mode(1) (2)

(1) In rfbi_csx, x is equal to 0 or 1.

(2) For more information, see the DSS chapter in the OMAP35x Technical Reference Manual (TRM) [literature number SPRUF98] .

AccessTime

ReCycleTime

CsPulseWidth

AccessTime

ReCycleTime

rfbi_a0

CsOffTime

CsOnTime

CsOffTime

CsOnTime

rfbi_csx

rfbi_rd

ReOffTime

ReOnTime

ReOffTime

ReOnTime

DR1

DR0

DATA0

rfbi_da[15:0]

rfbi_wr

DATA1

034-003

Figure 6-31. LCD Display in RFBI Mode – Data Read Mode(1) (2)

(1) In rfbi_csx, x is equal to 0 or 1.

(2) For more information, see the DSS chapter in the OMAP35x Technical Reference Manual (TRM) [literature number SPRUF98].

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WeCycleTime

ReCycleTime

AccessTime

WeCycleTime

rfbi_a0

CsOffTime

CsOnTime

CsOffTime

CsOnTime

CsOffTime

CsOnTime

rfbi_csx

rfbi_wr

WeOffTime

WeOnTime

WeOffTime

WeOnTime

ReOffTime

ReOnTime

rfbi_rd

CsPulseWidth

WRITE

READ

rfbi_da[15:0]

WRITE

034-004

Figure 6-32. LCD Display in RFBI Mode – Command / Data Write-to-Read and Read-to-Write Timing

Modes(1) (2)

(1) In rfbi_csx, x is equal to 0 or 1.

(2) For more information, see the DSS chapter in the OMAP35x Technical Reference Manual (TRM) [literature number SPRUF98].

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6.6 Serial Communications Interfaces

6.6.1 Multichannel Buffered Serial Port (McBSP) Timing

There are five McBSP modules called McBSP1 through McBSP5. McBSP provides a full-duplex, direct

serial interface between the OMAP3515/03 device and other devices in a system such as other

application devices or codecs. It can accommodate a wide range of peripherals and clocked frame-

oriented protocols (I2S, PCM, and TDM) due to its high level of versatility.

The McBSP1-5 modules may support two types of data transfer at the system level:

•

The full-cycle mode, for which one clock period is used to transfer the data, generated on one edge

and captured on the same edge (one clock period later).

•

The half-cycle mode, for which one half clock period is used to transfer the data, generated on one

edge and captured on the opposite edge (one half clock period later). Note that a new data is

generated only every clock period, which secures the required hold time.

The interface clock (CLKX/CLKR) activation edge (data/frame sync capture and generation) has to be

configured accordingly with the external peripheral (activation edge capability) and the type of data

transfer required at the system level.

The OMAP3515/03 McBSP1-5 timing characteristics are described for both rising and falling activation

edges. McBSP1 supports:

•

6-pin mode: dx and dr as data pins; clkx, clkr, fsx, and fsr as control pins.

4-pin mode: dx and dr as data pins; clkx and fsx pins as control pins. The clkx and fsx pins are

internally looped back via software configuration, respectively, to the clkr and fsr internal signals for

data receive.

McBSP2, 3, 4, and 5 support only the 4-pin mode.

The following sections describe the timing characteristics for applications in normal mode (that is,

OMAP3515/03 McBSPx connected to one peripheral) and TDM applications in multipoint mode.

6.6.1.1 McBSP in Normal Mode

Table 6-42. McBSP Timing Conditions—Normal Mode

TIMING CONDITION PARAMETER

Input Conditions

VALUE

UNIT

t_R

Input signal rise time

Input signal fall time

2

ns

t_F

Output Conditions

C_LOAD

Output load capacitance

10

pF

Table 6-43. McBSP Output Clock Pulse Duration

NO.

PARAMETER

OPP3

OPP2

UNIT

MIN

MAX

MIN

MAX

Inputs and Outputs

McBSP1 t_c(CLK)

Cycle time, mcbsp1_clkx / mcbsp1_clkr (multiplexing mode

0)

20.83

41.67

ns

McBSP2 t_c(CLK)

McBSP3 t_c(CLK)

Cycle time, mcbsp2_clkx (multiplexing mode 0)

20.83

31.25

20.83

31.25

41.67

62.50

41.67

62.50

ns

Cycle time,

mcbsp3_clkx

IO set 1 (multiplexing mode 0)

IO set 2 (multiplexing mode 1)

IO set 3 (multiplexing mode 2)

IO set 1 (multiplexing mode 0)

IO set 2 (multiplexing mode 2)

McBSP4 t_c(CLK)

Cycle time,

mcbsp4_clkx

ns

McBSP5 t_c(CLK)

Cycle time, mcbsp5_clkx (multiplexing mode 1)

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UNIT

Table 6-43. McBSP Output Clock Pulse Duration (continued)

NO.

PARAMETER

OPP3

OPP2

MIN

MAX

MIN

MAX

Outputs

t_w(CLKH)

t_w(CLKL)

t_dc(CLK)

Typical pulse duration, mcbsp1_clkr / mcbspx_clkx high⁽²⁾

Typical pulse duration, mcbsp1_clkr / mcbspx_clkx low⁽²⁾

Duty cycle error, mcbsp1_clkr / mcbspx_clkx⁽²⁾

0.5*P⁽¹⁾

ns

–0.75

0.75

–0.75

0.75

(1) P = mcbsp1_clkr / mcbspx_clkx clock period.

(2) In mcbspx, x identifies the McBSP number: 1, 2, 3, 4, or 5.

6.6.1.1.1 Receive Timing with Rising Edge as Activation Edge

Table 6-44 through Table 6-49 assume testing over the recommended operating conditions (see Figure 6-

33 through Figure 6-34).

Table 6-44. McBSP1, 2, and 3 (Sets #2 and #3) Timing Requirements – Rising Edge and Receive Mode⁽¹⁾

NO.

PARAMETER

1.15 V

MIN MAX

1.0 V

MIN MAX

UNIT

B3

t_{su(DRV-CLKAE)}

Setup time, mcbspx_dr valid before mcbsp1_clkr /

mcbspx_clkx active edge

Master

Slave

3.5

3.7

1

7.7

7.9

1

ns

B4

t_h(CLKAE-DRV)

Hold time, mcbspx_dr valid after mcbsp1_clkr /

mcbspx_clkx active edge

Master

Slave

0.4

3.7

0.4

7.9

B5

B6

t_{su(FSV-CLKAE)}

t_h(CLKAE-FSV)

Setup time, mcbsp1_fsr / mcbspx_fsx valid before mcbsp1_clkr /

mcbspx_clkx active edge

Hold time, mcbsp1_fsr / mcbspx_fsx valid after mcbsp1_clkr /

mcbspx_clkx active edge

0.5

ns

(1) In mcbspx, x identifies the McBSP number: 1, 2, or 3. Note that for the McBSP3, these timings concern only Set #2 (multiplexing mode

on UART pins) and Set #3 (multiplexing mode on McBSP1 pins).

Table 6-45. McBSP1, 2, and 3 (Sets #2 and #3) Switching Characteristics – Rising Edge and Receive

Mode⁽¹⁾

NO.

PARAMETER

1.15 V

1.0 V

UNIT

MIN

0.7

MAX

MIN

0.7

MAX

B2

t_d(CLKAE-FSV)

Delay time, mcbsp1_clkr / mcbspx_clkx active edge to mcbsp1_fsr /

mcbspx_fsx valid

14.8

29.6

ns

(1) In mcbspx, x identifies the McBSP number: 1, 2, or 3. Note that for the McBSP3, these timings concern only Set #2 (multiplexing mode

on UART pins) and Set #3 (multiplexing mode on McBSP1 pins).

Table 6-46. McBSP4 (Set #1) Timing Requirements – Rising Edge and Receive Mode⁽¹⁾

NO.

B3

PARAMETER

1.15 V

MIN MAX

1.0 V

MIN MAX

UNIT

t_{su(DRV-CLKXAE)}

Setup time, mcbspx_dr valid before

mcbspx_clkx active edge

Master

Slave

2.7

3.7

1

7.7

7.9

1

ns

B4

t_{h(CLKXAE-DRV)}

Hold time, mcbspx_dr valid after mcbspx_clkx

active edge

Master

Slave

0.4

3.7

0.5

0.4

7.9

0.5

B5

B6

t_{su(FSXV-CLKXAE)}

t_{h(CLKXAE-FSXV)}

Setup time mcbspx_fsx valid before mcbspx_clkx active edge

Hold Time mcbspx_fsx valid after mcbspx_clkx active edge

(1) In mcbspx, x identifies the McBSP number: 4. Note that for the McBSP4, these timings concern only Set #1: multiplexing mode by

default. The McBSP4 is also multiplexed on GPMC pins (Set #2): the corresponding timings are specified in Table 6-48 and Table 6-49

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Table 6-47. McBSP4 (Set #1) Switching Characteristics – Rising Edge and Receive Mode⁽¹⁾

NO.

PARAMETER

1.15 V

1.0 V

UNIT

MIN

0.7

MAX

MIN MAX

B2

t_{d(CLKXAE-FSXV)}

Delay time, mcbspx_clkx active edge to mcbspx_fsx valid

16.6

0.7

33.1

ns

(1) In mcbspx, x identifies the McBSP number: 4. Note that for the McBSP4, these timings concern only Set #1: multiplexing mode by

default. The McBSP4 is also multiplexed on GPMC pins (Set #2): the corresponding timings are specified in Table 6-48 and Table 6-49

Table 6-48. McBSP3 (Set #1), 4 (Set #2), and 5 Timing Requirements – Rising Edge and Receive Mode⁽¹⁾

NO.

PARAMETER

1.15 V

MIN MAX

1.0 V

MIN MAX

UNIT

B3

t_{su(DRV-CLKXAE)}

Setup time, mcbspx_dr valid before

mcbspx_clkx active edge

Master

Slave

5.6

5.8

1

12

12.2

1

ns

B4

t_{h(CLKXAE-DRV)}

Hold time, mcbspx_dr valid after mcbspx_clkx Master

active edge

Slave

0.4

5.8

0.5

0.4

12.2

0.5

B5

B6

t_{su(FSXV-CLKXAE)}

t_{h(CLKXAE-FSXV)}

Setup time, mcbspx_fsx valid before mcbspx_clkx active edge

Hold time, mcbspx_fsx valid after mcbspx_clkx active edge

(1) In mcbspx, x identifies the McBSP number: 3, 4, or 5. Note that for the McBSP3, these timings concern only Set #1: multiplexing mode

by default. The McBSP3 is also multiplexed on UART pins (Set #2) and on McBSP1 pins (Set #3): the corresponding timings are

specified in Table 6-46 and Table 6-47.

For the McBSP4, these timings concern only Set #2 (multiplexing mode on GPMC pins).

Table 6-49. McBSP3 (Set #1), 4 (Set #2), and 5 Switching Requirements – Rising Edge and Receive

Mode⁽¹⁾

NO.

PARAMETER

1.15 V

1.0 V

MAX

44.4

UNIT

MIN

0.7

MAX

MIN

B2

t_{d(CLKXAE-FSXV)}

Delay time, mcbspx_clkx active edge to mcbspx_fsx valid

22.2

0.7

ns

(1) In mcbspx, x identifies the McBSP number: 3, 4, or 5. Note that for the McBSP3, these timings concern only Set #1: multiplexing mode

by default. The McBSP3 is also multiplexed on UART pins (Set #2) and on McBSP1 pins (Set #3): the corresponding timings are

specified in Table 6-46 and Table 6-47.

For the McBSP4, these timings concern only Set #2 (multiplexing mode on GPMC pins).

mcbspx_clkr

B2

mcbspx_fsr

mcbspx_dr

B3

B4

D7

D6

D5

030-068

Figure 6-33. McBSP Rising Edge Receive Timing in Master Mode

mcbspx_clkr

mcbspx_fsr

mcbspx_dr

B5

B6

B3

B4

D7

D6

D5

030-069

Figure 6-34. McBSP Rising Edge Receive Timing in Slave Mode

6.6.1.1.2 Transmit Timing with Rising Edge as Activation Edge

Table 6-50 through Table 6-55 assume testing over the recommended operating conditions (see Figure 6-

35 and Figure 6-36).

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Table 6-50. McBSP1, 2, and 3 (Sets #2 and #3) Timing Requirements – Rising Edge and Transmit Mode⁽¹⁾

NO.

PARAMETER

1.15 V

MAX

1.0 V

UNIT

MIN

MAX

B5

B6

t_{su(FSXV-CLKXAE)}

t_{h(CLKXAE-FSXV)}

Setup time, mcbspx_fsx valid before mcbspx_clkx

active edge

3.7

7.9

ns

Hold time, mcbspx_fsx valid after mcbspx_clkx active

edge

0.5

(1) In mcbspx, x identifies the McBSP number: 1, 2, or 3. Note that for the McBSP3, these timings concern only Set #2 (multiplexing mode

on UART pins) and Set #3 (multiplexing mode on McBSP1 pins).

Table 6-51. McBSP1, 2, and 3 (Sets #2 and #3) Switching Characteristics – Rising Edge and Transmit

Mode⁽¹⁾

NO.

PARAMETER

1.15 V

1.0 V

UNIT

MIN

MAX

MIN

MAX

B2

B8

t_{d(CLKXAE-FSXV)}

t_{d(CLKXAE-DXV)}

Delay time, mcbspx_clkx active edge to mcbspx_fsx

valid

0.7

14.8

0.7

29.6

ns

Delay time, mcbspx_clkx active edge to Master

0.6

14.8

0.6

29.6

ns

mcbspx_dx valid

Slave

(1) In mcbspx, x identifies the McBSP number: 1, 2, or 3. Note that for the McBSP3, these timings concern only Set #2 (multiplexing mode

on UART pins) and Set #3 (multiplexing mode on McBSP1 pins).

Table 6-52. McBSP4 (Set #1) Timing Requirements – Rising Edge and Transmit Mode⁽¹⁾

NO.

PARAMETER

1.15 V

MAX

1.0 V

UNIT

MIN

MAX

B5

B6

t_{su(FSXV-CLKXAE)}

t_{h(CLKXAE-FSXV)}

Setup time, mcbspx_fsx valid before mcbspx_clkx

active edge

3.7

7.9

ns

Hold time, mcbspx_fsx valid after mcbspx_clkx active

edge

0.5

(1) In mcbspx, x identifies the McBSP number: 4. Note that for the McBSP4, these timings concern only Set #1: multiplexing mode by

default. The McBSP4 is also multiplexed on GPMC pins (Set #2): the corresponding timings are specified in Table 6-54.

Table 6-53. McBSP4 (Set #1) Switching Characteristics – Rising Edge and Transmit Mode⁽¹⁾

NO.

PARAMETER

1.15 V

1.0 V

UNIT

MIN

MAX

MIN

MAX

B2

B8

t_{d(CLKXAE-FSXV)}

t_{d(CLKXAE-DXV)}

Delay time, mcbspx_clkx active edge to

mcbspx_fsx valid

0.7

16.6

0.7

33.1

ns

Delay time, mcbspx_clkx active edge

to mcbspx_dx valid

Master

Slave

0.6

16.6

17.3

0.6

33.1

ns

(1) In mcbspx, x identifies the McBSP number: 4. Note that for the McBSP4, these timings concern only Set #1: multiplexing mode by

default. The McBSP4 is also multiplexed on GPMC pins (Set #2): the corresponding timings are specified in Table 6-54.

Table 6-54. McBSP3 (Set #1), 4 (Set #2), and 5 Timing Requirements – Rising Edge and Transmit Mode⁽¹⁾

NO.

PARAMETER

1.15 V

MAX

1.0 V

UNIT

MIN

MAX

B5

B6

t_{su(FSXV-CLKXAE)}

t_{h(CLKXAE-FSXV)}

Setup time, mcbspx_fsx valid before mcbspx_clkx

active edge

5.8

12.2

ns

Hold time, mcbspx_fsx valid after mcbspx_clkx active

edge

0.5

(1) In mcbspx, x identifies the McBSP number: 4. Note that for the McBSP4, these timings concern only Set #1: multiplexing mode by

default. The McBSP4 is also multiplexed on GPMC pins (Set #2): the corresponding timings are specified in Table 6-54.

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Table 6-55. McBSP 3 (Set #1), 4 (Set #2), and 5 Switching Requirements – Rising Edge and Transmit

Mode⁽¹⁾

NO.

PARAMETER

1.15 V

1.0 V

UNIT

MIN

MAX

MIN

MAX

B2

B8

t_{d(CLKXAE-FSXV)}

t_{d(CLKXAE-DXV)}

Delay time, mcbspx_clkx active edge to mcbspx_fsx

valid

0.7

22.2

0.7

44.4

ns

Delay time, mcbspx_clkx active edge to Master

0.6

22.2

0.6

44.4

ns

mcbspx_dx valid

Slave

(1) In mcbspx, x identifies the McBSP number: 3, 4 or 5. Note that for the McBSP3, these timings concern only Set #1: multiplexing mode

by default. The McBSP3 is also multiplexed on UART pins (Set #2) and on McBSP1 pins (Set #3): the corresponding timings are

specified in the table above. For the McBSP4, these timings concern only Set #2 (multiplexing mode on GPMC pins).

mcbspx_clkx

B2

B8

mcbspx_fsx

mcbspx_dx

D7

D6

D5

030-070

Figure 6-35. McBSP Rising Edge Transmit Timing in Master Mode

mcbspx_clkx

mcbspx_fsx

mcbspx_dx

B5

B6

B8

D7

D6

D5

030-071

Figure 6-36. McBSP Rising Edge Transmit Timing in Slave Mode

6.6.1.1.3 Receive Timing with Falling Edge as Activation Edge

Table 6-56 through Table 6-61 assume testing over the recommended operating conditions (see Figure 6-

37 and Figure 6-38).

Table 6-56. McBSP1, 2, and 3 (Sets #2 and #3) Timing Requirements – Falling Edge and Receive Mode⁽¹⁾

NO.

PARAMETER

1.15 V

MAX

1.0 V

UNIT

MIN

3.5

3.7

1

MIN

7.7

7.9

1

MAX

B3

t_{su(DRV-CLKAE)}

Setup time, mcbspx_dr valid before

mcbsp1_clkr / mcbspx_clkx active edge

Master

Slave

ns

B4

t_h(CLKAE-DRV)

Hold time, mcbspx_dr valid after

mcbsp1_clkr / mcbspx_clkx active edge

Master

Slave

0.4

3.7

0.4

7.9

B5

B6

t_{su(FSV-CLKAE)}

t_h(CLKAE-FSV)

Setup time, mcbsp1_fsr / mcbspx_fsx valid before

mcbsp1_clkr /mcbspx_clkx active edge

Hold time, mcbsp1_fsr / mcbspx_fsx valid after

mcbsp1_clkr /mcbspx_clkx active edge

0.5

ns

(1) In mcbspx, x identifies the McBSP number: 1, 2, or 3. Note that for the McBSP3, these timings concern only Set #2 (multiplexing mode

on UART pins) and Set #3 (multiplexing mode on McBSP1 pins).

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Table 6-57. McBSP1, 2, and 3 (Sets #2 and #3) Switching Characteristics – Falling Edge and Receive

Mode⁽¹⁾

NO.

PARAMETER

1.15 V

1.0 V

UNIT

MIN

MAX

MIN

MAX

B2

t_d(CLKAE-FSV)

Delay time, mcbsp1_clkr / mcbspx_clkx active edge to

mcbsp1_fsr / mcbspx_fsx valid

0.7

14.8

0.7

29.6

ns

(1) In mcbspx, x identifies the McBSP number: 1, 2, or 3. Note that for the McBSP3, these timings concern only Set #2 (multiplexing mode

on UART pins) and Set #3 (multiplexing mode on McBSP1 pins).

Table 6-58. McBSP4 (Set #1) Timing Requirements – Falling Edge and Receive Mode⁽¹⁾

NO.

B3

PARAMETER

1.15 V

MAX

1.0 V

UNIT

MIN

2.7

3.7

1

MIN

7.7

7.9

1

MAX

t_{su(DRV-CLKXAE)}

Setup time, mcbspx_dr valid before

mcbspx_clkx active edge

Master

Slave

ns

B4

t_{h(CLKXAE-DRV)}

Hold time, mcbspx_dr valid after

mcbspx_clkx active edge

Master

Slave

0.4

3.7

0.4

7.9

B5

B6

t_{su(FSXV-CLKXAE)}

t_{h(CLKXAE-FSXV)}

Setup time mcbspx_fsx valid before mcbspx_clkx active

edge

Hold time mcbspx_fsx valid after mcbspx_clkx active

edge

0.5

ns

(1) In mcbspx, x identifies the McBSP number: 4. Note that for the McBSP4, these timings concern only Set #1: multiplexing mode by

default. The McBSP4 is also multiplexed on GPMC pins (Set #2): the corresponding timings are specified in Table 6-60

Table 6-59. McBSP4 (Set #1) Switching Characteristics – Falling Edge and Receive Mode⁽¹⁾

NO.

PARAMETER

1.15 V

MAX

16.6

1.0 V

UNIT

MIN

MAX

B2

t_{d(CLKXAE-FSXV)}

Delay time, mcbspx_clkx active edge to mcbspx_fsx valid

0.7

33.1

ns

(1) In mcbspx, x identifies the McBSP number: 4. Note that for the McBSP4, these timings concern only Set #1: multiplexing mode by

default. The McBSP4 is also multiplexed on GPMC pins (Set #2): the corresponding timings are specified in Table 6-60

Table 6-60. McBSP3 (Set #1), 4 (Set #2), and 5 Timing Requirements – Falling Edge and Receive Mode⁽¹⁾

NO.

PARAMETER

1.15 V

MAX

1.0 V

UNIT

MIN

5.6

5.8

1

MIN

12

MAX

B3

t_{su(DRV-CLKXAE)}

Setup time, mcbspx_dr valid before

mcbspx_clkx active edge

Master

Slave

ns

12.2

1

B4

t_{h(CLKXAE-DRV)}

Hold time, mcbspx_dr valid after mcbspx_clkx Master

active edge

Slave

0.4

5.8

0.4

12.2

B5

B6

t_{su(FSXV-CLKXAE)}Setup time, mcbspx_fsx valid before mcbspx_clkx active

edge

t_{h(CLKXAE-FSXV)}

Hold time, mcbspx_fsx valid after mcbspx_clkx active

edge

0.5

ns

(1) In mcbspx, x identifies the McBSP number: 3, 4, or 5. Note that for the McBSP3, these timings concern only Set #1: multiplexing mode

by default. The McBSP3 is also multiplexed on UART pins (Set #2) and on McBSP1 pins (Set #3): the corresponding timings are

specified in the table above. For the McBSP4, these timings concern only Set #2 (multiplexing mode on GPMC pins).

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Table 6-61. McBSP3 (Set #1), 4 (Set #2), and 5 Switching Requirements – Falling Edge and Receive

Mode⁽¹⁾

NO.

PARAMETER

1.15 V

1.0 V

UNIT

MIN

MAX

MIN

MAX

B2

t_{d(CLKXAE-FSXV)}

Delay time, mcbspx_clkx active edge to mcbspx_fsx

valid

0.7

22.2

0.7

44.4

ns

(1) In mcbspx, x identifies the McBSP number: 3, 4, or 5. Note that for the McBSP3, these timings concern only Set #1: multiplexing mode

by default. The McBSP3 is also multiplexed on UART pins (Set #2) and on McBSP1 pins (Set #3): the corresponding timings are

specified in the table above. For the McBSP4, these timings concern only Set #2 (multiplexing mode on GPMC pins).

mcbspx_clkr

B2

mcbspx_fsr

mcbspx_dr

B3

B4

D7

D6

D5

030-072

Figure 6-37. McBSP Falling Edge Receive Timing in Master Mode

mcbspx_clkr

mcbspx_fsr

mcbspx_dr

B5

B6

B3

B4

D7

D6

D5

030-073

Figure 6-38. McBSP Falling Edge Receive Timing in Slave Mode

6.6.1.1.4 Transmit Timing with Falling Edge as Activation Edge

Table 6-62 through Table 6-67 assume testing over the recommended operating conditions (see Figure 6-

39 and Figure 6-40).

Table 6-62. McBSP1, 2, and 3 (Sets #2 and #3) Timing Requirements – Falling Edge and Transmit Mode⁽¹⁾

NO.

PARAMETER

1.15 V

MAX

1.0 V

UNIT

MIN

MAX

B5

B6

t_{su(FSXV-CLKXAE)}

t_{h(CLKXAE-FSXV)}

Setup time, mcbspx_fsx valid before mcbspx_clkx

active edge

3.7

7.9

ns

Hold time, mcbspx_fsx valid after mcbspx_clkx

active edge

0.5

(1) In mcbspx, x identifies the McBSP number: 1, 2, or 3. Note that for the McBSP3, these timings concern only Set #2 (multiplexing mode

on UART pins) and Set #3 (multiplexing mode on McBSP1 pins).

Table 6-63. McBSP1, 2, and 3 (Sets #2 and #3) Switching Characteristics – Falling Edge and Transmit

Mode⁽¹⁾

NO.

PARAMETER

1.15 V

1.0 V

UNIT

MIN

MAX

MIN

MAX

B2

B8

t_{d(CLKXAE-FSXV)}

t_{d(CLKXAE-DXV)}

Delay time, mcbspx_clkx active edge to mcbspx_fsx

valid

0.7

14.8

0.7

29.6

ns

Delay time, mcbspx_clkx active edge to Master

0.6

14.8

0.6

29.6

ns

mcbspx_dx valid

Slave

(1) In mcbspx, x identifies the McBSP number: 1, 2, or 3. Note that for the McBSP3, these timings concern only Set #2 (multiplexing mode

on UART pins) and Set #3 (multiplexing mode on McBSP1 pins).

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UNIT

Table 6-64. McBSP4 (Set #1) Timing Requirements – Falling Edge and Transmit Mode⁽¹⁾

NO.

PARAMETER

1.15 V

1.0 V

MIN

MAX

MIN

MAX

B5

B6

t_{su(FSXV-CLKXAE)}

t_{h(CLKXAE-FSXV)}

Setup time, mcbspx_fsx valid before

mcbspx_clkx active edge

3.7

7.9

ns

Hold time, mcbspx_fsx valid after mcbspx_clkx

active edge

0.5

(1) In mcbspx, x identifies the McBSP number: 4. Note that for the McBSP4, these timings concern only Set #1: multiplexing mode by

default. The McBSP4 is also multiplexed on GPMC pins (Set #2): the corresponding timings are specified in Table 6-66.

Table 6-65. McBSP4 (Set #1) Switching Characteristics – Falling Edge and Transmit Mode⁽¹⁾

NO.

PARAMETER

1.15 V

1.0 V

UNIT

MIN

MAX

MIN

MAX

B2

B8

t_{d(CLKXAE-FSXV)}

t_{d(CLKXAE-DXV)}

Delay time, mcbspx_clkx active edge to mcbspx_fsx

valid

0.7

16.6

0.7

33.1

ns

Delay time, mcbspx_clkx active edge to

mcbspx_dx valid

Master

Slave

0.6

16.6

17.3

0.6

33.1

ns

(1) In mcbspx, x identifies the McBSP number: 4. Note that for the McBSP4, these timings concern only Set #1: multiplexing mode by

default. The McBSP4 is also multiplexed on GPMC pins (Set #2): the corresponding timings are specified in Table 6-66.

Table 6-66. McBSP3 (Set #1), 4 (Set #2), and 5 Timing Requirements – Falling Edge and Transmit Mode⁽¹⁾

NO.

PARAMETER

1.15 V

1.0 V

UNIT

MIN

MAX

MIN

MAX

B5

B6

t_{su(FSXV-CLKXAE)}

t_{h(CLKXAE-FSXV)}

Setup time, mcbspx_fsx valid before mcbspx_clkx

active edge

5.8

12.2

ns

Hold time, mcbspx_fsx valid after mcbspx_clkx

active edge

0.5

(1) In mcbspx, x identifies the McBSP number: 3, 4, or 5. Note that for the McBSP3, these timings concern only Set #1: multiplexing mode

by default. The McBSP3 is also multiplexed on UART pins (Set #2) and on McBSP1 pins (Set #3): the corresponding timings are

specified in Table 6-66. For the McBSP4, these timings concern only Set #2 (multiplexing mode on GPMC pins).

Table 6-67. McBSP3 (Set #1), 4 (Set #2), and 5 Switching Requirements – Falling Edge and Transmit

Mode⁽¹⁾

NO.

PARAMETER

1.15 V

MIN

1.0 V

MAX

UNIT

MAX

22.2

MIN

0.7

0.6

B2

B8

t_{d(CLKXAE-FSXV)}

t_{d(CLKXAE-DXV)}

Delay time, mcbspx_clkx active edge to mcbspx_fsx valid

0.7

0.6

44.4

ns

Delay time, mcbspx_clkx active edge to

mcbspx_dx valid

Master

Slave

(1) In mcbspx, x identifies the McBSP number: 3, 4, or 5. Note that for the McBSP3, these timings concern only Set #1: multiplexing mode

by default. The McBSP3 is also multiplexed on UART pins (Set #2) and on McBSP1 pins (Set #3): the corresponding timings are

specified in Table 6-66. For the McBSP4, these timings concern only Set #2 (multiplexing mode on GPMC pins).

mcbspx_clkx

B2

mcbspx_fsx

mcbspx_dx

B8

D7

D6

D5

030-074

Figure 6-39. McBSP Falling Edge Transmit Timing in Master Mode

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mcbspx_clkx

B5

B6

mcbspx_fsx

mcbspx_dx

B8

D7

D6

D5

030-075

Figure 6-40. McBSP Falling Edge Transmit Timing in Slave Mode

6.6.1.2 McBSP in TDM—Multipoint Mode (McBSP3)

For TDM application in multipoint mode, OMAP3515/03 is considered as a slave. Table 6-69 and Table 6-

70 assume testing over the operating conditions and electrical characteristic conditions described below.

Table 6-68. McBSP3 Timing Conditions—TDM in Multipoint Mode

TIMING CONDITION PARAMETER

VALUE

UNIT

MIN

MAX

Input Conditions

t_R

t_F

Input signal rising time

Input signal falling time

1.0

8.5

ns

Output Conditions

C_LOADOutput Load Capacitance

40

pF

Table 6-69. McBSP3 Timing Requirements—TDM in Multipoint Mode⁽¹⁾

NO.

PARAMETER

1.15 V

1.0 V

UNIT

MIN

MAX

MIN

MAX

t_W(CLKH)

Cycle Time, mcbsp3_clkx

162.8

ns

t_W(CLKH)

Typical Pulse duration, mcbsp3_clkx high

Typical Pulse duration, mcbsp3_clkx low

Duty cycle error, mcbsp3_clkx

0.5*P⁽²⁾

t_W(CLKL)

t_dc(CLK)

–8.14

8.14

–8.14

8.14

B3⁽³⁾

B4⁽³⁾

B5⁽³⁾

B6⁽³⁾

t_{su(DRV-CLKAE)}

Setup time, mcbsp3_dr valid before

mcbsp3_clkx active edge

9

2.4

9

2.4

9

t_h(CLKAE-DRV)

t_{su(FSV-CLKAE)}

t_h(CLKAE-FSV)

Hold time, mcbsp3_dr valid after mcbsp3_clkx

active edge

ns

Setup time, mcbsp3_fsx valid before

mcbsp3_clkx active edge

Hold time, mcbsp3_fsx valid after

mcbsp3_clkx active edge

2.4

(1) For McBSP3, these timings concern only Set #3 (multiplexing mode in McBSP1 pins).

(2) P = mcbsp3_clkx period in ns

(3) See Section 6.6.1.1, McBSP in Normal Mode for corresponding figures.

Table 6-70. McBSP3 Switching Characteristics—TDM in Multipoint Mode⁽¹⁾

NO.

B8⁽²⁾

PARAMETER

1.15 V

1.0 V

UNIT

MIN

MAX

MIN

MAX

t_{d(CLKXAE-DXV)}Delay time, mcbsp3_clkx active edge to

mcbsp3_dx valid

0.6

16.8

0.6

29.6

ns

(1) For McBSP3, these timings concern only Set #3 (multiplexing mode in McBSP1 pins).

(2) See Section 6.6.1.1, McBSP in Normal Mode for corresponding figures.

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6.6.2 Multichannel Serial Port Interface (McSPI) Timing

The multichannel SPI is a master/slave synchronous serial bus. The McSPI1 module supports up to four

peripherals and the others (McSPI2, McSPI3, and McSPI4) support up to two peripherals. The following

timings are applicable to the different configurations of McSPI in master/slave mode for any McSPI and

any channel (n).

6.6.2.1 McSPI in Slave Mode

Table 6-71 and Table 6-72 assume testing over the recommended operating conditions (see Figure 6-41).

Table 6-71. McSPI Interface Timing Requirements – Slave Mode^{(1) (2)}

NO.

PARAMETER

1.15 V

1.0 V

UNIT

MIN

MAX

MIN

MAX

1/SS 1/t_c(CLK)

0

Frequency, mcspix_clk

24

12

MHz

t_j(CLK)

Cycle jitter⁽³⁾, mcspix_clk

-200

200

-200

200

0.55*P⁽⁴⁾

ps

ns

SS1 t_w(CLK)

Pulse duration, mcspix_clk high or low

0.45*P⁽⁴⁾0.55*P⁽⁴⁾0.45*P⁽⁴⁾

SS2 t_{su(SIMOV-CLKAE)}

Setup time, mcspix_simo valid before mcspix_clk

active edge

4.2

9.5

SS3 t_{h(SIMOV-CLKAE)}

SS4 t_{su(CS0V-CLKFE)}

SS5 t_{h(CS0I-CLKLE)}

Hold time, mcspix_simo valid after mcspix_clk active

edge

4.6

9.9

ns

Setup time, mcspix_cs0 valid before mcspix_clk first

edge

13.8

28.6

Hold time, mcspix_cs0 invalid after mcspix_clk last

edge

(1) The input timing requirements are given by considering a rise time and a fall time of 4 ns.

(2) In mcspix, x is equal to 1, 2, 3, or 4.

(3) Maximum cycle jitter supported by mcspix_clk input clock.

(4) P = mcspix_clk clock period

Table 6-72. McSPI Interface Switching Requirements^{(1) (2) (3) (4)}

NO.

PARAMETER

1.15 V

1.0 V

UNIT

MIN

MAX

MIN

MAX

SS6 t_{d(CLKAE-SOMIV)}

SS7 t_{d(CS0AE-SOMIV)}

Delay time, mcspix_clk active edge to mcspix_somi

shifted

1.8

15.9

3.2

31.7

ns

Delay time, mcspix_cs0 active edge to Modes 0 and 2

mcspix_somi shifted

15.9

31.7

(1) The capacitive load is equivalent to 20 pF.

(2) In mcspix, x is equal to 1, 2, 3, or 4.

(3) The polarity of mcspix_clk and the active edge (rising or falling) on which mcspix_simo is driven and mcspix_somi is latched is all

software configurable.

(4) This timing applies to all configurations regardless of mcspix_clk polarity and which clock edges are used to drive output data and

capture input data.

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Mode 0 & 2

mcspix_cs0(EPOL=1)

SS0

SS1

SS4

SS5

mcspix_clk(POL=0)

mcspix_clk(POL=1)

SS0

SS1

SS2

SS3

Bit n-1

SS7

Bit n-1

mcspix_simo

mcspix_somi

Bit n-2

SS6

Bit n-3

Bit n-4

Bit 0

Bit n-2

Bit n-3

Bit 0

Mode 1 & 3

mcspix_cs0(EPOL=1)

mcspix_clk(POL=0)

mcspix_clk(POL=1)

SS0

SS1

SS0

SS1

SS4

SS5

SS3

SS2

Bit n-1

SS6

Bit n-1

mcspix_simo

mcspix_somi

Bit n-2

Bit n-3

Bit 1

Bit 0

Bit n-3

Bit 1

Bit 0

030-076

Figure 6-41. McSPI Interface – Transmit and Receive in Slave Mode(1) (2)

(1) The active clock edge (rising or falling) on which mcspi_somi is driven and mcspi_simo data is latched is software configurable with the

bit MSPI_CHCONFx[0] = PHA and the bit MSPI_CHCONFx[1] = POL.

(2) The polarity of mcspix_csi is software configurable with the bit MSPI_CHCONFx[6] = EPOL In mcspix, x is equal to 1, 2, 3, or 4.

6.6.2.2 McSPI in Master Mode

Table 6-73 and Table 6-74 assume testing over the recommended operating conditions (see Figure 6-42).

Table 6-73. McSPI1, 2, and 4 Interface Timing Requirements – Master Mode^{(1) (2)}

NO.

PARAMETER

1.15 V

MAX

1.0 V

UNIT

MIN

MAX

SM2 t_{su(SOMIV-CLKAE)}

SM3 t_{h(SOMIV-CLKAE)}

Setup time, mcspix_somi valid before mcspix_clk

active edge

1.1

1.5

ns

Hold time, mcspix_somi valid after mcspix_clk active

edge

1.9

2.8

(1) The input timing requirements are given by considering a rise time and a fall time of 4 ns.

(2) In mcspix, x is equal to 1, 2, or 4. In mcspix_csn, n is equal to 0, 1, 2, or 3 for x equal to 1, n is equal to 0 or 1 for x equal to 2 and 4.

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UNIT

Table 6-74. McSPI1, 2, and 4 Interface Switching Characteristics – Master Mode^{(1) (2) (3)}

NO.

PARAMETER

1.15 V

1.0 V

MIN

MAX

48

MIN

MAX

24

1/SM0 1/t_c(CLK)

t_j(CLK)

Frequency, mcspix_clk

Cycle jitter⁽⁴⁾, mcspix_clk

MHz

ps

-200

200

-200

200

SM1

SM4

SM5

t_w(CLK)

Pulse duration, mcspix_clk high or low

0.45*P⁽⁵⁾0.55*P⁽⁵⁾0.45*P⁽0.55*P⁽⁵⁾

ns

5)

t_{d(CLKAE-SIMOV)}

t_{d(CSnA-CLKFE)}

Delay time, mcspix_clk active edge to mcspix_simo

shifted

–2.1

5

–2.1

11.3

ns

Delay time, mcspix_csi active to

mcspix_clk first edge

Modes 1

and 3

A⁽⁶⁾– 3.1

B⁽⁷⁾– 3.1

A⁽⁶⁾– 3.1

A⁽⁶⁾

4.4

B⁽⁷⁾

4.4

B⁽⁷⁾

4.4

A⁽⁶⁾

4.4

–

Modes 0

and 2

–

SM6

SM7

t_{d(CLKLE-CSnI)}

Delay time, mcspix_clk last edge to

mcspix_csi inactive

Modes 1

and 3

Modes 0

and 2

t_{d(CSnAE-SIMOV)}

Delay time, mcspix_csi active edge to Modes 0

mcspix_simo shifted and 2

5.0

11.3

(1) Timings are given for a maximum load capacitance of 20 pF for spix_csn signals, 30 pF for spix_clk and spix_simo signals with x = 1 or

2, and 20 pF for spi4_clk and spi4_simo signals.

(2) In mcspix, x is equal to 1, 2, or 4. In mcspix_csn, n is equal to 0, 1, 2, or 3 for x equal to 1, n is equal to 0 or 1 for x equal to 2 and 4.

(3) The polarity of mcspix_clk and the active edge (rising or falling) on which mcspix_simo is driven and mcspix_somi is latched is all

software configurable.

(4) Maximum cycle jitter supported by mcspix_clk input clock.

(5) P = mcspix_clk clock period

(6) Case P = 20.8 ns, A = (TCS+0.5)*P⁽⁵⁾(TCS is a bit field of MSPI_CHCONFx[26:25] register). Case P > 20.8 ns, A = TCS*P⁽⁵⁾(TCS is a

bitfield of MSPI_CHCONFx[26:25] register). For more information, see the McSPI chapter of the OMAP35x Technical Reference Manual

(TRM) [literature number SPRUF98].

(7) B = TCS*P (TCS is a bit field of MSPI_CHCONFx[26:25] register). For more information, see the McSPI chapter of the OMAP35x

Technical Reference Manual (TRM) [literature number SPRUF98].

Table 6-75 and Table 6-76 assume testing over the recommended operating conditions (see Figure 6-42).

Table 6-75. McSPI 3 Interface Timing Requirements – Master Mode^{(1) (2)}

NO.

PARAMETER

1.15 V

MAX

1.0 V

UNIT

MIN

MAX

SM2 t_{su(SOMIV-CLKAE)}

SM3 t_{h(SOMIV-CLKAE)}

Setup time, mcspi3_somi valid before

mcspi3_clk active edge

1.5

4.3

ns

Hold time, mcspi3_somi valid after mcspi3_clk

active edge

2.8

5.9

(1) The input timing requirements are given by considering a rise time and a fall time of 4 ns.

(2) In mcspi3_csn, n is equal to 0 or 1. The polarity of mcspi3_clk and the active edge (rising or falling) on which mcspi3_simo is driven and

mcspi3_somi is latched is all software configurable.

Table 6-76. McSPI3 Interface Switching Requirements – Master Mode^{(1) (2) (3)}

NO.

PARAMETER

1.15 V

1.0 V

UNIT

MIN

MAX

MIN

MAX

1/SM 1/t_c(CLK)

0

Frequency, mcspix_clk

24

12

MHz

t_j(CLK)

Cycle jitter⁽⁴⁾, mcspix_clk

-200

0.45*P⁽⁵⁾

200

0.55*P⁽⁵⁾

-200

0.45*P⁽⁵⁾

200

0.55*P⁽⁵⁾

ps

ns

SM1 t_w(CLK)

Pulse duration, mcspix_clk high or low

(1) The capacitive load is equivalent to 20 pF.

(2) In mcspi3_csn, n is equal to 0 or 1. The polarity of mcspi3_clk and the active edge (rising or falling) on which mcspi3_simo is driven and

mcspi3_somi is latched is all software configurable.

(3) This timing applies to all configurations regardless of McSPI3_CLK polarity and which clock edges are used to drive output data and

capture input data.

(4) Maximum cycle jitter supported by mcspix_clk input clock.

(5) P = mcspi3_clk clock period

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Table 6-76. McSPI3 Interface Switching Requirements – Master Mode^{(1) (2) (3)}(continued)

PARAMETER

1.15 V

1.0 V

UNIT

MIN

MAX

MIN

MAX

SM4 t_{d(CLKAE-SIMOV)}

SM5 t_{d(CSnA-CLKFE)}

Delay time, mcspix_clk active edge to

mcspix_simo shifted

–2.1

11.3

–5.3

23.6

ns

Delay time, mcspix_csi active Modes 1

–4.4 + A⁽⁶⁾

–4.4 + B⁽⁷⁾

B – 4.4⁽⁷⁾

A⁽⁶⁾– 4.4

–10.1 + A⁽⁶⁾

–10.1 + B⁽⁷⁾

B – 10.1⁽⁷⁾

A⁽⁶⁾– 10.1

to mcspix_clk first edge

and 3

Modes 0

and 2

SM6 t_d(CLK-CSn)

Delay time, mcspix_clk last

edge to mcspix_csi inactive

Modes 1

and 3

Modes 0

and 2

SM7 t_{d(CSnAE-SIMOV)}

Delay time, mcspix_csi active Modes 0

edge to mcspix_simo shifted and 2

11.3

23.6

(6) Case P = 20.8 ns, A = (TCS + 0.5)*P⁽⁵⁾(TCS is a bit field of MSPI_CHCONFx[26:25] register). Case P > 20.8 ns, A = TCS*P⁽⁵⁾(TCS is

a bit field of MSPI_CHCONFx[26:25] register). For more information, see the McSPI chapter of the OMAP35x Technical Reference

Manual (TRM) [literature number SPRUF98].

(7) B = TCS*P (TCS is a bit field of MSPI_CHCONFx[26:25] register). For more information, see the McSPI chapter of the OMAP35x

Technical Reference Manual (TRM) [literature number SPRUF98].

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Mode 0 & 2

mcspix_csn(EPOL=1)

SM0

SM1

SM5

SM6

mcspix_clk(POL=0)

SM0

SM1

mcspix_clk(POL=1)

SM7

SM4

Bit n-2

mcspix_simo

mcspix_somi

Bit n-1

SM2

Bit n-3

Bit n-4

Bit 0

SM3

Bit n-1

Bit n-2

Bit n-3

Bit 0

Mode 1 & 3

mcspix_csn(EPOL=1)

mcspix_clk(POL=0)

SM0

SM1

SM0

SM1

SM5

SM6

mcspix_clk(POL=1)

mcspix_simo

SM4

Bit n-1

SM2

Bit n-2

Bit n-3

Bit 1

Bit 0

SM3

mcspix_somi

Bit n-1

Bit n-3

Bit 1

030-077

Figure 6-42. McSPI Interface – Transmit and Receive in Master Mode(1) (2) (3)

(1) The active clock edge (rising or falling) on which mcspix_simo is driven and mcspi_somi data is latched is software configurable with the

bit MSPI_CHCONFx[0] = PHA and the bit MSPI_CHCONFx[1] = POL.

(2) The polarity of mcspix_csi is software configurable with the bit MSPI_CHCONFx[6] = EPOL.

(3) In mcspix, x is equal to 1. In mcspix_csn, n is equal to 0, 1, 2, or 3.

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6.6.3 Multiport Full-Speed Universal Serial Bus (USB) Interface

The OMAP3515/03 processor provides three USB ports working in full- and low-speed data transactions

(up to 12Mbit/s).

Connected to either a serial link controller (TLL modes) or a serial PHY (PHY interface modes) it supports:

•

6-pin (Tx: Dat/Se0 or Tx: Dp/Dm) unidirectional mode

4-pin bidirectional mode

3-pin bidirectional mode

6.6.3.1 Multiport Full-Speed Universal Serial Bus (USB) – Unidirectional Standard 6-pin Mode

Table 6-78 and Table 6-79 assume testing over the recommended operating conditions (see Figure 6-43).

Table 6-77. Low-/Full-Speed USB Timing Conditions – Unidirectional Standard 6-pin Mode

TIMING CONDITION PARAMETER

Input Conditions

VALUE

UNIT

t_R

Input signal rise time

Input signal fall time

2.0

ns

t_F

Output Conditions

C_LOAD

Output load capacitance

15.0

pF

Table 6-78. Low-/Full-Speed USB Timing Requirements – Unidirectional Standard 6-pin Mode

NO.

PARAMETER

1.15 V

MIN MAX

1.0 V

UNIT

MIN

MAX

FSU1

FSU2

FSU3

FSU4

t_d(Vp,Vm)

t_d(RCVU0)

t_d(RCVU1)

Time duration, mmx_rxdp and mmx_rxdm low together during

transition

14.0

ns

Time duration, mmx_rxdp and mmx_rxdm high together during

transition

8.0

14.0

8.0

Time duration, mmx_rrxcv undefine during a single end 0

(mmx_rxdp and mmx_rxdm low together)

14.0

8.0

Time duration, mmx_rxrcv undefine during a single end 1

(mmx_rxdp and mmx_rxdm high together)

Table 6-79. Low-/Full-Speed USB Switching Characteristics – Unidirectional Standard 6-pin Mode

NO.

PARAMETER

1.15 V

MIN

1.0 V

UNIT

MAX

84.8

1.5

MIN

81.8

MAX

84.8

1.5

FSU5

FSU6

FSU7

FSU8

FSU9

t_{d(TXENL-DATV)}

t_{d(TXENL-SE0V)}

t_s(DAT-SE0)

t_{d(DATI-TXENH)}

t_{d(SE0I-TXENH)}

t_R(do)

Delay time, mmx_txen_n low to mmx_txdat valid

Delay time, mmx_txen_n low to mmx_txse0 valid

Skew between mmx_txdat and mmx_txse0 transition

Delay time, mmx_txdat invalid to mmx_txen_n high

Delay time, mmx_txse0 invalid to mmx_txen_n high

Rise time, mmx_txen_n

81.8

ns

81.8

4.0

t_F(do)

Fall time, mmx_txen_n

t_R(do)

Rise time, mmx_txdat

t_F(do)

Fall time, mmx_txdat

t_R(do)

Rise time, mmx_txse0

t_F(do)

Fall time, mmx_txse0

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Transmit

mmx_txen_n

Receive

FSU5

FSU8

FSU9

mmx_txdat

FSU6

FSU7

mmx_txse0

mmx_rxdp

mmx_rxdm

mmx_rxrcv

FSU1

FSU2

FSU4

FSU1

FSU3

030-080

In mmx, x is equal to 0, 1, or 2.

Figure 6-43. Low-/Full-Speed USB – Unidirectional Standard 6-pin Mode

6.6.3.2 Multiport Full-Speed Universal Serial Bus (USB) – Bidirectional Standard 4-pin Mode

Table 6-81 and Table 6-82 assume testing over the recommended operating conditions (see Figure 6-44).

Table 6-80. Low-/Full-Speed USB Timing Conditions – Bidirectional Standard 4-pin Mode

TIMING CONDITION PARAMETER

VALUE

UNIT

Input Conditions

t_R

Input signal rise time

Input signal fall time

2.0

ns

t_F

Output Conditions

C_LOAD

Output load capacitance

15.0

pF

Table 6-81. Low-/Full-Speed USB Timing Requirements – Bidirectional Standard 4-pin Mode

NO.

PARAMETER

1.15 V

MAX

1.0 V

UNIT

MIN

MAX

FSU10 t_d(DAT,SE0)

FSU11 t_d(DAT,SE0)

FSU12 t_d(RCVU0)

FSU13 t_d(RCVU1)

Time duration, mmx_txdat and mmx_txse0 low together

during transition

14.0

ns

Time duration, mmx_txdat and mmx_txse0 high together

during transition

8.0

14.0

8.0

Time duration, mmx_rrxcv undefine during a single end 0

(mmx_txdat and mmx_txse0 low together)

14.0

8.0

Time duration, mmx_rxrcv undefine during a single end 1

(mmx_txdat and mmx_txse0 high together)

Table 6-82. Low-/Full-Speed USB Switching Characteristics – Bidirectional Standard 4-pin Mode

NO.

PARAMETER

1.15 V

MAX

1.0 V

UNIT

MIN

81.8

MIN

81.8

MAX

84.8

1.5

FSU14

FSU15

FSU16

t_{d(TXENL-DATV)}

t_{d(TXENL-SE0V)}

t_s(DAT-SE0)

Delay time, mmx_txen_n low to mmx_txdat valid

Delay time, mmx_txen_n low to mmx_txse0 valid

84.8

1.5

ns

Skew between mmx_txdat and mmx_txse0

transition

FSU17

t_{d(DATV-TXENH)}

Delay time, mmx_txdat invalid before mmx_txen_n

high

81.8

ns

216

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Table 6-82. Low-/Full-Speed USB Switching Characteristics – Bidirectional Standard 4-pin

Mode (continued)

NO.

PARAMETER

1.15 V

MAX

1.0 V

UNIT

MIN

MAX

FSU18

t_{d(SE0V-TXENH)}

Delay time, mmx_txse0 invalid before mmx_txen_n

high

81.8

ns

t_R(txen)

t_F(txen)

t_R(dat)

t_F(dat)

t_R(se0)

t_F(se0)

Rise time, mmx_txen_n

Fall time, mmx_txen_n

Rise time, mmx_txdat

Fall time, mmx_txdat

Rise time, mmx_txse0

Fall time, mmx_txse0

4.0

ns

Transmit

FSU14

mmx_txen_n

Receive

FSU10

FSU17

FSU18

FSU11

mmx_txdat

mmx_txse0

mmx_rxrcv

FSU15

FSU16

FSU10

FSU12

FSU11

FSU13

030-081

In mmx, x is equal to 0, 1, or 2.

Figure 6-44. Low-/Full-Speed USB – Bidirectional Standard 4-pin Mode

6.6.3.3 Multiport Full-Speed Universal Serial Bus (USB) – Bidirectional Standard 3-pin Mode

Table 6-84 and Table 6-85 assume testing over the recommended operating conditions below (see

Figure 6-45).

Table 6-83. Low-/Full-Speed USB Timing Conditions – Bidirectional Standard 3-pin Mode

TIMING CONDITION PARAMETER

VALUE

UNIT

Input Conditions

t_R

Input signal rise time

Input signal fall time

2.0

ns

t_F

Output Conditions

C_LOAD

Output load capacitance

15.0

pF

Table 6-84. Low-/Full-Speed USB Timing Requirements – Bidirectional Standard 3-pin Mode

NO.

PARAMETER

1.15 V

MAX

1.0 V

UNIT

MIN

MAX

FSU19

FSU20

t_d(DAT,SE0)

Time duration, mmx_txdat and mmx_txse0 low together

during transition

14.0

ns

Time duration, mmx_tsdat and mmx_txse0 high

together during transition

8.0

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Table 6-85. Low-/Full-Speed USB Switching Characteristics – Bidirectional Standard 3-pin Mode

NO.

PARAMETER

1.15 V

1.0 V

UNIT

MIN

81.8

MAX

84.8

1.5

MIN

81.8

MAX

84.8

1.5

FSU21

FSU22

FSU23

t_{d(TXENL-DATV)}

t_{d(TXENL-SE0V)}

t_s(DAT-SE0)

Delay time, mmx_txen_n low to mmx_txdat valid

Delay time, mmx_txen_n low to mmx_txse0 valid

ns

Skew between mmx_txdat and mmx_txse0

transition

FSU24

FSU25

t_{d(DATI-TXENH)}

t_{d(SE0I-TXENH)}

Delay time, mmx_txdat invalid to mmx_txen_n

high

81.8

ns

Delay time, mmx_txse0 invalid to mmx_txen_n

high

t_R(do)

t_F(do)

t_R(do)

t_F(do)

t_R(do)

t_F(do)

Rise time, mmx_txen_n

Fall time, mmx_txen_n

Rise time, mmx_txdat

Fall time, mmx_txdat

Rise time, mmx_txse0

Fall time, mmx_txse0

4.0

ns

Transmit

mmx_txen_n

mmx_txdat

mmx_txse0

Receive

FSU21

FSU24

FSU25

FSU19

FSU20

FSU22

FSU23

FSU19

030-082

In mmx, x is equal to 0, 1, or 2.

Figure 6-45. Low-/Full-Speed USB – Bidirectional Standard 3-pin Mode

6.6.3.4 Multiport Full-Speed Universal Serial Bus (USB) – Unidirectional TLL 6-pin Mode

Table 6-87 and Table 6-88 assume testing over the recommended operating conditions (see Figure 6-46).

Table 6-86. Low-/Full-Speed USB Timing Conditions – Unidirectional TLL 6-pin Mode

TIMING CONDITION PARAMETER

VALUE

UNIT

Input Conditions

t_R

Input signal rise time

Input signal fall time

2

ns

t_F

Output Conditions

C_LOAD

Output load capacitance

15

pF

Table 6-87. Low-/Full-Speed USB Timing Requirements – Unidirectional TLL 6-pin Mode

NO.

PARAMETER

1.15 V

1.0 V

UNIT

MIN

MAX

MIN

MAX

FSUT1

FSUT2

t_d(SE0,DAT)

Time duration, mmx_txse0 and mmx_txdat low

together during transition

14

ns

Time duration, mmx_txse0 and mmx_txdat high

together during transition

8

218

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Table 6-88. Low-/Full-Speed USB Switching Characteristics – Unidirectional TLL 6-pin Mode

NO.

PARAMETER

1.15 V

1.0 V

UNIT

MIN

81.8

MAX

84.8

MIN

81.8

MAX

84.8

FSUT3

FSUT4

FSUT5

FSUT6

FSUT7

t_d(TXENH-DPV)

t_d(TXENH-DMV)

t_d(DPI-TXENL)

t_d(DMI-TXENL)

t_s(DP-DM)

Delay time, mmx_txen_n high to mmx_rxdp valid

Delay time, mmx_txen_n high to mmx_rxdm valid

Delay time, mmx_rxdp invalid mmx_txen_n low

Delay time, mmx_rxdm invalid mmx_txen_n low

ns

Skew between mmx_rxdp and mmx_rxdm

transition

1.5

FSUT8

t_s(DP,DM-RCV)

Skew between mmx_rxdp, mmx_rxdm, and

mmx_rxrcv transition

ns

t_R(rxrcv)

t_F(rxrcv)

t_R(dp)

Rise time, mmx_rxrcv

Fall time, mmx_rxrcv

Rise time, mmx_rxdp

Fall time, mmx_rxdp

Rise time, mmx_rxdm

Fall time, mmx_rxdm

4

ns

t_F(dp)

t_R(dm)

t_F(dm)

mmx_txen_n

Transmit

Receive

FSUT1

FSUT2

mmx_txdat

mmx_txse0

mmx_rxdp

mmx_rxdm

mmx_rxrcv

FSUT1

FSUT2

FSUT3

FSUT5

FSUT6

FSUT4

FSUT7

FSUT8

030-083

In mmx, x is equal to 0, 1, or 2.

Figure 6-46. Low-/Full-Speed USB – Unidirectional TLL 6-pin Mode

6.6.3.5 Multiport Full-Speed Universal Serial Bus (USB) – Bidirectional TLL 4-pin Mode

Table 6-90 and Table 6-91 assume testing over the recommended operating conditions (see Figure 6-47).

Table 6-89. Low-/Full-Speed USB Timing Conditions – Bidirectional TLL 4-pin Mode

TIMING CONDITION PARAMETER

VALUE

UNIT

Input Conditions

t_R

Input signal rise time

Input signal fall time

2

ns

t_F

Output Conditions

C_LOAD

Output load capacitance

15

pF

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UNIT

Table 6-90. Low-/Full-Speed USB Timing Requirements – Bidirectional TLL 4-pin Mode

NO.

PARAMETER

1.15 V

1.0 V

MIN

MAX

MIN

MAX

FSUT9

t_d(DAT,SE0)

Time duration, mmx_txdat and mmx_txse0 low

together during transition

14

ns

FSUT10 t_d(DAT,SE0)

Time duration, mmx_tsdat and mmx_txse0 high

together during transition

8

Table 6-91. Low-/Full-Speed USB Switching Characteristics – Bidirectional TLL 4-pin Mode

NO.

PARAMETER

1.15 V

MAX

1.0 V

UNIT

MIN

81.8

MIN

81.8

MAX

84.8

1.5

FSUT11 t_{d(TXENL-DATV)}

FSUT12 t_{d(TXENL-SE0V)}

FSUT13 t_s(DAT-SE0)

Delay time, mmx_txen_n active to mmx_txdat valid

Delay time, mmx_txen_n active to mmx_txse0 valid

84.8

1.5

ns

Skew between mmx_txdat and mmx_txse0

transition

FSUT14 t_s(DP,DM-RCV)

Skew between mmx_rxdp, mmx_rxdm, and

mmx_rxrcv transition

1.5

ns

FSUT15 t_{d(DATI-TXENL)}

Delay time, mmx_txse0 invalid to mmx_txen_n Low

Delay time, mmx_txdat invalid to mmx_txen_n Low

Rise time, mmx_rxrcv

81.8

ns

FSUT16 t_{d(SE0I-TXENL)}

t_R(rcv)

t_F(rcv)

t_R(dat)

t_F(dat)

t_R(se0)

t_F(se0)

4

Fall time, mmx_rxrcv

Rise time, mmx_txdat

Fall time, mmx_txdat

Rise time, mmx_txse0

Fall time, mmx_txse0

mmx_txen_n

mmx_txdat

mmx_txse0

mmx_rxrcv

Transmit

FSUT11

Receive

FSUT9

FSUT15

FSUT16

FSUT10

FSUT12

FSUT13

FSUT14

FSUT9

FSUT10

030-084

In mmx, x is equal to 0, 1, or 2.

Figure 6-47. Low-/Full-Speed USB – Bidirectional TLL 4-pin Mode

6.6.3.6 Multiport Full-Speed Universal Serial Bus (USB) – Bidirectional TLL 3-pin Mode

Table 6-93 and Table 6-94 assume testing over the recommended operating conditions (see Figure 6-48).

Table 6-92. Low-/Full-Speed USB Timing Conditions – Bidirectional TLL 3-pin Mode

TIMING CONDITION PARAMETER

VALUE

UNIT

Input Conditions

t_R

Input signal rise time

Input signal fall time

2

ns

t_F

Output Conditions

220

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Table 6-92. Low-/Full-Speed USB Timing Conditions – Bidirectional TLL 3-pin Mode (continued)

TIMING CONDITION PARAMETER

VALUE

UNIT

C_LOAD

Output load capacitance

15

pF

Table 6-93. Low-/Full-Speed USB Timing Requirements – Bidirectional TLL 3-pin Mode

NO.

PARAMETER

1.15 V

1.0 V

UNIT

MIN

MAX

MIN

MAX

FSUT17 t_d(DAT,SE0)Time duration, mmx_txdat and mmx_txse0 low

together during transition

14

ns

FSUT18 t_d(DAT,SE0)Time duration, mmx_tsdat and mmx_txse0 high

together during transition

8

Table 6-94. Low-/Full-Speed USB Switching Characteristics – Bidirectional TLL 3-pin Mode

NO.

PARAMETER

1.15 V

1.0 V

UNIT

MIN

81.8

MAX

84.8

1.5

MIN

81.8

MAX

84.8

1.5

FSUT19 t_{d(TXENH-DATV)}

FSUT20 t_{d(TXENH-SE0V)}

FSUT21 t_s(DAT-SE0)

Delay time, mmx_txen_n high to mmx_txdat valid

Delay time, mmx_txen_n high to mmx_txse0 valid

ns

Skew between mmx_txdat and mmx_txse0

transition

FSUT22 t_{d(DATI-TXENL)}

Delay time, mmx_txdat invalid mmx_txen_n low

Delay time, mmx_txse0 invalid mmx_txen_n low

Rise time, mmx_txdat

81.8

ns

FSUT23 t_{d(SE0I-TXENL)}

t_R(dat)

t_F(dat)

t_R(se0)

t_F(se0)

t_R(do)

t_F(do)

4

Fall time, mmx_txdat

Rise time, mmx_txse0

Fall time, mmx_txse0

Rise time, mmx_txse0

Fall time, mmx_txse0

Receive

FSUT17

mmx_txen_n

mmx_txdat

mmx_txse0

Transmit

FSUT19

FSUT22

FSUT23

FSUT18

FSUT20

FSUT21

FSUT17

FSUT18

030-085

In mmx, x is equal to 0, 1, or 2.

Figure 6-48. Low-/Full-Speed USB – Bidirectional TLL 3-pin Mode

6.6.4 Multiport High-Speed Universal Serial Bus (USB) Timing

In addition to the full-speed USB controller, a high-speed (HS) USB OTG controller is instantiated inside

OMAP3515/03. It allows high-speed transactions (up to 480 Mbit/s) on the USB ports 0, 1, 2, and 3.

•

Port 0:

–

12-bit slave mode (SDR)

•

Port 1 and port 2:

–

12-bit master mode (SDR)

12-bit TLL master mode (SDR)

8-bit TLL master mode (DDR)

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•

Port 3:

–

12-bit TLL master mode (SDR)

8-bit TLL master mode (DDR)

6.6.4.1 High-Speed Universal Serial Bus (USB) on Port 0 – 12-bit Slave Mode

Table 6-96 and Table 6-97 assume testing over the recommended operating conditions (see Figure 6-49).

Table 6-95. High-Speed USB Timing Conditions – 12-bit Slave Mode

TIMING CONDITION PARAMETER

VALUE

UNIT

Input Conditions

t_r

Input Signal Rising Time

Input Signal Falling Time

2.00

ns

t_f

Output Conditions

C_load

Output Load Capacitance

3.50

pF

Table 6-96. High-Speed USB Timing Requirements – 12-bit Slave Mode⁽¹⁾

NO.

PARAMETER

1.15 V

UNIT

MIN

MAX

60.03

500.00

HSU0

HSU3

HSU4

f_p(CLK)

hsusb0_clk clock frequency^{(2) (3)}

Cycle Jitter⁽³⁾, hsusb0_clk

MHz

ps

t_j(CLK)

t_s(DIRV-CLKH)

t_s(NXTV-CLKH)

t_{h(CLKH-DIRIV)}

t_{h(CLKH-NXT/IV)}

t_{s(DATAV-CLKH)}

t_{h(CLKH-DATIV)}

Setup time, hsusb0_dir valid before hsusb0_clk rising edge

Setup time, hsusb0_nxt valid before hsusb0_clk rising edge

Hold time, hsusb0_dir valid after hsusb0_clk rising edge

Hold time, hsusb0_nxt valid after hsusb0_clk rising edge

Setup time, hsusb0_data[0:7] valid before hsusb0_clk rising edge

Hold time, hsusb0_data[0:7] valid after hsusb0_clk rising edge

6.7

0.0

6.7

0.0

ns

HSU5

HSU6

ns

(1) The timing requirements are assured for the cycle jitter error condition specified.

(2) Related with the input maximum frequency supported by the I/F module.

(3) Maximum cycle jitter supported by clk input clock.

Table 6-97. High-Speed USB Switching Characteristics – 12-bit Slave Mode

NO.

PARAMETER

1.15 V

UNIT

MIN

0.5

MAX

HSU1 t_d(clkL-STPV)

t_{d(clkL-STPIV)}

HSU2 t_d(clkL-DV)

t_d(clkL-DIV)

Delay time, hsusb0_clk high to output usb0_stp valid

Delay time, hsusb0_clk high to output usb0_stp invalid

Delay time, hsusb0_clk high to output hsusb0_data[0:7] valid

Delay time, hsusb0_clk high to output hsusb0_data[0:7] invalid

Rising time, output signals

9.0

ns

9.0

0.5

t_r(do)

2.0

t_f(do)

Falling time, output signals

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HSU0

hsusb0_clk

HSU1

hsusb0_stp

hsusb0_dir_&_nxt

hsusb0_data[7:0]

HSU3

HSU4

HSU5

HSU2

HSU6

Data_OUT

Data_IN

030-086

Figure 6-49. High-Speed USB – 12-bit Slave Mode

6.6.4.2 High-Speed Universal Serial Bus (USB) on Ports 1 and 2 – 12-bit Master Mode

Table 6-99 and Table 6-100 assume testing over the recommended operating conditions (see Figure 6-

50).

Table 6-98. High-Speed USB Timing Conditions – 12-bit Master Mode

TIMING CONDITION PARAMETER

VALUE

UNIT

Input Conditions

t_R

Input signal rise time

Input signal fall time

2

ns

t_F

Output Conditions

C_LOAD

Output load capacitance

3

pF

Table 6-99. High-Speed USB Timing Requirements – 12-bit Master Mode⁽¹⁾

NO.

PARAMETER

1.15 V

UNIT

MIN

9.3

0.2

9.3

0.2

MAX

HSU3 t_s(DIRV-CLKH)

t_s(NXTV-CLKH)

HSU4 t_{h(CLKH-DIRIV)}

t_{h(CLKH-NXT/IV)}

Setup time, hsusbx_dir valid before hsusbx_clk rising edge

Setup time, hsusbx_nxt valid before hsusbx_clk rising edge

Hold time, hsusbx_dir valid after hsusbx_clk rising edge

Hold time, hsusbx_nxt valid after hsusbx_clk rising edge

Setup time, hsusbx_data[0:7] valid before hsusbx_clk rising edge

Hold time, hsusbx_data[0:7] valid after hsusbx_clk rising edge

ns

HSU5 t_{s(DATAV-CLKH)}

HSU6 t_{h(CLKH-DATIV)}

(1) In hsusbx, x is equal to 1 or 2.

Table 6-100. High-Speed USB Switching Characteristics – 12-bit Master Mode⁽¹⁾

N O.

PARAMETER

1.15 V

UNIT

MIN

MAX

60

HSU0

HSU1

HSU2

f_p(CLK)

hsusbx_clk clock frequency

Jitter standard deviation⁽²⁾, hsusbx_clk

MHz

ps

t_j(CLK)

200

13

t_d(clkL-STPV)

t_{d(clkL-STPIV)}

t_d(clkL-DV)

Delay time, hsusbx_clk high to output hsusbx_stp valid

Delay time, hsusbx_clk high to output hsusbx_stp invalid

Delay time, hsusbx_clk high to output hsusbx_data[0:7] valid

ns

2

ns

13

ns

(1) In hsusbx, x is equal to 1 or 2.

(2) The jitter probability density can be approximated by a Gaussian function.

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Table 6-100. High-Speed USB Switching Characteristics – 12-bit Master Mode⁽¹⁾(continued)

N O.

PARAMETER

1.15 V

UNIT

MIN

MAX

t_d(clkL-DIV)

t_R(do)

Delay time, hsusbx_clk high to output hsusbx_data[0:7] invalid

Rise time, output signals

2

ns

2

t_F(do)

Fall time, output signals

HSU0

hsusbx_clk

hsusbx_stp

HSU1

HSU3

HSU4

HSU6

hsusbx_dir_&_nxt

hsusbx_data[7:0]

HSU5

HSU2

Data_OUT

Data_IN

030-087

In hsusbx, x is equal to 1 or 2.

Figure 6-50. High-Speed USB – 12-bit Master Mode

6.6.4.3 High-Speed Universal Serial Bus (USB) on Ports 1, 2, and 3 – 12-bit TLL Master Mode

Table 6-102 and Table 6-103 assume testing over the recommended operating conditions (see Figure 6-

51).

Table 6-101. High-Speed USB Timing Conditions – 12-bit TLL Master Mode

TIMING CONDITION PARAMETER

Input Conditions

VALUE

UNIT

t_R

Input signal rise time

Input signal fall time

2

ns

t_F

Output Conditions

C_LOAD

Output load capacitance

3

pF

Table 6-102. High-Speed USB Timing Requirements – 12-bit TLL Master Mode⁽¹⁾

NO.

PARAMETER

1.15 V

UNIT

MIN

6

MAX

HSU2 t_s(STPV-CLKH)

HSU3 t_{s(CLKH-STPIV)}

HSU4 t_{s(DATAV-CLKH)}

HSU5 t_{h(CLKH-DATIV)}

Setup time, hsusbx_tll_stp valid before hsusbx_tll_clk rising edge

Hold time, hsusbx_tll_stp valid after hsusbx_tll_clk rising edge

Setup time, hsusbx_tll_data[7:0] valid before hsusbx_tll_clk rising edge

Hold time, hsusbx_tll_data[7:0] valid after hsusbx_tll_clk rising edge

ns

0

6

0

(1) In hsusbx, x is equal to 1, 2, or 3.

Table 6-103. High-Speed USB Switching Characteristics – 12-bit TLL Master Mode⁽¹⁾

NO.

PARAMETER

1.15 V

UNIT

MIN

MAX

HSU0 f_p(CLK)

hsusbx_tll_clk clock frequency

60

MHz

(1) In hsusbx, x is equal to 1, 2, or 3.

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Table 6-103. High-Speed USB Switching Characteristics – 12-bit TLL Master Mode⁽¹⁾(continued)

NO.

PARAMETER

1.15 V

UNIT

MIN

MAX

200

9

t_j(CLK)

Jitter standard deviation⁽²⁾, hsusbx_tll_clk

ps

ns

HSU6 t_d(CLKL-DIRV)

t_{d(CLKL-DIRIV)}

t_d(CLKL-NXTV)

t_{d(CLKL-NXTIV)}

HSU7 t_d(CLKL-DV)

t_d(CLKL-DIV)

Delay time, hsusbx_tll_clk high to output hsusbx_tll_dir valid

Delay time, hsusbx_tll_clk high to output hsusbx_tll_dir invalid

Delay time, hsusbx_tll_clk high to output hsusbx_tll_nxt valid

Delay time, hsusbx_tll_clk high to output hsusbx_tll_nxt invalid

Delay time, hsusbx_tll_clk high to output hsusbx_tll_data[7:0] valid

Delay time, hsusbx_tll_clk high to output hsusbx_tll_data[7:0] invalid

Rise time, output signals

0

9

t_R(do)

2

t_F(do)

Fall time, output signals

(2) The jitter probability density can be approximated by a Gaussian function.

HSU0

hsusbx_tll_clk

HSU3

HSU2

hsusbx_tll_stp

HSU6

hsusbx_tll_dir_&_nxt

HSU4

HSU7

HSU5

HSU7

Data_IN

Data_OUT

hsusbx_tll_data[7:0]

In hsusbx, x is equal to 1, 2, or 3.

030-088

Figure 6-51. High-Speed USB – 12-bit TLL Master Mode

6.6.4.4 High-Speed Universal Serial Bus (USB) on Ports 1, 2, and 3 – 8-bit TLL Master Mode

Table 6-105 and Table 6-106 assume testing over the recommended operating conditions (see Figure 6-

52).

Table 6-104. High-Speed USB Timing Conditions – 8-bit TLL Master Mode

TIMING CONDITION PARAMETER

Input Conditions

VALUE

UNIT

t_R

Input signal rise time

Input signal fall time

2

ns

t_F

Output Conditions

C_LOAD

Output load capacitance

3

pF

Table 6-105. High-Speed USB Timing Requirements – 8-bit TLL Master Mode⁽¹⁾

NO.

PARAMETER

1.15 V

UNIT

MIN

6

MAX

HSU2 t_s(STPV-CLKH)

HSU3 t_{s(CLKH-STPIV)}

HSU4 t_{s(DATAV-CLKH)}

HSU5 t_{h(CLKH-DATIV)}

Setup time, hsusbx_tll_stp valid before hsusbx_tll_clk rising edge

Hold time, hsusbx_tll_stp valid after hsusbx_tll_clk rising edge

Setup time, hsusbx_tll_data[3:0] valid before hsusbx_tll_clk rising edge

Hold time, hsusbx_tll_data[3:0] valid after hsusbx_tll_clk rising edge

ns

0

3

–0.8

(1) In hsusbx, x is equal to 1, 2, or 3.

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UNIT

Table 6-106. High-Speed USB Switching Characteristics – 8-bit TLL Master Mode⁽¹⁾

NO.

PARAMETER

1.15 V

MIN

MAX

60

HSU0

f_p(CLK)

hsusbx_tll_clk clock frequency

Jitter standard deviation⁽²⁾, hsusbx_tll_clk

MHz

ps

t_j(CLK)

200

52.4%

9

HSU1

HSU6

t_j(CLK)

Duty cycle, hsusbx_tll_clk pulse duration (low and high)

Delay time, hsusbx_tll_clk high to output hsusbx_tll_dir valid

Delay time, hsusbx_tll_clk high to output hsusbx_tll_dir invalid

Delay time, hsusbx_tll_clk high to output hsusbx_tll_nxt valid

Delay time, hsusbx_tll_clk high to output hsusbx_tll_nxt invalid

Delay time, hsusbx_tll_clk high to output hsusbx_tll_data[3:0] valid

Delay time, hsusbx_tll_clk high to output hsusbx_tll_data[3:0] invalid

Rise time, output signals

47.6%

t_d(CLKL-DIRV)

t_{d(CLKL-DIRIV)}

t_d(CLKL-NXTV)

t_{d(CLKL-NXTIV)}

t_d(CLKL-DV)

t_d(CLKL-DIV)

t_R(do)

ns

0

9

4

HSU7

HSU8

2

t_F(do)

Fall time, output signals

(1) In hsusbx, x is equal to 1, 2, or 3.

(2) The jitter probability density can be approximated by a Gaussian function.

HSU0

HSU1

hsusbx_tll_clk

HSU3

HSU2

hsusbx_tll_stp

HSU6

hsusbx_tll_dir_&_nxt

HSU5

HSU4

HSU5

HSU8

HSU7

HSU4

HSU7

Data_IN

Data_IN_(n+1)

Data_IN_(n+2)

Data_OUT

Data_OUT_(n+1)

hsusbx_tll_data[3:0]

030-089

In hsusbx, x is equal to 1, 2, or 3.

Figure 6-52. High-Speed USB – 8-bit TLL Master Mode

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6.6.5 I²C Interface

The multimaster I²C peripheral provides an interface between two or more devices via an I²C serial bus.

The I²C controller supports the multimaster mode which allows more than one device capable of

controlling the bus to be connected to it. Each I²C device is recognized by a unique address and can

operate as either transmitter or receiver, according to the function of the device. In addition to being a

transmitter or receiver, a device connected to the I²C bus can also be considered as master or slave when

performing data transfers. This data transfer is carried out via two serial bidirectional wires:

•

An SDA data line

An SCL clock line

The following sections illustrate the data transfer is in master or slave configuration with 7-bit addressing

format. The I²C interface is compliant with Philips I²C specification version 2.1. It supports standard mode

(up to 100K bits/s), fast mode (up to 400K bits/s) and high-speed mode (up to 3.4Mb/s) .

6.6.5.1 I²C Standard/Fast-Speed Mode

Table 6-107. I²C Standard/Fast-Speed Mode Timings

NO.

PARAMETER⁽¹⁾

Standard Mode

Fast Mode

UNIT

MIN

MAX

MIN

MAX

f_SCL

Clock Frequency, i2cX_scl

100

400

kHz

μs

ns

I1

I2

I3

I4

I5

t_w(SCLH)

Pulse Duration, i2cX_scl high

4

0.6

1.3

100⁽²⁾

0⁽³⁾

t_w(SCLL)

Pulse Duration, i2cX_scl low

4.7

250

0⁽³⁾

4.7

t_{su(SDAV-SCLH)}

t_{h(SCLH–SDAV)}

t_{su(SDAL-SCLH)}

Setup time, i2cX_sda valid before i2cX_scl active level

Hold time, i2cX_sda valid after i2cX_scl active level

3.45⁽⁴⁾

0.9⁽⁴⁾

μs

Setup time, i2cX_scl high after i2cX_sda low (for a

START⁽⁵⁾condition or a repeated START condition)

0.6

I6

I7

I8

t_{h(SCLH–SDAH)}

t_{h(SCLH–RSTART)}

t_w(SDAH)

Hold time, i2cX_sda low level after i2cX_scl high level

(STOP condition)

4

0.6

1.3

μs

Hold time, i2cX_sda low level after i2cX_scl high level (for

a repeated START condition)

Pulse duration, i2cX_sda high between STOP and START

conditions

4.7

t_R(SCL)

t_F(SCL)

t_R(SDA)

t_F(SDA)

CB

Rise time, i2cX_scl

1000

300

60⁽⁶⁾

ns

pF

Fall time, i2cX_scl

Rise time, i2cX_sda

Fall time, i2cX_sda

1000

300

60⁽⁶⁾

Capacitive load for each bus line

(1) In i2cX, X is equal to 1, 2, 3, or 4. Note that I2C4 is master transmitter only.

(2) A fast-mode I²C-bus device can be used in a standard-mode I²C-bus system, but the requirement t_{su(SDAV-SCLH)}≥ 250 ns must then be

met. This is automatically the case if the device does not stretch the low period of the i2cx_scl. If such a device does stretch the low

period of the i2cx_scl, it must output the next data bit to the i2cx_sda line t_r(SDA)max + t_{su(SDAV-SCLH)}= 1000 + 250 = 1250 ns (according

to the standard-mode I²C-bus specification) before the i2cx_scl line is released.

(3) The device provides (via the I²C bus) a hold time of at least 300 ns for the i2cx_sda signal (see the fall and rise time of i2cx_scl) to

bridge the undefined region of the falling edge of i2cx_scl.

(4) The maximum t_h(SCLH-SDA)has only to be met if the device does not stretch the low period of the i2cx_scl signal.

(5) After this time, the first clock is generated.

(6) Maximum reference load for i2c4_scl and i2c4_sda is CB = 15 pF.

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START REPEAT

START

STOP

i2cX_sda

I2

I5

I6

I8

I7

I6

I1

I3

I4

i2cX_scl

030-093

Figure 6-53. I²C – Standard/Fast Mode

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6.6.5.2 I²C High-Speed Mode

Table 6-108. I²C HighSpeed Mode Timings^{(1) (2)}

NO.

PARAMETER

CB = 100 pF MAX

CB = 400 pF MAX

UNIT

MIN

MAX

MIN

MAX

f_SCL

Clock frequency, i2cX_scl

Pulse duration, i2cX_scl high

Pulse duration, i2cX_scl low

3.4

1.7

MHz

μs

I1

I2

I3

t_w(SCLH)

t_w(SCLL)

60⁽³⁾

160⁽³⁾

10

120⁽³⁾

320⁽³⁾

10

μs

t_{su(SDAV-SCLH)}

Setup time, i2cX_sda valid before i2cX_scl

active level

ns

I4

I5

t_{h(SCLH–SDAV)}

t_{su(SDAL-SCLH)}

Hold time, i2cX_sda valid after i2cX_scl active

level

0⁽²⁾

160

70

0⁽²⁾

160

150

μs

Setup time, i2cX_scl high after i2cX_sda low

(for a START⁽⁴⁾condition or a repeated START

condition)

I6

I7

t_{h(SCLH–SDAH)}

Hold time, i2cX_sda low level after i2cX_scl high

level (STOP condition)

160

μs

t_{h(SCLH–RSTART)}

Hold time, i2cX_sda low level after i2cX_scl high

level (for a repeated START condition)

ns

t_R(SCL)

Rise time, i2cX_scl

40

80

ns

Rise time, i2cX_scl after a repeated START

condition and after a bit acknowledge

160

t_F(SCL)

t_R(SDA)

t_F(SDA)

C_B

Fall time, i2cX_scl

40

80

ns

Rise time, i2cX_sda

160

Fall time, i2cX_sda

80

60⁽⁵⁾

Capacitive load for each bus line

pF

(1) In i2cX, X is equal to 1, 2, 3, or 4. Note that I2C4 is master transmitter only.

(2) The device provides (via the I²C bus) a hold time of at least 300 ns for the i2cx_sda signal (see the fall and rise time of i2cx_scl) to

bridge the undefined region of the falling edge of i2cx_scl.

(3) HS-mode master devices generate a serial clock signal with a high to low ratio of 1 to 2. t_w(SCLL)> 2 × t_w(SCLH)

.

(4) After this time, the first clock is generated.

(5) Maximum reference load for i2c4_scl and i2c4_sda is C_B= 15 pF.

START REPEAT

STOP

I7

i2cX_sda

I5

I6

I1

I2

I3

I4

i2cX_scl

030-094

Figure 6-54. I²C – High-Speed Mode(1) (2) (3)

(1) HS-mode master devices generate a serial clock signal with a high-to-low ratio of 1 to 2. t_w(SCLL)> 2 x t_w(SCLH)

(2) In i2cX, X is equal to 1, 2, 3, or 4. Note that I2C4 is master transmitter only.

(3) After this time, the first clock is generated.

.

Table 6-109. Correspondence Standard vs. TI Timing References

TI-OMAP

STANDARD-I²C

S/F Mode

F_SCL

HS Mode

F_SCLH

T_HIGH

f_SCL

I1

I2

I3

I4

I5

I6

t_w(SCLH)

T_HIGH

t_w(SCLL)

T_LOW

t_{su(SDAV-SCLH)}

t_h(SCLH-SDAV)

t_{su(SDAL-SCLH)}

t_h(SCLH-SDAH)

T_SU;DAT

T_SU;STA

T_HD;STA

T_SU;DAT

T_SU;STA

T_HD;STA

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Table 6-109. Correspondence Standard vs. TI Timing References (continued)

TI-OMAP

STANDARD-I²C

S/F Mode

T_SU;STO

T_BUF

HS Mode

I7

I8

t_{h(SCLH-RSTART)}

t_w(SDAH)

T_SU;STO

6.6.6 HDQ / 1-Wire Interfaces

This module is intended to work with both the HDQ and the 1-Wire protocols. The protocols use a single

wire to communicate between the master and the slave. The protocols employ an asynchronous return to

1 mechanism where, after any command, the line is pulled high.

6.6.6.1 HDQ Protocol

Table 6-110 and Table 6-111 assume testing over the recommended operating conditions (see Figure 6-

55 through Figure 6-58).

Table 6-110. HDQ Timing Requirements

PARAMETER

t_CYCD

DESCRIPTION

Bit window

MIN

MAX

UNIT

253

μs

t_HW1

68

t_HW0

180

t_RSPS

Command to host respond time⁽¹⁾

(1) Defined by software.

Table 6-111. HDQ Switching Characteristics

PARAMETER

DESCRIPTION

MIN

TYP

193

63

MAX

UNIT

t_B

Break timing

Break recovery

Bit window

μs

t_BR

t_CYCH

t_DW1

t_DW0

253

1.3

Sends1 (write)

Sends0 (write)

101

tB

tBR

HDQ

030-095

Figure 6-55. HDQ Break (Reset) Timing

tCYCH

tHW0

tHW1

HDQ

030-096

Figure 6-56. HDQ Read Bit Timing (Data)

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tCYCD

tDW0

tDW1

HDQ

030-097

Figure 6-57. HDQ Write Bit Timing (Command/Address or Data)

Command _byte_written

0_(LSB)

Data_byte_received

tRSPS

1

Break

1

6

7_(MSB)

0_(LSB)

6

HDQ

030-098

Figure 6-58. HDQ Communication Timing

6.6.6.2 1-Wire Protocol

Table 6-112 and Table 6-113 assume testing over the recommended operating conditions (see Figure 6-

59 through Figure 6-61).

Table 6-112. 1-Wire Timing Requirements

PARAMETER

t_PDH

DESCRIPTION

MIN

MAX

UNIT

Presence pulse delay high

Presence pulse delay low

Read bit-zero time

68

μs

t_PDL

68 – t_PDH

t_RDV+ t_REL

102

Table 6-113. 1-Wire Switching Characteristics

PARAMETER

t_RSTL

DESCRIPTION

MIN

TYP

484

102

1.3

MAX

UNIT

Reset time low

μs

t_RSTH

Reset time high

Write bit cycle time

Write bit-one time

Write bit-zero time

Recovery time

t_SLOT

t_LOW1

t_LOW0

101

134

13

t_REC

t_LOWR

Read bit strobe time

tRSTH

tPDL

tRTSL

tPDH

1-WIRE

030-099

Figure 6-59. 1-Wire Break (Reset) Timing

tSLOT_and_ tREC

tRDV_and_ tREL

tLOWR

1-WIRE

030-100

Figure 6-60. 1-Wire Read Bit Timing (Data)

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tSLOT_and_tREC

tLOW0

1-WIRE

tLOW1

030-101

Figure 6-61. 1-Wire Write Bit Timing (Command/Address or Data)

6.6.7 UART IrDA Interface

The IrDA module can operate in three different modes:

•

Slow infrared (SIR) (≤115.2 Kbits/s)

Medium infrared (MIR) (0.576 Mbits/s and 1.152 Mbits/s)

Fast infrared (FIR) (4 Mbits/s)

For more information about this interface, see the UART/IrDA chapter in the OMAP35x Technical

Reference Manual (TRM) [literature number SPRUF98].

Pulse duration

90%

50%

10%

t_r

t_f

030-118

Figure 6-62. UART IrDA Pulse Parameters

6.6.7.1 IrDA—Receive Mode

Table 6-114. UART IrDA—Signaling Rate and Pulse Duration—Receive Mode

ELECTRICAL PULSE DURATION

SIGNALING RATE

UNIT

MIN

NOMINAL

SIR

MAX

2.4 Kbit/s

9.6 Kbit/s

1.41

78.1

19.5

9.75

4.87

3.25

1.62

88.55

22.13

11.07

5.96

μs

19.2 Kbit/s

38.4 Kbit/s

57.6 Kbit/s

115.2 Kbit/s

4.34

2.23

MIR

FIR

0.576 Mbit/s

1.152 Mbit/s

297.2

149.6

416

208

518.8

258.4

ns

4.0 Mbit/s (Single pulse)

67

125

164

ns

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Table 6-114. UART IrDA—Signaling Rate and Pulse Duration—Receive

Mode (continued)

ELECTRICAL PULSE DURATION

SIGNALING RATE

UNIT

MIN

NOMINAL

MAX

4.0 Mbit/s (Double pulse)

190

250

289

ns

Table 6-115. UART IrDA—Rise and Fall Time—Receive

Mode

PARAMETER

MAX

UNIT

t_R

t_F

Rising time,

uart3_rx_irrx

200

ns

Falling time,

uart3_rx_irrx

200

ns

6.6.7.2 IrDA—Transmit Mode

Table 6-116. UART IrDA—Signaling Rate and Pulse Duration—Transmit Mode

SIGNALING RATE

ELECTRICAL PULSE DURATION

UNIT

MIN

NOMINAL

SIR

MAX

2.4 Kbit/s

9.6 Kbit/s

78.1

19.5

9.75

4.87

3.25

1.62

78.1

19.5

9.75

4.87

3.25

1.62

MIR

78.1

19.5

9.75

4.87

3.25

1.62

μs

19.2 Kbit/s

38.4 Kbit/s

57.6 Kbit/s

115.2 Kbit/s

0.576 Mbit/s

1.152 Mbit/s

414

206

416

419

211

ns

208

FIR

4.0 Mbit/s (Single pulse)

4.0 Mbit/s (Double pulse)

123

248

125

128

253

ns

250

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6.7 Removable Media Interfaces

6.7.1 High-Speed Multimedia Memory Card (MMC) and Secure Digital IO Card (SDIO) Timing

The MMC/SDIO host controller provides an interface to high-speed and standard MMC, SD memory

cards, or SDIO cards. The application interface is responsible for managing transaction semantics. The

MMC/SDIO host controller deals with MMC/SDIO protocol at transmission level, packing data, adding

CRC, start/end bit, and checking for syntactical correctness.

There are three MMC interfaces on the OMAP3515/03:

•

MMC/SD/SDIO Interface 1:

–

1.8 V/3 V support

8 bits

•

MMC/SD/SDIO Interface 2:

–

1.8 V support

8 bits

4 bits with external transceiver allowing to support 3 V peripherals. Transceiver direction control

signals are multiplexed with the upper four data bits.

•

MMC/SD/SDIO Interface 3:

–

1.8 V support

8 bits

6.7.1.1 MMC/SD/SDIO in SD Identification Mode

Table 6-118 and Table 6-119 assume testing over the recommended operating conditions and electrical

characteristic conditions.

Table 6-117. MMC/SD/SDIO Timing Conditions – SD Identification Mode

TIMING CONDITION PARAMETER

VALUE

UNIT

SD Identification Mode

Input Conditions

t_R

Input signal rise time

Input signal fall time

10

ns

t_F

Output Conditions

C_LOAD

Output load capacitance

40

pF

Table 6-118. MMC/SD/SDIO Timing Requirements – SD Identification Mode^{(1) (2) (3)}

NO.

PARAMETER

1.15 V

1.0 V

UNIT

MIN

MAX

MIN

MAX

SD Identification Mode

MMC/SD/SDIO Interface 1 (1.8 V IO)

HSSD3/SD3 t_{su(CMDV-CLKIH)}

Setup time, mmc1_cmd valid before

mmc1_clk rising clock edge

1198.4

1249.2

1198.4

1249.2

ns

HSSD4/SD4 t_{su(CLKIH-CMDIV)}

Hold time, mmc1_cmd valid after

mmc1_clk rising clock edge

MMC/SD/SDIO Interface 1 (3.0 V IO)

HSSD3/SD3 t_{su(CMDV-CLKIH)}

HSSD4/SD4 t_{su(CLKIH-CMDIV)}

MMC/SD/SDIO Interface 2

Setup time, mmc1_cmd valid before

mmc1_clk rising clock edge

1198.4

1249.2

1198.4

1249.2

ns

Hold time, mmc1_cmd valid after

mmc1_clk rising clock edge

(1) Timing parameters are referred to output clock specified in Table 6-119.

(2) The timing requirements are assured for the cycle jitter and duty cycle error conditions specified in Table 6-119.

(3) Corresponding figures showing timing parameters are common with other interface modes. (See SD and HS SD modes).

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Table 6-118. MMC/SD/SDIO Timing Requirements – SD Identification Mode^{(1) (2) (3)}(continued)

NO.

PARAMETER

1.15 V

1.0 V

UNIT

MIN

MAX

MIN

MAX

HSSD3/SD3 t_{su(CMDV-CLKIH)}

HSSD4/SD4 t_{su(CLKIH-CMDIV)}

Setup time, mmc2_cmd valid before

mmc2_clk rising clock edge

1198.4

ns

Hold time, mmc2_cmd valid after

mmc2_clk rising clock edge

1249.2

MMC/SD/SDIO Interface 3

HSSD3/SD3 t_{su(CMDV-CLKIH)}

Setup time, mmc3_cmd valid before

mmc3_clk rising clock edge

1198.4

1249.2

1198.4

1249.2

ns

HSSD4/SD4 t_{su(CLKIH-CMDIV)}

Hold time, mmc3_cmd valid after

mmc3_clk rising clock edge

Table 6-119. MMC/SD/SDIO Switching Characteristics – SD Identification Mode⁽¹⁾

NO.

PARAMETER

1.15 V

1.0 V

UNIT

MIN

MAX

MIN

MAX

SD Identification Mode

(3)

1 /

1/t_c(clk)

Frequency⁽²⁾, mmcx_ clk

0.4

MHz

(HSSD1/SD1

)

HSSD2/SD2 t_W(clkH)

HSSD2/SD2 t_W(clkL)

t_dc(clk)

Typical pulse duration, output clk high

Typical pulse duration, output clk low

Duty cycle error, output clk

X⁽⁴⁾*PO⁽⁵⁾

Y⁽⁶⁾*PO⁽⁵⁾

X⁽⁴⁾*PO⁽⁵⁾

Y⁽⁶⁾*PO⁽⁵⁾

ns

ps

125

t_j(clk)

Jitter standard deviation⁽⁷⁾, output clk

200

MMC/SD/SDIO Interface 1 (1.8 V IO)

t_c(clk)

Rise time, output clk

10

ns

t_W(clkH)

t_W(clkL)

t_dc(clk)

Fall time, output clk

Rise time, output data

Fall time, output data

10

HSSD5/SD5 t_d(CLKOH-CMD)Delay time, mmc1_clk rising clock edge to

mmc1_cmd transition

6.3

2492.7

6.3

2492.7

MMC/SD/SDIO Interface 1 (3.0 V IO)

t_c(clk)

Rise time, output clk

Fall time, output clk

Rise time, output data

Fall time, output data

10

0

ns

t_W(clkH)

t_W(clkL)

t_dc(clk)

10

HSSD5/SD5 t_d(CLKOH-CMD)Delay time, mmc1_clk rising clock edge to

mmc1_cmd transition

2492.7

MMC/SD/SDIO Interface 2

t_c(clk)

Rise time, output clk

Fall time, output clk

Rise time, output data

Fall time, output data

10

ns

t_W(clkH)

t_W(clkL)

t_dc(clk)

10

HSSD5/SD5 t_d(CLKOH-CMD)Delay time, mmc2_clk rising clock edge to

mmc2_cmd transition

2492.7

MMC/SD/SDIO Interface 3

t_c(clk)

Rise time, output clk

10

ns

(1) Corresponding figures showing timing parameters are common with other interface modes (see SD and HS SD modes).

(2) Related with the output clk maximum and minimum frequencies programmable in I/F module.

(3) In mmcx_clk, 'x' is equal to 1, 2, or 3.

(4) The X parameter is defined as shown in Table 6-120.

(5) PO = output clk period in ns.

(6) The Y parameter is defined as shown in Table 6-121.

(7) The jitter probability density can be approximated by a Gaussian function.

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Table 6-119. MMC/SD/SDIO Switching Characteristics – SD Identification Mode⁽¹⁾(continued)

NO.

PARAMETER

1.15 V

1.0 V

UNIT

MIN

MAX

10

MIN

MAX

10

t_W(clkH)

t_W(clkL)

t_dc(clk)

Fall time, output clk

Rise time, output data

Fall time, output data

ns

10

HSSD5/SD5 t_d(CLKOH-CMD)Delay time, mmc3_clk rising clock edge to

mmc3_cmd transition

6.3

2492.7

6.3

2492.7

Table 6-120. X Parameter

CLKD

1 or Even

Odd

X

0.5

(trunk[CLKD/2]+1)/CLKD

Table 6-121. Y Parameter

CLKD

1 or Even

Odd

Y

0.5

(trunk[CLKD/2])/CLKD

For details about clock division factor CLKD, see the OMAP35x Technical Reference Manual (TRM)

[literature number SPRUF98].

6.7.1.2 MMC/SD/SDIO in High-Speed MMC Mode

Table 6-123 and Table 6-124 assume testing over the recommended operating conditions and electrical

characteristic conditions (see Figure 6-63 and Figure 6-64).

Table 6-122. MMC/SD/SDIO Timing Conditions – High-Speed MMC Mode

TIMING CONDITION PARAMETER

VALUE

UNIT

High-Speed MMC Mode

Input Conditions

t_R

Input signal rise time

Input signal fall time

3

ns

t_F

Output Conditions

C_LOAD

Output load capacitance

30

pF

Table 6-123. MMC/SD/SDIO Timing Requirements – High-Speed MMC Mode^{(1) (2) (3) (4)}

NO.

PARAMETER

1.15 V

1.0 V

UNIT

MIN

MAX

MIN

MAX

High-Speed MMC Mode

MMC/SD/SDIO Interface 1 (1.8 V IO)

MMC3 t_{su(CMDV-CLKIH)}

MMC4 t_{su(CLKIH-CMDIV)}

MMC7 t_{su(DATxV-CLKIH)}

MMC8 t_{su(CLKIH-DATxIV)}

Setup time, mmc1_cmd valid before mmc1_clk

rising clock edge

5.6

2.3

5.6

2.3

26

1.9

26

ns

Hold time, mmc1_cmd valid after mmc1_clk

rising clock edge

Setup time, mmc1_datx valid before mmc1_clk

rising clock edge

Hold time, mmc1_datx valid after mmc1_clk

rising clock edge

1.9

(1) Timing parameters are referred to output clock specified in Table 6-124.

(2) The timing requirements are assured for the cycle jitter and duty cycle error conditions specified in Table 6-124.

(3) Corresponding figures showing timing parameters are common with Standard MMC mode (See Figure 6-63 and Figure 6-64)

(4) In datx, x is equal to 1, 2, 3, 4, 5, 6, or 7.

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Table 6-123. MMC/SD/SDIO Timing Requirements – High-Speed MMC Mode^{(1) (2) (3) (4)}(continued)

NO.

PARAMETER

1.15 V

1.0 V

UNIT

MIN

MAX

MIN

MAX

MMC/SD/SDIO Interface 1 (3.0 V IO)

MMC3 t_{su(CMDV-CLKIH)}

MMC4 t_{su(CLKIH-CMDIV)}

MMC7 t_{su(DATxV-CLKIH)}

MMC8 t_{su(CLKIH-DATxIV)}

Setup time, mmc1_cmd valid before mmc1_clk

rising clock edge

5.6

2.3

5.6

2.3

26

1.9

26

ns

Hold time, mmc1_cmd valid after mmc1_clk

rising clock edge

Setup time, mmc1_datx valid before mmc1_clk

rising clock edge

Hold time, mmc1_datx valid after mmc1_clk

rising clock edge

1.9

MMC/SD/SDIO Interface 2

MMC3 t_{su(CMDV-CLKIH)}

Setup time, mmc2_cmd valid before mmc2_clk

rising clock edge

5.6

2.3

5.6

2.3

26

1.9

26

ns

MMC4 t_{su(CLKIH-CMDIV)}

MMC7 t_{su(DATxV-CLKIH)}

MMC8 t_{su(CLKIH-DATxIV)}

Hold time, mmc2_cmd valid after mmc2_clk

rising clock edge

Setup time, mmc2_datx valid before mmc2_clk

rising clock edge

Hold time, mmc2_datx valid after mmc2_clk

rising clock edge

1.9

MMC/SD/SDIO Interface 3

MMC3 t_{su(CMDV-CLKIH)}

Setup time, mmc3_cmd valid before mmc3_clk

rising clock edge

5.6

2.3

5.6

2.3

26

1.9

26

ns

MMC4 t_{su(CLKIH-CMDIV)}

MMC7 t_{su(DATxV-CLKIH)}

MMC8 t_{su(CLKIH-DATxIV)}

Hold time, mmc3_cmd valid after mmc3_clk

rising clock edge

Setup time, mmc3_datx valid before mmc3_clk

rising clock edge

Hold time, mmc3_datx valid after mmc3_clk

rising clock edge

1.9

Table 6-124. MMC/SD/SDIO Switching Characteristics – High-Speed MMC Mode⁽¹⁾

N O.

PARAMETER

1.15 V

1.0 V

UNIT

MIN

MAX

MIN

MAX

High-Speed MMC Mode

(3)

1/MMC 1/t_c(clk)

1

Frequency⁽²⁾, mmcx_ clk

48

24

MHz

MMC2

t_W(clkH)

t_W(clkL)

t_dc(clk)

t_j(clk)

Typical pulse duration, output clk high

Typical pulse duration, output clk low

Duty cycle error, output clk

X⁽⁴⁾*PO⁽⁵⁾

⁽⁶⁾*PO⁽⁵⁾

X⁽⁴⁾*PO⁽⁵⁾

Y

⁽⁶⁾*PO⁽⁵⁾

ns

ps

Y

1041.7

200

2083.3

200

Jitter standard deviation(3), output clk

MMC/SD/SDIO Interface 1 (1.8 V IO)

t_c(clk)

Rise time, output clk

3

ns

t_W(clkH)

t_W(clkL)

Fall time, output clk

Rise time, output data

Fall time, output data

3

t_dc(clk)

3

MMC5

t_d(CLKOH-CMD)

Delay time, mmc1_clk rising clock edge to

mmc1_cmd transition

3.7

14.1

4.1

34.5

(1) In datx, x is equal to 1, 2, 3, 4, 5, 6, or 7.

(2) Related with the output clk maximum and minimum frequencies programmable in I/F module.

(3) In mmcx_clk, 'x' is equal to 1, 2, or 3.

(4) The X parameter is defined as shown in Table 6-125.

(5) PO = output clk period in ns.

(6) The Y parameter is defined as shown in Table 6-126.

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Table 6-124. MMC/SD/SDIO Switching Characteristics – High-Speed MMC Mode⁽¹⁾(continued)

N O.

PARAMETER

1.15 V

1.0 V

UNIT

MIN

MAX

MIN

MAX

MMC6

t_{d(CLKOH-DATx)}

Delay time, mmc1_clk rising clock edge to

mmc1_datx transition

3.7

14.1

4.1

34.5

ns

MMC/SD/SDIO Interface 1 (3.0 V IO)

t_c(clk)

Rise time, output clk

3

ns

t_W(clkH)

t_W(clkL)

Fall time, output clk

Rise time, output data

Fall time, output data

3

t_dc(clk)

3

MMC5

MMC6

t_d(CLKOH-CMD)

Delay time, mmc1_clk rising clock edge to

mmc1_cmd transition

3.7

14.1

4.1

34.5

t_{d(CLKOH-DATx)}

Delay time, mmc1_clk rising clock edge to

mmc1_datx transition

14.1

34.5

ns

MMC/SD/SDIO Interface 2

t_c(clk)

Rise time, output clk

Fall time, output clk

Rise time, output data

Fall time, output data

3

ns

t_W(clkH)

t_W(clkL)

t_dc(clk)

3

MMC5

MMC6

t_d(CLKOH-CMD)

Delay time, mmc2_clk rising clock edge to

mmc2_cmd transition

3.7

14.1

4.1

34.5

t_{d(CLKOH-DATx)}

Delay time, mmc2_clk rising clock edge to

mmc2_datx transition

16.5

36.9

ns

MMC/SD/SDIO Interface 3

t_c(clk)

Rise time, output clk

Fall time, output clk

Rise time, output data

Fall time, output data

3

ns

t_W(clkH)

t_W(clkL)

t_dc(clk)

3

MMC5

MMC6

t_d(CLKOH-CMD)

Delay time, mmc3_clk rising clock edge to

mmc3_cmd transition

3.7

14.1

4.1

34.5

t_{d(CLKOH-DATx)}

Delay time, mmc3_clk rising clock edge to

mmc3_datx transition

14.1

34.5

ns

Table 6-125. X Parameter

CLKD

1 or Even

Odd

X

0.5

(trunk[CLKD/2]+1)/CLKD

Table 6-126. Y Parameter

CLKD

1 or Even

Odd

Y

0.5

(trunk[CLKD/2])/CLKD

For details about clock division factor CLKD, see the OMAP35x Technical Reference Manual (TRM)

[literature number SPRUF98].

6.7.1.3 MMC/SD/SDIO in Standard MMC Mode and MMC Identification Mode

Table 6-128 and Table 6-129 assume testing over the recommended operating conditions and electrical

characteristic conditions.

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Table 6-127. MMC/SD/SDIO Timing Conditions – Standard MMC Mode and MMC Identification Mode

TIMING CONDITION PARAMETER

Standard MMC Mode and MMC Identification Mode

Input Conditions

VALUE

UNIT

t_R

Input signal rise time

Input signal fall time

10

ns

t_F

Output Conditions

C_LOAD

Output load capacitance

30

pF

TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS

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Table 6-128. MMC/SD/SDIO Timing Requirements – Standard MMC Mode and MMC Identification Mode⁽¹⁾

(2)

NO.

PARAMETER

1.15 V

1.0 V

UNIT

MIN

MAX

MIN

MAX

Standard MMC Mode and MMC Identification Mode

MMC/SD/SDIO Interface 1 (1.8 V IO)

MMC3 t_{su(CMDV-CLKIH)}

MMC4 t_{su(CLKIH-CMDIV)}

MMC7 t_{su(DATxV-CLKIH)}

MMC8 t_{su(CLKIH-DATxIV)}

Setup time, mmc1_cmd valid before

mmc1_clk rising clock edge

13.6

8.9

65.7

8.9

ns

Hold time, mmc1_cmd valid after mmc1_clk

rising clock edge

Setup time, mmc1_datx valid before

mmc1_clk rising clock edge

13.6

8.9

65.7

8.9

Hold time, mmc1_datx valid after mmc1_clk

rising clock edge

MMC/SD/SDIO Interface 1 (3.0 V IO)

MMC3 t_{su(CMDV-CLKIH)}

MMC4 t_{su(CLKIH-CMDIV)}

MMC7 t_{su(DATxV-CLKIH)}

MMC8 t_{su(CLKIH-DATxIV)}

Setup time, mmc1_cmd valid before

mmc1_clk rising clock edge

13.6

8.9

65.7

8.9

ns

Hold time, mmc1_cmd valid after mmc1_clk

rising clock edge

Setup time, mmc1_datx valid before

mmc1_clk rising clock edge

13.6

8.9

65.7

8.9

Hold time, mmc1_datx valid after mmc1_clk

rising clock edge

MMC/SD/SDIO Interface 2

MMC3 t_{su(CMDV-CLKIH)}

Setup time, mmc2_cmd valid before

mmc2_clk rising clock edge

13.6

8.9

65.7

8.9

ns

MMC4 t_{su(CLKIH-CMDIV)}

MMC7 t_{su(DATxV-CLKIH)}

MMC8 t_{su(CLKIH-DATxIV)}

Hold time, mmc2_cmd valid after mmc2_clk

rising clock edge

Setup time, mmc2_datx valid before

mmc2_clk rising clock edge

13.6

8.9

65.7

8.9

Hold time, mmc2_datx valid after mmc2_clk

rising clock edge

MMC/SD/SDIO Interface 3

MMC3 t_{su(CMDV-CLKIH)}

Setup time, mmc3_cmd valid before

mmc3_clk rising clock edge

13.6

8.9

65.7

8.9

ns

MMC4 t_{su(CLKIH-CMDIV)}

MMC7 t_{su(DATxV-CLKIH)}

MMC8 t_{su(CLKIH-DATxIV)}

Hold time, mmc3_cmd valid after mmc3_clk

rising clock edge

Setup time, mmc3_datx valid before

mmc3_clk rising clock edge

13.6

8.9

65.7

8.9

Hold time, mmc3_datx valid after mmc3_clk

rising clock edge

(1) Timing parameters are referred to output clock specified in Table 6-129.

(2) The timing requirements are assured for the cycle jitter and duty cycle error conditions specified in Table 6-129.

Table 6-129. MMC/SD/SDIO Switching Characteristics – Standard MMC Mode and MMC Identification

Mode

NO.

PARAMETER

1.15 V

1.0 V

UNIT

MIN

MAX

MIN

MAX

MMC Identification Mode

(2)

1/MMC 1/t_c(clk)

1

Frequency⁽¹⁾, mmcx_ clk

0.4

MHz

ns

MMC2

t_W(clkH)

Typical pulse duration, output clk high

X⁽³⁾*PO⁽⁴⁾

(1) Related with the output clk maximum and minimum frequencies programmable in I/F module.

(2) In mmcx_clk, 'x' is equal to 1, 2, or 3.

(3) The X parameter is defined as shown in Table 6-130.

(4) PO = output clk period in ns.

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Table 6-129. MMC/SD/SDIO Switching Characteristics – Standard MMC Mode and MMC Identification

Mode (continued)

NO.

PARAMETER

1.15 V

1.0 V

UNIT

MIN

MAX

MIN

MAX

MMC2

t_W(clkL)

t_dc(clk)

t_j(clk)

Typical pulse duration, output clk low

Duty cycle error, output clk

Jitter standard deviation⁽⁵⁾, output clk

Y*PO⁽⁴⁾

ns

ps

125

200

125

200

Standard MMC Mode

(2)

1/MMC 1/t_c(clk)

1

Frequency⁽¹⁾, mmcx_ clk

19.2

9.6

MHz

MMC2

t_W(clkH)

t_W(clkL)

t_dc(clk)

t_j(clk)

Typical pulse duration, output clk high

Typical pulse duration, output clk low

Duty cycle error, output clk

X⁽³⁾*PO⁽⁴⁾

Y*PO⁽⁴⁾

X⁽³⁾*PO⁽⁴⁾

Y*PO⁽⁴⁾

ns

ps

2604.2

200

5208.3

200

Jitter standard deviation⁽⁵⁾, output clk

MMC/SD/SDIO Interface 1 (1.8 V IO)

t_c(clk)

Rise time, output clk

10

ns

t_W(clkH)

t_W(clkL)

Fall time, output clk

Rise time, output data

Fall time, output data

10

t_dc(clk)

10

MMC5

MMC6

t_d(CLKOH-CMD)

Delay time, mmc1_clk rising clock edge to

mmc1_cmd transition

4.3

47.8

4.3

99.9

t_{d(CLKOH-DATx)}

Delay time, mmc1_clk rising clock edge to

mmc1_datx transition

47.8

99.9

ns

MMC/SD/SDIO Interface 1 (3.0 V IO)

t_c(clk)

Rise time, output clk

10

ns

t_W(clkH)

t_W(clkL)

Fall time, output clk

Rise time, output data

Fall time, output data

10

t_dc(clk)

10

MMC5

MMC6

t_d(CLKOH-CMD)

Delay time, mmc1_clk rising clock edge to

mmc1_cmd transition

4.3

47.8

4.3

99.9

t_{d(CLKOH-DATx)}

Delay time, mmc1_clk rising clock edge to

mmc1_datx transition

47.8

99.9

ns

MMC/SD/SDIO Interface 2

t_c(clk)

Rise time, output clk

Fall time, output clk

Rise time, output data

Fall time, output data

10

ns

t_W(clkH)

t_W(clkL)

t_dc(clk)

10

MMC5

MMC6

t_d(CLKOH-CMD)

Delay time, mmc2_clk rising clock edge to

mmc2_cmd transition

4.3

47.8

4.3

99.9

t_{d(CLKOH-DATx)}

Delay time, mmc2_clk rising clock edge to

mmc2_datx transition

47.8

99.9

ns

MMC/SD/SDIO Interface 3

t_c(clk)

Rise time, output clk

Fall time, output clk

Rise time, output data

Fall time, output data

10

ns

t_W(clkH)

t_W(clkL)

t_dc(clk)

10

MMC5

MMC6

t_d(CLKOH-CMD)

Delay time, mmc3_clk rising clock edge to

mmc3_cmd transition

4.3

47.8

4.3

99.9

t_{d(CLKOH-DATx)}

Delay time, mmc3_clk rising clock edge to

mmc3_datx transition

47.8

99.9

ns

(5) The jitter probability density can be approximated by a Gaussian function.

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Table 6-130. X Parameter

CLKD

1 or Even

Odd

X

0.5

(trunk[CLKD/2]+1)/CLKD

Table 6-131. Y Parameter

CLKD

1 or Even

Odd

Y

0.5

(trunk[CLKD/2])/CLKD

For details about clock division factor CLKD, see the OMAP35x Technical Reference Manual (TRM)

[literature number SPRUF98].

MMC1

MMC2

mmcx_clk

MMC3

MMC7

MMC4

mmcx_cmd

MMC8

mmcx_dat[3:0]

030-104

In mmcx, x is equal to 1, 2, or 3.

Figure 6-63. MMC/SD/SDIO – High-Speed and Standard MMC Modes – Data/Command Receive

MMC1

MMC2

mmcx_clk

MMC5

MMC6

MMC5

mmcx_cmd

MMC6

mmcx_dat[3:0]

030-105

In mmcx, x is equal to 1, 2, or 3.

Figure 6-64. MMC/SD/SDIO – High-Speed and Standard MMC Modes – Data/Command Transmit

6.7.1.4 MMC/SD/SDIO in High-Speed SD Mode

Table 6-133 and Table 6-134 assume testing over the recommended operating conditions and electrical

characteristic conditions.

Table 6-132. MMC/SD/SDIO Timing Conditions – High-Speed SD Mode

TIMING CONDITION PARAMETER

VALUE

UNIT

High-Speed SD Mode

Input Conditions

t_R

Input signal rise time

Input signal fall time

3

ns

t_F

Output Conditions

C_LOAD

Output load capacitance

40

pF

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Table 6-133. MMC/SD/SDIO Timing Requirements – High-Speed SD Mode^{(1) (2) (3)}

NO.

PARAMETER

1.15 V

1.0 V

UNIT

MIN

MAX

MIN

MAX

High-Speed SD Mode

MMC/SD/SDIO Interface 1 (1.8 V IO)

HSSD3 t_{su(CMDV-CLKIH)}

HSSD4 t_{su(CLKIH-CMDIV)}

HSSD7 t_{su(DATxV-CLKIH)}

HSSD8 t_{su(CLKIH-DATxIV)}

Setup time, mmc1_cmd valid before

mmc1_clk rising clock edge

5.6

2.3

5.6

2.3

26

1.9

26

ns

Hold time, mmc1_cmd valid after mmc1_clk

rising clock edge

Setup time, mmc1_datx valid before

mmc1_clk rising clock edge

Hold time, mmc1_datx valid after mmc1_clk

rising clock edge

1.9

MMC/SD/SDIO Interface 1 (3.0 V IO)

HSSD3 t_{su(CMDV-CLKIH)}

HSSD4 t_{su(CLKIH-CMDIV)}

HSSD7 t_{su(DATxV-CLKIH)}

HSSD8 t_{su(CLKIH-DATxIV)}

Setup time, mmc1_cmd valid before

mmc1_clk rising clock edge

5.6

2.3

5.6

2.3

26

1.9

26

ns

Hold time, mmc1_cmd valid after mmc1_clk

rising clock edge

Setup time, mmc1_datx valid before

mmc1_clk rising clock edge

Hold time, mmc1_datx valid after mmc1_clk

rising clock edge

1.9

MMC/SD/SDIO Interface 2

HSSD3 t_{su(CMDV-CLKIH)}

Setup time, mmc2_cmd valid before

mmc2_clk rising clock edge

5.6

2.3

5.6

2.3

26

1.9

26

ns

HSSD4 t_{su(CLKIH-CMDIV)}

HSSD7 t_{su(DATxV-CLKIH)}

HSSD8 t_{su(CLKIH-DATxIV)}

Hold time, mmc2_cmd valid after mmc2_clk

rising clock edge

Setup time, mmc2_datx valid before

mmc2_clk rising clock edge

Hold time, mmc2_datx valid after mmc2_clk

rising clock edge

1.9

MMC/SD/SDIO Interface 3

HSSD3 t_{su(CMDV-CLKIH)}

Setup time, mmc3_cmd valid before

mmc3_clk rising clock edge

5.6

2.3

5.6

2.3

26

1.9

26

ns

HSSD4 t_{su(CLKIH-CMDIV)}

HSSD7 t_{su(DATxV-CLKIH)}

HSSD8 t_{su(CLKIH-DATxIV)}

Hold time, mmc3_cmd valid after mmc3_clk

rising clock edge

Setup time, mmc3_datx valid before

mmc3_clk rising clock edge

Hold time, mmc3_datx valid after mmc3_clk

rising clock edge

1.9

(1) Timing Parameters are referred to output clock specified in Table 6-134.

(2) The timing requirements are assured for the cycle jitter and duty cycle error conditions specified in Table 6-134.

(3) In datx, x is equal to 1, 2, 3, 4, 5, 6, or 7.

Table 6-134. MMC/SD/SDIO Switching Characteristics – High-Speed SD Mode

NO.

PARAMETER

1.15 V

1.0 V

UNIT

MIN

MAX

MIN

MAX

High-Speed SD Mode

(2)

1/HSSD 1/t_c(clk)

1

Frequency⁽¹⁾, mmcx_ clk

48

24

ns

HSSD2 t_W(clkH)

Typical pulse duration, output clk high

X⁽³⁾*PO⁽⁴⁾

(1) Related with the output clk maximum and minimum frequencies programmable in I/F module.

(2) In mmcx_clk, 'x' is equal to 1, 2, or 3.

(3) The X parameter is defined as shown in Table 6-135.

(4) PO = output clk period in ns.

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Table 6-134. MMC/SD/SDIO Switching Characteristics – High-Speed SD Mode (continued)

NO.

PARAMETER

1.15 V

1.0 V

UNIT

MIN

MAX

MIN

MAX

HSSD2 t_W(clkL)

t_dc(clk)

Typical pulse duration, output clk low

Duty cycle error, output clk

Jitter standard deviation⁽⁶⁾, output clk

Y⁽⁵⁾*PO⁽⁴⁾

ns

ps

1041.7

200

2083.3

200

t_j(clk)

MMC/SD/SDIO Interface 1 (1.8 V IO)

t_c(clk)Rise time, output clk

t_W(clkH)

3

ns

Fall time, output clk

Rise time, output data

Fall time, output data

t_W(clkL)

3

t_dc(clk)

3

HSSD5 t_d(CLKOH-CMD)

Delay time, mmc1_clk rising clock edge to

mmc1_cmd transition

3.7

14.1

4.1

34.5

HSSD6 t_{d(CLKOH-DATx)}

Delay time, mmc1_clk rising clock edge to

mmc1_datx transition

14.1

34.5

ns

MMC/SD/SDIO Interface 1 (3.0 V IO)

t_c(clk)Rise time, output clk

t_W(clkH)

3

ns

Fall time, output clk

Rise time, output data

Fall time, output data

t_W(clkL)

3

t_dc(clk)

3

HSSD5 t_d(CLKOH-CMD)

Delay time, mmc1_clk rising clock edge to

mmc1_cmd transition

3.7

14.1

4.1

34.5

HSSD6 t_{d(CLKOH-DATx)}

Delay time, mmc1_clk rising clock edge to

mmc1_datx transition

14.1

34.5

ns

MMC/SD/SDIO Interface 2

t_c(clk)

t_W(clkH)

Rise time, output clk

Fall time, output clk

Rise time, output data

Fall time, output data

3

ns

t_W(clkL)

3

t_dc(clk)

3

HSSD5 t_d(CLKOH-CMD)

Delay time, mmc2_clk rising clock edge to

mmc2_cmd transition

3.7

14.1

4.1

34.5

HSSD6 t_{d(CLKOH-DATx)}

Delay time, mmc2_clk rising clock edge to

mmc2_datx transition

14.1

34.5

ns

MMC/SD/SDIO Interface 3

t_c(clk)

t_W(clkH)

Rise time, output clk

Fall time, output clk

Rise time, output data

Fall time, output data

3

ns

t_W(clkL)

3

t_dc(clk)

3

HSSD5 t_d(CLKOH-CMD)

Delay time, mmc3_clk rising clock edge to

mmc3_cmd transition

3.7

14.1

4.1

34.5

HSSD6 t_{d(CLKOH-DATx)}

Delay time, mmc3_clk rising clock edge to

mmc3_datx transition

14.1

34.5

ns

(5) The Y parameter is defined as shown in Table 6-136.

(6) The jitter probability density can be approximated by a Gaussian function.

Table 6-135. X Parameters

CLKD

1 or Even

Odd

X

0.5

(trunk[CLKD/2]+1)/CLKD

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Table 6-136. Y Parameters

CLKD

1 or Even

Odd

Y

0.5

(trunk[CLKD/2])/CLKD

For details about clock division factor CLKD, see the OMAP35x Technical Reference Manual (TRM)

[literature number SPRUF98].

HSSD1

HSSD2

mmcx_clk

HSSD3

HSSD7

HSSD4

mmcx_cmd

HSSD8

mmcx_dat[3:0]

030-106

In mmcx, x is equal to 1, 2, or 3.

Figure 6-65. MMC/SD/SDIO – High-Speed SD Mode – Data/Command Receive

HSSD1

HSSD2

mmcx_clk

HSSD5

HSSD6

HSSD5

mmcx_cmd

HSSD6

mmcx_dat[3:0]

030-107

In mmcx, x is equal to 1, 2, or 3.

Figure 6-66. MMC/SD/SDIO – High-Speed SD Mode – Data/Command Transmit

6.7.1.5 MMC/SD/SDIO in Standard SD Mode

Table 6-138 and Table 6-139 assume testing over the recommended operating conditions and electrical

characteristic conditions (see Figure 6-67).

Table 6-137. MMC/SD/SDIO Timing Conditions – Standard SD Mode

TIMING CONDITION PARAMETER

VALUE

UNIT

Standard SD Mode

Input Conditions

t_R

Input signal rise time

Input signal fall time

10

ns

t_F

Output Conditions

C_LOAD

Output load capacitance

40

pF

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UNIT

Table 6-138. MMC/SD/SDIO Timing Requirements – Standard SD Mode^{(1) (2) (3)}

NO.

PARAMETER

1.15 V

1.0 V

MIN

MAX

MIN

MAX

Standard SD Mode

MMC/SD/SDIO Interface 1 (1.8 V IO)

SD3 t_{su(CMDV-CLKIH)}

SD4 t_{su(CLKIH-CMDIV)}

SD7 t_{su(DATxV-CLKIH)}

SD8 t_{su(CLKIH-DATxIV)}

Setup time, mmc1_cmd valid before mmc1_clk

rising clock edge

6.2

19.4

6.2

47.7

19.2

47.7

19.2

ns

Hold time, mmc1_cmd valid after mmc1_clk

rising clock edge

Setup time, mmc1_datx valid before mmc1_clk

rising clock edge

Hold time, mmc1_datx valid after mmc1_clk

rising clock edge

19.4

MMC/SD/SDIO Interface 1 (3.0 V IO)

SD3 t_{su(CMDV-CLKIH)}

SD4 t_{su(CLKIH-CMDIV)}

SD7 t_{su(DATxV-CLKIH)}

SD8 t_{su(CLKIH-DATxIV)}

Setup time, mmc1_cmd valid before mmc1_clk

rising clock edge

6.2

19.4

6.2

47.7

19.2

47.7

19.2

ns

Hold time, mmc1_cmd valid after mmc1_clk

rising clock edge

Setup time, mmc1_datx valid before mmc1_clk

rising clock edge

Hold time, mmc1_datx valid after mmc1_clk

rising clock edge

19.4

MMC/SD/SDIO Interface 2

SD3 t_{su(CMDV-CLKIH)}

Setup time, mmc2_cmd valid before mmc2_clk

rising clock edge

6.2

19.4

6.2

47.7

19.2

47.7

19.2

ns

SD4 t_{su(CLKIH-CMDIV)}

SD7 t_{su(DATxV-CLKIH)}

SD8 t_{su(CLKIH-DATxIV)}

Hold time, mmc2_cmd valid after mmc2_clk

rising clock edge

Setup time, mmc2_datx valid before mmc2_clk

rising clock edge

Hold time, mmc2_datx valid after mmc2_clk

rising clock edge

19.4

MMC/SD/SDIO Interface 3

SD3 t_{su(CMDV-CLKIH)}

Setup time, mmc3_cmd valid before mmc3_clk

rising clock edge

6.2

19.4

6.2

47.7

19.2

47.7

19.2

ns

SD4 t_{su(CLKIH-CMDIV)}

SD7 t_{su(DATxV-CLKIH)}

SD8 t_{su(CLKIH-DATxIV)}

Hold time, mmc3_cmd valid after mmc3_clk

rising clock edge

Setup time, mmc3_datx valid before mmc3_clk

rising clock edge

Hold time, mmc3_datx valid after mmc3_clk

rising clock edge

19.4

(1) Timing parameters are referred to output clock specified in Table 6-139.

(2) The timing requirements are assured for the cycle jitter and duty cycle error conditions specified in Table 6-139.

(3) In datx, x is equal to 1, 2, 3, 4, 5, 6, or 7.

Table 6-139. MMC/SD/SDIO Switching Characteristics – Standard SD Mode

NO.

PARAMETER

1.15 V

1.0 V

UNIT

MIN

MAX

MIN

MAX

Standard SD Mode

1/SD 1/t_c(clk)

1

Frequency ⁽¹⁾, mmcx_clk⁽²⁾

24

12

MHz

ns

SD2 t_W(clkH)

Typical pulse duration, output clk high

X⁽³⁾*PO⁽⁴⁾

(1) Related with the output clk maximum and minimum frequencies programmable in I/F module.

(2) In mmcx_clk, 'x' is equal to 1, 2, or 3.

(3) The X parameter is defined as shown in Table 6-140.

(4) PO = output clk period in ns.

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Table 6-139. MMC/SD/SDIO Switching Characteristics – Standard SD Mode (continued)

PARAMETER

1.15 V

1.0 V

UNIT

MIN

MAX

MIN

MAX

SD2 t_W(clkL)

t_dc(clk)

Typical pulse duration, output clk low

Duty cycle error, output clk

Jitter standard deviation⁽⁶⁾, output clk

Y⁽⁵⁾*PO⁽⁴⁾

ns

ps

2083.3

200

4166.7

200

t_j(clk)

MMC/SD/SDIO Interface 1 (1.8 V IO)

t_c(clk)Rise time, output clk

t_W(clkH)

10

77

ns

Fall time, output clk

Rise time, output data

Fall time, output data

t_W(clkL)

10

t_dc(clk)

10

SD5 t_d(CLKOH-CMD)

Delay time, mmc1_clk rising clock edge to

mmc1_cmd transition

6.1

35.5

6.3

SD6 t_{d(CLKOH-DATx)}

Delay time, mmc1_clk rising clock edge to

mmc1_datx transition

35.5

77

ns

MMC/SD/SDIO Interface 1 (3.0 V IO)

t_c(clk)Rise time, output clk

t_W(clkH)

10

77

ns

Fall time, output clk

Rise time, output data

Fall time, output data

t_W(clkL)

10

t_dc(clk)

10

SD5 t_d(CLKOH-CMD)

Delay time, mmc1_clk rising clock edge to

mmc1_cmd transition

6.1

35.5

6.3

SD6 t_{d(CLKOH-DATx)}

Delay time, mmc1_clk rising clock edge to

mmc1_datx transition

35.5

77

ns

MMC/SD/SDIO Interface 2

t_c(clk)Rise time, output clk

t_W(clkH)

10

77

ns

Fall time, output clk

Rise time, output data

Fall time, output data

t_W(clkL)

10

t_dc(clk)

10

SD5 t_d(CLKOH-CMD)

Delay time, mmc2_clk rising clock edge to

mmc2_cmd transition

6.1

35.5

6.3

SD6 t_{d(CLKOH-DATx)}

Delay time, mmc2_clk rising clock edge to

mmc2_datx transition

35.5

77

ns

MMC/SD/SDIO Interface 3

t_c(clk)Rise time, output clk

t_W(clkH)

10

77

ns

Fall time, output clk

Rise time, output data

Fall time, output data

t_W(clkL)

10

t_dc(clk)

10

SD5 t_d(CLKOH-CMD)

Delay time, mmc3_clk rising clock edge to

mmc3_cmd transition

6.1

35.5

6.3

SD6 t_{d(CLKOH-DATx)}

Delay time, mmc3_clk rising clock edge to

mmc3_datx transition

35.5

77

ns

(5) The Y parameter is defined as shown in Table 6-141.

(6) The jitter probability density can be approximated by a Gaussian function.

Table 6-140. X Parameter

CLKD

1 or Even

Odd

X

0.5

(trunk[CLKD/2]+1)/CLKD

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Table 6-141. Y Parameter

CLKD

1 or Even

Odd

Y

0.5

(trunk[CLKD/2])/CLKD

For details about clock division factor CLKD, see the OMAP35x Technical Reference Manual (TRM)

[literature number SPRUF98].

SD1

SD2

mmcx_clk

SD3

SD4

mmcx_cmd

SD7

SD8

mmcx_dat[3:0]

030-108

In mmcx, x is equal to 1, 2, or 3.

Figure 6-67. MMC/SD/SDIO – Standard SD Mode – Data/Command Receive

SD1

SD2

mmcx_clk

SD5

SD6

SD5

mmcx_cmd

SD6

mmcx_dat[3:0]

030-109

In mmcx, x is equal to 1, 2, or 3.

Figure 6-68. MMC/SD/SDIO – Standard SD Mode – Data/Command Transmit

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6.8 Test Interfaces

The emulation and trace interfaces allow tracing activities of the following CPUs:

•

ARM1136JF-STM through an Embedded Trace Macro-cell (ETM11) dedicated to enable real-time

trace of the ARM subsystem operations and a Serial Debug Trace Interface (SDTI)

All processors can be emulated via JTAG ports.

6.8.1 Embedded Trace Macro Interface (ETM)

Table 6-142 assumes testing over the recommended operating conditions (see Figure 6-69).

Table 6-142. Embedded Trace Macro Interface Switching Characteristics⁽¹⁾

NO.

PARAMETER

1.15 V

UNIT

MIN

MAX

f

1/t_c(CLK)

Frequency, etk_clk

Cycle time⁽²⁾, etk_clk

166

MHz

ns

ETM0 t_c(CLK)

6

ETM1 t_W(CLK)

ETM2 t_d(CLK-CTL)

ETM3 t_d(CLK-D)

Clock pulse width, etk_clk

2.7

ns

Delay time, etk_clk clock edge to etk_ctl transition

Delay time, etk_clk clock high to etk_d[15:0] transition

–0.5

0.5

ns

(1) The capacitive load is equivalent to 25 pF.

(2) Cycle time is given by considering a jitter of 5%.

ETM0

ETM1

etk_clk

ETM2

etk_ctl

ETM2

ETM3

etk_d[15:0]

030-110

Figure 6-69. Embedded Trace Macro Interface

6.8.2 System Debug Trace Interface (SDTI)

The system debug trace interface (SDTI) module provides real-time software tracing functionality to the

OMAP3515/03 device.

The trace interface has four trace data pins and a trace clock pin.

This interface is a dual-edge interface: the data are available on rising and falling edges of sdti_clk but can

be also configured in single edge mode where data are available on falling edge of sdti_clk.

Serial interface operates in clock stop regime: serial clock is not free running, when there is no trace data

there is no trace clock.

6.8.2.1 System Debug Trace Interface in Dual-Edge Mode

Table 6-144 assumes testing over the recommended operating conditions and electrical characteristic

conditions (see Figure 6-70).

Table 6-143. System Debug Trace Interface Timing Conditions – Dual-Edge Mode

TIMING CONDITION PARAMETER

Output Conditions

VALUE

UNIT

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Table 6-143. System Debug Trace Interface Timing Conditions – Dual-Edge Mode (continued)

TIMING CONDITION PARAMETER

Output load capacitance

VALUE

UNIT

C_LOAD

25

pF

Table 6-144. System Debug Trace Interface Switching Characteristics – Dual-Edge Mode

NO.

PARAMETER

1.15 V

MAX

1.0 V

UNIT

MIN

MAX

SD1 t_c(CLK)

SD2 t_w(CLK)

t_dc(CLK)

Cycle time, sdti_clk period

29

ns

Typical pulse duration, sdti_clk high or low

Duty cycle error, sdti_clk

Rise time, sdti_clk

0.5*P⁽¹⁾

–1.2

1.2

5

–1.2

1.2

5

t_R(CLK)

t_F(CLK)

Fall time, sdti_clk

5

SD3 t_d(CLK-TxD)

Delay time, sdti_clk

transition to sdti_txd[3:0]

transition

Multiplexing mode on etk pins

2.3

10.9

13.9

2.3

10.9

13.9

Multiplexing mode on

jtag_emu pins

t_R(CLK)

t_F(CLK)

Rise time, sdti_txd[3:0]

Fall time, sdti_txd[3:0]

5

ns

(1) P = sdti_clk clock period

SD1

SD2

sdti_clk

SD3

sdti_txd[3:0]

Header Header Ad[7:4]

Ad[3:0] Da[15:12] Da[11:8] Da[7:4]

Da[3:0]

030-111

Figure 6-70. System Debug Trace Interface – Dual-Edge Mode

6.8.2.2 System Debug Trace Interface in Single-Edge Mode

Table 6-146 assumes testing over the recommended operating conditions and electrical characteristic

conditions (see Figure 6-71).

Table 6-145. System Debug Trace Interface Timing Conditions – Single-Edge Mode

TIMING CONDITION PARAMETER

Output Conditions

VALUE

UNIT

C_LOAD

Output load capacitance

25

pF

Table 6-146. System Debug Trace Interface Switching Characteristics – Single-Edge Mode

NO.

PARAMETER

1.15 V

MAX

1.0 V

UNIT

MIN

MAX

SD1 t_c(CLK)

SD2 t_w(CLK)

t_dc(CLK)

Cycle time, sdti_clk period

29

ns

Typical pulse duration, sdti_clk high or low

Duty cycle error, sdti_clk

Rise time, sdti_clk

0.5*P⁽¹⁾

–1.2

1.2

5

–1.2

1.2

5

t_R(CLK)

t_F(CLK)

Fall time, sdti_clk

5

SD3 t_d(CLK-TxD)

Delay time, sdti_clk

transition to sdti_txd[3:0]

transition

Multiplexing mode on etk pins

2.3

26.5

33.2

2.3

26.5

33.2

Multiplexing mode on jtag_emu

pins

t_R(CLK)

t_F(CLK)

Rise time, sdti_txd[3:0]

Fall time, sdti_txd[3:0]

5

ns

(1) P = sdti_clk clock period.

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SD1

SD3

SD2

sdti_clk

SD3

Ad[7:4]

sdti_txd[3:0]

Header

Ad[3:0]

Da[15:12]

Da[11:8]

Da[7:4]

Da[3:0]

030-112

Figure 6-71. System Debug Trace Interface – Single-Edge Mode

6.8.3 JTAG Interfaces

OMAP3515/03 JTAG TAP controller handles standard IEEE JTAG interfaces. The following sections

define the timing requirements for several tools used to test the OMAP3515/03 processors as:

•

Free running clock tool, like XDS560 and XDS510 tools

Adaptive clock tool, like RealView® ICE tool and Lauterbach™ tool

6.8.3.1 JTAG – Free Running Clock Mode

Table 6-148 and Table 6-149 assume testing over the recommended operating conditions and electrical

characteristic conditions (see Figure 6-72).

Table 6-147. JTAG Timing Conditions – Free Running Clock Mode

TIMING CONDITION PARAMETER

VALUE

UNIT

Input Conditions

t_R

Input signal rise time

Input signal fall time

5

ns

t_F

Output Conditions

C_LOAD

Output load capacitance

30

pF

Table 6-148. JTAG Timing Requirements – Free Running Clock Mode⁽¹⁾

NO.

PARAMETER

1.15 V

1.0 V

UNIT

MIN

MAX

MIN

MAX

JT4 t_c(tck)

Cycle time⁽²⁾, jtag_tck period

25

33

ns

ps

ns

JT5 t_w(tckL)

JT6 t_w(tckH)

t_dc(tck)

Typical pulse duration, jtag_tck low

Typical pulse duration, jtag_tck high

Duty cycle error, jtag_tck

0.5*P⁽³⁾

–1250

1.8

1250

–1667

1.8

1667

t_j(tck)

Cycle jitter⁽⁴⁾, jtag_tck

JT7 t_{su(tdiV-rtckH)}

JT8 t_{h(tdiV-rtckH)}

JT9 t_{su(tmsV-rtckH)}

JT10 t_{h(tmsV-rtckH)}

JT12 t_{su(emuxV-rtckH)}

Setup time, jtag_tdi valid before jtag_rtck high

Hold time, jtag_tdi valid after jtag_rtck high

Setup time, jtag_tms valid before jtag_rtck high

Hold time, jtag_tms valid after jtag_rtck high

Setup time, jtag_emux⁽⁵⁾valid before jtag_rtck

high

0.7

1

1.8

0.7

1

14.6

19.8

JT13 t_{h(emuxV-rtckH)}

Hold time,jtag_emux⁽⁵⁾valid after jtag_rtck high

2

2.7

ns

(1) The timing requirements are assured for the cycle jitter and duty cycle error conditions specified.

(2) Related with the input maximum frequency supported by the JTAG module.

(3) P = jtag _tck period in ns.

(4) Maximum cycle jitter supported by jtag _tck input clock.

(5) x = 0 to 1

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Table 6-149. JTAG Switching Characteristics – Free Running Clock Mode

NO.

PARAMETER

1.15 V

1.0 V

UNIT

MIN

MAX

MIN

MAX

JT1 t_c(rtck)

JT2 t_w(rtckL)

JT3 t_w(rtckH)

t_dc(rtck)

Cycle time⁽¹⁾, jtag_rtck period

Typical pulse duration, jtag_rtck low

Typical pulse duration, jtag_rtck high

Duty cycle error, jtag_rtck

25

33

ns

ps

ns

0.5*PO⁽²⁾

–1250

1250

–1667

1667

t_j(rtck)

Jitter standard deviation⁽³⁾, jtag_rtck

33.3

4

33.3

4

t_R(rtck)

Rise time, jtag_rtck

t_F(rtck)

Fall time, jtag_rtck

4

JT11 t_{d(rtckL-tdoV)}

t_R(tdo)

Delay time, jtag_rtck low to jtag_tdo valid

Rise time, jtag_tdo

–5.8

2.7

5.8

4

–7.9

2.7

7.9

4

t_F(tdo)

Fall time, jtag_tdo

4

JT14 t_{d(rtckH-emuxV)}

t_R(emux)

Delay time, jtag_rtck high to ,jtag_emux⁽⁴⁾valid

Rise time, jtag_emux⁽⁴⁾

Fall time, jtag_emux⁽⁴⁾

15.1

6

20.4

6

t_F(emux)

6

(1) Related with the jtag_rtck maximum frequency.

(2) PO = jtag _rtck period in ns.

(3) The jitter probability density can be approximated by a Gaussian function.

(4) x = 0 to 1

JT4

JT1

JT5

JT6

jtag_tck

JT2

JT3

jtag_rtck

JT7

JT8

jtag_tdi

JT9

JT10

JT13

jtag_tms

JT12

jtag_emux(IN)

JT11

jtag_tdo

JT14

jtag_emux(OUT)

030-113

In jtag_emux, x is equal to 0 to 1.

Figure 6-72. JTAG Interface Timing – Free Running Clock Mode

6.8.3.2 JTAG – Adaptive Clock Mode

Table 6-151 and Table 6-152 assume testing over the recommended operating conditions and electrical

characteristic conditions (see Figure 6-73):

Table 6-150. JTAG Timing Conditions – Adaptive Clock Mode

TIMING CONDITION PARAMETER

VALUE

UNIT

Input Conditions

t_R

Input signal rise time

5

ns

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Table 6-150. JTAG Timing Conditions – Adaptive Clock Mode (continued)

TIMING CONDITION PARAMETER

VALUE

UNIT

t_F

Input signal fall time

5

ns

Output Conditions

C_LOAD

Output load capacitance

30

pF

Table 6-151. JTAG Timing Requirements – Adaptive Clock Mode⁽¹⁾

NO.

PARAMETER

1.15 V

1.0 V

UNIT

MIN

MAX

MIN

MAX

JA4

JA5

JA6

t_c(tck)

Cycle time⁽²⁾, jtag_tck period

50

ns

ps

ns

t_w(tckL)

Typical pulse duration, jtag_tck low

Typical pulse duration, jtag_tck high

Duty cycle error, jtag_tck

0.5*P⁽³⁾

t_w(tckH)

t_dc(lclk)

–2500

–1500

13.8

2500

1500

–2500

–1500

13.8

2500

1500

t_j(lclk)

Cycle jitter⁽⁴⁾, jtag_tck

JA7

JA8

JA9

t_{su(tdiV-tckH)}

t_h(tdiV-tckH)

t_{su(tmsV-tckH)}

Setup time, jtag_tdi valid before jtag_tck high

Hold time, jtag_tdi valid after jtag_tck high

Setup time, jtag_tms valid before jtag_tck high

Hold time, jtag_tms valid after jtag_tck high

13.8

JA10 t_h(tmsV-tckH)

13.8

(1) The timing requirements are assured for the cycle jitter and duty cycle error conditions specified.

(2) Related with the input maximum frequency supported by the JTAG module.

(3) P = jtag _tck period in ns.

(4) Maximum cycle jitter supported by jtag _tck input clock.

Table 6-152. JTAG Switching Characteristics – Adaptive Clock Mode

NO.

PARAMETER

1.15 V

1.0 V

UNIT

MIN

MAX

MIN

MAX

JA1

JA2

JA3

t_c(rtck)

Cycle time⁽¹⁾, jtag_rtck period

Typical pulse duration, jtag_rtck low

Typical pulse duration, jtag_rtck high

Duty cycle error, jtag_rtck

Jitter standard deviation⁽³⁾, jtag_rtck

Rise time, jtag_rtck

50

ns

ps

ns

t_w(rtckL)

t_w(rtckH)

t_dc(rtck)

t_j(rtck)

0.5*PO⁽²⁾

2500

–2500

–14.6

2500

–2500

–14.6

33.3

4

33.3

4

t_R(rtck)

t_F(rtck)

Fall time, jtag_rtck

4

JA11 t_{d(rtckL-tdoV)}

Delay time, jtag_rtck low to jtag_tdo valid

Rise time, jtag_tdo,

14.6

4

14.6

4

t_R(tdo)

t_F(tdo)

Fall time, jtag_tdo

4

(1) Related with the jtag _rtck maximum frequency programmable.

(2) PO = jtag _rtck period in ns.

(3) The jitter probability density can be approximated by a Gaussian function.

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JA4

JA5

JA6

jtag_tck

jtag_tdi

JA7

JA9

JA8

JA10

JA1

jtag_tms

JA2

JA3

jtag_rtck

jtag_tdo

JA11

030-114

Figure 6-73. JTAG Interface Timing – Adaptive Clock Mode

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7 PACKAGE CHARACTERISTICS

7.1 Package Thermal Resistance

Table 7-1 provides the thermal resistance characteristics for the recommended package types used on the

OMAP3515/03 Applications Processor.

Table 7-1. OMAP3515/03 Thermal Resistance Characteristics^{(1) (2)}

Package

Power (W)⁽³⁾

R_θJA(°C/W)

R_θJB(°C/W)

R

_θJC(°C/W)⁽⁴⁾

Board Type

(5)

OMAP3515/03

(CBB Pkg.)

0.92871

24.46

21.89

23.69

10.94

6.23

8.1

See

2.31

2S2P⁽⁶⁾

(5)

OMAP3515/03

(CBC Pkg.)

0.92871

2S2P⁽⁶⁾

OMAP3515/03

(CUS Pkg.)

(1)

R_θJA(Theta-JA) = Thermal Resistance Junction-to-Ambient, °C/W

(2) This table provides simulation data and may not represent actual use-case values.

R

_θJB(Theta-JB) = Thermal Resistance Junction-to-Board, °C/W

_θJC(Theta-JC) = Thermal Resistance Junction-to-Case, °C/W

(3) These numbers are based on simulation results and don’t necessarily represent the wattage that the part will take in actual use.

(4) It is recommended to dissipate the heat to the board instead of attempting to remove it from the top of the chip; therefore, top-side heat

sinks should not be used for package.

(5) Not applicable if the POP package has a memory package on top; no heat sink can be used.

(6) The board types are defined by JEDEC (reference JEDEC standard JESD51-9, Test Board for Area Array Surface Mount Package

Thermal Measurements).

7.2 Device Support

7.2.1 Device and Development-Support Tool Nomenclature

To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all

OMAP processors and support tools. Each OMAP device has one of three prefixes: X, P, or null (no

prefix). Texas Instruments recommends two of three possible prefix designators for its support tools:

TMDX and TMDS. These prefixes represent evolutionary stages of product development from engineering

prototypes (TMDX) through fully qualified production devices/tools (TMDS).

Device development evolutionary flow:

X

Experimental device that is not necessarily representative of the final device’s electrical

specifications and may not use production assembly flow. (TMX definition)

P

Prototype device that is not necessarily the final silicon die and may not necessarily meet

final electrical specifications. (TMP definition)

null

Production version of the silicon die that is fully qualified. (TMS definition)

Support tool development evolutionary flow:

TMDX

TMDS

Development support product that has not yet completed Texas Instruments internal

qualification testing.

Fully qualified development support product.

TMX and TMP devices and TMDX development-support tools are shipped against the following

disclaimer:

“Developmental product is intended for internal evaluation purposes.”

Production devices and TMDS development-support tools have been characterized fully, and the quality

and reliability of the device have been demonstrated fully. TI’s standard warranty applies.

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Predictions show that prototype devices (X or P), have a greater failure rate than the standard production

devices. Texas Instruments recommends that these devices not be used in any production system

because their expected end-use failure rate still is undefined. Only qualified production devices are to be

used.

For additional description of the device nomenclature markings, see the OMAP3530/25/15/03 Applications

Processor Silicon Errata (literature number SPRZ278).

X

OMAP3530

D

CBB

( ) ( )( )

blank = 600 MHz Cortex - A8

72 = 720 MHz Cortex - A8

PREFIX

X = Experimental Device

P = Prototype Device

blank= Production Device

blank = Tray

= Tape and Reel

R

blank = 0° C to 90° C (commercial temperature)

= -40° C to 105° C (extended temperature)

A

DEVICE

PACKAGE TYPE

SILICON REVISION

CBB = 515 pin s-PBGA

CBC = 515 pin s-PBGA

CUS = 423 pin s-PBGA

A. For more information on the silicon revision, please see the OMAP3530/25/15/03 Applications Processor Silicon

Errata (literature number SPRZ278).

Figure 7-1. Device Nomenclature

7.2.2 Documentation Support

7.2.2.1 Related Documentation from Texas Instruments

The following documents describe the OMAP3515/03 Applications Processor. Copies of these documents

are available on the Internet at www.ti.com. Tip: Enter the literature number in the search box provided at

www.ti.com.

The current documentation that describes the OMAP3515/03 Applications Processor, related peripherals,

and other technical collateral, is available in the product folder at: www.ti.com.

SPRUF98 OMAP35x Technical Reference Manual. Collection of documents providing detailed

information on the OMAP3 architecture including power, reset, and clock control, interrupts,

memory map, and switch fabric interconnect. Detailed information on the microprocessor unit

(MPU) subsystem, the image, video, and audio (IVA2.2) subsystem, as well a functional

description of the peripherals supported on OMAP35x devices is also included.

SPRU889

High-Speed DSP Systems Design Reference Guide. Provides recommendations for

meeting the many challenges of high-speed DSP system design. These recommendations

include information about DSP audio, video, and communications systems for the C5000 and

C6000 DSP platforms.

7.2.2.2 Related Documentation from Other Sources

The following documents are related to the OMAP3515/03 Applications Processor. Copies of these

documents can be obtained directly from the internet or from your Texas Instruments representative.

Cortex^TM-A8 Technical Reference Manual. This is the technical reference manual for the Cortex-A8

processor. A copy of this document can be obtained via the internet at http://infocenter.arm.com. Please

see the OMAP35x Applications Processor Silicon Errata (literature number SPRZ278) to determine the

revision of the Cortex-A8 core used on your device.

256

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ARM Core Cortex^TM-A8 (AT400/AT401) Errata Notice. Provides a list of advisories for the different

revisions of the Cortex-A8 processor. Contact your TI representative for a copy of this document. Please

see the OMAP35x Applications Processor Silicon Errata (literature number SPRZ278) to determine the

revision of the Cortex-A8 core used on your device.

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