MSP430C11X1_08 [TI]
MIXED SIGNAL MICROCONTROLLER; 混合信号微控制器
| 型号： | MSP430C11X1_08 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | MIXED SIGNAL MICROCONTROLLER |
| 文件： | 总40页 (文件大小：947K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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ꢀ ꢌꢍꢎ ꢏ ꢁꢌ ꢐ ꢑꢋꢒ ꢀ ꢌꢆꢓꢔ ꢆꢔ ꢑꢕ ꢓꢔ ꢒꢒ ꢎꢓ
SLAS241H − SEPTEMBER 1999 − REVISED SEPTEMBER 2004
D
D
Low Supply Voltage Range 1.8 V to 3.6 V
D
D
Serial Onboard Programming,
No External Programming Voltage Needed
Programmable Code Protection by
Security Fuse
Ultralow-Power Consumption
− Active Mode: 160 µA at 1 MHz, 2.2 V
− Standby Mode: 0.7 µA
− Off Mode (RAM Retention): 0.1 µA
Wake-Up From Standby Mode in less
than 6 µs
16-Bit RISC Architecture, 125 ns
Instruction Cycle Time
Family Members Include:
MSP430C1101: 1KB ROM, 128B RAM
MSP430C1111: 2KB ROM, 128B RAM
MSP430C1121: 4KB ROM, 256B RAM
MSP430F1101A: 1KB + 128B Flash Memory
128B RAM
MSP430F1111A: 2KB + 256B Flash Memory
128B RAM
MSP430F1121A: 4KB + 256B Flash Memory
256B RAM
Available in a 20-Pin Plastic Small-Outline
Wide Body (SOWB) Package, 20-Pin Plastic
Small-Outline Thin Package, 20-Pin TVSOP
(F11x1A only) and 24-Pin QFN
For Complete Module Descriptions, Refer
to the MSP430x1xx Family User’s Guide,
Literature Number SLAU049
D
D
D
Basic Clock Module Configurations:
− Various Internal Resistors
− Single External Resistor
− 32-kHz Crystal
− High-Frequency Crystal
− Resonator
D
D
− External Clock Source
D
D
16-Bit Timer_A With Three
Capture/Compare Registers
On-Chip Comparator for Analog Signal
Compare Function or Slope A/D
Conversion
description
The Texas Instruments MSP430 family of ultralow power microcontrollers consist of several devices featuring
different sets of peripherals targeted for various applications. The architecture, combined with five low power
modes is optimized to achieve extended battery life in portable measurement applications. The device features
a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that attribute to maximum code efficiency.
The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less than 6µs.
The MSP430x11x1(A) series is an ultralow-power mixed signal microcontroller with a built-in 16-bit timer,
versatile analog comparator and fourteen I/O pins.
Typical applications include sensor systems that capture analog signals, convert them to digital values, and then
process the data for display or for transmission to a host system. Stand alone RF sensor front end is another
area of application. The I/O port inputs provide single slope A/D conversion capability on resistive sensors.
AVAILABLE OPTIONS
PACKAGED DEVICES
PLASTIC
20-PIN SOWB
(DW)
PLASTIC
20-PIN TSSOP
(PW)
PLASTIC
20-PIN TVSOP
(DGV)
PLASTIC
24-PIN QFN
(RGE)
T
A
MSP430C1101IPW
MSP430C1111IPW
MSP430C1121IPW
MSP430F1101AIPW
MSP430F1111AIPW
MSP430F1121AIPW
MSP430C1101IRGE
MSP430C1111IRGE
MSP430C1121IRGE
MSP430F1101AIRGE
MSP430F1111AIRGE
MSP430F1121AIRGE
MSP430C1101IDW
MSP430C1111IDW
MSP430C1121IDW
MSP430F1101AIDW
MSP430F1111AIDW
MSP430F1121AIDW
MSP430F1101AIDGV
MSP430F1111AIDGV
MSP430F1121AIDGV
−40°C to 85°C
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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Copyright 1999 − 2004 Texas Instruments Incorporated
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1
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ꢀ ꢌ ꢍ ꢎꢏ ꢁꢌ ꢐꢑ ꢋ ꢒ ꢀꢌ ꢆ ꢓꢔꢆ ꢔꢑ ꢕꢓ ꢔꢒ ꢒꢎ ꢓ
SLAS241H − SEPTEMBER 1999 − REVISED SEPTEMBER 2004
RGE PACKAGE
(TOP VIEW)
DW, PW, or DGV PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
TEST
P1.7/TA2/TDO/TDI
P1.6/TA1/TDI/TCLK
P1.5/TA0/TMS
P1.4/SMCLK/TCK
P1.3/TA2
P1.2/TA1
P1.1/TA0
P1.0/TACLK
P2.4/CA1/TA2
P2.3/CA0/TA1
V
CC
osc
SS
XOUT
P2.5/R
V
XIN
RST/NMI
P2.0/ACLK
P2.1/INCLK
P2.2/CAOUT/TA0
23 22 21 20
1
NC
P1.5/TA0/TMS
17 P1.4/SMCLK/TCK
18
V
2
3
4
5
6
SS
XOUT
16
15
14
13
P1.3/TA2
P1.2/TA1
P1.1/TA0
P1.0/TACLK
XIN
RST/NMI
P2.0/ACLK
8
9 10 11
Note: NC pins not internally connected
Power Pad connection to V recommended
SS
functional block diagram
P1/JTAG
XIN XOUT
V
RST/NMI
POR
P2
V
CC
SS
8
6
R
OSC
RAM
256B
Flash/ROM
4KB
Oscillator
ACLK
I/O Port 1
8 I/Os, with 6 I/Os, with
Interrupt
Capability
I/O Port 2
System
Clock
SMCLK
Interrupt
Capability
128B
128B
2KB
1KB
MCLK
MAB,
4 Bit
Test
MAB,16-Bit
JTAG
CPU
MCB
Incl. 16 Reg.
Bus
Conv
MDB, 16-Bit
MDB, 8 Bit
TEST
Watchdog
Timer
Timer_A3
3 CC Reg
Comparator
A
15/16-Bit
2
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SLAS241H − SEPTEMBER 1999 − REVISED SEPTEMBER 2004
Terminal Functions
TERMINAL
DW, PW, or DGV
RGE
NO.
13
DESCRIPTION
NAME
I/O
NO.
13
P1.0/TACLK
P1.1/TA0
I/O General-purpose digital I/O pin/Timer_A, clock signal TACLK input
14
14
I/O General-purpose digital I/O pin/Timer_A, capture: CCI0A input,
compare: Out0 output/BSL transmit
P1.2/TA1
15
16
17
18
19
20
15
16
17
18
20
21
I/O General-purpose digital I/O pin/Timer_A, capture: CCI1A input,
compare: Out1 output
P1.3/TA2
I/O General-purpose digital I/O pin/Timer_A, capture: CCI2A input,
compare: Out2 output
P1.4/SMCLK/TCK
P1.5/TA0/TMS
P1.6/TA1/TDI/TCLK
I/O General-purpose digital I/O pin/SMCLK signal output/test clock, input
terminal for device programming and test
I/O General-purpose digital I/O pin/Timer_A, compare: Out0 output/test
mode select, input terminal for device programming and test
I/O General-purpose digital I/O pin/Timer_A, compare: Out1 output/test
data input or test clock input
†
P1.7/TA2/TDO/TDI
I/O General-purpose digital I/O pin/Timer_A, compare: Out2 output/test
data output terminal or data input during programming
P2.0/ACLK
8
9
6
7
8
I/O General-purpose digital I/O pin/ACLK output
P2.1/INCLK
I/O General-purpose digital I/O pin/Timer_A, clock signal at INCLK
P2.2/CAOUT/TA0
10
I/O General-purpose digital I/O pin/Timer_A, capture: CCI0B input/
comparator_A, output/BSL receive
P2.3/CA0/TA1
P2.4/CA1/TA2
11
12
3
10
11
24
I/O General-purpose digital I/O pin/Timer_A, compare: Out1 output/
comparator_A, input
I/O General-purpose digital I/O pin/Timer_A, compare: Out2 output/
comparator_A, input
P2.5/R
OSC
I/O General-purpose digital I/O pin/input for external resistor that defines
the DCO nominal frequency
RST/NMI
TEST
7
1
5
I
I
Reset or nonmaskable interrupt input
22
Selects test mode for JTAG pins on Port1. The device protection fuse
is connected to TEST.
V
V
2
4
23
Supply voltage
CC
2
Ground reference
SS
XIN
6
4
I
Input terminal of crystal oscillator
Output terminal of crystal oscillator
XOUT
QFN Pad
5
3
O
NA
Package Pad
NA QFN package pad connection to V recommended.
SS
†
TDO or TDI is selected via JTAG instruction.
3
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SLAS241H − SEPTEMBER 1999 − REVISED SEPTEMBER 2004
short-form description
CPU
Program Counter
Stack Pointer
PC/R0
The MSP430 CPU has a 16-bit RISC architecture
that is highly transparent to the application. All
operations, other than program-flow instructions,
are performed as register operations in
conjunction with seven addressing modes for
source operand and four addressing modes for
destination operand.
SP/R1
Status Register
SR/CG1/R2
Constant Generator
CG2/R3
R4
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
The CPU is integrated with 16 registers that
provide reduced instruction execution time. The
register-to-register operation execution time is
one cycle of the CPU clock.
R5
R6
R7
Four of the registers, R0 to R3, are dedicated as
program counter, stack pointer, status register,
and constant generator respectively. The
remaining registers are general-purpose
registers.
R8
R9
Peripherals are connected to the CPU using data,
address, and control buses, and can be handled
with all instructions.
R10
R11
instruction set
R12
R13
The instruction set consists of 51 instructions with
three formats and seven address modes. Each
instruction can operate on word and byte data.
Table 1 shows examples of the three types of
instruction formats; the address modes are listed
in Table 2.
R14
R15
Table 1. Instruction Word Formats
Dual operands, source-destination
Single operands, destination only
Relative jump, un/conditional
e.g. ADD R4,R5
R4 + R5 −−−> R5
e.g. CALL
e.g. JNE
R8
PC −−>(TOS), R8−−> PC
Jump-on-equal bit = 0
Table 2. Address Mode Descriptions
ADDRESS MODE
Register
S
D
SYNTAX
EXAMPLE
MOV R10,R11
MOV 2(R5),6(R6)
OPERATION
F
F
F
F
F
F
F
F
F
MOV Rs,Rd
R10 −−> R11
Indexed
MOV X(Rn),Y(Rm)
MOV EDE,TONI
MOV &MEM,&TCDAT
MOV @Rn,Y(Rm)
M(2+R5)−−> M(6+R6)
M(EDE) −−> M(TONI)
M(MEM) −−> M(TCDAT)
M(R10) −−> M(Tab+R6)
Symbolic (PC relative)
Absolute
Indirect
MOV @R10,Tab(R6)
MOV @R10+,R11
MOV #45,TONI
Indirect
autoincrement
M(R10) −−> R11
R10 + 2−−> R10
F
F
MOV @Rn+,Rm
Immediate
MOV #X,TONI
#45 −−> M(TONI)
NOTE: S = source
D = destination
4
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ꢀ ꢌꢍꢎ ꢏ ꢁꢌ ꢐ ꢑꢋꢒ ꢀ ꢌꢆꢓꢔ ꢆꢔ ꢑꢕ ꢓꢔ ꢒꢒ ꢎꢓ
SLAS241H − SEPTEMBER 1999 − REVISED SEPTEMBER 2004
operating modes
The MSP430 has one active mode and five software selectable low-power modes of operation. An interrupt
event can wake up the device from any of the five low-power modes, service the request and restore back to
the low-power mode on return from the interrupt program.
The following six operating modes can be configured by software:
D
D
Active mode AM;
All clocks are active
Low-power mode 0 (LPM0);
−
−
CPU is disabled
ACLK and SMCLK remain active. MCLK is disabled
D
D
Low-power mode 1 (LPM1);
−
CPU is disabled
ACLK and SMCLK remain active. MCLK is disabled
DCO’s dc-generator is disabled if DCO not used in active mode
Low-power mode 2 (LPM2);
−
CPU is disabled
MCLK and SMCLK are disabled
DCO’s dc-generator remains enabled
ACLK remains active
D
D
Low-power mode 3 (LPM3);
−
CPU is disabled
MCLK and SMCLK are disabled
DCO’s dc-generator is disabled
ACLK remains active
Low-power mode 4 (LPM4);
−
CPU is disabled
ACLK is disabled
MCLK and SMCLK are disabled
DCO’s dc-generator is disabled
Crystal oscillator is stopped
5
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SLAS241H − SEPTEMBER 1999 − REVISED SEPTEMBER 2004
interrupt vector addresses
The interrupt vectors and the power-up starting address are located in the address range of 0FFFFh−0FFE0h.
The vector contains the 16-bit address of the appropriate interrupt handler instruction sequence.
INTERRUPT SOURCE
INTERRUPT FLAG
SYSTEM INTERRUPT
WORD ADDRESS
PRIORITY
Power-up
External reset
Watchdog
WDTIFG
KEYV
(see Note 1)
Reset
0FFFEh
15, highest
Flash Memory
NMIIFG
OFIFG
ACCVIFG
NMI
Oscillator fault
Flash memory access violation
(non)-maskable,
(non)-maskable,
(non)-maskable
0FFFCh
14
(see Notes 1 & 4)
0FFFAh
0FFF8h
0FFF6h
0FFF4h
0FFF2h
13
12
11
10
9
Comparator_A
Watchdog Timer
Timer_A3
CAIFG
WDTIFG
maskable
maskable
maskable
TACCR0 CCIFG (see Note 2)
TACCR1 CCIFG.
TACCR2 CCIFG
Timer_A3
maskable
0FFF0h
8
TAIFG (see Notes 1 & 2)
0FFEEh
0FFECh
0FFEAh
0FFE8h
7
6
5
4
I/O Port P2
(eight flags; see Note 3)
P2IFG.0 to P2IFG.7
(see Notes 1 & 2)
maskable
maskable
0FFE6h
0FFE4h
3
2
I/O Port P1
(eight flags)
P1IFG.0 to P1IFG.7
(see Notes 1 & 2)
0FFE2h
0FFE0h
1
0, lowest
NOTES: 1. Multiple source flags
2. Interrupt flags are located in the module
3. There are eight Port P2 interrupt flags, but only six Port P2 I/O pins (P2.0−5) implemented on the ’C11x1 and ’F11x1A devices.
4. (non)-maskable: the individual interrupt-enable bit can disable an interrupt event, but the general interrupt enable cannot.
Nonmaskable: neither the individual nor the general interrupt-enable bit will disable an interrupt event.
6
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SLAS241H − SEPTEMBER 1999 − REVISED SEPTEMBER 2004
special function registers
Most interrupt and module enable bits are collected into the lowest address space. Special function register bits
not allocated to a functional purpose are not physically present in the device. Simple software access is provided
with this arrangement.
interrupt enable 1 and 2
7
6
5
4
3
2
1
0
Address
0h
OFIE
WDTIE
ACCVIE
NMIIE
rw-0
rw-0
rw-0
rw-0
WDTIE:
Watchdog Timer interrupt enable. Inactive if watchdog mode is selected. Active if Watchdog Timer
is configured in interval timer mode.
OFIE:
Oscillator fault enable
NMIIE:
ACCVIE:
(Non)maskable interrupt enable
Flash access violation interrupt enable
7
6
5
4
3
3
2
2
1
0
Address
01h
interrupt flag register 1 and 2
7
6
5
4
1
0
Address
02h
NMIIFG
OFIFG
WDTIFG
rw-0
rw-1
rw-(0)
WDTIFG:
Set on Watchdog Timer overflow (in watchdog mode) or security key violation.
Reset on V power-up or a reset condition at RST/NMI pin in reset mode.
Flag set on oscillator fault
Set via RST/NMI-pin
CC
OFIFG:
NMIIFG:
7
6
5
4
3
2
1
0
Address
03h
Legend
rw:
Bit can be read and written.
rw-0,1:
rw-(0,1):
Bit can be read and written. It is Reset or Set by PUC.
Bit can be read and written. It is Reset or Set by POR.
SFR bit is not present in device
7
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SLAS241H − SEPTEMBER 1999 − REVISED SEPTEMBER 2004
memory organization
MSP430C1101
MSP430C1111
MSP430C1121
Memory
Main: interrupt vector
Main: code memory
Size
ROM
ROM
1KB ROM
0FFFFh−0FFE0h
0FFFFh−0FC00h
2KB ROM
0FFFFh−0FFE0h
0FFFFh−0F800h
4KB ROM
0FFFFh−0FFE0h
0FFFFh−0F000h
Information memory
Boot memory
RAM
Size
Flash
Not applicable
Not applicable
Not applicable
Not applicable
Not applicable
Not applicable
Size
ROM
Size
128 Byte
128 Byte
256 Byte
027Fh − 0200h
027Fh − 0200h
02FFh − 0200h
Peripherals
16-bit
8-bit
8-bit SFR
01FFh − 0100h
0FFh − 010h
0Fh − 00h
01FFh − 0100h
0FFh − 010h
0Fh − 00h
01FFh − 0100h
0FFh − 010h
0Fh − 00h
MSP430F1101A
MSP430F1111A
MSP430F1121A
Memory
Main: interrupt vector
Main: code memory
Size
Flash
Flash
1KB Flash
0FFFFh−0FFE0h
0FFFFh−0FC00h
2KB Flash
0FFFFh−0FFE0h
0FFFFh−0F800h
4KB Flash
0FFFFh−0FFE0h
0FFFFh−0F000h
Information memory
Boot memory
RAM
Size
Flash
128 Byte
010FFh − 01080h
256 Byte
010FFh − 01000h
256 Byte
010FFh − 01000h
Size
ROM
1KB
0FFFh − 0C00h
1KB
0FFFh − 0C00h
1KB
0FFFh − 0C00h
Size
128 Byte
128 Byte
256 Byte
027Fh − 0200h
027Fh − 0200h
02FFh − 0200h
Peripherals
16-bit
8-bit
8-bit SFR
01FFh − 0100h
0FFh − 010h
0Fh − 00h
01FFh − 0100h
0FFh − 010h
0Fh − 00h
01FFh − 0100h
0FFh − 010h
0Fh − 00h
bootstrap loader (BSL)
The MSP430 bootstrap loader (BSL) enables users to program the flash memory or RAM using a UART serial
interface. Access to the MSP430 memory via the BSL is protected by user-defined password. For complete
description of the features of the BSL and its implementation, see the Application report Features of the MSP430
Bootstrap Loader, Literature Number SLAA089.
BSL Function
Data Transmit
Data Receive
DW, PW & DGV Package Pins
14 - P1.1
RGE Package Pins
14 - P1.1
10 - P2.2
8 - P2.2
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SLAS241H − SEPTEMBER 1999 − REVISED SEPTEMBER 2004
flash memory
The flash memory can be programmed via the JTAG port, the bootstrap loader, or in-system by the CPU. The
CPU can perform single-byte and single-word writes to the flash memory. Features of the flash memory include:
D
Flash memory has n segments of main memory and two segments of information memory (A and B) of 128
bytes each. Each segment in main memory is 512 bytes in size.
D
D
Segments 0 to n may be erased in one step, or each segment may be individually erased.
Segments A and B can be erased individually, or as a group with segments 0−n.
Segments A and B are also called information memory.
D
New devices may have some bytes programmed in the information memory (needed for test during
manufacturing). The user should perform an erase of the information memory prior to the first use.
0FFFFh
0FE00h
Segment0 w/
Interrupt Vectors
0FDFFh
0FC00h
Segment1
Segment2
Segment3
Segment4
Segment5
Segment6
Segment7
SegmentA
SegmentB
0FBFFh
0FA00h
0F9FFh
0F800h
Flash Main Memory
0F7FFh
0F600h
0F5FFh
0F400h
0F3FFh
0F200h
0F1FFh
0F000h
010FFh
01080h
Information
Memory
0107Fh
01000h
NOTE: All segments not implemented on all devices.
9
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SLAS241H − SEPTEMBER 1999 − REVISED SEPTEMBER 2004
peripherals
Peripherals are connected to the CPU through data, address, and control busses and can be handled using
all instructions. For complete module descriptions, refer to the MSP430x1xx Family User’s Guide, literature
number SLAU049.
oscillator and system clock
The clock system is supported by the basic clock module that includes support for a 32768-Hz watch crystal
oscillator, an internal digitally-controlled oscillator (DCO) and a high frequency crystal oscillator. The basic clock
module is designed to meet the requirements of both low system cost and low-power consumption. The internal
DCO provides a fast turn-on clock source and stabilizes in less than 6 µs. The basic clock module provides the
following clock signals:
D
D
D
Auxiliary clock (ACLK), sourced from a 32768-Hz watch crystal or a high frequency crystal.
Main clock (MCLK), the system clock used by the CPU.
Sub-Main clock (SMCLK), the sub-system clock used by the peripheral modules.
digital I/O
There are two 8-bit I/O ports implemented—ports P1 and P2 (only six P2 I/O signals are available on external
pins):
D
D
D
D
All individual I/O bits are independently programmable.
Any combination of input, output, and interrupt conditions is possible.
Edge-selectable interrupt input capability for all the eight bits of port P1 and six bits of port P2.
Read/write access to port-control registers is supported by all instructions.
NOTE:
Six bits of port P2, P2.0 to P2.5, are available on external pins − but all control and data bits for port
P2 are implemented.
watchdog timer
The primary function of the watchdog timer (WDT) module is to perform a controlled system restart after a
software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog
function is not needed in an application, the module can be configured as an interval timer and can generate
interrupts at selected time intervals.
comparator_A
The primary function of the comparator_A module is to support precision slope analog-to-digital conversions,
battery-voltage supervision, and monitoring of external analog signals.
10
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SLAS241H − SEPTEMBER 1999 − REVISED SEPTEMBER 2004
timer_A3
Timer_A3 is a 16-bit timer/counter with three capture/compare registers. Timer_A3 can support multiple
capture/compares, PWM outputs, and interval timing. Timer_A3 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
Timer_A3 Signal Connections
Input
Pin Number
Device
Input Signal
Module
Input Name
Module
Block
Module
Output Signal
Output
Pin Number
DW, PW, DGV
RGE
DW, PW DGV
RGE
13 - P1.0
13 - P1.0
TACLK
ACLK
SMCLK
INCLK
TA0
TACLK
ACLK
Timer
CCR0
CCR1
CCR2
NA
TA0
TA1
TA2
SMCLK
INCLK
CCI0A
CCI0B
GND
9 - P2.1
14 - P1.1
10 - P2.2
7 - P2.1
14 - P1.1
8 - P2.2
14 - P1.1
18 - P1.5
14 - P1.1
18 - P1.5
TA0
V
SS
V
V
CC
CC
15 - P1.2
16 - P1.3
15 - P1.2
16 - P1.3
TA1
CCI1A
CCI1B
GND
11 - P2.3
15 - P1.2
19 - P1.6
10 - P2.3
15 - P1.2
20 - P1.6
CAOUT (internal)
V
SS
V
CC
V
CC
TA2
CCI2A
CCI2B
GND
12 - P2.4
16 - P1.3
20 - P1.7
11 - P2.4
16 - P1.3
21 - P1.7
ACLK (internal)
V
SS
V
CC
V
CC
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SLAS241H − SEPTEMBER 1999 − REVISED SEPTEMBER 2004
peripheral file map
PERIPHERALS WITH WORD ACCESS
Timer_A
Reserved
Reserved
Reserved
Reserved
Capture/compare register
Capture/compare register
Capture/compare register
Timer_A register
Reserved
Reserved
Reserved
Reserved
Capture/compare control
Capture/compare control
Capture/compare control
Timer_A control
Timer_A interrupt vector
017Eh
017Ch
017Ah
0178h
0176h
0174h
0172h
0170h
016Eh
016Ch
016Ah
0168h
0166h
0164h
0162h
0160h
012Eh
TACCR2
TACCR1
TACCR0
TAR
TACCTL2
TACCTL1
TACCTL0
TACTL
TAIV
Flash Memory
Flash control 3
Flash control 2
Flash control 1
FCTL3
FCTL2
FCTL1
012Ch
012Ah
0128h
Watchdog
Watchdog/timer control
WDTCTL
0120h
PERIPHERALS WITH BYTE ACCESS
Comparator_A
Comparator_A port disable
Comparator_A control 2
Comparator_A control 1
CAPD
CACTL2
CACTL1
05Bh
05Ah
059h
Basic Clock
Port P2
Basic clock system control 2
Basic clock system control 1
DCO clock frequency control
BCSCTL2 058h
BCSCTL1 057h
DCOCTL
056h
Port P2 selection
P2SEL
P2IE
02Eh
02Dh
02Ch
02Bh
02Ah
029h
028h
Port P2 interrupt enable
Port P2 interrupt edge select
Port P2 interrupt flag
Port P2 direction
Port P2 output
Port P2 input
P2IES
P2IFG
P2DIR
P2OUT
P2IN
Port P1
Port P1 selection
P1SEL
P1IE
026h
025h
024h
023h
022h
021h
020h
Port P1 interrupt enable
Port P1 interrupt edge select
Port P1 interrupt flag
Port P1 direction
Port P1 output
Port P1 input
P1IES
P1IFG
P1DIR
P1OUT
P1IN
Special Function
SFR interrupt flag 2
SFR interrupt flag 1
SFR interrupt enable 2
SFR interrupt enable 1
IFG2
IFG1
IE2
003h
002h
001h
000h
IE1
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SLAS241H − SEPTEMBER 1999 − REVISED SEPTEMBER 2004
†
absolute maximum ratings
Voltage applied at V
to V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 4.1 V
CC
SS
Voltage applied to any pin (see Note) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to V +0.3 V
Diode current at any device terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 mA
CC
Storage temperature, T (unprogrammed device) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 150°C
stg
Storage temperature, T (programmed device) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 85°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE: All voltages referenced to V . The JTAG fuse-blow voltage, V , is allowed to exceed the absolute maximum rating. The voltage is applied
SS
FB
to the TEST pin when blowing the JTAG fuse.
recommended operating conditions
MIN
NOM
MAX UNITS
MSP430C11x1
MSP430F11x1A
MSP430F11x1A
1.8
1.8
2.7
3.6
V
Supply voltage during program execution, V
CC
(see Note 1)
3.6
Supply voltage during program/erase flash memory, V
CC
3.6
V
V
Supply voltage, V
SS
0
Operating free-air temperature range, T
MSP430x11x1(A)
Watch crystal
Ceramic resonator
Crystal
−40
85
°C
Hz
A
LF mode selected, XTS=0
32768
LFXT1 crystal frequency,
(see Note 1 & 2)
450
8000
8000
f
(LFXT1)
XT1 mode selected, XTS=1
kHz
1000
V
= 1.8 V,
CC
MSP430x11x1(A)
dc
dc
4.15
8
Processor frequency f
(system)
(MCLK signal)
MHz
V
= 3.6 V,
CC
MSP430x11x1(A)
NOTES: 1. In LF mode, the LFXT1 oscillator requires a watch crystal. A 5.1MΩ resistor from XOUT to V
is recommended when V
<
SS
CC
2.5 V. In XT1 mode, the LFXT1 and XT2 oscillators accept a ceramic resonator or crystal up to 4.15MHz at V
≥ 2.2 V. In XT1 mode,
CC
the LFXT1 and XT2 oscillators accept a ceramic resonator or crystal up to 8MHz at V
≥ 2.8 V.
2. In LF mode, the LFXT1 oscillator requires a watch crystal. In XT1 mode, LFXT1 accepts a ceramic resonator or a crystal.
CC
f
(MHz)
SYSTEM
8.0 MHz
Supply voltage range,
’x11x1(A), during
Supply voltage range, ’F11x1A,
during flash memory programming
program execution
4.15 MHz
1.8 V
2.7 V 3 V
Supply Voltage − V
3.6 V
NOTE: Minimum processor frequency is defined by system clock. Flash
program or erase operations require a minimum V of 2.7 V.
CC
Figure 1. Frequency vs Supply Voltage, MSP430x11x1(A)
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SLAS241H − SEPTEMBER 1999 − REVISED SEPTEMBER 2004
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
supply current (into V ) excluding external current
CC
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
T
= −40°C to + 85°C,
V
V
= 2.2 V
= 3 V
160
240
200
300
A
CC
f
f
= f = 1 MHz,
= 32,768 Hz
(MCLK) (SMCLK)
CC
(ACLK)
C11x1
V
V
= 2.2 V
= 3 V
1.3
2.5
2
T
= −40°C to + 85°C,
CC
A
f
= f = 4096 Hz
= f
= −40°C to + 85°C,
3.2
(MCLK) (SMCLK) (ACLK)
CC
T
I
Active mode
µA
A
(AM)
V
CC
V
CC
= 2.2 V
= 3 V
200
300
250
350
f
= f
= 1 MHz,
MCLK (SMCLK)
= 32,768 Hz,
f(ACLK)
Program executes in flash
F11x1A
T
= −40°C to + 85°C,
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 2.2 V
= 3 V
3
11
30
51
32
55
11
17
1.2
2
5
18
40
60
45
70
14
22
1.7
2.7
A
Program executes in flash
= f = f
f
= 4096 Hz
(MCLK) (SMCLK) (ACLK)
= −40°C to + 85°C,
T
= 2.2 V
= 3 V
A
C11x1
f
= 0, f = 1 MHz,
(MCLK)
(SMCLK)
= 32,768 Hz
Low-power mode,
(LPM0)
f(ACLK)
I
I
µA
µA
(CPUOff)
T
= −40°C to + 85°C,
= 2.2 V
= 3 V
A
F11x1A
f
= 0, f = 1 MHz,
(SMCLK)
= 32,768 Hz
(MCLK)
f(ACLK)
T
= −40°C to + 85°C,
= 2.2 V
= 3 V
A
Low-power mode,
(LPM2)
f
= f = 0 MHz,
= 32,768 Hz, SCG0 = 0
(LPM2)
(MCLK) (SMCLK)
f(ACLK)
T
= −40°C to + 85°C,
= 2.2 V
= 3 V
A
C11x1
f
= f
= 0 MHz,
(MCLK) (SMCLK)
= 32,768 Hz, SCG0 = 1
f(ACLK)
T
= −40°C
0.8
0.7
1.6
1.8
1.6
2.3
0.1
0.1
0.4
1.2
1
A
Low-power mode,
(LPM3)
T
A
= 25°C
= 85°C
= −40°C
= 25°C
= 85°C
= −40°C
= 25°C
= 85°C
V
V
= 2.2 V
CC
I
(LPM3)
µA
f
f
f
= 0 MHz,
(MCLK)
T
A
2.3
2.2
1.9
3.4
0.5
0.5
0.8
= 0 MHz,
= 32,768 Hz,
(SMCLK)
F11x1A
T
A
(ACLK)
SCG0 = 1
T
A
= 3 V
CC
T
A
T
A
C11x1
T
A
V
V
= 2.2 V/3 V
= 2.2 V/3 V
CC
f
f
f
= 0 MHz,
= 0 MHz,
= 0 Hz, SCG0 = 1
(MCLK)
(SMCLK)
(ACLK)
T
A
Low-power mode,
(LPM4)
I
(LPM4)
µA
T
A
= −40°C
= 25°C
= 85°C
0.1
0.1
0.8
0.5
0.5
1.9
F11x1A
T
A
CC
T
A
NOTE: All inputs are tied to 0 V or V . Outputs do not source or sink any current.
CC
current consumption of active mode versus system frequency, C version, F version
= I × f [MHz]
I
AM
AM[1 MHz]
system
current consumption of active mode versus supply voltage, C version
= I + 105 µA/V × (V −3 V)
I
AM
AM[3 V]
CC
current consumption of active mode versus supply voltage, F version
= I + 120 µA/V × (V −3 V)
I
AM
AM[3 V]
CC
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SLAS241H − SEPTEMBER 1999 − REVISED SEPTEMBER 2004
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
Schmitt-trigger inputs − Ports P1 and P2; (P1.0 to P1.7, P2.0 to P2.5)
PARAMETER
TEST CONDITIONS
MIN
1.1
1.5
0.4
0.9
0.3
0.5
TYP
MAX
1.5
1.9
0.9
1.3
1.1
1
UNIT
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 2.2 V
= 3 V
V
IT+
V
IT−
V
hys
Positive-going input threshold voltage
V
= 2.2 V
= 3 V
Negative-going input threshold voltage
V
V
= 2.2 V
= 3 V
Input voltage hysteresis (V
IT+
− V )
IT−
standard inputs − RST/NMI, JTAG: TCK, TMS, TDI/TCLK
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
V
V
Low-level input voltage
High-level input voltage
V
SS
V
+0.6
SS
IL
V
CC
= 2.2 V / 3 V
0.8×V
V
CC
V
IH
CC
inputs Px.x, TAx
PARAMETER
TEST CONDITIONS
V
CC
MIN
TYP
MAX
UNIT
2.2 V/3 V
2.2 V
3 V
1.5
62
50
62
50
cycle
Port P1, P2: P1.x to P2.x, External trigger signal
for the interrupt flag, (see Note 1)
t
External interrupt timing
Timer_A, capture timing
(int)
ns
ns
2.2 V
3 V
t
f
f
TA0, TA1, TA2
(cap)
2.2 V
3 V
8
10
8
Timer_A clock frequency
externally applied to pin
TACLK, INCLK t = t
(H) (L)
MHz
MHz
(TAext)
2.2 V
3 V
Timer_A clock frequency
SMCLK or ACLK signal selected
(TAint)
10
NOTES: 1. The external signal sets the interrupt flag every time the minimum t
(int)
cycle and time parameters are met. It may be set even with
is measured in
trigger signals shorter than t
MCLK cycles.
. Both the cycle and timing specifications must be met to ensure the flag is set. t
(int)
(int)
leakage current
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Port P1: P1.x, 0 ≤ × ≤ 7
(see Notes 1, 2)
V
= 2.2 V/3 V,
CC
50
50
I
High-impedance leakage current
nA
lkg(Px.x)
Port P2: P2.x, 0 ≤ × ≤ 5
(see Notes 1, 2)
V
CC
= 2.2 V/3 V,
NOTES: 1. The leakage current is measured with V
SS
or V applied to the corresponding pin(s), unless otherwise noted.
CC
2. The leakage of the digital port pins is measured individually. The port pin must be selected for input and there must be no optional
pullup or pulldown resistor.
15
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ꢀ ꢌ ꢍ ꢎꢏ ꢁꢌ ꢐꢑ ꢋ ꢒ ꢀꢌ ꢆ ꢓꢔꢆ ꢔꢑ ꢕꢓ ꢔꢒ ꢒꢎ ꢓ
SLAS241H − SEPTEMBER 1999 − REVISED SEPTEMBER 2004
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
outputs − Ports P1 and P2; (P1.0 to P1.7, P2.0 to P2.5)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
I
I
I
I
I
I
I
I
I
I
I
I
= −1.5 mA
= −6 mA
= −1.5 mA
= −6 mA
= −1 mA
= −3.4 mA
= −1 mA
= −3.4 mA
= 1.5 mA
= 6 mA
See Note 1
See Note 2
See Note 1
See Note 2
See Note 3
See Note 3
See Note 3
See Note 3
See Note 1
See Note 2
See Note 1
See Note 2
V
−0.25
V
V
V
V
V
V
V
V
(OHmax)
(OHmax)
(OHmax)
(OHmax)
(OHmax)
(OHmax)
(OHmax)
(OHmax)
(OLmax)
(OLmax)
(OLmax)
(OLmax)
CC
CC
CC
CC
CC
CC
CC
CC
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 2.2 V
= 3 V
High-level output voltage
Port 1 and Port 2 (C11x1)
Port 1 (F11x1A)
V
−0.6
CC
−0.25
V
OH
V
OH
V
OL
V
V
CC
V
−0.6
CC
−0.25
V
CC
= 2.2 V
= 3 V
V
−0.6
CC
−0.25
High-level output voltage
Port 2 (F11x1A)
V
V
V
CC
V
−0.6
CC
V
V
+0.25
SS
SS
SS
SS
SS
= 2.2 V
= 3 V
Low-level output voltage
Port 1 and Port 2 (C11x1,
F11x1A)
V
V
V
V
+0.6
SS
= 1.5 mA
= 6 mA
V
SS
+0.25
V
+0.6
SS
NOTES: 1. The maximum total current, I
drop specified.
and I
, for all outputs combined, should not exceed 12 mA to hold the maximum voltage
OHmax
OLmax
OLmax
2. The maximum total current, I
drop specified.
and I
, for all outputs combined, should not exceed 48 mA to hold the maximum voltage
OHmax
3. One output loaded at a time.
output frequency
PARAMETER
TEST CONDITIONS
P2.0/ACLK, C = 20 pF
VCC
MIN
TYP
MAX
UNIT
f
f
2.2 V/3 V
f
f
P20
L
System
Output frequency
MHz
TA0, TA1, TA2, C = 20 pF
L
Internal clock source, SMCLK signal applied (see Note 1)
2.2 V/3 V
dc
TAx
System
f
= f
= f
40%
35%
60%
65%
SMCLK LFXT1 XT1
f
= f
= f
= f
SMCLK
SMCLK
LFXT1 LF
2.2 V/3 V
2.2 V/3 V
P1.4/SMCLK,
= 20 pF
50%−
15 ns
50%+
15 ns
C
f
f
50%
50%
L
LFXT1/n
DCOCLK
50%−
15 ns
50%+
15 ns
t
t
Xdc
Duty cycle of O/P
frequency
= f
SMCLK
f
f
f
= f
= f
40%
30%
60%
70%
P20 LFXT1 XT1
P2.0/ACLK,
= 20 pF
= f
= f
= f
2.2 V/3 V
2.2 V/3 V
P20
P20
LFXT1 LF
C
L
50%
0
LFXT1/n
TA0, TA1, TA2, C = 20 pF, duty cycle = 50%
50
ns
TAdc
L
NOTE 1: The limits of the system clock MCLK has to be met. MCLK and SMCLK can have different frequencies.
16
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂꢃ ꢄ ꢅ ꢆꢇꢇ ꢈ ꢇ ꢉ ꢀ ꢁꢂꢃ ꢄꢅ ꢊꢇꢇꢈ ꢇꢋ
ꢀ ꢌꢍꢎ ꢏ ꢁꢌ ꢐ ꢑꢋꢒ ꢀ ꢌꢆꢓꢔ ꢆꢔ ꢑꢕ ꢓꢔ ꢒꢒ ꢎꢓ
SLAS241H − SEPTEMBER 1999 − REVISED SEPTEMBER 2004
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
outputs − Ports P1 and P2 (continued)
TYPICAL LOW-LEVEL OUTPUT CURRENT
TYPICAL LOW-LEVEL OUTPUT CURRENT
vs
vs
LOW-LEVEL OUTPUT VOLTAGE
LOW-LEVEL OUTPUT VOLTAGE
16
14
12
10
8
25
20
15
10
5
V
CC
P1.0
= 2.2 V
T
= 25°C
V
CC
P1.0
= 3 V
A
T
= 25°C
A
T
= 85°C
A
T
= 85°C
A
6
4
2
0
0.0
0
0.0
0.5
1.0
1.5
2.0
2.5
0.5
1.0
1.5
2.0
2.5
3.0
3.5
V
OL
− Low-Level Output Voltage − V
V
OL
− Low-Level Output Voltage − V
Figure 2
Figure 3
TYPICAL HIGH-LEVEL OUTPUT CURRENT
TYPICAL HIGH-LEVEL OUTPUT CURRENT
vs
vs
HIGH-LEVEL OUTPUT VOLTAGE
HIGH-LEVEL OUTPUT VOLTAGE
0
−2
0
−5
V
CC
P1.0
= 2.2 V
V
CC
P1.0
= 3 V
−4
−10
−15
−20
−25
−30
−6
−8
T
A
= 85°C
−10
−12
−14
T
A
= 85°C
T
A
= 25°C
T
A
= 25°C
0.0
0.5
OH
1.0
1.5
2.0
2.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
V
− High-Level Output Voltage − V
V
OH
− High-Level Output Voltage − V
Figure 4
Figure 5
NOTE: One output loaded at a time.
17
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇꢇ ꢈꢇ ꢉ ꢀꢁ ꢂ ꢃꢄ ꢅ ꢊ ꢇꢇ ꢈ ꢇꢋ
ꢀ ꢌ ꢍ ꢎꢏ ꢁꢌ ꢐꢑ ꢋ ꢒ ꢀꢌ ꢆ ꢓꢔꢆ ꢔꢑ ꢕꢓ ꢔꢒ ꢒꢎ ꢓ
SLAS241H − SEPTEMBER 1999 − REVISED SEPTEMBER 2004
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
optional resistors, individually programmable with ROM code (see Note 1)
PARAMETER
TEST CONDITIONS
MIN
2.5
3.8
7.6
11.5
23
TYP
5
MAX
10
UNIT
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
R
R
R
R
R
R
R
R
R
R
(opt1)
(opt2)
(opt3)
(opt4)
(opt5)
(opt6)
(opt7)
(opt8)
(opt9)
(opt10)
7.7
15
15
31
23
46
45
90
Resistors, individually programmable with ROM code, all port pins,
values applicable for pulldown and pullup
V
CC
= 2.2 V/3 V
46
90
180
280
460
640
830
70
140
230
320
420
115
160
205
NOTE 1: Optional resistors R
optx
for pulldown or pullup are not available in standard flash memory device MSP430F11x1A.
wake-up from lower power modes (LPMx)
PARAMETER
TEST CONDITIONS
= 2.2 V/3 V
MIN
TYP
100
100
MAX
UNIT
t
t
V
V
(LPM0)
CC
ns
= 2.2 V/3 V
(LPM2)
CC
f
f
f
= 1 MHz,
= 2 MHz,
= 3 MHz,
V
V
V
= 2.2 V/3 V
= 2.2 V/3 V
= 2.2 V/3 V
6
6
6
(MCLK)
(MCLK)
(MCLK)
CC
CC
CC
t
t
µs
µs
(LPM3)
Delay time (see Note 1)
f
f
f
= 1 MHz,
= 2 MHz,
= 3 MHz,
V
CC
V
CC
V
CC
= 2.2 V/3 V
= 2.2 V/3 V
= 2.2 V/3 V
6
6
6
(MCLK)
(MCLK)
(MCLK)
(LPM4)
NOTE 1: Parameter applicable only if DCOCLK is used for MCLK.
RAM
PARAMETER
MIN NOM
MAX
UNIT
V
CPU halted (see Note 1)
1.6
V
(RAMh)
NOTE 1: This parameter defines the minimum supply voltage V
when the data in the program memory RAM remains unchanged. No program
CC
execution should happen during this supply voltage condition.
18
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂꢃ ꢄ ꢅ ꢆꢇꢇ ꢈ ꢇ ꢉ ꢀ ꢁꢂꢃ ꢄꢅ ꢊꢇꢇꢈ ꢇꢋ
ꢀ ꢌꢍꢎ ꢏ ꢁꢌ ꢐ ꢑꢋꢒ ꢀ ꢌꢆꢓꢔ ꢆꢔ ꢑꢕ ꢓꢔ ꢒꢒ ꢎꢓ
SLAS241H − SEPTEMBER 1999 − REVISED SEPTEMBER 2004
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
Comparator_A (see Note 1)
PARAMETER
TEST CONDITIONS
MIN
TYP
25
MAX UNIT
V
V
= 2.2 V
= 3 V
40
µA
60
CC
I
I
CAON=1, CARSEL=0, CAREF=0
(DD)
45
CC
CAON=1, CARSEL=0,
CAREF=1/2/3, no load at
P2.3/CA0/TA1 and P2.4/CA1/TA2
V
= 2.2 V
= 3 V
30
45
50
µA
71
CC
CC
(Refladder/RefDiode)
V
Common-mode input
voltage
V
CAON =1
V
= 2.2 V/3 V
= 2.2 V/3 V
0
V −1
CC
V
(IC)
CC
CC
PCA0=1, CARSEL=1, CAREF=1,
No load at P2.3/CA0/TA1 and
P2.4/CA1/TA2
Voltage @ 0.25 V
CC
node
V
V
0.23
0.24
0.48
0.25
0.5
(Ref025)
V
CC
PCA0=1, CARSEL=1, CAREF=2,
No load at P2.3/CA0/TA1 and
P2.4/CA1/TA2
Voltage @ 0.5V
node
CC
V
V
CC
= 2.2 V/3 V
0.47
(Ref050)
(RefVT)
V
CC
PCA0=1, CARSEL=1, CAREF=3,
No load at P2.3/CA0/TA1 and
P2.4/CA1/TA2, T = 85°C
V
V
= 2.2 V
= 3 V
390
400
480
490
540
550
CC
V
(see Figure 6 and Figure 7)
mV
CC
A
V
V
Offset voltage
See Note 2
V
V
V
V
V
V
V
V
= 2.2 V/3 V
= 2.2 V/3 V
= 2.2 V
= 3 V
−30
0
30
1.4
mV
mV
(offset)
CC
CC
CC
CC
CC
CC
CC
CC
Input hysteresis
CAON=1
0.7
210
150
1.9
hys
160
90
300
240
3.4
T
= 25°C, Overdrive 10 mV,
A
ns
µs
ns
µs
Without filter: CAF=0
t
(response LH)
= 2.2 V
= 3 V
1.4
0.9
130
80
T
= 25°C, Overdrive 10 mV,
A
With filter: CAF=1
1.5
2.6
= 2.2 V
= 3 V
210
150
300
240
T
= 25°C, Overdrive 10 mV,
A
Without filter: CAF=0
t
(response HL)
V
CC
CC
= 2.2 V
= 3 V
1.4
0.9
1.9
1.5
3.4
2.6
T
= 25°C, Overdrive 10 mV,
A
With filter: CAF=1
V
NOTES: 1. The leakage current for the Comparator_A terminals is identical to I
specification.
lkg(Px.x)
2. The input offset voltage can be cancelled by using the CAEX bit to invert the Comparator_A inputs on successive measurements.
The two successive measurements are then summed together.
19
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇꢇ ꢈꢇ ꢉ ꢀꢁ ꢂ ꢃꢄ ꢅ ꢊ ꢇꢇ ꢈ ꢇꢋ
ꢀ ꢌ ꢍ ꢎꢏ ꢁꢌ ꢐꢑ ꢋ ꢒ ꢀꢌ ꢆ ꢓꢔꢆ ꢔꢑ ꢕꢓ ꢔꢒ ꢒꢎ ꢓ
SLAS241H − SEPTEMBER 1999 − REVISED SEPTEMBER 2004
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
650
600
550
500
450
400
650
600
550
500
450
400
V
= 2.2 V
V
CC
= 3 V
CC
Typical
Typical
−45
−25
−5
15
35
55
75
95
−45
−25
−5
15
35
55
75
95
T
A
− Free-Air Temperature − °C
T
A
− Free-Air Temperature − °C
Figure 7. V
vs Temperature, V
= 2.2 V
Figure 6. V
vs Temperature, V
= 3 V
(RefVT)
CAF
CC
(RefVT)
CC
0 V
V
CC
0
1
CAON
To Internal
Modules
Low Pass Filter
0
1
0
1
+
_
V+
V−
CAOUT
Set CAIFG
Flag
τ ≈ 2.0 µs
Figure 8. Block Diagram of Comparator_A Module
V
CAOUT
Overdrive
V−
400 mV
V+
t
(response)
Figure 9. Overdrive Definition
20
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂꢃ ꢄ ꢅ ꢆꢇꢇ ꢈ ꢇ ꢉ ꢀ ꢁꢂꢃ ꢄꢅ ꢊꢇꢇꢈ ꢇꢋ
ꢀ ꢌꢍꢎ ꢏ ꢁꢌ ꢐ ꢑꢋꢒ ꢀ ꢌꢆꢓꢔ ꢆꢔ ꢑꢕ ꢓꢔ ꢒꢒ ꢎꢓ
SLAS241H − SEPTEMBER 1999 − REVISED SEPTEMBER 2004
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
PUC/POR
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
250
1.8
UNIT
µs
V
t
Internal time delay to release POR
150
(POR_Delay)
T
= −40°C
= 25°C
= 85°C
1.4
1.1
0.8
A
V
threshold at which POR
CC
T
A
1.5
V
release delay time begins
(see Note 1)
V
POR
V
CC
= 2.2 V/3 V
T
A
1.2
V
V
threshold required to
CC
V
V
|dV/dt| ≥ 1V/ms
0.2
2
V
(min)
CC
generate a POR (see Note 2)
RST/NMI low time for PUC/POR
rise time dV/dt ≥ 1V/ms.
t
Reset is accepted internally
µs
(reset)
NOTES: 1. V
CC
2. When driving V
low in order to generate a POR condition, V should be driven to 200mV or lower with a dV/dt equal to or less
CC
CC
than −1V/ms. The corresponding rising V
CC
must also meet the dV/dt requirement equal to or greater than +1V/ms.
V
VCC
V
POR
No POR
POR
POR
V
(min)
t
Figure 10. Power-On Reset (POR) vs Supply Voltage
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
1.8
1.4
1.5
Max
1.2
0.8
Min
1.1
25°C
−40
−20
0
20
40
60
80
Temperature [°C]
Figure 11. V
vs Temperature
POR
21
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇꢇ ꢈꢇ ꢉ ꢀꢁ ꢂ ꢃꢄ ꢅ ꢊ ꢇꢇ ꢈ ꢇꢋ
ꢀ ꢌ ꢍ ꢎꢏ ꢁꢌ ꢐꢑ ꢋ ꢒ ꢀꢌ ꢆ ꢓꢔꢆ ꢔꢑ ꢕꢓ ꢔꢒ ꢒꢎ ꢓ
SLAS241H − SEPTEMBER 1999 − REVISED SEPTEMBER 2004
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
DCO
PARAMETER
TEST CONDITIONS
MIN
0.08
0.08
0.14
0.14
0.22
0.22
0.37
0.37
0.61
0.61
TYP
0.12
0.13
0.19
0.18
0.30
0.28
0.49
0.47
0.77
0.75
MAX
0.15
0.16
0.23
0.22
0.36
0.34
0.59
0.56
0.93
0.9
UNIT
V
V
V
V
V
V
V
V
V
V
= 2.2 V
= 3 V
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
f
f
f
R
R
R
= 0, DCO = 3, MOD = 0, DCOR = 0,
= 1, DCO = 3, MOD = 0, DCOR = 0,
= 2, DCO = 3, MOD = 0, DCOR = 0,
T
A
= 25°C
= 25°C
= 25°C
MHz
(DCO03)
(DCO13)
(DCO23)
sel
sel
sel
= 2.2 V
= 3 V
T
A
MHz
MHz
= 2.2 V
= 3 V
T
A
= 2.2 V
= 3 V
f
f
f
f
f
R
R
R
R
R
= 3, DCO = 3, MOD = 0, DCOR = 0,
= 4, DCO = 3, MOD = 0, DCOR = 0,
= 5, DCO = 3, MOD = 0, DCOR = 0,
= 6, DCO = 3, MOD = 0, DCOR = 0,
= 7, DCO = 3, MOD = 0, DCOR = 0,
T
A
= 25°C
= 25°C
= 25°C
= 25°C
= 25°C
MHz
MHz
MHz
MHz
MHz
(DCO33)
(DCO43)
(DCO53)
(DCO63)
(DCO73)
sel
sel
sel
sel
sel
= 2.2 V
= 3 V
T
A
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 2.2 V
= 3 V
1
1
1.2
1.3
1.9
2
1.5
1.5
T
A
= 2.2 V
= 3 V
1.6
1.69
2.4
2.7
4
2.2
T
A
2.29
3.4
= 2.2 V
= 3 V
2.9
3.2
4.5
4.9
T
A
3.65
4.9
= 2.2 V
= 3 V
f
R
R
= 7, DCO = 7, MOD = 0, DCOR = 0,
= 4, DCO = 7, MOD = 0, DCOR = 0,
T
A
= 25°C
= 25°C
MHz
MHz
ratio
(DCO77)
(DCO47)
sel
sel
4.4
5.4
f
f
f
DCO40
x1.7
DCO40
x2.1
DCO40
x2.5
f
T
A
V
CC
= 2.2 V/3 V
S
S
S
= f
/f
DCO DCO+1 DCO
V
CC
V
CC
V
CC
V
CC
= 2.2 V/3 V
= 2.2 V/3 V
= 2.2 V
1.35
1.07
1.65
1.12
2
1.16
(Rsel)
R
Rsel+1 Rsel
S
= f /f
(DCO)
−0.31
−0.33
−0.36
−0.38
−0.40
−0.43
Temperature drift, R
(see Note 1)
= 4, DCO = 3, MOD = 0
sel
D
D
%/°C
t
= 3 V
Drift with V
CC
(see Note 1)
variation, R = 4, DCO = 3, MOD = 0
sel
V
CC
= 2.2 V/3 V
0
5
10
%/V
V
NOTE 1: These parameters are not production tested.
Max
f
f
(DCOx7)
(DCOx0)
Min
Max
Min
0
1
2
3
4
5
6
7
2.2 V
3 V
V
CC
DCO Steps
Figure 12. DCO Characteristics
22
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂꢃ ꢄ ꢅ ꢆꢇꢇ ꢈ ꢇ ꢉ ꢀ ꢁꢂꢃ ꢄꢅ ꢊꢇꢇꢈ ꢇꢋ
ꢀ ꢌꢍꢎ ꢏ ꢁꢌ ꢐ ꢑꢋꢒ ꢀ ꢌꢆꢓꢔ ꢆꢔ ꢑꢕ ꢓꢔ ꢒꢒ ꢎꢓ
SLAS241H − SEPTEMBER 1999 − REVISED SEPTEMBER 2004
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
main DCO characteristics
D
Individual devices have a minimum and maximum operation frequency. The specified parameters for
to f are valid for all devices.
f
DCOx0)
DCOx7)
(
(
D
D
D
All ranges selected by Rsel(n) overlap with Rsel(n+1): Rsel0 overlaps Rsel1, ... Rsel6 overlaps Rsel7.
DCO control bits DCO0, DCO1, and DCO2 have a step size as defined by parameter S
.
DCO
Modulation control bits MOD0 to MOD4 select how often f
is used within the period of 32 DCOCLK
DCO+1)
(
cycles. The frequency f
is used for the remaining cycles. The frequency is an average equal to:
(DCO)
32 f(DCO) f(DCO)1)
faverage
+
MOD f(DCO))(32*MOD) f(DCO)1)
DCO when using R
(see Note 1)
OSC
PARAMETER
TEST CONDITIONS
= 4, DCO = 3, MOD = 0, DCOR = 1,
= 25°C
V
MIN
NOM
1.8 15%
1.95 15%
0.1
MAX
UNIT
MHz
MHz
%/°C
%/V
CC
2.2 V
R
T
sel
A
f
, DCO output frequency
DCO
3 V
D , Temperature drift
R
R
= 4, DCO = 3, MOD = 0, DCOR = 1
= 4, DCO = 3, MOD = 0, DCOR = 1
2.2 V/3 V
2.2 V/3 V
t
sel
sel
D , Drift with V
v
variation
10
CC
NOTES: 1. R
= 100kΩ. Metal film resistor, type 0257. 0.6 watt with 1% tolerance and T
=
50ppm/°C.
OSC
K
crystal oscillator, LFXT1
PARAMETER
TEST CONDITIONS
XTS=0; LF mode selected.
= 2.2 V / 3 V
MIN
TYP
MAX
UNIT
12
V
CC
XTS=1; XT1 mode selected.
= 2.2 V / 3 V (see Note 1)
C
C
Input capacitance
pF
XIN
2
12
2
V
CC
XTS=0; LF mode selected.
= 2.2 V / 3 V
V
CC
Output capacitance
Input levels at XIN
pF
V
XOUT
XTS=1; XT1 mode selected.
V
V
= 2.2 V / 3 V (see Note 1)
= 2.2 V/3 V (see Note 2)
CC
V
V
V
SS
0.2×V
IL
CC
CC
0.8×V
CC
V
CC
IH
NOTES: 1. Requires external capacitors at both terminals. Values are specified by crystal manufacturers.
2. Applies only when using an external logic-level clock source. Not applicable when using a crystal or resonator.
23
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇꢇ ꢈꢇ ꢉ ꢀꢁ ꢂ ꢃꢄ ꢅ ꢊ ꢇꢇ ꢈ ꢇꢋ
ꢀ ꢌ ꢍ ꢎꢏ ꢁꢌ ꢐꢑ ꢋ ꢒ ꢀꢌ ꢆ ꢓꢔꢆ ꢔꢑ ꢕꢓ ꢔꢒ ꢒꢎ ꢓ
SLAS241H − SEPTEMBER 1999 − REVISED SEPTEMBER 2004
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
Flash Memory
TEST
CONDITIONS
PARAMETER
V
CC
MIN NOM
MAX
UNIT
V
CC(PGM/
ERASE)
Program and Erase supply voltage
Flash Timing Generator frequency
2.7
3.6
V
f
I
I
t
t
257
476
5
kHz
mA
FTG
Supply current from V
Supply current from V
during program
during erase
2.7 V/ 3.6 V
2.7 V/ 3.6 V
2.7 V/ 3.6 V
2.7 V/ 3.6 V
3
PGM
CC
3
7
mA
ERASE
CPT
CC
Cumulative program time
see Note 1
see Note 2
4
ms
Cumulative mass erase time
Program/Erase endurance
Data retention duration
200
ms
CMErase
4
5
10
10
100
cycles
years
t
T = 25°C
J
Retention
t
t
t
t
t
t
Word or byte program time
35
30
Word
st
Block program time for 1 byte or word
Block, 0
Block program time for each additional byte or word
Block program end-sequence wait time
Mass erase time
21
Block, 1-63
Block, End
Mass Erase
Seg Erase
see Note 3
t
FTG
6
5297
4819
Segment erase time
NOTES: 1. The cumulative program time must not be exceeded when writing to a 64-byte flash block. This parameter applies to all programming
methods: individual word/byte write and block write modes.
2. The mass erase duration generated by the flash timing generator is at least 11.1ms ( = 5297x1/f
,max = 5297x1/476kHz). To
FTG
achieve the required cumulative mass erase time the Flash Controller’s mass erase operation can be repeated until this time is met.
(A worst case minimum of 19 cycles are required).
3. These values are hardwired into the Flash Controller’s state machine (t
FTG
= 1/f
FTG
).
JTAG Interface
TEST
CONDITIONS
PARAMETER
V
CC
MIN NOM
MAX
UNIT
2.2 V
3 V
0
0
5
10
90
MHz
MHz
kΩ
f
TCK input frequency
Internal pull-down resistance on TEST
see Note 1
see Note 2
TCK
R
2.2 V/ 3 V
25
60
Internal
NOTES: 1. f
may be restricted to meet the timing requirements of the module selected.
TCK
2. TEST pull-down resistor implemented in all versions.
JTAG Fuse (see Note 1)
TEST
CONDITIONS
PARAMETER
V
CC
MIN NOM
MAX
UNIT
V
V
Supply voltage during fuse-blow condition
Voltage level on TEST for fuse-blow - ’C11x1
Voltage level on TEST for fuse-blow - ’F11x1A
Supply current into TEST during fuse blow
Time to blow fuse
T
A
= 25°C
2.5
3.5
6
V
V
CC(FB)
3.9
7
FB
V
I
t
100
1
mA
ms
FB
FB
NOTES: 1. Once the fuse is blown, no further access to the MSP430 JTAG/Test and emulation features is possible. The JTAG block is switched
to bypass mode.
24
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂꢃ ꢄ ꢅ ꢆꢇꢇ ꢈ ꢇ ꢉ ꢀ ꢁꢂꢃ ꢄꢅ ꢊꢇꢇꢈ ꢇꢋ
ꢀ ꢌꢍꢎ ꢏ ꢁꢌ ꢐ ꢑꢋꢒ ꢀ ꢌꢆꢓꢔ ꢆꢔ ꢑꢕ ꢓꢔ ꢒꢒ ꢎꢓ
SLAS241H − SEPTEMBER 1999 − REVISED SEPTEMBER 2004
APPLICATION INFORMATION
input/output schematic
Port P1, P1.0 to P1.3, input/output with Schmitt-trigger
V
CC
P1SEL.x
0
(See Note 1)
P1DIR.x
1
0
Direction Control
From Module
(See Note 2)
Pad Logic
P1.0 − P1.3
P1OUT.x
1
Module X OUT
(See Note 2)
(See Note 1)
P1IN.x
GND
EN
D
Module X IN
P1IRQ.x
P1IE.x
Interrupt
Edge
Select
EN
Q
P1IFG.x
Set
Interrupt
Flag
P1IES.x
P1SEL.x
NOTE: x = Bit/identifier, 0 to 3 for port P1
Direction
PnSel.x
PnDIR.x
control from
module
PnOUT.x
Module X OUT
PnIN.x
Module X IN
PnIE.x
PnIFG.x
PnIES.x
†
P1Sel.0
P1Sel.1
P1Sel.2
P1Sel.3
P1DIR.0
P1DIR.1
P1DIR.2
P1DIR.3
P1DIR.0
P1DIR.1
P1DIR.2
P1DIR.3
P1OUT.0
P1OUT.1
P1OUT.2
P1OUT.3
V
P1IN.0
P1IN.1
P1IN.2
P1IN.3
TACLK
P1IE.0
P1IE.1
P1IE.2
P1IE.3
P1IFG.0
P1IFG.1
P1IFG.2
P1IFG.3
P1IES.0
P1IES.1
P1IES.2
P1IES.3
SS
†
†
†
†
†
†
Out0 signal
Out1 signal
Out2 signal
CCI0A
CCI1A
CCI2A
†
Signal from or to Timer_A
NOTES: 1. Optional selection of pullup or pulldown resistors with ROM (masked) versions
2. Fuses for optional pullup and pulldown resistors can only be programmed at the factory (ROM versions only).
25
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇꢇ ꢈꢇ ꢉ ꢀꢁ ꢂ ꢃꢄ ꢅ ꢊ ꢇꢇ ꢈ ꢇꢋ
ꢀ ꢌ ꢍ ꢎꢏ ꢁꢌ ꢐꢑ ꢋ ꢒ ꢀꢌ ꢆ ꢓꢔꢆ ꢔꢑ ꢕꢓ ꢔꢒ ꢒꢎ ꢓ
SLAS241H − SEPTEMBER 1999 − REVISED SEPTEMBER 2004
APPLICATION INFORMATION
Port P1, P1.4 to P1.7, input/output with Schmitt-trigger and in-system access features
V
CC
See Note 1
P1SEL.x
P1DIR.x
0
1
Direction Control
From Module
See Note 2
0
1
Pad Logic
P1OUT.x
P1.4−P1.7
Module X OUT
See Note 2
See Note 1
GND
TST
Bus Keeper
P1IN.x
EN
D
Module X IN
TEST
TST
Fuse
P1IRQ.x
P1IE.x
P1IFG.x
Interrupt
Edge
Select
60 kΩ
Typical
EN
Set
Q
GND
Fuse
Blow
Interrupt
Flag
Control By JTAG
P1IES.x
Control
P1SEL.x
P1.x
TDO
Controlled By JTAG
P1.7/TDI/TDO
P1.x
Controlled by JTAG
TDI
TST
TST
P1.6/TDI/TCLK
P1.x
NOTE: The test pin should be protected from potential EMI
and ESD voltage spikes. This may require a smaller
external pulldown resistor in some applications.
TMS
TCK
P1.5/TMS
P1.x
x = Bit identifier, 4 to 7 for port P1
TST
During programming activity and during blowing
of the fuse, the pin TDO/TDI is used to apply the test
input for JTAG circuitry.
P1.4/TCK
Direction
PnSel.x
PnDIR.x
control from
module
PnOUT.x
Module X OUT
SMCLK
PnIN.x
Module X IN
PnIE.x
PnIFG.x
PnIES.x
P1Sel.4
P1Sel.5
P1Sel.6
P1Sel.7
P1DIR.4
P1DIR.5
P1DIR.6
P1DIR.7
P1DIR.4
P1DIR.5
P1DIR.6
P1DIR.7
P1OUT.4
P1OUT.5
P1OUT.6
P1OUT.7
P1IN.4
P1IN.5
P1IN.6
P1IN.7
unused
unused
unused
unused
P1IE.4
P1IE.5
P1IE.6
P1IE.7
P1IFG.4
P1IFG.5
P1IFG.6
P1IFG.7
P1IES.4
P1IES.5
P1IES.6
P1IES.7
†
†
†
Out0 signal
Out1 signal
Out2 signal
†
Signal from or to Timer_A
NOTES: 1. Optional selection of pullup or pulldown resistors with ROM (masked) versions
2. Fuses for optional pullup and pulldown resistors can only be programmed at the factory (ROM versions only).
26
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂꢃ ꢄ ꢅ ꢆꢇꢇ ꢈ ꢇ ꢉ ꢀ ꢁꢂꢃ ꢄꢅ ꢊꢇꢇꢈ ꢇꢋ
ꢀ ꢌꢍꢎ ꢏ ꢁꢌ ꢐ ꢑꢋꢒ ꢀ ꢌꢆꢓꢔ ꢆꢔ ꢑꢕ ꢓꢔ ꢒꢒ ꢎꢓ
SLAS241H − SEPTEMBER 1999 − REVISED SEPTEMBER 2004
APPLICATION INFORMATION
Port P2, P2.0 to P2.2, input/output with Schmitt-trigger
P2SEL.x
P2DIR.x
V
CC
0
1
0: Input
See Note 1
Direction Control
From Module
1: Output
See Note 2
Pad Logic
0
1
P2.0 − P2.2
P2OUT.x
Module X OUT
See Note 2
See Note 1
GND
Bus Keeper
P2IN.x
EN
D
Module X IN
CAPD.X
P2IRQ.x
P2IE.x
Interrupt
Edge
Select
EN
Q
P2IFG.x
Set
Interrupt
Flag
NOTE: x = Bit Identifier, 0 to 2 for port P2
Direction
P2IES.x
P2SEL.x
PnSel.x
PnDIR.x
control from
module
PnOUT.x
Module X OUT
ACLK
PnIN.x
Module X IN
unused
PnIE.x
PnIFG.x
PnIES.x
P2Sel.0
P2Sel.1
P2Sel.2
P2DIR.0
P2DIR.1
P2DIR.2
P2DIR.0
P2DIR.1
P2DIR.2
P2OUT.0
P2OUT.1
P2OUT.2
P2IN.0
P2IN.1
P2IN.2
P2IE.0
P2IE.1
P2IE.2
P2IFG.0
P2IFG.1
P2IFG.2
P1IES.0
P1IES.1
P1IES.2
†
V
INCLK
CCI0B
SS
CAOUT
†
†
Signal from or to Timer_A
NOTES: 1. Optional selection of pullup or pulldown resistors with ROM (masked) versions
2. Fuses for optional pullup and pulldown resistors can only be programmed at the factory (ROM versions only).
27
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇꢇ ꢈꢇ ꢉ ꢀꢁ ꢂ ꢃꢄ ꢅ ꢊ ꢇꢇ ꢈ ꢇꢋ
ꢀ ꢌ ꢍ ꢎꢏ ꢁꢌ ꢐꢑ ꢋ ꢒ ꢀꢌ ꢆ ꢓꢔꢆ ꢔꢑ ꢕꢓ ꢔꢒ ꢒꢎ ꢓ
SLAS241H − SEPTEMBER 1999 − REVISED SEPTEMBER 2004
APPLICATION INFORMATION
Port P2, P2.3 to P2.4, input/output with Schmitt-trigger
P2SEL.3
V
CC
0
P2DIR.3
0: Input
1: Output
Pad Logic
See Note 1
See Note 2
1
Direction Control
From Module
0
1
P2.3
P2OUT.3
Module X
OUT
See Note 2
See Note 1
GND
P2IN.3
Bus Keeper
EN
D
Module X IN
P2IRQ.3
P2IE.3
Interrupt
Edge
Select
EN
Set
Q
CAPD.3
P2IFG.3
Comparator_A
CAREF P2CA CAEX
Interrupt
Flag
P2IES.3 P2SEL.3
CAF
+
_
CCI1B
0 V
P2SEL.4
P2IES.4
Interrupt
Flag
CAREF
Reference Block
CAPD.4
Interrupt
Edge
Select
Set
Q
P2IFG.4
EN
P2IRQ.4
Module X IN
P2IE.4
D
EN
Bus Keeper
V
P2IN.4
CC
See Note 1
See Note 2
Module X OUT
P2OUT.4
1
0
P2.4
Pad Logic
See Note 2
See Note 1
Direction Control
From Module
1: Output
0: Input
1
0
P2DIR.4
P2SEL.4
GND
PnSel.x PnDIR.x
Direction
PnOUT.x
Module X OUT
PnIN.x
Module X IN
PnIE.x
PnIFG.x
PnIES.x
control from module
†
†
P2Sel.3 P2DIR.3
P2Sel.4 P2DIR.4
Signal from Timer_A
P2DIR.3
P2OUT.3
P2OUT.4
Out1 signal
P2IN.3
P2IN.4
unused
unused
P2IE.3 P2IFG.3
P2IE.4 P2IFG.4
P1IES.3
P1IES.4
P2DIR.4
Out2 signal
†
NOTES: 1. Optional selection of pullup or pulldown resistors with ROM (masked) versions
2. Fuses for optional pullup and pulldown resistors can only be programmed at the factory (ROM versions only).
28
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂꢃ ꢄ ꢅ ꢆꢇꢇ ꢈ ꢇ ꢉ ꢀ ꢁꢂꢃ ꢄꢅ ꢊꢇꢇꢈ ꢇꢋ
ꢀ ꢌꢍꢎ ꢏ ꢁꢌ ꢐ ꢑꢋꢒ ꢀ ꢌꢆꢓꢔ ꢆꢔ ꢑꢕ ꢓꢔ ꢒꢒ ꢎꢓ
SLAS241H − SEPTEMBER 1999 − REVISED SEPTEMBER 2004
APPLICATION INFORMATION
Port P2, P2.5, input/output with Schmitt-trigger and R
function for the Basic Clock module
OSC
V
CC
P2SEL.5
0: Input
Pad Logic
0
1: Output
P2DIR.5
See Note 1
1
Direction Control
From Module
See Note 2
0
1
P2.5
P2OUT.5
Module X OUT
See Note 2
See Note 1
GND
Bus Keeper
P2IN.5
EN
D
Module X IN
P2IRQ.5
Internal to
Basic Clock
Module
P2IE.5
Interrupt
Edge
Select
1
0
V
CC
EN
Q
P2IFG.5
Set
Interrupt
Flag
P2IES.5
DC
Generator
DCOR
P2SEL.5
CAPD.5
NOTE: DCOR: Control bit from Basic Clock Module if it is set, P2.5 Is disconnected from P2.5 pad
Direction
PnSel.x
P2Sel.5
PnDIR.x
P2DIR.5
control from
module
PnOUT.x
P2OUT.5
Module X OUT
PnIN.x
P2IN.5
Module X IN
unused
PnIE.x
P2IE.5
PnIFG.x
P2IFG.5
PnIES.x
P2IES.5
P2DIR.5
V
SS
NOTES: 1. Optional selection of pullup or pulldown resistors with ROM (masked) versions
2. Fuses for optional pullup and pulldown resistors can only be programmed at the factory (ROM versions only).
29
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢇꢇ ꢈꢇ ꢉ ꢀꢁ ꢂ ꢃꢄ ꢅ ꢊ ꢇꢇ ꢈ ꢇꢋ
ꢀ ꢌ ꢍ ꢎꢏ ꢁꢌ ꢐꢑ ꢋ ꢒ ꢀꢌ ꢆ ꢓꢔꢆ ꢔꢑ ꢕꢓ ꢔꢒ ꢒꢎ ꢓ
SLAS241H − SEPTEMBER 1999 − REVISED SEPTEMBER 2004
APPLICATION INFORMATION
Port P2, unbonded bits P2.6 and P2.7
P2SEL.x
P2DIR.x
0: Input
1: Output
0
1
Direction Control
From Module
0
1
P2OUT.x
Module X OUT
P2IN.x
Node Is Reset With PUC
Bus Keeper
EN
Module X IN
D
P2IRQ.x
P2IE.x
PUC
Interrupt
Edge
Select
EN
Set
Q
P2IFG.x
Interrupt
Flag
P2IES.x
P2SEL.x
NOTE: x = Bit/identifier, 6 to 7 for port P2 without external pins
Direction
P2Sel.x
P2DIR.x
control from
module
P2OUT.x
Module X OUT
P2IN.x
Module X IN
P2IE.x
P2IFG.x
P2IES.x
P2Sel.6
P2Sel.7
P2DIR.6
P2DIR.7
P2DIR.6
P2DIR.7
P2OUT.6
P2OUT.7
V
V
P2IN.6
P2IN.7
unused
unused
P2IE.6
P2IE.7
P2IFG.6
P2IFG.7
P2IES.6
P2IES.7
SS
SS
NOTE 1: Unbonded bits 6 and 7 of port P2 can be used as software interrupt flags. The interrupt flags can only be influenced by software. They
work then as a software interrupt.
30
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂꢃ ꢄ ꢅ ꢆꢇꢇ ꢈ ꢇ ꢉ ꢀ ꢁꢂꢃ ꢄꢅ ꢊꢇꢇꢈ ꢇꢋ
ꢀ ꢌꢍꢎ ꢏ ꢁꢌ ꢐ ꢑꢋꢒ ꢀ ꢌꢆꢓꢔ ꢆꢔ ꢑꢕ ꢓꢔ ꢒꢒ ꢎꢓ
SLAS241H − SEPTEMBER 1999 − REVISED SEPTEMBER 2004
JTAG fuse check mode
MSP430 devices that have the fuse on the TEST terminal have a fuse check mode that tests the continuity of
the fuse the first time the JTAG port is accessed after a power-on reset (POR). When activated, a fuse check
current, I , of 1 mA at 3 V, 2.5 mA at 5 V can flow from the TEST pin to ground if the fuse is not burned. Care
TF
must be taken to avoid accidentally activating the fuse check mode and increasing overall system power
consumption.
When the TEST pin is taken back low after a test or programming session, the fuse check mode and sense
currents are terminated.
Activation of the fuse check mode occurs with the first negative edge on the TMS pin after power up or if TMS
is being held low during power up. The second positive edge on the TMS pin deactivates the fuse check mode.
After deactivation, the fuse check mode remains inactive until another POR occurs. After each POR the fuse
check mode has the potential to be activated.
The fuse check current will only flow when the fuse check mode is active and the TMS pin is in a low state (see
Figure 13). Therefore, the additional current flow can be prevented by holding the TMS pin high (default
condition).
Time TMS Goes Low After POR
TMS
I
TF
I
TEST
Figure 13. Fuse Check Mode Current, MSP430F11x1A and MSP430C11x1
NOTE:
The CODE and RAM data protection is ensured if the JTAG fuse is blown and the 256-bit bootloader
access key is used. Also, see the bootstrap loader section for more information.
31
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
18-Jul-2006
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
MSP430C1101
ACTIVE
ACTIVE
TBD
Call TI
Call TI
MSP430F1101AIDGV
TVSOP
TVSOP
SOIC
DGV
DGV
DW
20
20
20
20
20
20
24
24
20
20
20
20
20
20
24
24
20
20
20
20
20
20
24
24
90 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
MSP430F1101AIDGVR
MSP430F1101AIDW
MSP430F1101AIDWR
MSP430F1101AIPW
MSP430F1101AIPWR
MSP430F1101AIRGER
MSP430F1101AIRGET
MSP430F1111AIDGV
MSP430F1111AIDGVR
MSP430F1111AIDW
MSP430F1111AIDWR
MSP430F1111AIPW
MSP430F1111AIPWR
MSP430F1111AIRGER
MSP430F1111AIRGET
MSP430F1121AIDGV
MSP430F1121AIDGVR
MSP430F1121AIDW
MSP430F1121AIDWR
MSP430F1121AIPW
MSP430F1121AIPWR
MSP430F1121AIRGER
MSP430F1121AIRGET
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOIC
DW
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TSSOP
TSSOP
QFN
PW
70 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
PW
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
RGE
RGE
DGV
DGV
DW
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
QFN
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
TVSOP
TVSOP
SOIC
90 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOIC
DW
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TSSOP
TSSOP
QFN
PW
70 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
PW
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
RGE
RGE
DGV
DGV
DW
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
QFN
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
TVSOP
TVSOP
SOIC
90 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOIC
DW
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TSSOP
TSSOP
QFN
PW
70 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
PW
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
RGE
RGE
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
QFN
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
18-Jul-2006
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
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