MSP430C1351_技术文档

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SLAS341B − SEPTEMBER 2001 − REVISED SEPTEMBER 2004

D

Low Supply-Voltage Range, 1.8 V to 3.6 V

D

On-Chip Comparator

Ultralow-Power Consumption:

− Active Mode: 160 µA at 1 MHz, 2.2 V

− Standby Mode: 0.9 µA

− Off Mode (RAM Retention) : 0.1 µA

Five Power-Saving Modes

Serial Communication Interface (USART),

Software Selects Asynchronous UART or

Synchronous SPI

D

Programmable Code Protection With

Security Fuse

D

Wake-Up From Standby Mode in less

than 6 µs

16-Bit RISC Architecture,

125-ns Instruction Cycle Time

Family Members Include:

− MSP430C1331: 8KB ROM, 256B RAM

− MSP430C1351: 16KB ROM, 512B RAM

D

Available in 64-Pin Quad Flat Pack (QFP)

Emulation: Use MSP430F13xIPM

16-Bit Timer_B With Three

Capture/Compare-With-Shadow Registers

For Complete Module Descriptions, See the

MSP430x1xx Family User’s Guide,

Literature Number SLAU049

16-Bit Timer_A With Three

Capture/Compare Registers

description

The Texas Instruments MSP430 family of ultralow-power microcontrollers consist of several devices featuring

different sets of peripherals targeted for various applications. The architecture, combined with five low power

modes is optimized to achieve extended battery life in portable measurement applications. The device features

a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that attribute to maximum code efficiency.

The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less than 6 µs.

The MSP430C13x1 is a microcontroller configuration with two built-in 16-bit timers, one universal serial

synchronous/asynchronous communication interfaces (USART), and 48 I/O pins.

Typical applications include sensor systems that capture analog signals, convert them to digital values, and

process and transmit the data to a host system. The timers make the configurations ideal for industrial control

applications, hand-held meters, etc.

AVAILABLE OPTIONS

PACKAGED DEVICES

T

A

PLASTIC 64-PIN QFP

(PM)

MSP430C1331IPM

MSP430C1351IPM

−40°C to 85°C

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

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Copyright  2001 − 2004, Texas Instruments Incorporated

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1

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SLAS341B − SEPTEMBER 2001 − REVISED SEPTEMBER 2004

pin designation, MSP430C1331, MSP430C1351

PM PACKAGE

(TOP VIEW)

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

DV

P5.4/MCLK

P5.3

1

2

3

4

5

6

7

8

9

48

47

46

45

44

43

42

41

40

CC

P6.3

P6.4

P6.5

P6.6

P6.7

NC

P5.2

P5.1

P5.0

P4.7/TBCLK

P4.6

XIN

P4.5

XOUT

NC

P4.4

10

39 P4.3

NC 11

P1.0/TACLK 12

P1.1/TA0 13

38 P4.2/TB2

37 P4.1/TB1

36

35

34

33

P4.0/TB0

P3.7

14

15

16

P1.2/TA1

P1.3/TA2

P3.6

P1.4/SMCLK

P3.5/URXD0

1718 19 20 21 22 23 24 25 26 27 28 29 30 31 32

NC − No internal connection

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SLAS341B − SEPTEMBER 2001 − REVISED SEPTEMBER 2004

functional block diagrams

MSP430C13x1

P1

XIN XOUT/TCLK

DV

RST/NMI

P2

P3

P4

P5

P6

DV

AV

SS

CC

SS

CC

8

R

OSC

Oscillator

ACLK

16KB ROM

8KB ROM

512B RAM

256B RAM

I/O Port 1/2 I/O Port 3/4 I/O Port 5/6

16 I/Os,

with

16 I/Os

XT2IN

System

Clock

SMCLK

Interrupt

Capability

XT2OUT

MCLK

MAB,

4 Bit

Test

MAB,M1A6BB,it16-Bit

JTAG

CPU

MCB

Incl. 16 Reg.

Bus

Conv

MDB, 16-Bit

MDB, 16 Bit

MDB, 8 Bit

4

TMS

TCK

Watchdog

Timer

Timer_B3

Timer_A3

3 CC Reg

POR

Comparator

A

USART0

3 CC Reg

Shadow

Reg

UART Mode

SPI Mode

TDI

15/16-Bit

TDO/TDI

Terminal Functions

TERMINAL

NAME

CC

SS

I/O

DESCRIPTION

NO.

64

62

1

AV

Supply voltage, positive terminal. AV

CC

and DV

CC

are internally connected together.

Supply voltage, negative terminal. AV

and DV

SS

CC

SS

CC

DV

Supply voltage, positive terminal. AV

and DV

CC

SS

63

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

Supply voltage, negative terminal. AV

SS

and DV

SS

P1.0/TACLK

P1.1/TA0

I/O General-purpose digital I/O pin/Timer_A, clock signal TACLK input

I/O General-purpose digital I/O pin/Timer_A, capture: CCI0A input, compare: Out0 output

I/O General-purpose digital I/O pin/Timer_A, capture: CCI1A input, compare: Out1 output

I/O General-purpose digital I/O pin/Timer_A, capture: CCI2A input, compare: Out2 output

I/O General-purpose digital I/O pin/SMCLK signal output

P1.2/TA1

P1.3/TA2

P1.4/SMCLK

P1.5/TA0

I/O General-purpose digital I/O pin/Timer_A, compare: Out0 output

I/O General-purpose digital I/O pin/Timer_A, compare: Out1 output

I/O General-purpose digital I/O pin/Timer_A, compare: Out2 output

I/O General-purpose digital I/O pin/ACLK output

P1.6/TA1

P1.7/TA2

P2.0/ACLK

P2.1/TAINCLK

P2.2/CAOUT/TA0

P2.3/CA0/TA1

P2.4/CA1/TA2

I/O General-purpose digital I/O pin/Timer_A, clock signal at INCLK

I/O General-purpose digital I/O pin/Timer_A, capture: CCI0B input/Comparator_A output

I/O General-purpose digital I/O pin/Timer_A, compare: Out1 output/Comparator_A input

I/O General-purpose digital I/O pin/Timer_A, compare: Out2 output/Comparator_A input

I/O General-purpose digital I/O pin/input for external resistor defining the DCO nominal frequency

I/O General-purpose digital I/O pin

P2.5/R

P2.6

OSC

P2.7/TA0

I/O General-purpose digital I/O pin/Timer_A, compare: Out0 output

I/O General-purpose digital I/O pin/slave transmit enable – USART0/SPI mode

P3.0/STE0

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SLAS341B − SEPTEMBER 2001 − REVISED SEPTEMBER 2004

Terminal Functions (Continued)

TERMINAL

NAME

I/O

DESCRIPTION

NO.

29

P3.1/SIMO0

P3.2/SOMI0

P3.3/UCLK0

I/O

General-purpose digital I/O pin/slave in/master out of USART0/SPI mode

General-purpose digital I/O pin/slave out/master in of USART0/SPI mode

30

31

General-purpose digital I/O pin/external clock input − USART0/UART or SPI mode, clock output –

USART0/SPI mode

P3.4/UTXD0

P3.5/URXD0

P3.6

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

I/O

General-purpose digital I/O pin/transmit data out – USART0/UART mode

General-purpose digital I/O pin/receive data in – USART0/UART mode

General-purpose digital I/O pin

P3.7

General-purpose digital I/O pin

P4.0/TB0

P4.1/TB1

P4.2/TB2

P4.3

General-purpose digital I/O pin/Timer_B, capture: CCI0A/B input, compare: Out0 output

General-purpose digital I/O pin/Timer_B, capture: CCI1A/B input, compare: Out0 output

General-purpose digital I/O pin/Timer_B, capture: CCI2A/B input, compare: Out0 output

General-purpose digital I/O pin

P4.4

General-purpose digital I/O pin

P4.5

General-purpose digital I/O pin

P4.6

General-purpose digital I/O pin

P4.7/TBCLK

P5.0

General-purpose digital I/O pin/Timer_B, clock signal TBCLK input

General-purpose digital I/O pin

P5.1

General-purpose digital I/O pin

P5.2

General-purpose digital I/O pin

P5.3

General-purpose digital I/O pin

P5.4/MCLK

P5.5/SMCLK

P5.6/ACLK

P5.7/TBOUTH

General-purpose digital I/O pin/main system clock MCLK output

General-purpose digital I/O pin/submain system clock SMCLK output

General-purpose digital I/O pin/auxiliary clock ACLK output

General-purpose digital I/O pin/switch all PWM digital output ports to high impedance − Timer_B7 TB0

to TB2

P6.0

59

60

61

2

I/O

I

General-purpose digital I/O pin

P6.1

General-purpose digital I/O pin

P6.2

General-purpose digital I/O pin

P6.3

General-purpose digital I/O pin

P6.4

3

General-purpose digital I/O pin

P6.5

4

General-purpose digital I/O pin

P6.6

5

General-purpose digital I/O pin

P6.7

6

General-purpose digital I/O pin

RST/NMI

TCK

58

57

55

Reset input, nonmaskable interrupt input port

Test clock. TCK is the clock input port for device programming test.

I

TDI/TCLK

I

Test data input or test clock input. TDI is used as a data input port. The device protection fuse is

connected to TDI.

TDO/TDI

TMS

54

I/O

I

Test data output port. TDO/TDI data output

56

Test mode select. TMS is used as an input port for device test.

No internal connection

NC

7, 10, 11

XIN

8

9

I

Input port for crystal oscillator XT1. Standard or watch crystals can be connected.

Output terminal of crystal oscillator XT1

XOUT

XT2IN

XT2OUT

O

I

53

52

Input port for crystal oscillator XT2. Only standard crystals can be connected.

Output terminal of crystal oscillator XT2

O

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SLAS341B − SEPTEMBER 2001 − REVISED SEPTEMBER 2004

short-form description

CPU

Program Counter

Stack Pointer

PC/R0

The MSP430 CPU has a 16-bit RISC architecture

that is highly transparent to the application. All

operations, other than program-flow instructions,

are performed as register operations in

conjunction with seven addressing modes for

source operand and four addressing modes for

destination operand.

SP/R1

Status Register

SR/CG1/R2

Constant Generator

CG2/R3

R4

General-Purpose Register

The CPU is integrated with 16 registers that

provide reduced instruction execution time. The

register-to-register operation execution time is

one cycle of the CPU clock.

R5

R6

R7

Four of the registers, R0 to R3, are dedicated as

program counter, stack pointer, status register,

and constant generator respectively. The

remaining registers are general-purpose

registers.

R8

R9

Peripherals are connected to the CPU using data,

address, and control buses, and can be handled

with all instructions.

R10

R11

instruction set

R12

R13

The instruction set consists of 51 instructions with

three formats and seven address modes. Each

instruction can operate on word and byte data.

Table 1 shows examples of the three types of

instruction formats; the address modes are listed

in Table 2.

R14

R15

Table 1. Instruction Word Formats

Dual operands, source-destination

Single operands, destination only

Relative jump, un/conditional

e.g. ADD R4,R5

R4 + R5 −−−> R5

e.g. CALL

e.g. JNE

R8

PC −−>(TOS), R8−−> PC

Jump-on-equal bit = 0

Table 2. Address Mode Descriptions

ADDRESS MODE

Register

S

D

SYNTAX

MOV Rs,Rd

EXAMPLE

MOV R10,R11

MOV 2(R5),6(R6)

OPERATION

D D

R10 −−> R11

Indexed

D D

MOV X(Rn),Y(Rm)

MOV EDE,TONI

M(2+R5)−−> M(6+R6)

M(EDE) −−> M(TONI)

M(MEM) −−> M(TCDAT)

M(R10) −−> M(Tab+R6)

Symbolic (PC relative) D D

Absolute

Indirect

D D MOV &MEM,&TCDAT

D

MOV @Rn,Y(Rm)

MOV @Rn+,Rm

MOV #X,TONI

MOV @R10,Tab(R6)

MOV @R10+,R11

MOV #45,TONI

Indirect

autoincrement

M(R10) −−> R11

R10 + 2−−> R10

Immediate

#45 −−> M(TONI)

NOTE: S = source

D = destination

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SLAS341B − SEPTEMBER 2001 − REVISED SEPTEMBER 2004

operating modes

The MSP430 has one active mode and five software selectable low-power modes of operation. An interrupt

event can wake up the device from any of the five low-power modes, service the request and restore back to

the low-power mode on return from the interrupt program.

The following six operating modes can be configured by software:

D

Active mode AM;

All clocks are active

Low-power mode 0 (LPM0);

−

CPU is disabled

ACLK and SMCLK remain active. MCLK is disabled

D

Low-power mode 1 (LPM1);

−

CPU is disabled

ACLK and SMCLK remain active. MCLK is disabled

DCO’s dc-generator is disabled if DCO not used in active mode

Low-power mode 2 (LPM2);

−

CPU is disabled

MCLK and SMCLK are disabled

DCO’s dc-generator remains enabled

ACLK remains active

D

Low-power mode 3 (LPM3);

−

CPU is disabled

MCLK and SMCLK are disabled

DCO’s dc-generator is disabled

ACLK remains active

Low-power mode 4 (LPM4);

−

CPU is disabled

ACLK is disabled

MCLK and SMCLK are disabled

DCO’s dc-generator is disabled

Crystal oscillator is stopped

6

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SLAS341B − SEPTEMBER 2001 − REVISED SEPTEMBER 2004

interrupt vector addresses

The interrupt vectors and the power-up starting address are located in the address range 0FFFFh − 0FFE0h.

The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.

INTERRUPT SOURCE

INTERRUPT FLAG

SYSTEM INTERRUPT

WORD ADDRESS

PRIORITY

Power-up

External reset

Watchdog

WDTIFG

(see Note 1)

Reset

0FFFEh

15, highest

NMI

Oscillator fault

NMIIFG (see Notes 1 & 4)

OFIFG (see Notes 1 & 4)

(Non)maskable

0FFFCh

0FFFAh

14

13

Timer_B3

TBCCR0 CCIFG

(see Note 2)

Maskable

TBCCR1 and TBCCR2

CCIFGs, TBIFG

Timer_B3

Maskable

0FFF8h

12

(see Notes 1 & 2)

Comparator_A

Watchdog timer

USART0 receive

USART0 transmit

CAIFG

WDTIFG

URXIFG0

UTXIFG0

Maskable

0FFF6h

0FFF4h

0FFF2h

0FFF0h

0FFEEh

0FFECh

11

10

9

8

7

Timer_A3

TACCR0 CCIFG

(see Note 2)

Maskable

6

TACCR1 and TACCR2

CCIFGs, TAIFG

(see Notes 1 & 2)

Timer_A3

Maskable

0FFEAh

0FFE8h

5

4

P1IFG.0 to P1IFG.7

(see Notes 1 & 2)

I/O port P1 (eight flags)

0FFE6h

0FFE4h

3

2

P2IFG.0 to P2IFG.7

(see Notes 1 & 2)

I/O port P2 (eight flags)

Maskable

0FFE2h

0FFE0h

1

0, lowest

NOTES: 1. Multiple source flags

2. Interrupt flags are located in the module.

3. Nonmaskable: neither the individual nor the general interrupt-enable bit will disable an interrupt event.

4. (Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable can not disable

it.

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SLAS341B − SEPTEMBER 2001 − REVISED SEPTEMBER 2004

special function registers

Most interrupt and module-enable bits are collected in the lowest address space. Special-function register bits

not allocated to a functional purpose are not physically present in the device. This arrangement provides simple

software access.

interrupt enable 1 and 2

7

6

5

4

3

2

1

0

Address

0h

UTXIE0

URXIE0

NMIIE

OFIE

WDTIE

rw-0

WDTIE:

Watchdog Timer interrupt enable. Inactive if watchdog mode is selected. Active if Watchdog

Timer is configured in interval timer mode.

OFIE:

Oscillator-fault-interrupt enable

NMIIE:

URXIE0:

UTXIE0:

Nonmaskable-interrupt enable

USART0: UART and SPI receive-interrupt enable

USART0: UART and SPI transmit-interrupt enable

7

6

5

4

3

2

1

0

Address

01h

interrupt flag register 1 and 2

7

6

URXIFG0

rw-0

4

3

1

0

Address

02h

UTXIFG0

NMIIFG

OFIFG

WDTIFG

rw-1

rw-0

rw-1

rw-(0)

WDTIFG: Set on Watchdog Timer overflow (in watchdog mode) or security key violation. Reset on V

power-up or a reset condition at RST/NMI pin in reset mode.

CC

OFIFG:

Flag set on oscillator fault

Set via RST/NMI pin

NMIIFG:

URXIFG0: USART0: UART and SPI receive flag

UTXIFG0: USART0: UART and SPI transmit flag

7

6

5

4

3

2

1

0

Address

03h

module enable registers 1 and 2

7

6

5

4

Address

04h

UTXE0

URXE0

USPIE0

rw-0

URXE0:

USART0: UART receive enable

USART0: UART transmit enable

UTXE0:

USPIE0:

USART0: SPI (synchronous peripheral interface) transmit and receive enable

8

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SLAS341B − SEPTEMBER 2001 − REVISED SEPTEMBER 2004

7

6

5

4

3

2

1

0

Address

05h

Legend: rw:

Bit Can Be Read and Written

rw-0,1:

rw-(0,1):

Bit Can Be Read and Written. It Is Reset or Set by PUC.

Bit Can Be Read and Written. It Is Reset or Set by POR.

SFR Bit Not Present in Device

memory organization

MSP430C1331

MSP430C1351

Memory

Interrupt vector

Code memory

Size

ROM

8KB

16KB

0FFFFh − 0FFE0h

0FFFFh − 0C000h

0FFFFh − 0FFE0h

0FFFFh − 0E000h

RAM

Size

256 Byte

512 Byte

02FFh − 0200h

03FFh − 0200h

Peripherals

16-bit

8-bit

8-bit SFR

01FFh − 0100h

0FFh − 010h

0Fh − 00h

01FFh − 0100h

0FFh − 010h

0Fh − 00h

peripherals

Peripherals are connected to the CPU through data, address, and control busses and can be handled using

all instructions. For complete module descriptions, see the MSP430x1xx Family User’s Guide, literature number

SLAU049.

digital I/O

There are six 8-bit I/O ports implemented—ports P1 through P6:

D

All individual I/O bits are independently programmable.

Any combination of input, output, and interrupt conditions is possible.

Edge-selectable interrupt input capability for all the eight bits of ports P1 and P2.

Read/write access to port-control registers is supported by all instructions.

oscillator and system clock

The clock system is supported by the basic clock module that includes support for a 32768-Hz watch crystal

oscillator, an internal digitally-controlled oscillator (DCO) and a high frequency crystal oscillator. The basic clock

module is designed to meet the requirements of both low system cost and low-power consumption. The internal

DCO provides a fast turn-on clock source and stabilizes in less than 6 µs. The basic clock module provides the

following clock signals:

D

Auxiliary clock (ACLK), sourced from a 32768-Hz watch crystal or a high frequency crystal.

Main clock (MCLK), the system clock used by the CPU.

Sub-Main clock (SMCLK), the sub-system clock used by the peripheral modules.

watchdog timer

The primary function of the watchdog timer (WDT) module is to perform a controlled system restart after a

software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog

function is not needed in an application, the module can be configured as an interval timer and can generate

interrupts at selected time intervals.

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SLAS341B − SEPTEMBER 2001 − REVISED SEPTEMBER 2004

USART0

The MSP430C13x1 devices have one hardware universal synchronous/asynchronous receive transmit

(USART0) peripheral module that is used for serial data communication. The USART supports synchronous

SPI (3 or 4 pin) and asynchronous UART communication protocols, using double-buffered transmit and receive

channels.

comparator_A

The primary function of the comparator_A module is to support precision slope analog−to−digital conversions,

battery−voltage supervision, and monitoring of external analog signals.

timer_A3

Timer_A3 is a 16-bit timer/counter with three capture/compare registers. Timer_A3 can support multiple

capture/compares, PWM outputs, and interval timing. Timer_A3 also has extensive interrupt capabilities.

Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare

registers.

Timer_A3 Signal Connections

Input Pin Number Device Input Signal Module Input Name

Module Block

Module Output Signal

Output Pin Number

12 - P1.0

TACLK

ACLK

TACLK

ACLK

Timer

NA

SMCLK

TAINCLK

TA0

SMCLK

INCLK

CCI0A

CCI0B

GND

21 - P2.1

13 - P1.1

22 - P2.2

13 - P1.1

17 - P1.5

27 - P2.7

TA0

CCR0

CCR1

CCR2

TA0

TA1

TA2

DV

SS

V

CC

14 - P1.2

15 - P1.3

TA1

CAOUT (internal)

CCI1A

CCI1B

GND

14 - P1.2

18 - P1.6

23 - P2.3

DV

SS

V

CC

TA2

ACLK (internal)

CCI2A

CCI2B

GND

15 - P1.3

19 - P1.7

24 - P2.4

DV

SS

V

CC

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SLAS341B − SEPTEMBER 2001 − REVISED SEPTEMBER 2004

timer_B3

Timer_B3 is a 16-bit timer/counter with three capture/compare registers. Timer_B3 can support multiple

capture/compares, PWM outputs, and interval timing. Timer_B3 also has extensive interrupt capabilities.

Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare

registers.

Timer_B3 Signal Connections

Input Pin Number Device Input Signal Module Input Name

Module Block

Module Output Signal

Output Pin Number

43 - P4.7

TBCLK

ACLK

SMCLK

TBCLK

TB0

TBCLK

ACLK

Timer

NA

SMCLK

INCLK

CCI0A

CCI0B

GND

43 - P4.7

36 - P4.0

37 - P4.1

38 - P4.2

TB0

CCR0

CCR1

CCR2

TB0

TB1

TB2

DV

SS

V

CC

37 - P4.1

TB1

CCI1A

CCI1B

GND

DV

SS

DV

V

CC

38 - P4.2

TB2

CCI2A

CCI2B

GND

DV

SS

DV

V

CC

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SLAS341B − SEPTEMBER 2001 − REVISED SEPTEMBER 2004

peripheral file map

PERIPHERALS WITH WORD ACCESS

Watchdog

Timer_B3

Watchdog Timer control

Timer_B interrupt vector

Timer_B control

WDTCTL

TBIV

0120h

011Eh

0180h

0182h

0184h

0186h

0188h

018Ah

018Ch

018Eh

0190h

0192h

0194h

0196h

0198h

019Ah

019Ch

019Eh

012Eh

0160h

0162h

0164h

0166h

0168h

016Ah

016Ch

016Eh

0170h

0172h

0174h

0176h

0178h

017Ah

017Ch

017Eh

TBCTL

Capture/compare control 0

Capture/compare control 1

Capture/compare control 2

Reserved

TBCCTL0

TBCCTL1

TBCCTL2

Reserved

Timer_B register

Capture/compare register 0

Capture/compare register 1

Capture/compare register 2

Reserved

TBR

TBCCR0

TBCCR1

TBCCR2

Reserved

Timer_A3

Timer_A interrupt vector

Timer_A control

TAIV

TACTL

Capture/compare control 0

Capture/compare control 1

Capture/compare control 2

Reserved

TACCTL0

TACCTL1

TACCTL2

Reserved

Timer_A register

Capture/compare register 0

Capture/compare register 1

Capture/compare register 2

Reserved

TAR

TACCR0

TACCR1

TACCR2

Reserved

PERIPHERALS WITH BYTE ACCESS

USART0

Transmit buffer

Receive buffer

Baud rate

U0TXBUF

U0RXBUF

U0BR1

077h

076h

075h

074h

073h

072h

071h

070h

Baud rate

U0BR0

Modulation control

Receive control

Transmit control

USART control

U0MCTL

U0RCTL

U0TCTL

U0CTL

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SLAS341B − SEPTEMBER 2001 − REVISED SEPTEMBER 2004

peripheral file map (continued)

PERIPHERALS WITH BYTE ACCESS (CONTINUED)

Comparator_A

Basic Clock

Port P6

Comparator_A port disable

Comparator_A control2

Comparator_A control1

Basic clock system control2

Basic clock system control1

DCO clock frequency control

Port P6 selection

CAPD

CACTL2

CACTL1

BCSCTL2

BCSCTL1

DCOCTL

P6SEL

P6DIR

P6OUT

P6IN

05Bh

05Ah

059h

058h

057h

056h

037h

036h

035h

034h

033h

032h

031h

030h

01Fh

01Eh

01Dh

01Ch

01Bh

01Ah

019h

018h

02Eh

02Dh

02Ch

02Bh

02Ah

029h

028h

026h

025h

024h

023h

022h

021h

020h

005h

004h

003h

002h

001h

000h

Port P6 direction

Port P6 output

Port P6 input

Port P5

Port P4

Port P3

Port P2

Port P5 selection

P5SEL

P5DIR

P5OUT

P5IN

Port P5 direction

Port P5 output

Port P5 input

Port P4 selection

P4SEL

P4DIR

P4OUT

P4IN

Port P4 direction

Port P4 output

Port P4 input

Port P3 selection

P3SEL

P3DIR

P3OUT

P3IN

Port P3 direction

Port P3 output

Port P3 input

Port P2 selection

P2SEL

P2IE

Port P2 interrupt enable

Port P2 interrupt-edge select

Port P2 interrupt flag

Port P2 direction

P2IES

P2IFG

P2DIR

P2OUT

P2IN

Port P2 output

Port P2 input

Port P1

Port P1 selection

P1SEL

P1IE

Port P1 interrupt enable

Port P1 interrupt-edge select

Port P1 interrupt flag

Port P1 direction

P1IES

P1IFG

P1DIR

P1OUT

P1IN

Port P1 output

Port P1 input

Special Functions

SFR module enable 2

SFR module enable 1

SFR interrupt flag 2

SFR interrupt flag 1

SFR interrupt enable 2

SFR interrupt enable 1

ME2

ME1

IFG2

IFG1

IE2

IE1

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SLAS341B − SEPTEMBER 2001 − REVISED SEPTEMBER 2004

†

absolute maximum ratings over operating free-air temperature (unless otherwise noted)

Voltage applied at V

to V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to + 4.1 V

CC

SS

Voltage applied to any pin (see Note) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to V +0.3 V

CC

Diode current at any device terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 mA

Storage temperature (unprogrammed device) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 150°C

Storage temperature (programmed device) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 85°C

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE: All voltages referenced to V . The JTAG fuse-blow voltage, V , is allowed to exceed the absolute maximum rating. The voltage is applied

SS

FB

to the TDI/TCLK pin when blowing the JTAG fuse.

recommended operating conditions

PARAMETER

MIN

1.8

NOM

MAX UNITS

Supply voltage during program execution, V

(AV

CC

= DV

CC

= V

)

3.6

0.0

85

V

CC

)

CC

Supply voltage, V

SS

(AV

SS

= DV

SS

= V

SS

0.0

Operating free-air temperature range, T

−40

°C

A

LF selected, XTS=0

Watch crystal

32768

Hz

kHz

LFXT1 crystal frequency, f

(see Notes 1 and 2)

(LFXT1)

XT1 selected, XTS=1 Ceramic resonator

XT1 selected, XTS=1 Crystal

Ceramic resonator

450

1000

450

8000

4.15

8

XT2 crystal frequency, f

(XT2)

kHz

Crystal

1000

DC

V

= 1.8 V

= 3.6 V

CC

Processor frequency (signal MCLK), f

(System)

MHz

DC

CC

NOTES: 1. In LF mode, the LFXT1 oscillator requires a watch crystal and the LFXT1 oscillator requires a 5.1-MΩ resistor from XOUT to V

SS

when V

< 2.5 V. In XT1 mode, the LFXT1. and XT2 oscillators accept a ceramic resonator or a 4-MHz crystal frequency at

≥ 2.8 V.

CC

V

≥ 2.2 V. In XT1 mode, the LFXT1 and XT2 oscillators accept a ceramic resonator or an 8-MHz crystal frequency at V

CC

2. In LF mode, the LFXT1 oscillator requires a watch crystal. In XT1 mode, FXT1 accepts a ceramic resonator or a crystal.

f

MHz

(System)

8.0 MHz

4.15 MHz

1.8 V

2.7 V 3 V

3.6 V

Supply Voltage − V

Figure 1. Frequency vs Supply Voltage

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SLAS341B − SEPTEMBER 2001 − REVISED SEPTEMBER 2004

electrical characteristics over recommended operating free-air temperature (unless otherwise

noted)

supply current into AV

+ DV

excluding external current

CC

PARAMETER

TEST CONDITIONS

MIN NOM

MAX

UNIT

Active mode, (see Note 1)

V

= 2.2 V

= 3 V

160

200

CC

f

= f

= 1 MHz,

= 32,768 Hz, XTS=0, SELM=(0,1)

T

= −40°C to 85°C

µA

(MCLK) (SMCLK)

A

V

240

2.5

300

7

f

(ACLK)

I

(AM)

Active mode, (see Note 1)

V

= 2.2 V

= 3 V

CC

f

= f = 4 096 Hz,

(MCLK) (SMCLK)

T

A

µA

f

= 4,096 Hz

(ACLK)

2.5

7

CC

XTS=0, SELM=(0,1), XTS=0, SELM=3

V

= 2.2 V

= 3 V

32

55

45

70

CC

I

Low-power mode, (LPM0) (see Note 1)

T

= −40°C to 85°C

µA

(LPM0)

A

CC

Low-power mode, (LPM2),

f(MCLK) = f (SMCLK) = 0 MHz,

f(ACLK) = 32.768 Hz, SCG0 = 0

V

= 2.2 V

= 3 V

11

17

14

22

CC

T

A

(LPM2)

V

T

= −40°C

= 25°C

= 85°C

= −40°C

= 25°C

= 85°C

= −40°C

= 25°C

= 85°C

= −40°C

= 25°C

= 85°C

0.8

0.9

1.6

1.8

2.3

0.1

0.8

0.1

0.8

1.5

2.8

2.2

3.9

0.5

2.5

0.5

2.5

A

T

A

V

CC

V

CC

V

CC

V

CC

= 2.2 V

= 3 V

µA

Low-power mode, (LPM3)

T

A

f

= f

= 0 MHz,

= 32,768 Hz, SCG0 = 1

(MCLK) (SMCLK)

I

(LPM3)

f

T

A

(ACLK)

(see Note 2)

T

A

T

A

T

A

T

A

= 2.2 V

= 3 V

Low-power mode, (LPM4)

T

A

f

= 0 MHz, f = 0 MHz,

= 0 Hz, SCG0 = 1

I

(MCLK)

(ACLK)

(SMCLK)

(LPM4)

T

A

T

A

T

A

NOTES: 1. Timer_B is clocked by f(DCOCLK) = 1 MHz. All inputs are tied to 0 V or to V . Outputs do not source or sink any current.

CC

2. Timer_B is clocked by f(ACLK) = 32,768 Hz. All inputs are tied to 0 V or to V . Outputs do not source or sink any current. The current

CC

consumption in LPM2 and LPM3 are measured with ACLK selected.

Current consumption of active mode versus system frequency

I(AM) = I(AM) [1 MHz] × f(System) [MHz]

Current consumption of active mode versus supply voltage

I

= I

+ 175 µA/V × (V

– 3 V)

(AM)

(AM) [3 V]

CC

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SLAS341B − SEPTEMBER 2001 − REVISED SEPTEMBER 2004

electrical characteristics over recommended operating free-air temperature (unless otherwise

noted)

SCHMITT-trigger inputs − Ports P1, P2, P3, P4, P5, and P6

PARAMETER

TEST CONDITIONS

MIN

1.1

TYP

MAX

1.5

1.9

0.9

1.3

1.1

1

UNIT

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

= 2.2 V

= 3 V

V

IT+

V

IT−

V

hys

Positive-going input threshold voltage

V

1.5

= 2.2 V

= 3 V

0.4

Negative-going input threshold voltage

V

0.90

0.3

= 2.2 V

= 3 V

Input voltage hysteresis (V

IT+

− V )

IT−

0.4

standard inputs − RST/NMI; JTAG: TCK, TMS, TDI/TCLK, TDO/TDI

PARAMETER

Low-level input voltage

High-level input voltage

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V

SS

V

+0.6

SS

IL

V

CC

= 2.2 V / 3 V

0.8×V

V

CC

V

IH

CC

input frequency − Ports P1, P2, P3, P4, P5, and P6

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

8

UNIT

f

V

= 2.2 V

= 3 V

(IN)

CC

t = t

(h) (L)

MHz

10

CC

capture timing _ Timer_A3: TA0, TA1, TA2; Timer_B3: TB0, TB1, TB2

PARAMETER

TEST CONDITIONS

MIN

1.5

62

MAX

UNIT

V

CC

V

CC

V

CC

= 2.2 V/3 V

= 2.2 V

= 3 V

Cycle

Ports P2, P4:

External trigger signal for the interrupt flag (see Notes 1 and 2)

t

(int)

ns

50

NOTES: 1. The external signal sets the interrupt flag every time t

(int)

is met. It may be set even with trigger signals shorter than t .

(int)

The conditions to set the flag must be met independently of this timing constraint. t

is defined in MCLK cycles.

(int)

2. The external signal needs additional timing because of the maximum input-frequency constraint.

external interrupt timing

PARAMETER

TEST CONDITIONS

MIN

1.5

62

TYP

MAX

UNIT

V

CC

V

CC

V

CC

= 2.2 V/3 V

= 2.2 V

= 3 V

Cycle

Ports P1, P2:

t

(int)

External trigger signal for the interrupt flag (see Notes 1 and 2)

ns

50

NOTES: 1. The external signal sets the interrupt flag every time t

(int)

is met. It may be set even with trigger signals shorter than t .

(int)

The conditions to set the flag must be met independently of this timing constraint. t

is defined in MCLK cycles.

(int)

2. The external signal needs additional timing because of the maximum input-frequency constraint.

leakage current (see Note 1)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

50

UNIT

I

Port P1

Port P2

V

(see Note 2)

(P1.x)

lkg(P1.x)

Leakage

current

V

= 2.2 V/3 V

nA

CC

V

(see Note 2)

50

lkg(P2.x)

(P2.3) (P2.4)

or V

NOTES: 1. The leakage current is measured with V

SS

applied to the corresponding pin(s), unless otherwise noted.

CC

2. The port pin must be selected as input and there must be no optional pullup or pulldown resistor.

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SLAS341B − SEPTEMBER 2001 − REVISED SEPTEMBER 2004

electrical characteristics over recommended operating free-air temperature (unless otherwise

noted) (continued)

outputs − Ports P1, P2, P3, P4, P5, and P6

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

I

= −1.5 mA,

= −6 mA,

= −1.5 mA,

= −6 mA,

= 1.5 mA,

= 6 mA,

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

= 2.2 V,

= 3 V,

See Note 1

See Note 2

See Note 1

See Note 2

See Note 1

See Note 2

See Note 1

See Note 2

V

−0.25

V

OH(max)

OL(max)

CC

V

−0.6

CC

−0.25

V

High-level output voltage

V

OH

OL

V

CC

= 3 V,

V

−0.6

CC

= 2.2 V,

= 3 V,

V

+0.25

SS

V

+0.6

SS

V

Low-level output voltage

V

= 1.5 mA,

= 6 mA,

V

SS

+0.25

= 3 V,

V

+0.6

SS

NOTES: 1. The maximum total current, I

specified voltage drop.

and I

for all outputs combined, should not exceed 12 mA to satisfy the maximum

OH(max)

OL(max),

2. The maximum total current, I

specified voltage drop.

and I

for all outputs combined, should not exceed 48 mA to satisfy the maximum

OH(max)

output frequency

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

TA0..2, TB0..2

f

, f

Internal clock source, SMCLK signal

applied (see Note 1)

C

= 20 pF

DC

f

TAx TBx

L

System

MHz

f

ACLK,

MCLK,

SMCLK

P5.6/ACLK, P5.4/MCLK,

P5.5/SMCLK

System

f

= f

40%

30%

60%

70%

ACLK LFXT1 XT1

P2.0/ACLK

= f

C

= 20 pF,

= 2.2 V / 3 V

ACLK LFXT1 LF

L

V

CC

= f

50%

ACLK LFXT1/n

= f

SMCLK LFXT1 XT1

40%

35%

60%

65%

t

Duty cycle of output frequency

Xdc

= f

SMCLK LFXT1 LF

P1.4/SMCLK,

50%−

15 ns

50%−

15 ns

C

= 20 pF,

= 2.2 V / 3 V

f

= f

50%

L

SMCLK LFXT1/n

V

CC

50%−

15 ns

50%−

15 ns

f = f

SMCLK DCOCLK

NOTE 1: The limits of the system clock MCLK has to be met; the system (MCLK) frequency should not exceed the limits. MCLK and SMCLK

frequencies can be different.

17

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SLAS341B − SEPTEMBER 2001 − REVISED SEPTEMBER 2004

electrical characteristics over recommended operating free-air temperature (unless otherwise

noted) (continued)

outputs − Ports P1, P2, P3, P4, P5, and P6 (continued)

TYPICAL LOW-LEVEL OUTPUT CURRENT

vs

LOW-LEVEL OUTPUT VOLTAGE

50

45

40

35

30

25

20

15

10

5

30

25

20

15

10

V

CC

= 2.2 V

V

CC

= 3 V

−40°C

25°C

85°C

−40°C

25°C

85°C

5

0

0.5

1

1.5

2

2.5

0

0.5

1

1.5

2

2.5

3

3.5

V

OL

− Low-Level Output Voltage − V

V

OL

− Low-Level Output Voltage − V

Figure 2

Figure 3

TYPICAL HIGH-LEVEL OUTPUT CURRENT

vs

HIGH-LEVEL OUTPUT VOLTAGE

−35

−60

−50

−40

−30

−20

V

= 2.2 V

−40°C

V

CC

= 3 V

CC

−30

−25

−20

−15

−40°C

85°C

25°C

−10

−5

0

−10

0

0.5

1

1.5

2

2.5

3

3.5

0

0.5

1

1.5

2

2.5

V

OH

− High-Level Output Voltage − V

V

OH

− High-Level Output Voltage − V

Figure 4

Figure 5

18

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SLAS341B − SEPTEMBER 2001 − REVISED SEPTEMBER 2004

electrical characteristics over recommended operating free-air temperature (unless otherwise

noted) (continued)

wake-up LPM3

PARAMETER

TEST CONDITIONS

f = 1 MHz

MIN

TYP

MAX

UNIT

6

f = 2 MHz

f = 3 MHz

t

Delay time

V

CC

= 2.2 V/3 V

µs

(LPM3)

RAM

PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

VRAMh

CPU HALTED (see Note 1)

1.6

V

NOTE 1: This parameter defines the minimum supply voltage when the data in program memory RAM remain unchanged. No program execution

should take place during this supply voltage condition.

Comparator_A (see Note 1)

PARAMETER

TEST CONDITIONS

MIN

TYP

30

MAX UNIT

V

= 2.2 V

= 3 V

47

µA

74

CC

I

CAON=1, CARSEL=0, CAREF=0

(DD)

55

CC

CAON=1, CARSEL=0,

CAREF=1/2/3, no load at

P2.3/CA0/TA1 and P2.4/CA1/TA2

V

= 2.2 V

= 3 V

40

60

57

µA

87

CC

(Refladder/Refdiode)

V

Common-mode input

voltage

V

CAON =1

V

= 2.2 V/3 V

0

V −1

CC

V

(IC)

CC

PCA0=1, CARSEL=1, CAREF=1,

no load at P2.3/CA0/TA1 and

P2.4/CA1/TA2

Voltage at 0.25 V

node

CC

V

0.23

0.24

0.48

0.25

0.5

(Ref025)

V

CC

PCA0=1, CARSEL=1, CAREF=2,

no load at P2.3/CA0/TA1 and

P2.4/CA1/TA2

Voltage at 0.5V

node

CC

V

CC

= 2.2 V/3 V

0.47

(Ref050)

(RefVT)

V

CC

PCA0=1, CARSEL=1, CAREF=3,

no load at P2.3/CA0/TA1 and

P2.4/CA1/TA2 T = 85°C

V

= 2.2 V

= 3 V

390

400

480

490

540

550

CC

V

(see Figure 6 and Figure 7)

mV

CC

A

V

Offset voltage

See Note 2

V

= 2.2 V/3 V

= 2.2 V

= 3 V

−30

0

30

1.4

mV

(offset)

CC

Input hysteresis

CAON=1

0.7

210

150

1.9

hys

130

80

300

240

3.4

T

= 25°C, Overdrive 10 mV,

A

ns

µs

ns

µs

Without filter: CAF=0

t

(response LH)

= 2.2 V

= 3 V

1.4

0.9

130

80

T

= 25°C, Overdrive 10 mV,

A

With filter: CAF=1

1.5

2.6

= 2.2 V

= 3 V

210

150

300

240

T

= 25°C, Overdrive 10 mV,

A

Without filter: CAF=0

t

(response HL)

V

CC

= 2.2 V

= 3 V

1.4

0.9

1.9

1.5

3.4

2.6

T

= 25°C, Overdrive 10 mV,

A

With filter: CAF=1

V

NOTES: 1. The leakage current for the Comparator_A terminals is identical to I

specification.

lkg(Px.x)

2. The input offset voltage can be cancelled by using the CAEX bit to invert the Comparator_A inputs on successive measurements.

The two successive measurements are then summed together.

19

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SLAS341B − SEPTEMBER 2001 − REVISED SEPTEMBER 2004

electrical characteristics over recommended operating free-air temperature (unless otherwise

noted) (continued)

650

600

550

500

450

400

650

600

550

500

450

400

V

= 2.2 V

V

CC

= 3 V

CC

Typical

−45

−25

−5

15

35

55

75

95

−45

−25

−5

15

35

55

75

95

T

A

− Free-Air Temperature − °C

T

A

− Free-Air Temperature − °C

Figure 7. V

vs Temperature, V

= 2.2 V

Figure 6. V

vs Temperature, V

= 3 V

(RefVT)

CAF

CC

(RefVT)

CC

0 V

V

CC

0

1

CAON

To Internal

Modules

Low Pass Filter

0

1

0

1

+

_

V+

V−

CAOUT

Set CAIFG

Flag

τ ≈ 2.0 µs

Figure 8. Block Diagram of Comparator_A Module

V

CAOUT

Overdrive

V−

400 mV

V+

t

(response)

Figure 9. Overdrive Definition

20

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SLAS341B − SEPTEMBER 2001 − REVISED SEPTEMBER 2004

electrical characteristics over recommended operating free-air temperature (unless otherwise

noted) (continued)

PUC/POR

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

250

1.8

UNIT

µs

V

t

Internal time delay to release POR

150

(POR_Delay)

T

= −40°C

= 25°C

= 85°C

1.4

1.1

0.8

A

V

threshold at which POR

CC

T

A

1.5

V

release delay time begins

(see Note 1)

V

POR

V

CC

= 2.2 V/3 V

T

A

1.2

V

threshold required to

CC

V

|dV/dt| ≥ 1V/ms

0.2

2

V

(min)

CC

generate a POR (see Note 2)

RST/NMI low time for PUC/POR

rise time dV/dt ≥ 1V/ms.

t

Reset is accepted internally

µs

(reset)

NOTES: 1. V

CC

2. When driving V

low in order to generate a POR condition, V should be driven to 200mV or lower with a dV/dt equal to or less

CC

than −1V/ms. The corresponding rising V

CC

must also meet the dV/dt requirement equal to or greater than +1V/ms.

V

cc

V

POR

No POR

POR

V

(min)

t

Figure 10. Power-On Reset (POR) vs Supply Voltage

2

1.8

1.6

1.4

1.2

1

1.8

1.4

1.5

1.2

0.8

1.2

0.8

0.6

0.4

0.2

0

25°C

−40

−20

20

40

60

80

0

T

A

− Temperature − °C

Figure 11. V

vs Temperature

POR

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SLAS341B − SEPTEMBER 2001 − REVISED SEPTEMBER 2004

electrical characteristics over recommended operating free-air temperature (unless otherwise

noted) (continued)

DCO (see Note 1)

PARAMETER

TEST CONDITIONS

= 0, DCO = 3, MOD = 0, DCOR = 0, T = 25°C

MIN

0.08

NOM

0.12

MAX

0.15

UNIT

R

V

= 2.2 V

= 3 V

sel

A

CC

f

MHz

(DCO03)

(DCO13)

(DCO23)

(DCO33)

(DCO43)

(DCO53)

(DCO63)

0.08

0.14

0.22

0.37

0.61

1

0.13

0.19

0.18

0.30

0.28

0.49

0.47

0.77

0.75

1.2

0.16

0.23

0.22

0.36

0.34

0.59

0.56

0.93

0.90

1.5

= 1, DCO = 3, MOD = 0, DCOR = 0, T = 25°C

= 2.2 V

= 3 V

A

f

MHz

= 2, DCO = 3, MOD = 0, DCOR = 0, T = 25°C

= 2.2 V

= 3 V

A

= 3, DCO = 3, MOD = 0, DCOR = 0, T = 25°C

= 2.2 V

= 3 V

A

= 4, DCO = 3, MOD = 0, DCOR = 0, T = 25°C

= 2.2 V

= 3 V

A

= 5, DCO = 3, MOD = 0, DCOR = 0, T = 25°C

= 2.2 V

= 3 V

A

1

1.3

1.5

= 6, DCO = 3, MOD = 0, DCOR = 0, T = 25°C

= 2.2 V

= 3 V

1.6

1.9

2.2

A

1.69

2.4

2.0

2.29

3.4

= 7, DCO = 3, MOD = 0, DCOR = 0, T = 25°C

= 2.2 V

= 3 V

2.9

A

f

MHz

(DCO73)

2.7

3.2

3.65

f

DCO40 DCO40 DCO40

× 1.7

R

= 4, DCO = 7, MOD = 0, DCOR = 0, T = 25°C

V

CC

= 2.2 V/3 V

(DCO47)

sel

A

× 2.1

× 2.5

V

= 2.2 V

= 3 V

4

4.5

4.9

CC

f

= 7, DCO = 7, MOD = 0, DCOR = 0, T = 25°C

MHz

(DCO77)

A

4.4

4.9

5.4

CC

S

= f

/ f

DCO DCO+1 DCO

V

= 2.2 V/3 V

= 2.2 V

= 3 V

1.35

1.07

−0.31

−0.33

1.65

1.12

−0.36

−0.38

2

(Rsel)

R

Rsel+1 Rsel

CC

S

= f / f

V

1.16

−0.40

−0.43

(DCO)

V

Temperature drift, R

(see Note 2)

= 4, DCO = 3, MOD = 0

sel

D

%/°C

%/V

t

Drift with V

CC

(see Note 2)

variation, R = 4, DCO = 3, MOD = 0

sel

V

CC

= 2.2 V/3 V

0

5

10

V

NOTES: 1. The DCO frequency may not exceed the maximum system frequency defined by parameter processor frequency, f

2. This parameter is not production tested.

.

(System)

1

DCOCLK

f

Max

DCO_7

f

Min

Max

f

DCO_0

Min

0

1

2

3

4

5

6

7

DCO

2.2

3

V

CC

− V

Figure 12. DCO Characteristics

22

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SLAS341B − SEPTEMBER 2001 − REVISED SEPTEMBER 2004

electrical characteristics over recommended operating free-air temperature (unless otherwise

noted) (continued)

main DCO characteristics

D

Individual devices have a minimum and maximum operation frequency. The specified parameters for

to f are valid for all devices.

f

DCOx0)

DCOx7)

(

D

All ranges selected by Rsel(n) overlap with Rsel(n+1): Rsel0 overlaps Rsel1, ... Rsel6 overlaps Rsel7.

DCO control bits DCO0, DCO1, and DCO2 have a step size as defined by parameter S

.

DCO

Modulation control bits MOD0 to MOD4 select how often f

is used within the period of 32 DCOCLK

DCO+1)

(

cycles. The frequency f

is used for the remaining cycles. The frequency is an average equal to:

(DCO)

32 f_(DCO) f_(DCO)1)

f_average

+

MOD f_(DCO))(32*MOD) f_(DCO)1)

DCO when using R

(see Note 1)

OSC

PARAMETER

TEST CONDITIONS

= 4, DCO = 3, MOD = 0, DCOR = 1,

= 25°C

V

MIN

NOM

2.0 15%

2.1 15%

0.1

MAX

UNIT

MHz

%/°C

%/V

CC

2.2 V

R

T

sel

A

f

, DCO output frequency

DCO

3 V

D , Temperature drift

R

= 4, DCO = 3, MOD = 0, DCOR = 1

2.2 V/3 V

t

sel

D , Drift with V

v

variation

10

CC

NOTES: 1. R

= 100kΩ. Metal film resistor, type 0257. 0.6 watt with 1% tolerance and T

=

50ppm/°C.

OSC

K

crystal oscillator, LFXT1 oscillator (see Note 1)

PARAMETER

TEST CONDITIONS

MIN

NOM

12

2

MAX

UNIT

XTS=0; LF oscillator selected V

= 2.2 V/3 V

CC

XTS=1; XT1 oscillator selected V

C

Integrated input capacitance

pF

XIN

CC

= 2.2 V/3 V

XTS=0; LF oscillator selected V

12

2

CC

Integrated output capacitance

Input levels at XIN

pF

XOUT

XTS=1; XT1 oscillator selected V

CC

= 2.2 V/3 V

V

0.2 × V

CC

V

IL

SS

0.8 × V

V

CC

= 2.2 V/3 V (see Note 2)

V

CC

IH

CC

NOTES: 1. The oscillator needs capacitors at both terminals, with values specified by the crystal manufacturer.

2. Applies only when using an external logic-level clock source. Not applicable when using a crystal or resonator.

crystal oscillator, XT2 oscillator (see Note 1)

PARAMETER

TEST CONDITIONS

= 2.2 V/3 V

MIN

NOM

MAX

UNIT

pF

V

C

Integrated input capacitance

Integrated output capacitance

V

2

XIN

XOUT

IL

CC

= 2.2 V/3 V

CC

V

0.2 × V

CC

SS

0.8 × V

Input levels at XT2IN

V

CC

= 2.2 V/3 V (see Note 2)

V

CC

V

IH

CC

NOTES: 1. The oscillator needs capacitors at both terminals, with values specified by the crystal manufacturer.

2. Applies only when using an external logic-level clock source. Not applicable when using a crystal or resonator.

USART0 (see Note 1)

PARAMETER

TEST CONDITIONS

MIN

200

150

NOM MAX

UNIT

V

= 2.2 V

= 3 V

430

280

800

500

CC

t

(τ)

USART0: deglitch time

ns

CC

NOTE 1: The signal applied to the USART0 receive signal/terminal (URXD0) should meet the timing requirements of t to ensure that the URXS

(τ)

flip-flop is set. The URXS flip-flop is set with negative pulses meeting the minimum-timing condition of t . The operating conditions to

(τ)

set the flag must be met independently from this timing constraint. The deglitch circuitry is active only on negative transitions on the

URXD0 line.

23

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SLAS341B − SEPTEMBER 2001 − REVISED SEPTEMBER 2004

electrical characteristics over recommended operating free-air temperature (unless otherwise

noted) (continued)

JTAG Interface

TEST

CONDITIONS

PARAMETER

V

CC

MIN NOM

MAX

UNIT

2.2 V

3 V

0

5

10

90

MHz

kΩ

f

TCK input frequency

see Note 1

TCK

R

Internal pull-up resistance on TMS, TCK, TDI/TCLK see Note 2

may be restricted to meet the timing requirements of the module selected.

2.2 V/ 3 V

25

60

Internal

NOTES: 1. f

TCK

2. TMS, TDI/TCLK, and TCK pull-up resistors are implemented in all versions.

JTAG Fuse (see Note 1)

TEST

CONDITIONS

PARAMETER

V

CC

MIN NOM

MAX

UNIT

V

Voltage level on TDI/TCLK for fuse-blow

Supply current into TDI/TCLK during fuse blow

Time to blow fuse

3.6V

5

5.5

100

20

V

FB

I

t

mA

ms

FB

NOTES: 1. Once the fuse is blown, no further access to the MSP430 JTAG/Test and emulation features is possible. The JTAG block is switched

to bypass mode.

24

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SLAS341B − SEPTEMBER 2001 − REVISED SEPTEMBER 2004

APPLICATION INFORMATION

input/output schematic

port P1, P1.0 to P1.7, input/output with Schmitt-trigger

P1SEL.x

0

P1DIR.x

Direction Control

1

0

1

From Module

Pad Logic

P1.0/TACLK ..

P1.7/TA2

P1OUT.x

Module X OUT

P1IN.x

EN

D

Module X IN

P1IRQ.x

P1IE.x

Interrupt

Edge

Select

EN

Q

Set

P1IFG.x

Interrupt

Flag

P1IES.x

P1SEL.x

Dir. CONTROL

FROM MODULE

PnSel.x

PnDIR.x

PnOUT.x MODULE X OUT PnIN.x

MODULE X IN

PnIE.x PnIFG.x PnIES.x

†

P1Sel.0

P1Sel.1

P1Sel.2

P1Sel.3

P1Sel.4

P1Sel.5

P1Sel.6

P1Sel.7

P1DIR.0

P1DIR.1

P1DIR.2

P1DIR.3

P1DIR.4

P1DIR.5

P1DIR.6

P1DIR.7

P1DIR.0

P1DIR.1

P1DIR.2

P1DIR.3

P1DIR.4

P1DIR.5

P1DIR.6

P1DIR.7

P1OUT.0

P1OUT.1

P1OUT.2

P1OUT.3

P1OUT.4

P1OUT.5

P1OUT.6

P1OUT.7

DV

P1IN.0

P1IN.1

P1IN.2

P1IN.3

P1IN.4

P1IN.5

P1IN.6

P1IN.7

TACLK

P1IE.0 P1IFG.0 P1IES.0

P1IE.1 P1IFG.1 P1IES.1

P1IE.2 P1IFG.2 P1IES.2

P1IE.3 P1IFG.3 P1IES.3

P1IE.4 P1IFG.4 P1IES.4

P1IE.5 P1IFG.5 P1IES.5

P1IE.6 P1IFG.6 P1IES.6

P1IE.7 P1IFG.7 P1IES.7

SS

†

Out0 signal

Out1 signal

Out2 signal

SMCLK

CCI0A

CCI1A

CCI2A

unused

†

Out0 signal

Out1 signal

Out2 signal

†

Signal from or to Timer_A

25

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SLAS341B − SEPTEMBER 2001 − REVISED SEPTEMBER 2004

APPLICATION INFORMATION

input/output schematic (continued)

port P2, P2.0 to P2.2, P2.6, and P2.7 input/output with Schmitt-trigger

P2SEL.x

0

0: Input

P2DIR.x

Direction Control

From Module

1: Output

1

0

1

P2OUT.x

Module X OUT

P2.0/ACLK

P2.1/TAINCLK

P2.2/CAOUT/TA0

P2.6

Pad Logic

P2IN.x

P2.7/TA0

EN

D

Bus Keeper

Module X IN

P2IRQ.x

CAPD.X

P2IE.x

P2IFG.x

EN

Interrupt

Edge

Select

Q

Set

Interrupt

Flag

P2IES.x

P2SEL.x

x: Bit Identifier 0 to 2, 6, and 7 for Port P2

Dir. CONTROL

PnSel.x

PnDIR.x

PnOUT.x MODULE X OUT PnIN.x

MODULE X IN

PnIE.x PnIFG.x PnIES.x

FROM MODULE

P2Sel.0

P2Sel.1

P2Sel.2

P2Sel.6

P2Sel.7

P2DIR.0

P2DIR.1

P2DIR.2

P2DIR.6

P2DIR.7

P2DIR.0

P2OUT.0

P2OUT.1

P2OUT.2

P2OUT.6

P2OUT.7

ACLK

DV

P2IN.0

P2IN.1

P2IN.2

P2IN.6

P2IN.7

unused

P2IE.0 P2IFG.0 P2IES.0

P2IE.1 P2IFG.1 P2IES.1

P2IE.2 P2IFG.2 P2IES.2

P2IE.6 P2IFG.6 P2IES.6

P2IE.7 P2IFG.7 P2IES.7

‡

P2DIR.1

INCLK

CCI0B

SS

†

‡

P2DIR.2

CAOUT

DV

P2DIR.6

unused

SS

§

P2DIR.7

Out0 signal

†

‡

§

Signal from Comparator_A

Signal to Timer_A

Signal from Timer_A

26

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SLAS341B − SEPTEMBER 2001 − REVISED SEPTEMBER 2004

APPLICATION INFORMATION

input/output schematic (continued)

port P2, P2.3 to P2.4, input/output with Schmitt-trigger

P2SEL.3

0: Input

0

1: Output

P2DIR.3

Direction Control

1

From Module

Pad Logic

P2.3/CA0/TA1

0

P2OUT.3

Module X OUT

1

P2IN.3

EN

Bus Keeper

Module X IN

P2IRQ.3

D

P2IE.3

Interrupt

Edge

Select

EN

Set

CAPD.3

CAREF

Q

P2IFG.3

Comparator_A

CAF

CAEX

P2CA

Interrupt

Flag

P2IES.3

P2SEL.3

+

−

CCI1B

To Timer_A3

P2SEL.4

Reference Block

P2IES.4

CAREF

Interrupt

Flag

Edge

Select

Interrupt

P2IFG.4

Set

Q

EN

CAPD.4

P2IRQ.4

Module X IN

P2IE.4

D

Bus Keeper

EN

P2IN.4

1

Module X OUT

P2OUT.4

0

1

P2.4/CA1/TA2

Pad Logic

From Module

Direction Control

P2DIR.4

1: Output

0: Input

0

P2SEL.4

DIRECTION

CONTROL

PnSel.x

PnDIR.x

PnOUT.x MODULE X OUT PnIN.x

MODULE X IN

PnIE.x PnIFG.x PnIES.x

FROM MODULE

†

P2Sel.3

P2Sel.4

P2DIR.3

P2DIR.4

P2DIR.3

P2OUT.3

P2OUT.4

Out1 signal

P2IN.3

P2IN.4

unused

P2IE.3 P2IFG.3 P2IES.3

P2IE.4 P2IFG.4 P2IES.4

P2DIR.4

Out2 signal

†

Signal from Timer_A

27

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SLAS341B − SEPTEMBER 2001 − REVISED SEPTEMBER 2004

APPLICATION INFORMATION

input/output schematic (continued)

port P2, P2.5, input/output with Schmitt-trigger and R

function for the basic clock module

osc

0: Input

1: Output

P2SEL.5

Pad Logic

0

1

0

1

P2DIR.5

Direction Control

From Module

P2.5/Rosc

P2OUT.5

Module X OUT

Bus Keeper

P2IN.5

EN

D

Internal to

Basic Clock

Module

Module X IN

P2IRQ.5

1

0

V

CC

Edge

Select

Interrupt

P2IE.5

EN

Q

Set

P2IFG.5

Interrupt

Flag

To DC Generator

P2IES.5

P2SEL.5

DCOR

CAPD.5

DCOR: Control Bit From Basic Clock Module

If it Is Set, P2.5 Is Disconnected From P2.5 Pad

DIRECTION

PnSel.x

PnDIR.x

CONTROL

FROM MODULE

PnOUT.x MODULE X OUT PnIN.x

P2OUT.5 DV P2IN.5

MODULE X IN

PnIE.x PnIFG.x PnIES.x

P2Sel.5

P2DIR.5

unused

P2IE.5 P2IFG.5 P2IES.5

SS

28

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SLAS341B − SEPTEMBER 2001 − REVISED SEPTEMBER 2004

APPLICATION INFORMATION

input/output schematic (continued)

port P3, P3.0 and P3.4 to P3.7, input/output with Schmitt-trigger

P3SEL.x

0: Input

0

1: Output

P3DIR.x

Direction Control

1

0

1

From Module

Pad Logic

P3.0/STE0

P3OUT.x

Module X OUT

P3.4/UTXD0

P3.5/URXD0

P3.6

P3.7

P3IN.x

EN

D

Module X IN

x: Bit Identifier, 0 and 4 to 7 for Port P3

DIRECTION

PnSel.x

PnDIR.x

CONTROL

FROM MODULE

PnOUT.x

MODULE X OUT

DV

PnIN.x

MODULE X IN

P3Sel.0

P3Sel.4

P3Sel.5

P3Sel.6

P3Sel.7

P3DIR.0

P3DIR.4

P3DIR.5

P3DIR.6

P3DIR.7

DV

P3OUT.0

P3OUT.4

P3OUT.5

P3OUT.6

P3OUT.7

P3IN.0

P3IN.4

P3IN.5

P3IN.6

P3IN.7

STE0

SS

CC

SS

CC

SS

†

UTXD0

Unused

‡

DV

URXD0

Unused

SS

†

‡

Output from USART0 module

Input to USART0 module

port P3, P3.1, input/output with Schmitt-trigger

P3SEL.1

P3DIR.1

0: Input

1: Output

0

1

0

1

SYNC

MM

DCM_SIMO

STC

STE

Pad Logic

P3.1/SIMO0

P3OUT1

(SI)MO0

From USART0

P3IN.1

EN

D

SI(MO)0

To USART0

29

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SLAS341B − SEPTEMBER 2001 − REVISED SEPTEMBER 2004

APPLICATION INFORMATION

input/output schematic (continued)

port P3, P3.2, input/output with Schmitt-trigger

P3SEL.2

P3DIR.2

0: Input

1: Output

0

1

0

1

SYNC

MM

DCM_SOMI

Pad Logic

STC

STE

P3.2/SOMI0

P3OUT.2

SO(MI)0

From USART0

P3IN.2

EN

D

(SO)MI0

To USART0

port P3, P3.3, input/output with Schmitt-trigger

0: Input

1: Output

P3SEL.3

P3DIR.3

0

1

0

1

SYNC

MM

DCM_UCLK

STC

STE

Pad Logic

P3.3/UCLK0

P3OUT.3

UCLK.0

From USART0

P3IN.3

EN

D

UCLK0

To USART0

NOTE: UART mode:

The UART clock can only be an input. If UART mode and UART function are selected, the P3.3/UCLK0 is always

an input.

SPI, slave mode:

The clock applied to UCLK0 is used to shift data in and out.

SPI, master mode: The clock to shift data in and out is supplied to connected devices on pin P3.3/UCLK0 (in slave mode).

30

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SLAS341B − SEPTEMBER 2001 − REVISED SEPTEMBER 2004

APPLICATION INFORMATION

input/output schematic (continued)

port P4, P4.0 to P4.6, input/output with Schmitt-trigger

P4SEL.x

0: Input

1: Output

0

1

0

1

P4DIR.x

Direction Control

From Module

Pad Logic

TBOUTHiZ

P4OUT.x

Module X OUT

P4.0/TB0

P4.1/TB1

P4.2/TB2

P4.3

P4.4

P4.5

P4.6

Bus Keeper

P4IN.x

EN

D

Module X IN

x: bit identifier, 0 to 6 for Port P4

DIRECTION

CONTROL

PnSel.x

PnDIR.x

PnOUT.x

MODULE X OUT

PnIN.x

MODULE X IN

FROM MODULE

†

‡

P4Sel.0

P4Sel.1

P4DIR.0

P4DIR.1

P4DIR.0

P4OUT.0

P4OUT.1

Out0 signal

Out1 signal

P4IN.0

P4IN.1

CCI0A / CCI0B

CCI1A / CCI1B

‡

P4DIR.1

†

P4Sel.2

P4DIR.2

P4OUT.2

Out2 signal

P4IN.2

CCI2A / CCI2B

P4Sel.3

P4Sel.4

P4Sel.5

P4Sel.6

P4DIR.3

P4DIR.4

P4DIR.5

P4DIR.6

P4DIR.3

P4DIR.4

P4DIR.5

P4DIR.6

P4OUT.3

P4OUT.4

P4OUT.5

P4OUT.6

DV

P4IN.3

P4IN.4

P4IN.5

P4IN.6

Unused

SS

†

‡

Signal from Timer_B

Signal to Timer_B

NOTE: TBoutHiZ signal is used by port module P4, pins P4.0 to P4.6. The function TBoutHiZ is mainly used with Timer_B. Port pins P4.3 to P4.6

have the TBoutHiZ function, but no Timer_B output is available for secondary functions. The port selection function can be used to get

the port pin to high impedance and to use the P4DIR.x bits.

31

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SLAS341B − SEPTEMBER 2001 − REVISED SEPTEMBER 2004

APPLICATION INFORMATION

input/output schematic (continued)

port P4, P4.7, input/output with Schmitt-trigger

P4SEL.7

P4DIR.7

0: Input

1: Output

0

1

0

1

Pad Logic

P4.7/TBCLK

P4OUT.7

DV

SS

P4IN.7

EN

D

Timer_B,

TBCLK

port P5, P5.0 to P5.7, input/output with Schmitt-trigger

P5SEL.x

0: Input

0

1

0

1

1: Output

P5DIR.x

Direction Control

From Module

Pad Logic

P5OUT.x

Module X OUT

P5.0

P5.1

P5.2

P5.3

P5.4/MCLK

P5.5/SMCLK

P5.6/ACLK/

TBOUTH

P5IN.x

EN

D

Module X IN

x: Bit Identifier, 0 to 7 for Port P5

PnSel.x

P5Sel.0

P5Sel.1

P5Sel.2

P5Sel.3

P5Sel.4

P5Sel.5

P5Sel.6

P5Sel.7

PnDIR.x

P5DIR.0

P5DIR.1

P5DIR.2

P5DIR.3

P5DIR.4

P5DIR.5

P5DIR.6

P5DIR.7

Dir. CONTROL FROM MODULE

PnOUT.x

MODULE X OUT

PnIN.x

P5IN.0

P5IN.1

P5IN.2

P5IN.3

P5IN.4

P5IN.5

P5IN.6

P5IN.7

MODULE X IN

unused

DV

P5OUT.0

P5OUT.1

P5OUT.2

P5OUT.3

P5OUT.4

P5OUT.5

P5OUT.6

P5OUT.7

DV

SS

CC

SS

unused

MCLK

SMCLK

ACLK

unused

DV

TBOUTHiZ

SS

NOTE: TBOUTHiZ signal is used by port module P4, pins P4.0 to P4.6. The function of TBOUTHiZ is mainly useful when used with Timer_B.

32

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SLAS341B − SEPTEMBER 2001 − REVISED SEPTEMBER 2004

APPLICATION INFORMATION

input/output schematic (continued)

port P6, P6.0 to P6.7, input/output with Schmitt-trigger

P6SEL.x

0

0: Input

P6DIR.x

Direction Control

From Module

1: Output

1

0

1

Pad Logic

P6.0 .. P6.7

P6OUT.x

Module X OUT

Bus Keeper

P6IN.x

EN

D

Module X IN

x: Bit Identifier, 0 to 7 for Port P6

DIR. CONTROL

FROM MODULE

PnSel.x

PnDIR.x

PnOUT.x

MODULE X OUT

PnIN.x

MODULE X IN

P6Sel.0

P6Sel.1

P6Sel.2

P6Sel.3

P6Sel.4

P6Sel.5

P6Sel.6

P6Sel.7

P6DIR.0

P6DIR.1

P6DIR.2

P6DIR.3

P6DIR.4

P6DIR.5

P6DIR.6

P6DIR.7

P6DIR.0

P6OUT.0

P6OUT.1

P6OUT.2

P6OUT.3

P6OUT.4

P6OUT.5

P6OUT.6

P6OUT.7

DV

P6IN.0

P6IN.1

P6IN.2

P6IN.3

P6IN.4

P6IN.5

P6IN.6

P6IN.7

unused

SS

P6DIR.1

P6DIR.2

P6DIR.3

P6DIR.4

P6DIR.5

P6DIR.6

P6DIR.7

NOTE: Direction control bits P6DIR.x and P6SEL.x control whether the port function is active (P6DIR.x=0) or whether the input P6.x is in the

high-impedance state. This is identical to the port P6 function in the MSP430F13x devices (used for emulation/prototyping), but different

from other digital-only ports such as P5.

33

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SLAS341B − SEPTEMBER 2001 − REVISED SEPTEMBER 2004

APPLICATION INFORMATION

JTAG pins TMS, TCK, TDI, TDO/TDI, input/output with Schmitt-trigger

TDO

Controlled by JTAG

JTAG

TDO/TDI

Controlled

by JTAG

DV

CC

TDI

Fuse

Burn & Test

Fuse

TDI/TCLK

Test

and

DV

CC

Emulation

Module

TMS

TCK

TMS

TCK

DV

CC

During Blowing of the Fuse, Pin

TDO/TDI Is Used to Apply the Test

Input Data for JTAG Circuitry

JTAG fuse check mode

MSP430 devices that have the fuse on the TDI/TCLK terminal have a fuse check mode that tests the continuity

of the fuse the first time the JTAG port is accessed after a power-on reset (POR). When activated, a fuse check

current, I , of 1 mA at 3 V can flow from the TDI/TCLK pin to ground if the fuse is not burned. Care must be

TF

taken to avoid accidentally activating the fuse check mode and increasing overall system power consumption.

Activation of the fuse check mode occurs with the first negative edge on the TMS pin after power up or if the

TMS is being held low during power up. The second positive edge on the TMS pin deactivates the fuse check

mode. After deactivation, the fuse check mode remains inactive until another POR occurs. After each POR the

fuse check mode has the potential to be activated.

The fuse check current will only flow when the fuse check mode is active and the TMS pin is in a low state (see

Figure 13). Therefore, the additional current flow can be prevented by holding the TMS pin high (default

condition).

Time TMS Goes Low After POR

TMS

I

TF

I

TDI/TCLK

Figure 13. Fuse Check Mode Current

34

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Mailing Address:

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Post Office Box 655303 Dallas, Texas 75265


型号：	MSP430C1351
厂家：	TEXAS INSTRUMENTS
描述：	MIXED SIGNAL MICROCONTROLLER 混合信号微控制器微控制器
文件：	总35页 (文件大小：543K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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