MSP430C311S [TI]
MIXED SIGNAL MICROCONTROLLERS; 混合信号微控制器
| 型号： | MSP430C311S |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | MIXED SIGNAL MICROCONTROLLERS |
| 文件： | 总30页 (文件大小：399K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MSP430x31x
MIXED SIGNAL MICROCONTROLLERS
SLAS165D – FEBRUARY 1998 – REVISED APRIL 2000
DL PACKAGE
Low Supply Voltage Range 2.5 V – 5.5 V
Ultra Low-Power Consumption
(56-PIN TOP VIEW)
TDO/TDI
TDI/VPP
TMS
NC
1
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
Low Operation Current, 400 µA at 1 MHz,
3 V
COM3
2
COM2
3
TCK
4
COM1
RST/NMI
XBUF
5
COM0
Five Power Saving Modes: (Standby Mode:
1.3 µA, RAM Retention/Off Mode: 0.1 µA)
6
S27/O27/CMPI
S26/O26
S23/O23
S22/O22
S18/O18
S17/O17
S16/O16
S15/O15
S14/O14
S13/O13
S12/O12
S11/O11
S10/O10
S9/O9
V
7
SS
CC
V
R23
R13
8
9
Wakeup From Standby Mode in 6 µs
Maximum
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Xin
Xout/TCLK
P0.0
16-Bit RISC Architecture, 300 ns Instruction
Cycle Time
P0.1/RXD
P0.2/TXD
P0.3
P0.4
Single Common 32 kHz Crystal, Internal
System Clock up to 3.3 MHz
P0.5
P0.6
P0.7
S8/O8
Integrated LCD Driver for up to 64 or 92
Segments
TP0.0
TP0.1
TP0.2
TP0.3
TP0.4
TP0.5
CIN
S7/O7
S6/O6
S5/O5
S4/O4
Slope A/D Converter With External
Components
S3/O3
S2/O2
S1
S0
NC
Serial Onboard Programming
Program Code Protection by Security Fuse
DL PACKAGE
(48-PIN TOP VIEW)
Family Members Include:
MSP430C311S: 2k Byte ROM,128 Byte RAM
MSP430C312: 4k Byte ROM, 256 Byte RAM
MSP430C313: 8k Byte ROM, 256 Byte RAM
MSP430C314: 12k Byte ROM, 512 Byte RAM
MSP430C315: 16k Byte ROM, 512 Byte RAM
MSP430P313: 8k Byte OTP, 256 Byte RAM
MSP430P315: 16k Byte OTP, 512 Byte RAM
MSP430P315S: 16k Byte OTP, 512 ByteRAM
TDI/VPP
TMS
TDO/TDI
COM3
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
2
TCK
COM2
3
RST/NMI
XBUF
COM1
4
5
COM0
V
6
S27/O27/CMPI
NC
SS
V
7
CC
†
R23
R13
8
V
SS
9
NC
Xin
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
S16/O16
S15/O15
S14/O14
S13/O13
S12/O12
S11/O11
S10/O10
S9/O9
Xout/TCLK
P0.1/RXD
P0.2/TXD
P0.3
EPROM Version Available for Prototyping :
†
PMS430E313FZ , PMS430E315FZ
P0.4
P0.5
P0.6
Available in:
56-Pin Plastic Small-Outline Package
(SSOP),
48-Pin SSOP (MSP430C311S,
MSP430P315S),
NC
S8/O8
TP0.0
TP0.1
TP0.2
TP0.3
TP0.5
CIN
S7/O7
S6/O6
S5/O5
S4/O4
S3/O3
S2/O2
68-Pin J-Leaded Ceramic Chip Carrier
(JLCC) Package (EPROM Only)
NC – No internal connection
description
The MSP430 is an ultralow-power mixed signal microcontroller family consisting of several devices that feature
differentsetsofmodulestargetedtovariousapplications. Themicrocontrollerisdesignedtobebatteryoperated
for an extended application lifetime. With 16-bit RISC architecture, 16-bit integrated registers on the CPU, and
a constant generator, the MSP430 achieves maximum code efficiency. The digitally-controlled oscillator,
together with the frequency-locked-loop (FLL), provides a wakeup from a low-power mode to active mode in
less than 6 s.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
†
MSP430P313/E313 not recommended for new designs – replaced by MSP430P315/E315.
Copyright 2000, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x31x
MIXED SIGNAL MICROCONTROLLERS
SLAS165D – FEBRUARY 1998 – REVISED APRIL 2000
description (continued)
Typical applications include sensor systems that capture analog signals, converting them to digital values, and
then processes the data and displays them or transmits them to a host system. The timer/port module provides
single-slope A/D conversion capability for resistive sensors.
AVAILABLE OPTIONS
PACKAGED DEVICES
SSOP
56-Pin
(DL)
JLCC
68-Pin
(FZ)
SSOP
48-Pin
(DL)
T
A
MSP430C312IDL
MSP430C313IDL
MSP430C314IDL
MSP430C315IDL
MSP430P313IDL
MSP430P315IDL
MSP430C311SIDL
MSP430P315SIDL
–40°C to 85°C
25°C
†
†
PMS430E313FZ
PMS430E315FZ
—
—
†
MSP430P313/E313 not recommended for new designs – replaced by MSP430P315/E315.
functional block diagram
†
MSP430C312,313,314,315 and MSP430P313 ,315 and PMS430E313,315
V
V
SS
CC
XIN
Xout
XBUF
RST/NMI
P0.0–7
4/8/12/16 kB
8
ROM
Oscillator
FLL
System Clock
8/16 kB
ACLK
MCLK
256/512 B
RAM
Power-On-
Reset
8-Bit Timer/
Counter
I/O Port
OPT or EPROM
C: ROM
8 I/O’s, All With
Interr. Cap.
TXD
RXD
Serial Protocol
Support
P: OTP
E: EPROM
3 Int. Vectors
TDI/VPP
TDO/TDI
MAB, 16 Bit
MDB, 16 Bit
MAB, 4 Bit
CPU
Test
JTAG
MCB
Incl. 16 Reg.
MDB, 8 Bit
Bus
Conv
TMS
TCK
LCD
Watchdog
Timer
Timer/Port
Basic
Timer1
92 Segments
Applications:
Com0–3
S0–18,22,23,26/
O2–18,22,23,26
A/D Conv.
Timer, O/P
f
15/16 Bit
LCD
1, 2, 3, 4 MUX
S27/O27/CMPI
CMPI
5
TP0.0–4
CIN
R13
R23
TP0.5
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x31x
MIXED SIGNAL MICROCONTROLLERS
SLAS165D – FEBRUARY 1998 – REVISED APRIL 2000
Terminal Functions
†
MSP430C312, MSP430C313†, MSP430C314, MSP430C315, MSP430P313 , MSP430P315
56-pin SSOP package
TERMINAL
I/O
DESCRIPTION
NAME
NO.
27
CIN
I
O
I/O
I/O
I/O
I/O
I
Counter enable. CIN input enables counter (TPCNT1) (timer/port).
Common output pins. COM0–COM3 are used for LCD back planes.
General-purpose digital I/O pin
COM0–COM3
P0.0
52–55
13
P0.1/RXD
P0.2/TXD
14
General-purpose digital I/O pin, receive data input port – 8-bit (timer/counter)
General-purpose digital I/O pin, transmit data output port – 8-bit (timer/counter)
Five general-purpose digital I/O pins, bit 3–7
15
P0.3–P0.7
R23
16–20
9
Input of second positive analog LCD level (V2) (LCD)
R13
10
I
Input of third positive analog LCD level (V3 of V4) (LCD)
Reset input or nonmaskable interrupt input
RST/NMI
5
I
S0
29
O
O
O
O
O
O
O
O
O
I/O
Segment line S0 (LCD)
S1
30
Segment line S1 (LCD)
S2/O2–S5/O5
S6/O6–S9/O9
S10/O10–S13/O13
S14/O14–S17/O17
S18/O18
31–34
35–38
39–42
43–46
47
Segment lines (S2 to S5) or digital output port O2 to O5, group 1 (LCD)
Segment lines (S6 to S9) or digital output port O6 to O9, group 2 (LCD)
Segment lines (S10 to S13) or digital output port O10 to O13, group 3 (LCD)
Segment lines (S14 to S17) or digital output port O14 to O17, group 4 (LCD)
Segment line (S18) or digital output port O18 , group 5 (LCD)
Segment lines (S22 to S23) or digital output port O22 to O23, group 6 (LCD)
Segment line (S26) or digital output port O26, group 7 (LCD)
S22/O22–S23/O23
S26/O26
48,49
50
S27/O27/CMPI
51
Segment line (S27) or digital output port O27 group 7, can be used as a comparator input port CMPI
(timer/port)
TCK
4
2
1
I
I
Test clock. TCK is a clock input terminal for device programming and test.
TDI/VPP
TDO/TDI
Test data input port. TDI/VPP is used as a data input terminal or an input for programming voltage.
I/O
Test data output port. TDO/TDI is used as a data output terminal or as a data input during
programming.
TMS
3
I
Test mode select. TMS is an input terminal for device programming and test.
General-purpose 3-state digital output port, bit 0 (timer/port)
General-purpose 3-state digital output port, bit 1 (timer/port)
General-purpose 3-state digital output port, bit 2 (timer/port)
General-purpose 3-state digital output port, bit 3( timer/port)
General-purpose 3-state digital output port, bit 4 (timer/port)
TP0.0
TP0.1
TP0.2
TP0.3
TP0.4
TP0.5
21
22
23
24
25
26
8
O/Z
O/Z
O/Z
O/Z
O/Z
I/O/Z General-purpose 3-state digital I/O pin, bit 5 (timer/port)
V
V
Supply voltage
CC
7
Ground reference
SS
XBUF
6
O
I
Clock signal output of system clock (MCLK) or crystal clock (ACLK)
Input terminal of crystal oscillator
Xin
11
12
Xout/TCLK
I/O
Output terminal of crystal oscillator or test clock input
†
MSP430P313/E313 not recommended for new designs – replaced by MSP430P315/E315.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x31x
MIXED SIGNAL MICROCONTROLLERS
SLAS165D – FEBRUARY 1998 – REVISED APRIL 2000
functional block diagram
MSP430C311S and MSP430P315S
V
V
SS
XIN
Xout
XBUF
CC
RST/NMI
P0.1–6
6
2 kB
Oscillator
FLL
System Clock
ROM
16 kB
ACLK
MCLK
128/512B
RAM
Power-On-
Reset
8-bit Timer/
Counter
I/O Port
6 I/O’s, All With
Interr. Cap.
TXD
RXD
OTP
Serial Protocol
Support
C: ROM
P: OTP
2 Int. Vectors
TDI/VPP
TDO/TDI
MAB, 16 Bit
MDB, 16 Bit
MAB, 4 Bit
CPU
Test
JTAG
MCB
Incl. 16 Reg.
MDB, 8 Bit
Bus
Conv
TMS
TCK
LCD
Watchdog
Timer
Timer/Port
Basic
Timer1
64 Segments
Applications:
COM0–3
A/D Conv.
Timer, O/P
S2–16/O2–16
S27/O27/CMPI
f
15/16 Bit
LCD
1, 2, 3, 4 MUX
CMPI
4
TP0.0–3
R13
R23
TP0.5
CIN
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x31x
MIXED SIGNAL MICROCONTROLLERS
SLAS165D – FEBRUARY 1998 – REVISED APRIL 2000
Terminal Functions
MSP430C311S, MSP430P315S
48-pin SSOP package
TERMINAL
I/O
DESCRIPTION
NAME
NO.
CIN
24
I
Counter enable. CIN input enables counter (TPCNT1) (timer/port).
Common output pins, COM0–COM3 are used for LCD back planes.
General-purpose digital I/O pin, receive data input port – 8-Bit (timer/counter)
General-purpose digital I/O pin, transmit data output port – 8-Bit (timer/counter)
General-purpose digital I/O pins, bit 3
COM0–COM3
P0.1/RXD
P0.2/TXD
P0.3
44–47
12
O
I/O
I/O
I/O
I/O
I/O
I/O
I
13
14
P0.4
15
General-purpose digital I/O pins, bit 4
P0.5
16
General-purpose digital I/O pins, bit 5
P0.6
17
General-purpose digital I/O pins, bit 6
R23
8
Input of second positive analog LCD level (V2) (LCD)
R13
9
I
Input of third positive analog LCD level (V3 of V4) (LCD)
Reset input or nonmaskable interrupt input
RST/NMI
4
I
S2/O2–S5/O5
S6/O6–S9/O9
S10/O10–S13/O13
S14/O14–S16/O16
S27/O27/CMPI
25–28
29–32
33–36
37–39
43
O
Segment lines (S2 to S5) or digital output port O2 to O5, group 1 (LCD)
Segment lines (S6 to S9) or digital output port O6 to O9, group 2 (LCD)
Segment lines (S10 to S13) or digital output port O10 to O13, group 3 (LCD)
Segment lines (S14 to S17) or digital output port O14 to O17, group 4 (LCD)
O
O
O
I/O
Segment line (S27) or digital output port O27 group 7, can be used as a comparator input port CMPI
(timer/port)
TCK
3
1
I
I
Test clock. TCK is a clock input terminal for device programming and test.
TDI/VPP
TDO/TDI
Test data input port. TDI/VPP is used as a data input terminal or an input for programming voltage.
48
I/O
Test data output port. TDO/TDI is used as a data output terminal or as a data input during
programming.
TMS
2
I
Test mode select. TMS is an input terminal for device programming and test.
General-purpose 3-state digital output port, bit 0 (timer/port)
General-purpose 3-state digital output port, bit 1 (timer/port)
General-purpose 3-state digital output port, bit 2 (timer/port)
General-purpose 3-state digital output port, bit 3 (timer/port)
TP0.0
TP0.1
TP0.2
TP0.3
TP0.5
19
20
21
22
23
7
O/Z
O/Z
O/Z
O/Z
I/O/Z General-purpose 3-state digital I/O pin, bit 5 (timer/port)
Supply voltage
V
V
CC
6, 41
5
Ground references
SS
XBUF
O
I
Clock signal output of system clock (MCLK) or crystal clock (ACLK)
Input terminal of crystal oscillator
Xin
10
Xout/TCLK
11
I/O
Output terminal of crystal oscillator or test clock input
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x31x
MIXED SIGNAL MICROCONTROLLERS
SLAS165D – FEBRUARY 1998 – REVISED APRIL 2000
short-form description
processing unit
The processing unit is based on a consistent and orthogonal designed CPU and instruction set. This design
structure results in a RISC-like architecture, highly transparent to the application development and
distinguishable by the ease of programming. All operations other than program-flow instructions are
consequently performed as register operations in conjunction with seven addressing modes for source and four
modes for destination operand.
CPU
PC/R0
SP/R1
SR/CG1/R2
CG2/R3
R4
Program Counter
Stack Pointer
Sixteen registers located inside the CPU provide
reduced instruction execution time. This reduces
a register-register operation execution time to one
cycle of the processor frequency.
Status Register
Four registers are reserved for special use as a
program counter, a stack pointer, a status register,
and a constant generator. The remaining ones are
available as general-purpose registers.
Constant Generator
General-Purpose Register
General-Purpose Register
R5
Peripherals connected to the CPU using a data
address and control bus can be handled easily
with all instructions for memory manipulation.
General-Purpose Register
General-Purpose Register
R14
R15
instruction set
The instruction set for this register-register
architecture provides a powerful and easy-to-use
assembly language. The instruction set consists of 51 instructions with three formats and seven addressing
modes. Table 1 provides a summation and example of the three types of instruction formats; the addressing
modes are listed in Table 2.
Table 1. Instruction Word Formats
Dual operands, source-destination e.g. ADD R4, R5
R4 + R5 → R5
Single operands, destination only
Relative jump, un-/conditional
e.g. CALL R8
e.g. JNE
PC → (TOS), R8 → PC
Jump-on equal bit = 0
Each instruction that operates on word and byte data is identified by the suffix B.
Examples: Instructions for word operation Instructions for byte operation
MOV
ADD
EDE,TONI
#235h,&MEM
R5
MOV.B
ADD.B
EDE,TONI
#35h,&MEM
PUSH
SWPB
PUSH.B R5
—
R5
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x31x
MIXED SIGNAL MICROCONTROLLERS
SLAS165D – FEBRUARY 1998 – REVISED APRIL 2000
Table 2. Address Mode Descriptions
ADDRESS MODE
Register
s
d
√
√
√
√
SYNTAX
MOV Rs, Rd
EXAMPLE
MOV R10, R11
OPERATION
√
R10 → R11
Indexed
√
MOV X(Rn), Y(Rm)
MOV EDE, TONI
MOV &MEM, &TCDAT
MOV @Rn, Y(Rm)
MOV @Rn+, RM
MOV #X, TONI
MOV 2(R5), 6(R6)
M(2 + R5) → M(6 + R6)
M(EDE) → M(TONI)
Symbolic (PC relative)
Absolute
√
√
M(MEM) → M(TCDAT)
M(R10) → M(Tab + R6)
M(R10) → R11, R10 + 2 → R10
#45 → M(TONI)
Indirect
√
MOV @R10, Tab(R6)
MOV @R10+, R11
MOV #45, TONI
Indirect autoincrement
Immediate
√
√
NOTE: s = source
d = destination
Computed branches (BR) and subroutine call (CALL) instructions use the same addressing modes as the other
instructions. These addressing modes provide indirect addressing, ideally suited for computed branches and
calls. The full use of this programming capability permits a program structure different from conventional 8- and
16-bit controllers. For example, numerous routines can easily be designed to deal with pointers and stacks
instead of using flag type programs for flow control.
operation modes and interrupts
TheMSP430operatingmodessupportvariousadvancedrequirementsforultralow-powerandultra-lowenergy
consumption. This is achieved by the management of the operations during the different module operation
modes and CPU states. The requirements are fully supported during interrupt event handling. An interrupt event
awakensthesystemfromeachofthevariousoperatingmodesandreturnswiththeRETIinstructiontothemode
that was selected before the interrupt event. The clocks used are ACLK and MCLK. ACLK is the crystal
frequency and MCLK , a multiple of ACLK, is used as the system clock.
The software can configure five operating modes:
Active mode (AM). The CPU is enabled with different combinations of active peripheral modules.
Low-power mode 0 (LPM0). The CPU is disabled, peripheral operation continues, ACLK and MCLK signals
are active, and loop control for MCLK is active.
Low-power mode 1 (LPM1). The CPU is disabled, peripheral operation continues, ACLK and MCLK signals
are active, and loop control for MCLK is inactive.
Low-power mode 2 (LPM2). The CPU is disabled, peripheral operation continues, ACLK signal is active,
and MCLK and loop control for MCLK are inactive.
Low-power mode 3 (LPM3). The CPU is disabled, peripheral operation continues, ACLK signal is active,
MCLKand loop control for MCLK are inactive, and the dc generator for the digital controlled oscillator(DCO)
(
MCLK generator) is switched off.
Low-power mode 4 (LPM4). The CPU is disabled, peripheral operation continues, ACLK signal is inactive
(crystal oscillator stopped), MCLK and loop control for MCLK are inactive, and the dc generator for the DCO
is switched off.
The special function registers (SFR) include module-enable bits that stop or enable the operation of the specific
peripheral module. All registers of the peripherals may be accessed if the operational function is stopped or
enabled. However, some peripheral current-saving functions are accessed through the state of local register
bits. An example is the enable/disable of the analog voltage generator in the LCD peripheral, which is turned
on or off using one register bit.
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x31x
MIXED SIGNAL MICROCONTROLLERS
SLAS165D – FEBRUARY 1998 – REVISED APRIL 2000
operation modes and interrupts (continued)
The most general bits that influence current consumption and support fast turn-on from low power operating
modesarelocatedinthestatusregister(SR). FourofthesebitscontroltheCPUandthesystemclockgenerator:
SCG1, SCG0, OscOff, and CPUOff.
15
Reserved For Future
Enhancements
rw-0
9
8
7
0
V
SCG1
rw-0
SCG0
rw-0
OscOff
rw-0
CPUOff
rw-0
GIE
N
Z
C
rw-0
rw-0
rw-0
rw-0
rw-0
interrupt vector addresses
The interrupt vectors and the power-up starting address are located in the ROM with an address range of
0FFFFh-0FFE0h. The vector contains the 16-bit address of the appropriate interrupt handler instruction
sequence.
INTERRUPT SOURCE
INTERRUPT FLAG
SYSTEM INTERRUPT
WORD ADDRESS
PRIORITY
Power-up, external reset, watchdog
Reset
0FFFEh
15, highest
WDTIFG (see Note 1)
Nonmaskable,
(Non)maskable
NMIIFG (see Notes 1 and 3)
OFIFG (see Notes 1 and 4)
NMI, oscillator fault
0FFFCh
0FFFAh
0FFF8h
14
13
12
Dedicated I/O P0.0
Dedicated I/O P0.1
8-Bit Timer/Counter
P0.0IFG
Maskable
Maskable
P0.1IFG
0FFF6h
0FFF4h
0FFF2h
0FFF0h
0FFEEh
0FFECh
11
10
9
Watchdog Timer
WDTIFG
Maskable
Maskable
8
7
6
RC1FG, RC2FG, EN1FG
(see Note 2)
Timer/Port
0FFEAh
5
0FFE8h
0FFE6h
0FFE4h
0FFE2h
0FFE0h
4
3
2
1
Basic Timer1
BTIFG
Maskable
Maskable
I/O Port 0.2–7
0, lowest
P0.27IFG (see Note 1)
NOTES: 1. Multiple source flags
2. Timer/port interrupt flags are located in the timer/port registers
3. Non maskable: neither the individual nor the general interrupt enable bit will disable an interrupt event.
4. (Non) maskable: the individual interrupt enable bit can disable an interrupt event, but the general interrupt enable bit cannot.
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x31x
MIXED SIGNAL MICROCONTROLLERS
SLAS165D – FEBRUARY 1998 – REVISED APRIL 2000
special function registers
Most interrupt and module enable bits are collected into the lowest address space. Special function register bits
that are not allocated to a functional purpose are not physically present in the device. Simple software access
is provided with this arrangement.
interrupt enable 1 and 2
7
6
5
4
3
2
1
0
Address
0h
P0IE.1
P0IE.0
OFIE
WDTIE
rw-0
rw-0
rw-0
rw-0
WDTIE:
OFIE:
P0IE.0:
P0IE.1:
Watchdog Timer enable signal
Oscillator fault enable signal
Dedicated I/O P0.0
P0.1 or 8-Bit Timer/Counter, RXD
7
6
5
4
3
2
1
0
Address
01h
BTIE
TPIE
rw-0
rw-0
TPIE:
BTIE:
Timer/Port enable signal
Basic Timer1 enable signal
interrupt flag register 1 and 2
7
6
5
4
3
2
1
0
Address
02h
NMIIFG
P0IFG.1
P0IFG.0
OFIFG
WDTIFG
rw-0
rw-0
rw-0
rw-1
rw-0
WDTIFG:
Set on overflow or security key violation
OR
Reset on V
power-on or reset condition at RST/NMI-pin
CC
OFIFG:
Flag set on oscillator fault
Dedicated I/O P0.0
P0.1 or 8-Bit Timer/Counter, RXD
Signal at RST/NMI-pin
P0.0IFG:
P0.1IFG:
NMIIFG:
7
6
5
4
3
2
1
0
Address
03h
BTIFG
rw
BTIFG:
Basic Timer1 flag
module enable register 1 and 2
7
7
6
6
5
5
4
4
3
3
2
2
1
1
0
0
Address
04h
Address
05h
Legend rw:
Bit can be read and written.
rw-0:
Bit can be read and written. It is reset by PUC
SFR bit is not present in device.
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x31x
MIXED SIGNAL MICROCONTROLLERS
SLAS165D – FEBRUARY 1998 – REVISED APRIL 2000
memory organization
MSP430C311S
Int. Vector
MSP430C312
Int. Vector
MSP430C313
Int. Vector
MSP430C314
Int. Vector
MSP430C315
Int. Vector
FFFFh
FFFFh
FFFFh
FFFFh
FFFFh
FFE0h
FFDFh
FFE0h
FFDFh
FFE0h
FFDFh
FFE0h
FFDFh
FFE0h
FFDFh
2 kB ROM
4 kB ROM
F800h
8 kB ROM
F000h
12 kB ROM
16 kB ROM
E000h
D000h
C000h
03FFh
0200h
03FFh
0200h
512B RAM
512B RAM
027Fh
0200h
01FFh
0100h
00FFh
0010h
000Fh
0000h
02FFh
0200h
02FFh
0200h
128B RAM
16b Per.
8b Per.
SFR
256B RAM
16b Per.
8b Per.
SFR
256B RAM
16b Per.
8b Per.
SFR
01FFh
0100h
00FFh
0010h
000Fh
0000h
01FFh
0100h
00FFh
0010h
000Fh
0000h
01FFh
0100h
00FFh
0010h
000Fh
0000h
01FFh
0100h
00FFh
0010h
000Fh
0000h
16b Per.
8b Per.
SFR
16b Per.
8b Per.
SFR
MSP430P315
MSP430P315S
PMS430E315
†
MSP430P313
†
PMS430E313
FFFFh
FFFFh
Int. Vector
Int. Vector
FFE0h
FFDFh
FFE0h
FFDFh
8 kB OTP
or
EPROM
16 kB
OTP
E000h
or
EPROM
C000h
03FFh
0200h
512B RAM
02FFh
0200h
256B RAM
16b Per.
8b Per.
SFR
01FFh
0100h
00FFh
0010h
000Fh
0000h
01FFh
0100h
00FFh
0010h
000Fh
0000h
16b Per.
8b Per.
SFR
†
MSP430P313/E313 not recommended for new designs – replaced by MSP430P315/E315.
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x31x
MIXED SIGNAL MICROCONTROLLERS
SLAS165D – FEBRUARY 1998 – REVISED APRIL 2000
peripherals
Peripherals connected to the CPU through a data, address, and control busses can be handled easily with
instructions for memory manipulation.
oscillator and system clock
Twoclocksareusedinthesystem:thesystem(master)clock(MCLK)andtheauxiliaryclock(ACLK). TheMCLK
isamultipleoftheACLK. TheACLK runswiththecrystaloscillatorfrequency. Thespecialdesignoftheoscillator
supports the feature of low current consumption and the use of a 32 768 Hz crystal. The crystal is connected
across two terminals without requiring any other external components.
The oscillator starts after applying VCC, due to a reset of the control bit (OscOff) in the status register (SR). It
can be stopped by setting the OscOff bit to a 1. The enabled clock signals ACLK, ACLK/2, ACLK/4, or MCLK
are accessible for use by external devices at output terminal XBUF.
The controller system clock has to operate with different requirements according to the application and system
conditions. Requirements include:
•
•
•
•
High frequency in order to react quickly to system hardware requests or events
Low frequency in order to minimize current consumption, EMI, etc.
Stable frequency for timer applications e.g. real-time clock (RTC)
Enable start-stop operation with a minimum delay
These requirements cannot all be met with fast frequency high-Q crystals or with RC-type low-Q oscillators. The
compromise selected for the MSP430 uses a low-crystal frequency, which is multiplied to achieve the desired
nominal operating range:
f
= (N+1) × f
(crystal)
(system)
The crystal frequency multiplication is achieved with a frequency locked loop (FLL) technique. The factor N is
set to 31 after a power-up clear condition. The FLL technique, in combination with a digital controlled oscillator
(DCO), provides immediate start-up capability together with long-term crystal stability. The frequency variation
of the DCO with the FLL inactive is typically 330 ppm, which means that with a cycle time of 1 µs, the maximum
possible variation is 0.33 ns. For more precise timing, the FLL can be used. This forces longer cycle times if
the previous cycle time was shorter than the selected one. This switching of cycle times makes it possible to
meet the chosen system frequency over a long period of time.
The start-up operation of the system clock depends on the previous machine state. During a power-up clear
(PUC), the DCO is reset to its lowest possible frequency. The control logic starts operation immediately after
removal of the PUC condition. Correct operation of the FLL control logic requires the presence of a stable crystal
oscillator.
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x31x
MIXED SIGNAL MICROCONTROLLERS
SLAS165D – FEBRUARY 1998 – REVISED APRIL 2000
peripherals (continued)
digital I/O
There is one eight-bit I/O port, Port0, that is implemented (MSP430C311S and MSP430P315S have six bits
available on external pins). Six control registers give maximum digital input/output flexibility to the application:
•
•
•
•
All individual I/O bits are programmable independently.
Any combination of input, output, and interrupt conditions is possible.
Interrupt processing of external events is fully implemented for all eight bits of port P0.
Provides read/write access to all registers with all instructions
The six registers are:
•
•
•
•
•
•
Input register
8 bits
8 bits
8 bits
6 bits
8 bits
6 bits
contains information at the pins
contains output information
Output register
Direction register
Interrupt flags
controls direction
indicates if interrupt(s) are pending
contains input signal change necessary for interrupt
contains interrupt enable bits
Interrupt edge select
Interrupt enable
All these registers contain eight bits except for the interrupt flag register and the interrupt enable register. The
two least significant bits (LSBs) of the interrupt flag and interrupt enable registers are located in the special
functions register (SFR). Three interrupt vectors are implemented, one for Port0.0, one for Port0.1, and one
commonly used for any interrupt event on Port0.2 to Port0.7. The Port0.1 and Port0.2 pin function is shared with
the 8-bit timer/counter.
LCD drive
Liquid crystal displays (LCDs) for static, 2-, 3-, and 4-MUX operations can be driven directly. The controller LCD
logic operation is defined by software using memory-bit manipulation. LCD memory is part of the LCD module
and not part of the data memory. Eight mode and control bits define the operation and current consumption of
the LCD drive. The information for the individual digits can be easily obtained using table programming
techniques combined with the correct addressing mode. The segment information is stored in LCD memory
using instructions for memory manipulation.
The drive capability is mainly defined by the external resistor divider that supports the analog levels for 2-, 3-,
and 4-MUX operation. Groups of the LCD segment lines can be selected for digital output signals. The
MSP430x31x has four common signals and 23 segment lines. The MSP430C311S and MSP430P315S have
four common lines and 16 segment lines.
Timer/Port
The Timer/Port module has two 8-bit counters, an input that triggers one counter, and six digital outputs in the
MSP430x31x (MSP430C311S, MSP430C315S have five digital outputs available on external pins) with
high-impedance state capability. Both counters have an independent clock-selector for selecting an external
signal or one of the internal clocks (ACLK or MCLK). One counter has an extended control capability to halt,
count continuously, or gate the counter by selecting one of two external signals. This gate signal sets the
interrupt flag, if an external signal is selected, and the gate stops the counter.
Both timers can be read from and written to by software. The two 8-bit counters can be cascaded to a 16-bit
counter. A common interrupt vector is implemented. The interrupt flag can be set from three events in the 8-bit
counter mode (gate signal, overflow from the counters) or from two events in the 16-bit counter mode (gate
signal, overflow from the MSB of the cascaded counter).
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x31x
MIXED SIGNAL MICROCONTROLLERS
SLAS165D – FEBRUARY 1998 – REVISED APRIL 2000
peripherals (continued)
slope A/D conversion
Slope A/D conversion is accomplished with the timer/port module using external resistor(s) for reference (R ),
ref
external resistor(s) to the measured (R
), and an external capacitor. The external components are driven
meas
by software in such a way that the internal counter measures the time that is needed to charge or discharge
the capacitor. The reference resistor’s (R ) charge or discharge time is represented by N counts. The
ref
ref
unknown resistors (R
) charge or discharge time is represented by N
counts. The unknown resistor’s
meas
meas
value(R
)isthevalueofR multipliedbytherelativenumberofcounts(N
/N ).Thisvaluedetermines
meas
ref
meas ref
resistive sensor values that correspond to the physical data, for example temperature, when an NTC or PTC
resistor is used.
Basic Timer1
The Basic Timer1 (BT1) divides the frequency of MCLK or ACLK, as selected with the SSEL bit, to provide low
frequency control signals. This is done within the system by one central divider, the basic timer1, to support low
current applications. The BTCTL control register contains the flags which controls or selects the different
operational functions. When the supply voltage is applied or when a reset of the device (RST/NMI pin), a
watchdog overflow, or a watchdog security key violation occurs, all bits in the register hold undefined or
unchanged status. The user software usually configures the operational conditions on the BT1 during
initialization.
The Basic Timer1 has two 8 bit timers which can be cascaded to a 16 bit timer. Both timers can be read and
written by software. Two bits in the SFR address range handle the system control interaction according to the
function implemented in the Basic Timer1. These two bits are the Basic Timer1 interrupt flag (BTIFG) and the
basic timer interrupt enable (BTIE) bit.
Watchdog Timer
The primary function of the Watchdog Timer (WDT) module is to perform a controlled system restart after a
software problem has occurred. If the selected time interval expires, a system reset is generated. If this
watchdog function is not needed in an application, the module can work as an interval timer, which generates
an interrupt after the selected time interval.
The Watchdog Timer counter (WDTCNT) is a 15/16-bit up-counter which is not directly accessible by software.
The WDTCNT is controlled using the Watchdog Timer control register (WDTCTL), which is a 16-bit read/write
register. Writing to WDTCTL, in both operating modes (watchdog or timer) is only possible by using the correct
password in the high-byte. The low-byte stores data written to the WDTCTL. The high-byte password is 05Ah.
If any value other than 05Ah is written to the high-byte of the WDTCTL, a system reset PUC is generated. When
the password is read its value is 069h. This minimizes accidental write operations to the WDTCTL register. In
addition to the Watchdog Timer control bits, there are two bits included in the WDTCTL which configure the NMI
pin.
8-Bit Timer/Counter
The 8-bit interval timer supports three major functions for the application:
•
•
•
Serial communication or data exchange
Pulse counting or pulse accumulation
Timer
The 8-bit Timer/Counter peripheral includes the following major blocks: an 8-bit up-counter with
preload-register, an 8-bit control register, an input clock selector, an edge detection (e.g. start bit detection for
asynchronous protocols), and an input and output data latch, triggered by the carry-out-signal from the 8-bit
counter.
The 8-bit counter counts up with an input clock, which is selected by two control bits from the control register.
The four possible clock sources are MCLK, ACLK, the external signal from terminal P0.1, and the signal from
the logical AND of MCLK and terminal P0.1.
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x31x
MIXED SIGNAL MICROCONTROLLERS
SLAS165D – FEBRUARY 1998 – REVISED APRIL 2000
8-Bit Timer/Counter (continued)
Two counter inputs (load, enable) control the counter operation. The load input controls load operations. A
write-access to the counter results in loading the content of the preload-register into the counter. The software
writes or reads the preload-register with all instructions. The preload-register acts as a buffer and can be written
immediately after the load of the counter is completed. The enable input enables the count operation. When
the enable signal is set to high, the counter will count up each time a positive clock edge is applied to the clock
input of the counter.
Serial protocols, like UART protocol, need start-bit edge-detection to determine, at the receiver, the start of a
data transmission. When this function is activated, the counter starts counting after start-bit condition is
detected. The first signal level is sampled into the RXD input data-latch after completing the first timing interval,
which is programmed into the counter. Two latches used for input and output data (RXD_FF and TXD_FF) are
clocked by the counter after the programmed timing interval has elapsed.
UART
The serial communication is realized by using software and the 8-bit timer/counter hardware. The hardware
supports the output of the serial data stream, bit-by-bit, with the timing determined by the counter. The
software/hardware interface connects the mixed signal controller to external devices, systems, or networks.
peripheral file map
PERIPHERALS WITH WORD ACCESS
Watchdog
Watchdog Timer control
PERIPHERALS WITH BYTE ACCESS
EPROM control
WDTCTL
0120h
EPROM
EPCTL
CBCTL
054h
053h
Crystal buffer
System clock
Crystal buffer control
SCG frequency control
SCG frequency integrator
SCG frequency integrator
SCFQCTL 052h
SCFI1
SCFI0
051h
050h
Timer /Port
Timer/Port enable
Timer/Port data
Timer/Port counter2
Timer/Port counter1
Timer/Port control
TPE
TPD
TPCNT2
TPCNT1
TPCTL
04Fh
04Eh
04Dh
04Ch
04Bh
8-Bit Timer/Counter
Basic Timer1
LCD
8-Bit Timer/Counter data
8-Bit Timer/Counter preload
8-Bit Timer/Counter control
TCDAT
TCPLD
TCCTL
044h
043h
042h
Basic Timer/Counter2
Basic Timer/Counter1
Basic Timer control
BTCNT2
BTCNT1
BTCTL
047h
046h
040h
LCD memory 15
:
LCDM15
03Fh
LCD memory1
LCD control & mode
LCDM1
LCDCTL
031h
030h
Port P0
Port P0 interrupt enable
Port P0 interrupt edge select
Port P0 interrupt flag
Port P0 direction
Port P0 output
Port P0 input
P0IE
015h
014h
013h
012h
011h
010h
P0IES
P0IFG
P0DIR
P0OUT
P0IN
Special function
SFR interrupt flag2
SFR interrupt flag1
SFR interrupt enable2
SFR interrupt enable1
IFG2
IFG1
IE2
003h
002h
001h
000h
IE1
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x31x
MIXED SIGNAL MICROCONTROLLERS
SLAS165D – FEBRUARY 1998 – REVISED APRIL 2000
†
absolute maximum ratings
Voltage applied at V
to V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 6 V
SS
CC
Voltage applied to any pin (referenced to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to V
+0.3 V
SS
CC
Diode current at any device terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±2 mA
Storage temperature, T (unprogrammed device) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 150°C
stg
Storage temperature, T (programmed device) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 85°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE: All voltages referenced to V
.
SS
recommended operating conditions
MIN
2.5
2.7
2.7
2.7
4.5
NOM
MAX
5.5
5.5
5.5
5.5
5.5
UNIT
MSP430Cxxx
‡
‡
Supply voltage, V
MSP430P313 , PMS430E313
MSP430P315, PMS430E315
MSP430P313
V
CC
V
V
V
Supply voltage during programming, V
CC
MSP430P315
Supply voltage, V
0
SS
MSP430C31x
MSP430P31x
PMS430E31x
–40
85
Operating free-air temperature range, T
°C
A
25
XTAL frequency, f
(XTAL)
32 768
Hz
V
V
= 3 V
= 5 V
DC
DC
2.2
3.3
CC
Processor frequency f
(signal MCLK) f
MHz
(system)
system
CC
Low-level input voltage, V (excluding Xin, Xout)
V
V
+0.8
IL
SS
SS
V
V
High-level input voltage, V (excluding Xin, Xout)
IH
0.7×V
V
CC
CC
0.2×V
CC
V
CC
= 3 V/5 V
Low-level input voltage, V
V
SS
IL(Xin, Xout)
High-level input voltage, V
0.8×V
V
CC
IH(Xin, Xout)
CC
‡
MSP430P313/E313 not recommended for new designs – replaced by MSP430P315/E315.
f(MHz)
3.3
2.2
Minimum
3
5
5.5
V
CC
(V)
2.5
V
CC
– Supply Voltage – V
NOTE: Minimum processor frequency is defined by system clock.
Figure 1. Processor Frequency vs Supply Voltage, C Versions
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x31x
MIXED SIGNAL MICROCONTROLLERS
SLAS165D – FEBRUARY 1998 – REVISED APRIL 2000
f(MHz)
3.3
2.2
1.5
Minimum
2.7
3
5
5.5
V
CC
(V)
V
CC
– Supply Voltage – V
NOTE: Minimum processor frequency is defined by system clock.
Figure 2. Processor Frequency vs Supply Voltage, P/E Versions
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
supply current (into V ) excluding external current (f
CC
= 1 MHz)
(system)
PARAMETER
TEST CONDITIONS
MIN NOM
400
730
2100
7000
490
960
50
MAX
500
850
2700
8600
550
1050
70
UNIT
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 3 V
= 5 V
= 3 V
= 5 V
= 3 V
= 5 V
= 3 V
= 5 V
= 3 V
= 5 V
= 3 V
= 5 V
= 3 V
= 5 V
C31x
P313
T
= –40°C + 85°C
= –40°C + 85°C
= –40°C + 85°C
= –40°C + 85°C
= –40°C + 85°C
= –40°C + 85°C
= –40°C + 85°C
A
I
Active mode
T
A
µA
(AM)
P315(S)
C31x
T
A
T
A
100
70
130
85
P313
I
I
I
Low-power mode, (LPM0,1)
Low-power mode, (LPM2)
Low-power mode, (LPM3)
T
A
µA
µA
µA
(CPUOff)
(LPM2)
(LPM3)
150
50
170
70
P315(S)
T
A
100
6
130
12
T
A
13
25
T
A
= –40°C
= 25°C
= 85°C
= –40°C
= 25°C
= 85°C
= –40°C
= 25°C
= 85°C
1.5
2.4
2
T
A
V
= 3 V
1.3
CC
CC
T
A
1.6
2.8
7
T
A
5.2
T
A
V
= 5 V
4.2
6
T
A
4.8
5.4
0.8
0.8
1.3
T
A
0.1
I
Low-power mode, (LPM4)
T
A
V = 3 V/5 V
CC
0.1
µA
(LPM4)
T
A
0.4
†
MSP430P313/E313 not recommended for new designs – replaced by MSP430P315/E315.
NOTE: All inputs are tied to 0 V or V . Outputs do not source or sink any current. The current consumption in LPM2 and LPM3 are measured
CC
with active basic timer (ACLK selected) and LCD module. (f
= 1024 Hz, 4 mux)
LCD
16
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x31x
MIXED SIGNAL MICROCONTROLLERS
SLAS165D – FEBRUARY 1998 – REVISED APRIL 2000
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted) (continued)
current consumption of active mode versus system frequency, C versions only
I
= I
× f
[MHz]
system
AM
AM[1 MHz]
current consumption of active mode versus supply voltage, C versions only
= I + 200 µA/V × (V –3 V)
I
AM
AM[3 V]
CC
schmitt-trigger inputs port 0, Timer/Port, CIN, TP0.5
PARAMETER
TEST CONDITIONS
MIN NOM
MAX
2.1
3.4
1.35
2.3
1
UNIT
V
V
V
V
V
V
= 3 V
= 5 V
= 3 V
= 5 V
= 3 V
= 5 V
1.2
2.3
0.5
1.4
0.3
0.6
CC
CC
CC
CC
CC
CC
V
IT+
V
IT–
V
hys
Positive-going input threshold voltage
Negative-going input threshold voltage
V
V
V
Input hysteresis (V – V
)
IT+ IT–
1.4
standard inputs TCK, TMS, TDI, RST/NMI
PARAMETER
TEST CONDITIONS
= 3 V/5 V
MIN
NOM
MAX
V +0.8
SS
UNIT
V
V
Low-level input voltage
High-level input voltage
V
IL
SS
0.7V
V
V
CC
V
CC
IH
CC
outputs port 0, P0.x, Timer/Port, TP0.0 – 5, LCD: S2/O2 to S26/O26 XBUF:XBUF, JTAG:TDO
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX
UNIT
I
I
I
I
I
I
I
I
= –1.2 mA,
= –3.5 mA,
= –1.5 mA,
= –4.5 mA,
= 1.2 mA,
= 3.5 mA,
= 1.5 mA,
= 4.5 mA,
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 3 V,
= 3 V,
= 5 V,
= 5 V,
= 3 V,
= 3 V,
= 5 V,
= 5 V,
See Note 5
See Note 6
See Note 5
See Note 6
See Note 5
See Note 6
See Note 5
See Note 6
V
–0.4
V
V
V
V
OH
OH
OH
OH
OL
OL
OL
OL
CC
CC
CC
CC
CC
V
–1
CC
V
High-level output voltage
V
OH
OL
V
CC
–0.4
–1
V
CC
V
V
V
V
V
+0.4
SS
SS
V
SS
+1
SS
SS
SS
V
Low-level output voltage
V
V
+0.4
+1
SS
V
SS
NOTES: 5. Themaximumtotalcurrent, I
drop specified.
maxandI max, foralloutputscombined, shouldnotexceed±9.6mAtoholdthemaximumvoltage
OL
OH
6. Themaximum total current, I
drop specified.
max and I max, for all outputs combined, should not exceed ±20 mA to hold the maximum voltage
OL
OH
leakage current (see Note 7)
PARAMETER
TEST CONDITIONS
Timer/port:V CIN = V , V
MIN NOM
MAX
±50
±50
UNIT
nA
,
TP0.x, SS CC
I
I
High-impedance leakage current, timer/port
High-impedance leakage current, S27
lkg(TP)
V
CC
= 3 V/5 V, (see Note 8)
V
= V
to V
,
V
= 3 V/5 V
nA
lkg(S27)
S27
SS
CC
CC
CC
Port P0: P0.x, 0 ≤ × ≤ 7,
(see Note 9)
V
= 3 V/5 V,
I
Leakage current, port 0
±50
nA
lkg(P0x)
NOTES: 7. The leakage current is measured with V
SS
or V
applied to the corresponding pin(s), unless otherwise noted.
CC
8. Alltimer/portpinsTP0.0toTP0.5areHi-Z. PinsCINandTP.0toTP0.5areconnectedtogetherduringleakagecurrentmeasurement.
In the leakage measurement the input CIN is included. The input voltage is V or V
.
CC
SS
9. The port pin must be selected for input and there must be no optional pullup or pulldown resistor.
17
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x31x
MIXED SIGNAL MICROCONTROLLERS
SLAS165D – FEBRUARY 1998 – REVISED APRIL 2000
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted) (continued)
optional resistors, individually programmable with ROM code, P0.x, (see Note 10)
PARAMETER
TEST CONDITIONS
MIN NOM
MAX
6.2
9.3
18
UNIT
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
R
R
R
R
R
R
R
R
R
R
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 3 V/5 V
= 3 V/5 V
= 3 V/5 V
= 3 V/5 V
= 3 V/5 V
= 3 V/5 V
= 3 V/5 V
= 3 V/5 V
= 3 V/5 V
= 3 V/5 V
2.1
3.1
6
4.1
6.2
12
(opt1)
(opt2)
(opt3)
(opt4)
(opt5)
(opt6)
(opt7)
(opt8)
(opt9)
(opt10)
10
19
29
19
37
56
Resistors, individually programmable with ROM code, all port pins,
values applicable for pulldown and pullup
38
75
113
168
281
392
56
112
187
261
337
94
131
167
506
kΩ
NOTE 10: Optional resistors R
optx
for pull-down or pull-up are not programmed in standard OTP/EPROM devices P/E313 (MSP430P313/E313
not recommended for new designs – replaced by MSP430P315/E315) and P/E315(s)
inputs P0.x, CIN, TP.5; output XBUF
PARAMETER
TEST CONDITIONS
VCC
MIN NOM
MAX
UNIT
Port P0
t
External interrupt timing
External trigger signal for the
interrupt flag, (see Notes 11 and 12)
3 V/5 V
1.5
cycle
(int)
f
t
Input frequency
(IN)
(H)
(H)
3 V/5 V
DC
f
f
MHz
(system)
or t
or t
P0.x, CIN, TP.5
(L)
(L)
3 V
5 V
225
150
ns
ns
High level or low level time
Clock output frequency
t
f
XBUF,
XBUF,
C
C
= 20 pF
= 20 pF,
3 V/5 V
MHz
(XBUF)
L
L
(system)
f
f
f
= 1.1 MHz
3V/5V
3V/5V
3V/5V
40%
35%
50%
(MCLK)
t
Duty cycle of clock output frequency
(Xdc)
= f
(XBUF) (ACLK)
60%
65%
= f
(XBUF) (ACLK/n)
NOTES: 11. Theexternal signal sets the interrupt flag every time t is met. It may be set even with trigger signals shorter than t . The conditions
int int
to set the flag must be met independently from this timing constraint. T is defined in MCLK cycles.
int
12. The external interrupt signal cannot exceed the maximum inut frequency (f ).
(in)
crystal oscillator, Xin, Xout
PARAMETER
Integrated capacitance at input
Integrated capacitance at output
TEST CONDITIONS
MIN NOM
MAX
UNIT
pF
C
C
V
V
= 3 V/5 V
= 3 V/5 V
12
12
(Xin)
CC
pF
(Xout)
CC
18
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x31x
MIXED SIGNAL MICROCONTROLLERS
SLAS165D – FEBRUARY 1998 – REVISED APRIL 2000
electrical characteristics over recommended and operating free-air temperature range (unless
otherwise noted) (continued)
PARAMETER
TEST CONDITIONS
= 1A0h FN_4=FN_3=FN_2=0
MIN NOM
1
MAX
UNIT
f
DCO
N
N
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 3 V/5 V
= 3 V
= 5 V
= 3 V
= 5 V
= 3 V
= 5 V
= 3 V
= 5 V
= 3 V
= 5 V
= 3 V
= 5 V
= 3 V
= 5 V
= 3 V
= 5 V
MHz
(NOM)
DCO
DCO
0.15
0.18
1.25
1.45
0.36
0.39
2.5
0.6
0.62
4.7
f
f
f
f
f
f
f
f
= 00 0110 0000 FN_4=FN_3=FN_2=0
= 11 0100 0000 FN_4=FN_3=FN_2=0
= 00 0110 0000 FN_4=FN_3=0, FN_2=1
= 11 0100 0000 FN_4=FN_3=0, FN_2=1
= 00 0110 0000 FN_4=0, FN_3= 1, FN_2=X
= 11 0100 0000 FN_4= 0, FN_3=1, FN_2=X
= 00 0110 0000 FN_4 =1, FN_3=FN_2=X
= 11 0100 0000 FN_4=1, FN_3=FN_2=X
DCO3
DCO26
DCO3
DC26
f
MHz
MHz
MHz
MHz
(NOM)
N
N
N
N
N
N
N
DCO
DCO
DCO
DCO
DCO
DCO
DCO
5.5
1.05
1.2
2xf
3xf
4xf
(NOM)
(NOM)
(NOM)
8.1
3
9.9
0.5
1.5
DCO3
DCO26
DCO3
DCO26
0.6
1.8
3.7
11
4.5
13.8
1.85
2.4
0.7
0.8
4.8
13.3
17.7
6
N
S
f
= f
MCLK NOM
FN_4=FN_3=FN_2=0
NDCO
V
= 3 V/5 V
= 3 V/5 V
A0h 1A0h
1.07
340h
1.13
DCO
CC
CC
f
= S × f
V
NDCO+1
f
(DCO26)
4xf
NOM
f
(DCO26)
f
(DCO3)
Legend
3xf
NOM
f
(DCO26)
f
(DCO3)
2xf
f
NOM
Tolerance at Tap 26
f
(DCO26)
DCO Frequency
Adjusted by Bits
2 9–2 5 in SCFI1
f
(DCO3)
NOM
Tolerance at Tap 3
f
(DCO3)
FN_2 = 0
FN_3 = 0
FN_4 = 0
FN_2 = 1
FN_3 = 0
FN_4 = 0
FN_2 = X
FN_3 = 1
FN_4 = 0
FN_2 = X
FN_3 = X
FN_4 = 1
Figure 3
19
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x31x
MIXED SIGNAL MICROCONTROLLERS
SLAS165D – FEBRUARY 1998 – REVISED APRIL 2000
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
LCD
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX
UNIT
(V
–V )×
CC SS
2/3+V
V
V
Voltage at R23
Voltage at R13
V
= 3 V/5 V
= 3 V/5 V
V
23
CC
CC
SS
Analog voltage
(V
–V ) ×
CC SS
1/3+V
V
V
V
13
SS
V
V
I
Output 1 (HLCD)
Output 0 (LLCD)
I
I
<= 10 nA
<= 10 nA
V
CC
–0.125
V
O(HLCD)
(HLCD)
CC
+0.125
V
SS
V
SS
O(LLCD)
(LLCD)
V
CC
= 3 V/5 V
R13 = V
/3
Input leakage
(see Note 13)
I(R13)
I(R23)
CC
±20
nA
I
R23 = 2 V /3
CC
r
r
to S
to S
o(R13)
o(R23)
(XX)
(XX)
Output (SXX)
I
= –3 µA,
V
CC
= 3 V/5 V
33
kΩ
(SXX)
NOTE 13: I
is measured with no load on the segment or common LCD I/O pins.
(IRxx)
comparator (Timer/Port)
PARAMETER
TEST CONDITIONS
MIN
NOM
250
MAX
350
UNIT
µA
V
CC
V
CC
V
CC
V
CC
V
CC
= 3 V
I
Comparator (timer/port)
CPON = 1
CPON = 1
CPON = 1
(com)
= 5 V
450
600
V
Internal reference voltage at (–) terminal
Input hysteresis (comparator)
= 3 V/5 V
= 3 V
0.230×V
CC
0.25×V
0.260×V
37
V
ref(com)
CC
CC
5
V
mV
hys(com)
= 5 V
10
42
RAM
PARAMETER
TEST CONDITIONS
MIN NOM
MAX
UNIT
V
CPU halted (see Note 14)
1.8
V
RAMh
NOTE 14: This parameter defines the minimum supply voltage when the data in the program memory RAM remains unchanged. No program
execution should happen during this supply voltage condition.
PUC/POR
PARAMETER
TEST CONDITIONS
MIN NOM
MAX
UNIT
t
150
250
µs
(POR_delay)
T
= –40°C
= 25°C
= 85°C
1.5
1.2
0.9
0
2.4
2.1
1.8
0.4
V
V
A
V
POR
T
A
(POR)
V
CC
= 3 V/5 V
T
A
V
V
(min)
V
t
PUC/POR
Reset is accepted internally
2
µs
(reset)
20
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x31x
MIXED SIGNAL MICROCONTROLLERS
SLAS165D – FEBRUARY 1998 – REVISED APRIL 2000
V
VCC
V
(POR)
No POR
POR
POR
V
(min)
t
Figure 4. Power-On Reset (POR) vs Supply Voltage
3
2.4
1.5
2.5
2.1
1.8
0.9
2
1.5
1
1.2
0.5
0
25°C
–40
–20
0
20
40
60
80
Temperature [°C]
Figure 5. V
vs Temperature
(POR)
wakeup from LPM3
PARAMETER
TEST CONDITIONS
MIN NOM
MAX
UNIT
V
CC
V
CC
V
CC
V
CC
V
CC
= 3 V
= 5 V
= 3 V
= 5 V
= 5 V
f = 1 MHz
6
t
Delay time
µs
(LPM3)
f = 2 MHz
f = 3 MHz
6
6
21
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x31x
MIXED SIGNAL MICROCONTROLLERS
SLAS165D – FEBRUARY 1998 – REVISED APRIL 2000
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
JTAG, program memory
PARAMETER
TEST CONDITIONS
MIN NOM
MAX
5
UNIT
V
V
= 3 V
= 5 V
DC
DC
CC
f
TCK frequency
MHz
(TCK)
10
CC
JTAG/Test
Pullup resistors on TMS, TCK, TDI
(see Note 15)
R
V
V
CC
V
CC
V
CC
= 3 V/ 5 V
= 3 V/ 5 V
= 3 V/ 5 V
25
5.5
11
60
90
6
kΩ
(TEST)
Fuse blow voltage, C versions (see Note 15)
V
Fuse blow voltage, E/P versions
(see Note 17)
(FB)
12
JTAG/Fuse (see Note 16)
I
t
Supply current on TDI/VPP to blow fuse
Time to blow the fuse
100
1
mA
ms
V
(FB)
(FB)
P313, E313
Programming voltage, applied to TDI/VPP
Programming voltage, applied to TDI/VPP
Current from programming voltage source
Programming time, single pulse
11
12
11.5
12.5
13
13
70
V
(PP)
P315(S), E315
V
I
t
t
mA
ms
µs
(PP)
(pps)
(ppf)
EPROM (E) and OTP(P) –
versions only
(see Note 18)
5
Programming time, fast algorithm
100
P
Pulses for successful programming
Erase time wave length 2537 Å at 15 Ws/cm
4
100 Pulses
n
2
t
30
min
(erase)
2
(UV lamp of 12 mW/ cm )
EPROM (E)
Write/erase cycles
1000
10
cycles
years
Data retention T < 55°C
J
NOTES: 15. The TMS and TCK pullup resistors are implemented in all ROM(C) and EPROM(E) versions.
16. Once the JTAG fuse is blown no further access to the MSP430 JTAG/test feature is possible.
17. The voltage supply to blow the JTAG fuse is applied to TDI/VPP pin when fuse blowing is desired.
18. Refer to the Recommended Operating Conditions for the correct V during programing.
CC
22
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x31x
MIXED SIGNAL MICROCONTROLLERS
SLAS165D – FEBRUARY 1998 – REVISED APRIL 2000
TYPICAL CHARACTERISTICS
JTAG fuse check mode
MSP430 devices that have the fuse on the TDI/VPP terminal have a fuse check mode that tests the continuity
of the fuse the first time the JTAG port is accessed after a power-on reset (POR). When activated, a fuse check
current, I , of 1 mA at 3 V, 2.5 mA at 5 V can flow from the TDI/VPP pin to ground if the fuse is not burned.
TF
Care must be taken to avoid accidentally activating the fuse check mode and increasing overall system power
consumption.
Activation of the fuse check mode occurs with the first negative edge on the TMS pin, after power up, or if the
TMS is being held low after power-up. The second positive edge on the TMS pin deactivates the fuse check
mode. After deactivation, the fuse check mode remains inactive until another POR occurs. After each POR the
fuse check mode has the potential to be activated.
Time TMS Goes Low After POR
TMS
I
TF
I
TDI
Figure 6. Fuse Check Mode Current, MSP430P/E313,P/E315,C31x
Care must be taken to avoid accidentally activating the fuse check mode, including guarding against EMI/ESD
spikes that could cause signal edges on the TMS pin.
Configuration of TMS, TCK, TDI/VPP and TDO/TDI pins in applications.
C3xx
Open
Open
Open
Open
P/E3xx
68k, pulldown
68k, pulldown
Open
TDI
TDO
TMS
TCK
Open
23
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x31x
MIXED SIGNAL MICROCONTROLLERS
SLAS165D – FEBRUARY 1998 – REVISED APRIL 2000
TYPICAL CHARACTERISTICS
DIGITAL CONTROLLED OSCILLATOR FREQUENCY
DIGITAL CONTROLLED OSCILLATOR FREQUENCY
vs
SUPPLY VOLTAGE
1.2
vs
OPERATING FREE-AIR TEMPERATURE
1.8
1.5
1.2
0.9
1
0.8
0.6
0.4
0.6
0.2
0
0.3
0
0
2
4
6
–40
–20
0
20
40
60
80
90
V
– Supply Voltage – V
CC
T – Operating Free-Air Temperature – °C
Figure 7
Figure 8
24
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x31x
MIXED SIGNAL MICROCONTROLLERS
SLAS165D – FEBRUARY 1998 – REVISED APRIL 2000
TYPICAL CHARACTERISTICS
typical input/output schematics
V
CC
V
CC
(see Note A)
(see Note A)
(see Note B)
(see Note B)
(see Note B)
(see Note B)
(see Note A)
GND
(see Note A)
GND
CMOS INPUT (RST/NMI)
CMOS SCHMITT-TRIGGER INPUT (CIN)
V
CC
(see Note A)
(see Note B)
(see Note B)
(see Note A)
GND
I/O WITH SCHMITT-TRIGGER INPUT (P0.x,
TP0.5)
CMOS 3-STATE OUTPUT
(TP0.0–4, XBUF)
TDO_Internal
V
CC
TDO_Control
TDI_Control
60 k TYP
TDI_Internal
MSP430C31x: TMS, TCK
MSP430P/E31x: TMS, TCK
MSP430C31x: TDO/TDI
MSP430P/E31x: TDO/TDI
NOTES: A. Optional selection of pull-up or pull-down resistors with ROM (masked) versions.
B. Fuses for the optional pull-up and pull-down resistors can only be programmed at the factory.
25
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x31x
MIXED SIGNAL MICROCONTROLLERS
SLAS165D – FEBRUARY 1998 – REVISED APRIL 2000
TYPICAL CHARACTERISTICS
typical input/output schematics
VC
VD
COM0–3
Control COM0–3
VA
S0, S1
VB
Segment control
VA
VB
S2/O2–Sn/On
Segment control
LCDCTL (LCDM5,6,7)
Data (LCD RAM bits 0–3
or bits 4–7)
LCD OUTPUT (COM0–4, Sn, Sn/On)
NOTE: The signals VA, VB, VC, and VD come from the LCD module analog voltage generator.
VPP_ Internal
TDI_ Internal
TDI/VPP
JTAG
Fuse
TDO/TDI_Control
TDO_ Internal
TDO/TDI
TMS
JTAG Fuse
Blow
Control
From/To JTAG_CBT_SIG_REG
NOTES: A. During programming activity and when blowing the JTAG enable fuse, the TDI/VPP terminal is used to apply the correct voltage
source. The TDO/TDI terminal is used to apply the test input data for JTAG circuitry.
B. The TDI/VPP terminal of the ’P31x and ’E31x does not have an internal pullup resistor. An external pulldown resistor is
recommended to avoid a floating node, which could increase the current consumption of the device.
C. The TDO/TDI terminal is in a high-impedance state after POR. The ’P31x and ’E31x need a pullup or a pulldown resistor to avoid
floating a node, which could increase the current consumption of the device.
Figure 9. MSP430P313/E313/P315(S)/E315: TDI/VPP, TDO/TDI
26
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x31x
MIXED SIGNAL MICROCONTROLLERS
SLAS165D – FEBRUARY 1998 – REVISED APRIL 2000
MECHANICAL DATA
DL (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48-PIN SHOWN
0.025 (0,635)
48
0.012 (0,305)
0.008 (0,203)
0.005 (0,13)
M
25
0.006 (0,15) NOM
0.299 (7,59)
0.291 (7,39)
0.420 (10,67)
0.395 (10,03)
Gage Plane
0.010 (0,25)
0°–8°
1
24
0.040 (1,02)
0.020 (0,51)
A
Seating Plane
0.004 (0,10)
0.008 (0,20) MIN
PINS **
0.110 (2,79) MAX
28
48
0.630
56
DIM
0.380
(9,65)
0.730
A MAX
A MIN
(16,00) (18,54)
0.370
(9,40)
0.620
0.720
(15,75) (18,29)
4040048/D 08/97
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
D. Falls within JEDEC MO-118
27
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x31x
MIXED SIGNAL MICROCONTROLLERS
SLAS165D – FEBRUARY 1998 – REVISED APRIL 2000
†
PMS430E313 , PMS430E315 (FZ package)
FZ PACKAGE
(TOP VIEW)
9
8
7
6
5
4
3
2
1 68 67 66 65 64 63 62 61
60 NC
NC
NC
10
11
12
13
14
15
16
17
59
S23/O23
S22/O22
S18/O18
S17/O17
S16/O16
S15/O15
S14/O14
S13/O13
S12/O12
S11/O11
S10/O10
S9/O9
V
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
CC
R23
R13
Xin
Xout/TCLK
P0.0
P0.1/RXD 18
19
20
21
22
23
24
25
26
P0.2/TXD
P0.3
P0.4
P0.5
P0.6
S8/O8
P0.7
S7/O7
TP0.0
NC
NC
NC
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
NC – No internal connection
†
MSP430P313/E313 not recommended for new designs – replaced by MSP430P315/E315.
28
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MSP430x31x
MIXED SIGNAL MICROCONTROLLERS
SLAS165D – FEBRUARY 1998 – REVISED APRIL 2000
MECHANICAL DATA
FZ (S-CQCC-J**)
J-LEADED CERAMIC CHIP CARRIER
28 LEAD SHOWN
0.040 (1,02)
45°
Seating Plane
0.180 (4,57)
0.155 (3,94)
0.140 (3,55)
0.120 (3,05)
A
B
1
4
26
25
5
0.050 (1,27)
C
(at Seating
Plane)
A
B
0.032 (0,81)
0.026 (0,66)
0.020 (0,51)
0.014 (0,36)
19
11
18
12
0.025 (0,64) R TYP
0.040 (1,02) MIN
0.120 (3,05)
0.090 (2,29)
A
B
C
JEDEC
NO. OF
PINS**
OUTLINE
MIN
MAX
MIN
MAX
MIN
MAX
0.485
0.495
0.430
0.455
0.410
0.430
MO-087AA
MO-087AB
MO-087AC
MO-087AD
28
44
52
68
(12,32)
(12,57)
(10,92)
(11,56)
(10,41)
(10,92)
0.685
0.695
0.630
0.655
0.610
0.630
(17,40)
(17,65)
(16,00)
(16,64)
(15,49)
(16,00)
0.785
0.795
0.730
0.765
0.680
0.740
(19,94)
(20,19)
(18,54)
(19,43)
(17,28)
(18,79)
0.985
0.995
0.930
0.955
0.910
0.930
(25,02)
(25,27)
(23,62)
(24,26)
(23,11)
(23,62)
4040219/B 03/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
29
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