LP39542RLX/NOPB_技术文档

LP39542

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SNVS503B –APRIL 2007–REVISED MAY 2013

Advanced Lighting Management Unit

Check for Samples: LP39542

1

FEATURES

APPLICATIONS

2

•

Audio Synchronization for Color/RGB LEDs

•

Cellular Phones

PDAs, MP3 players

Command-Based PWM-Controlled RGB LED

Drivers

DESCRIPTION

•

Programmable ON/OFF Blinking Sequences

for RGB LED

LP39542 is an advanced lighting management unit

for handheld devices. It drives any phone lights

including display backlights, RGB, keypad and

camera flash LEDs. The boost DC-DC converter

drives high current loads with high efficiency. White

LED backlight drivers are high efficiency low voltage

structures with excellent matching and automatic fade

in/ fade out function. The stand-alone command

based RGB controller is feature rich and easy to

configure. Built-in audio synchronization feature

allows user to synchronize the color LEDs to audio

input. Integrated high current driver can drive camera

flash LED or motor/vibra. Internal ADC can be used

for ambient light or temperature sensing. The flexible

I²C interface allows easy control of LP39542. Small

DSBGA package together with minimum number of

external components is a best fit for handheld

devices.

High-Current Driver for Flash LED With Built-In

Timing and Safety Feature

4+2 or 6 Low-Voltage Constant-Current White

LED Drivers With Programmable 8-Bit

Adjustment (0...25 mA/LED)

•

High-Efficiency Boost DC-DC Converter

I²C Compatible Interface

Possibility for External PWM Dimming Control

Possibility for Clock Synchronization for RGB

Timing

•

Ambient Light and Temperature Sensing

Possibility

Small package – DSBGA-36, 3.0x3.0x0.6mm

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2

All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

LP39542

SNVS503B –APRIL 2007–REVISED MAY 2013

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Typical Applications

D1

L1 4.7 mH

SW

I

MAX

= 400 mA

= 4...5.3V

C

OUT

IN

VDD

10 mF

V

10 mF

100 nF

OUT

-

FB

V

DD1

C

VDDA

BATTERY

DD2

WLED1

WLED2

WLED3

WLED4

1 éF

V

DDA

MAIN

BACKLIGHT

0...25 mA/LED

C

REF

V

REF

100 nF

R

RGB

IRGB

IRT

R

RT

FLASH

R

SUB

BACKLIGHT

0...25 mA/LED

WLED5

WLED6

IFLASH

ADDR_SEL

NRST

SCL

LP39542

R1

G1

B1

SDA

SYNC/PWM

RGB1

Up to 40 mA/LED

MCU

V

DDIO

C

VDDIO

100 nF

R2

FLASH_EN

ASE

CAMERA

RGB2

Up to 40 mA/LED

G2

B2

TEMP SENSOR

or

LIGHT

SENSOR

FLASH

Up to 400 mA

FLASH

or

AUDIO INPUT

GNDs

2

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SNVS503B –APRIL 2007–REVISED MAY 2013

Connection Diagrams

DSBGA-36 Package, 3.0 x 3.0 x 0.6 mm, 0.5 mm pitch, Package Number YZR0036 or

DSBGA-36 Package, 3.0 x 3.0 x 0.65 mm, 0.5 mm pitch, Package Number YPG0036

6

5

4

3

2

1

SW

FB

FLASH

R1

G1

B1

G1

R1

FLASH

FB

SW

6

5

4

3

2

1

GND_

SW

GND_

RGB

GND_

RGB

GND_

SW

GND

SDA

IRGB

NRST

SCL

V

DDIO

IRGB

NRST

SCL

SDA

GND

V

DDIO

GND_

WLED

SYNC_

PWM

ADDR_

SEL

ADDR_

SEL

SYNC_

PWM

GND_

WLED

IFLASH

R2

G2

B2

R2

G2

B2

IFLASH

WLED

5

WLED

6

FLASH

_EN

FLASH

_EN

WLED

6

WLED

5

V

DD1

V

DD1

WLED

3

WLED

4

WLED

4

WLED

3

ASE

IRT

GNDT

IRT

ASE

WLED

1

WLED

2

WLED

2

WLED

1

GNDA

V

REF

V

DDA

V

DD2

GNDA

V

REF

DD2

DDA

F

E

D

C

B

A

B

C

D

E

F

TOP VIEW

BOTTOM VIEW

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SNVS503B –APRIL 2007–REVISED MAY 2013

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PIN DESCRIPTIONS

Pin No.

6F

Name

SW

Type

Output

Description

Boost Converter Power Switch

Boost Converter Feedback

High Current Flash Output

Red LED 1 Output

6E

6D

6C

6B

6A

5F

FB

Input

FLASH

R1

Output

G1

Output

Green LED 1 Output

Blue LED 1 Output

B1

Output

GND_SW

GND

Ground

Power

Power Switch Ground

Ground

5E

5D

5C

5B

5A

4F

V_DDIO

Supply Voltage for Logic Input/Output Buffers and Drivers

Serial Data In/Out (I²C)

Bias Current Set Resistor for RGB Drivers

Ground for RGB Currents

Ground for WLED Currents

High Current Flash Current Set Resistor

External PWM Control for LEDs or External Clock for RGB Sync

Address Select (I²C)

SDA

Logic Input/Output

Input

IRGB

GND_RGB

GND_WLED

IFLASH

SYNC_PWM

ADDR_SEL

NRST

R2

Ground

Input

4E

4D

4C

4B

4A

3F

Logic Input

Output

Reset Pin

Red LED 2 Output

WLED5

WLED6

V_DD1

Output

White LED 5 Output

3E

3D

3C

3B

3A

2F

Output

White LED 6 Output

Power

Supply Voltage

FLASH_EN

SCL

Logic Input

Output

Enable for High Current Flash

Clock (I²C)

G2

Green LED 2 Output

WLED3

WLED4

ASE

Output

White LED 3 Output

2E

2D

2C

2B

2A

1F

Output

White LED 4 Output

Input

Audio Synchronization Input

Oscillator Frequency Resistor

Ground

IRT

Input

GNDT

B2

Ground

Output

Blue LED 2 Output

WLED1

WLED2

GNDA

VREF

V_DDA

Output

White LED 1 Output

1E

1D

1C

1B

1A

Output

White LED 2 Output

Ground

Output

Ground for Analog Circuitry

Reference Voltage

Power

Internal LDO Output

V_DD2

Power

Supply Voltage

4

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SNVS503B –APRIL 2007–REVISED MAY 2013

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

Absolute Maximum Ratings^{(1) (2)(3)}

V (SW, FB, R1-2, G1-2, B1-2, FLASH, WLED1-6)^{(4) (5)}

-0.3V to +7.2V

V_DD1, V_DD2, V_DDIO, V_DDA

-0.3V to +6.0V

Voltage on ASE, IRT, IFLASH, IRGB, VREF

Voltage on Logic Pins

-0.3V to V_DD1+0.3V with 6.0V max

-0.3V to V_DDIO+0.3V with 6.0V max

V(all other pins): Voltage to GND

-0.3V to 6.0V

10 μA

I (V_REF

)

I(R1, G1, B1, R2, G2, B2)

I(FLASH)⁽⁶⁾

100 mA

400 mA

Continuous Power Dissipation⁽⁷⁾

Internally Limited

150°C

Junction Temperature (T_J-MAX

Storage Temperature Range

)

-65°C to +150°C

260°C

(8)

Maximum Lead Temperature (Soldering)

ESD Rating

Human Body Model⁽⁹⁾

2 kV

(1) Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under

which operation of the device is ensured. Operating Ratings do not imply performance limits. For performance limits and associated test

conditions, see the Electrical Characteristics tables.

(2) All voltages are with respect to the potential at the GND pins.

(3) If Military/Aerospace specified devices are required, please contact the TI Sales Office/Distributors for availability and specifications.

(4) Battery/Charger voltage should be above 6V no more than 10% of the operational lifetime.

(5) Voltage tolerance of LP39542 above 6.0V relies on fact that V_DD1and V_DD2(2.8V) are available (ON) at all conditions. If V_DD1and V_DD2

are not available (ON) at all conditions, Texas Instuments does not ensure any parameters or reliability for this device.

(6) The total load current of the boost converter in worst-case conditions is limited to 300 mA (min. input and max. output voltage).

(7) Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at T_J=160°C (typ.) and

disengages at T_J=140°C (typ.).

(8) For detailed soldering specifications and information, see Application Note AN-1112 : DSBGA Wafer Level Chip Scale Package

SNVA009or Application Note AN-1412: Micro DSBGA Wafer Lever Chip Scale Package SNVA131

(9) The Human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin.

(1) (2)

Operating Ratings

V (SW, FB, WLED1-6, R1-2, G1-2, B1-2, FLASH)

V_DD1,2with external LDO

V_DD1,2with internal LDO

V_DDA

0 to 6.0V

2.7 to 5.5V

3.0 to 5.5V

2.7 to 2.9V

V_DDIO

1.65V to V_DD1

0.1V to V_DDA–0.1V

0 mA to 400 mA

-30°C to +125°C

-30°C to +85°C

Voltage on ASE

Recommended Load Current

Junction Temperature (T_J)

Ambient Temperature (T_A)⁽³⁾

(1) Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under

which operation of the device is ensured. Operating Ratings do not imply performance limits. For performance limits and associated test

conditions, see the Electrical Characteristics tables.

(2) All voltages are with respect to the potential at the GND pins.

(3) In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may

have to be derated. Maximum ambient temperature (T_A-MAX) is dependent on the maximum operating junction temperature (T_J-MAX-OP

=

125°C), the maximum power dissipation of the device in the application (P_D-MAX), and the junction-to ambient thermal resistance of the

part/package in the application (θ_JA), as given by the following equation: T_A-MAX= T_J-MAX-OP– (θ_JA× P_D-MAX).

Thermal Properties

Junction-to-Ambient Thermal Resistance(θ_JA

(1)

)

60°C/W

(1) Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power

dissipation exists, special care must be paid to thermal dissipation issues in board design.

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(1) (2)

Electrical Characteristics

Limits in standard typeface are for T_J= 25°C. Limits in boldface type apply over the operating ambient temperature range (-

30°C < T_A< +85°C). Unless otherwise noted, specifications apply to the LP39542 Block Diagram with: V_DD1= V_DD2= 3.6V,

V_DDIO= 2.8V, C_VDD= C_VDDIO= 100 nF, C_OUT= C_IN= 10 μF, C_VDDA= 1 μF, C_REF= 100 nF, L₁= 4.7 μH, R_FLASH= 910Ω, R_RGB

=

(3)

5.6 kΩ and R_RT= 82 kΩ

.

Symbol

Parameter

Test Conditions

Min

Typ

Max

8

Unit

I_VDD

Standby supply current

NSTBY (bit) = L, NRST (pin) = H

SCL=H, SDA = H

1

μA

(V_DD1+ V_DD2

No-boost supply current

(V_DD1+ V_DD2

)

NSTBY (bit) = H,

450

μA

)

EN_BOOST(bit) = L

SCL = H, SDA = H

Audio sync and LEDs OFF

No-load supply current

NSTBY (bit) = H,

1

mA

(V_DD1+ V_DD2

)

EN_BOOST (bit) = H

SCL = H, SDA = H

Audio sync and LEDs OFF

Autoload OFF

RGB drivers

(V_DD1+ V_DD2

CC mode at R1, G1, B1 and R2, G2, B2 set to 15 mA

SW mode

150

500

μA

)

WLED drivers

(V_DD1+ V_DD2

4+2 banks I_OUT= 25.5 mA per LED

)

Audio synchronization

Audio sync ON

V_DD1,2= 2.8V

V_DD1,2= 3.6V

(V_DD1+ V_DD2

)

390

700

2

μA

Flash

(V_DD1+ V_DD2

I(R_FLASH) = 1 mA

Peak current during flash

mA

μA

)

I_VDDIO

I_{EXT_LDO}

V_DDA

V_DDIOstandby supply current

NSTBY (bit)=L

1

SCL = H, SDA = H

External LDO output current

7V tolerant application only

I_BOOST= 300 mA

6.5

mA

(V_DD1, V_DD2, V_DDA

)

(4)

Output voltage of internal LDO

for analog parts

See

2.72

-3

2.80

2.88

+3

V

%

(1) All voltages are with respect to the potential at the GND pins.

(2) Min and Max limits are specified by design, test, or statistical analysis. Typical numbers represent the most likely norm.

(3) Low-ESR Surface-Mount Ceramic Capacitors (MLCCs) used in setting electrical characteristics.

(4) V_DDAoutput is not recommended for external use.

6

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SNVS503B –APRIL 2007–REVISED MAY 2013

BLOCK DIAGRAM

L1

4.7 µH

I

= 400 mA

= 4...5.3 V

MAX

D1

V

OUT

C

OUT

10 µF

SW

FB

V

DD1

DD2

C

VDD

IN

10 µF 100 nF

Logic supply

LDO

BG

PWM

Li-Ion

Battery

Or

V

DDA

POR

GND_SW

WLED1

Charger

V

REF

BOOST

THSD

OSC

REF

C

VDDA

REF

100 nF

IRGB

8-Bit

IDAC

1 µF

WLED2

WLED3

WLED4

MAIN

BACKLIGHT

0...25 mA/LED

BIAS

D

A

IRT

GND_WLED

R

RGB

R

RT

8-Bit

IDAC

WLED5

WLED6

SUB

BACKLIGHT

0...25 mA/LED

D

A

CONTROL

NRST

ADDR_SEL

SCL

MCU

SDA

I2C

SYNC/PWM

R1

G1

B1

V

DDIO

RGB1

Up to

40 mA/LED

C

VDDIO

100 nF

COMMAND

BASED

PATTERN

R2

GENERATOR

RGB2

Up to

40 mA/LED

SINGLE ENDED

ANALOG

G2

B2

AUDIO

ASE

AUDIO SYNC

GND_RGB

FLASH

Up to 400 mA

FCLTASH

CRTLRL

EN_FLASH

FLASH

LOGIC

CAMERA

IFLASH

GNDA

GND

GNDT

R

FLASH

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DETAILED DESCRIPTION

Modes of Operation

RESET: In the RESET mode all the internal registers are reset to the default values and the chip goes to

STANDBY mode after reset. NSTBY control bit is low after reset by default. Reset is active always if

NRST input pin is low or internal Power On Reset is active. LP39542 can be also reset by writing any data

to Reset Register in address 60H. Power On Reset (POR) will activate during the chip startup or when the

supply voltage V_DD2falls below 1.5V. Once V_DD2rises above 1.5V, POR will inactivate and the chip will

continue to the STANDBY mode.

STANDBY: The STANDBY mode is entered if the register bit NSTBY is LOW. This is the low power

consumption mode, when all circuit functions are disabled. Registers can be written in this mode and the

control bits are effective immediately after power up.

STARTUP: When NSTBY bit is written high, the INTERNAL STARTUP SEQUENCE powers up all the needed

internal blocks (Vref, Bias, Oscillator etc..). To ensure the correct oscillator initialization, a 10 ms delay is

generated by the internal state-machine. If the chip temperature rises too high, the Thermal Shutdown

(TSD) disables the chip operation and STARTUP mode is entered until no thermal shutdown event is

present.

BOOST STARTUP:Soft start for boost output is generated in the BOOST STARTUP mode. The boost output is

raised in PFM mode during the 10 ms delay generated by the state-machine. The Boost startup is entered

from Internal Startup Sequence if EN_BOOST is HIGH or from Normal mode when EN_BOOST is written

HIGH. During the 10 ms Boost Startup time all LED outputs are switched off to ensure smooth start-up.

NORMAL: During NORMAL mode the user controls the chip using the Control Registers. The registers can be

written in any sequence and any number of bits can be altered in a register in one write

RESET

2

I C reset or NRST = L

NSTBY (bit) = L and

NRST = H

or POR = H

STANDBY

NSTBY (bit) = L and

NRST = H

NSTBY (bit) = H and

NRST = H

INTERNAL

STARTUP

SEQUENCE

V

REF

= 95% OK*

TSD = H

~10 ms Delay

EN_BOOST (bit) = H*

EN_BOOST (bit) = L*

BOOST STARTUP

~10 ms Delay

EN_BOOST (bit)

rising edge*

NORMAL MODE

* TSD = L

8

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SNVS503B –APRIL 2007–REVISED MAY 2013

Magnetic Boost DC/DC Converter

The LP39542 Boost DC/DC Converter generates a 4.0 – 5.3V voltage for the LEDs from single Li-Ion battery

(3V…4.5V). The output voltage is controlled with an 8-bit register in 9 steps. The converter is a magnetic

switching PWM mode DC/DC converter with a current limit. The converter has three options for switching

frequency, 1 MHz, 1.67 MHz and 2 MHz (default), when timing resistor RT is 82 kΩ. Timing resistor defines the

internal oscillator frequency and thus directly affects boost frequency and all circuit's internally generated timing

(RGB, Flash, WLED fading).

The LP39542 Boost Converter uses pulse-skipping elimination to stabilize the noise spectrum. Even with light

load or no load a minimum length current pulse is fed to the inductor. An active load is used to remove the

excess charge from the output capacitor at very light loads. At very light load and when input and output voltages

are very close to each other, the pulse skipping is not completely eliminated. Output voltage should be at least

0.5V higher than input voltage to avoid pulse skipping. Reducing the switching frequency will also reduce the

required voltage difference.

Active load can be disabled with the en_autoload bit. Disabling will increase the efficiency at light loads, but the

downside is that pulse skipping will occur. The Boost Converter should be stopped when there is no load to

minimise the current consumption.

The topology of the magnetic boost converter is called CPM control, current programmed mode, where the

inductor current is measured and controlled with the feedback. The user can program the output voltage of the

boost converter. The output voltage control changes the resistor divider in the feedback loop.

Figure 1 shows the boost topology with the protection circuitry. Four different protection schemes are

implemented:

1. Over voltage protection, limits the maximum output voltage

–

Keeps the output below breakdown voltage.

Prevents boost operation if battery voltage is much higher than desired output.

2. Over current protection, limits the maximum inductor current

Voltage over switching NMOS is monitored; too high voltages turn the switch off.

–

3. Feedback break protection. Prevents uncontrolled operation if FB pin gets disconnected.

4. Duty cycle limiting, done with digital control.

V

OUT

2 MHz clock

Duty control

IN

SW

FBNCCOMP

FB

+

-

R

S

R

OVPCOMP

SWITCH

+

-

RESETCOMP

+

-

+

R

ERRORAMP

ACTIVE

LOAD

+

-

R

+

-

LOOPC

OLPCOMP

SLOPER

Figure 1. Boost Converter Topology

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Magnetic Boost DC/DC Converter Electrical Characteristics

Symbol

I_LOAD

Parameter

Test Conditions

3.0V ≤ V_IN

V_OUT= 5V

Min

Typ

Max

Unit

Load Current

0

300

mA

3.0V ≤ V_IN

V_OUT= 4V

0

400

V_OUT

Output Voltage Accuracy (FB Pin)

Output Voltage (FB Pin)

3.0V ≤ V_IN≤ V_OUT- 0.5

V_OUT= 5.0V

−5

+5

%

1 mA ≤ I_LOAD≤ 300 mA

V_IN> 5V + V_(SCHOTTKY)

V_IN–V_(SCHOTTKY)

V

Ω

RDS_ON

f_boost

Switch ON Resistance

V_DD1,2= 2.8V, I_SW= 0.5A

0.4

2

0.8

PWM Mode Switching Frequency

RT = 82 kΩ

freq_sel[2:0] = 1XX

MHz

Frequency Accuracy

2.7 ≤ VDDA ≤ 2.9

RT = 82 kΩ

−6

−9

±3

+6

%

+9

t_PULSE

Switch Pulse Minimum Width

Startup Time

no load

25

10

ns

t_STARTUP

I_{SW_MAX}

Boost startup from STANDBY

ms

SW Pin Current Limit

700

800

900

mA

550

950

BOOST STANDBY MODE

User can stop the Boost Converter operation by writing the Enables register bit EN_BOOST low. When

EN_BOOST is written high, the converter starts for 10 ms in PFM mode and then goes to PWM mode.

BOOST OUTPUT VOLTAGE CONTROL

User can control the boost output voltage by boost output 8-bit register.

Boost Output [7:0]

Register 0DH

Boost Output

Voltage (typical)

Bin

Hex

00

01

03

07

0F

1F

3F

7F

FF

0000 0000

0000 0001

0000 0011

0000 0111

0000 1111

0001 1111

0011 1111

0111 1111

1111 1111

4.00

4.25

4.40

4.55

4.70

4.85

5.00 Default

5.15

5.30

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Figure 2. Boost Output Voltage Control

5.4

5.2

5.0

4.8

4.6

4.4

V

IN

=3.6V

4.2

4.0

I

= 50mA

LOAD

Control= 00»FF»00

0

0.2 0.4 0.6 0.8 1.0 1.2 1.4

TIME( 200ms/ DIV)

BOOST FREQUENCY CONTROL

freq_sel[2:0]⁽¹⁾

frequency

1XX

01X

001

2.00 MHz

1.67 MHz

1.00 MHz

(1) Register ‘boost freq’ (address 0EH). Register default value after reset is 07H.

Boost Converter Typical Performance Characteristics

Vin = 3.6V, Vout = 5.0V if not otherwise stated

Boost Converter Efficiency

Boost Typical Waveforms at 100mA Load

TIME (200 ns/DIV)

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Vin = 3.6V, Vout = 5.0V if not otherwise stated

Battery Current vs Voltage

Boost Startup with No Load

Boost Switching Frequency

Boost Line Regulation

Boost Load Transient, 50 mA–100 mA

12

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Vin = 3.6V, Vout = 5.0V if not otherwise stated

Output Voltage vs Load Current

Efficiency at Low Load vs Autoload

90

80

70

60

50

40

30

20

5.2

5.0

4.8

4.6

V

= 3V

IN

4.4

4.2

4.0

3.8

3.6

f = 2 MHz

L - TDK VLF0410 4.7 mH

C

= C = 10 mF

OUT

IN

Autoload ON

Autoload OFF

0

5

10

15

20

25

30

0

100

200

300

400

500

LOAD CURRENT (mA)

OUTPUT CURRENT (mA)

Functionality of Color LED Outputs (R1, G1, B1; R2, G2, B2)

LP39542 has 2 sets of RGB/color LED outputs. Both sets have 3 outputs and the sets can be controlled in 4

different ways:

1. Command based pattern generator control (internal PWM)

2. Audio synchronization control

3. Programmable ON/OFF blinking sequences for RGB1

4. External PWM control

By using command based pattern generator user can program any kind of color effect patterns. LED intensity,

blinking cycles and slopes are independently controlled with 8 16-bit commands. Also real time commands are

possible as well as loops and step by step control. If analog audio is available on system, the user can use

audio synchronization for synchronizing LED blinking to the music. The different modes together with the

various sub modes generate very colorful and interesting lighting effects. Direct ON/OFF control is mainly for

switching on and off LEDs. External PWM control is for applications where external PWM signal is available

and required to control the color LEDs. PWM signal can be connected to any color LED separately as shown

later.

COLOR LED CONTROL MODE SELECTION

The RGB_SEL[1:0] bits in the Enables register (08H) control the output modes for RGB1 (R1, G1, B1) and RGB2

(R2, G2, B2) outputs as seen in the following table.

RGB_SEL[1:0]

Audio sync

Pattern generator

Blinking control

00

01

10

11

-

RGB1 & RGB2

-

RGB2

RGB1

-

RGB1

RGB2

-

RGB1 & RGB2

RGB Control register (00H) has control bits for direct on/off control of all color LEDs. Note that the LEDs have

to be turned on in order to control them with audio synchronization or pattern generator.

The external PWM signal can control any LED depending on the control register setup. External PWM signal is

connected to PWM/SYNC pin. The controls are in the Ext. PWM Control register (address 07H) except the

FLASH control in HC_Flash (10H) register as follows:

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Ext. PWM Control (07H)⁽¹⁾

PWM controls WLED 1-4

PWM controls WLED 5-6

PWM controls R1 output

PWM controls G1 output

PWM controls B1 output

PWM controls R2 output

PWM controls G2 output

PWM controls B2 output

HC_Flash (10H)

wled1-4_pwm

wled5-6_pwm

r1_pwm

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

g1_pwm

b1_pwm

r2_pwm

g2_pwm

b2_pwm

hc_pwm

bit 5

PWM controls FLASH

(1) Note: If DISPL=1, wled1-4pwm controls WLED1-6

Note: Maximum external PWM frequency is 1kHz. If during the external PWM control the internal PWM is on, the result will be product

of both functions.

CURRENT CONTROL OF COLOR LED OUTPUTS (R1, R2, G1, G2, B1, B2)

Both RGB output sets can be separately controlled as constant current sinks or as switches. This is done using

cc_rgb1/2 bits in the RGB control register. In constant current mode one or both RGB output sets are controlled

with constant current sinks (no external ballast resistors required). The maximum output current for both drivers

is set by one external resistor R_RGB. User can decrease the maximum current for an individual LED driver by

programming as shown later.

The maximum current for all RGB drivers is set with R_RGB. The equation for calculating the maximum current is

I_MAX= 100 × 1.23V / (R_RGB+ 50Ω)

(1)

where

I_MAX- maximum RGB current in any RGB output in constant current mode

1.23V - reference voltage

100 - internal current mirror multiplier

R_RGB- resistor value in Ohms

50Ω - internal resistor in the I_RGBinput

For example if 22mA is required for maximum RGB current R_RGBequals to

R_RGB=100×1.23V / I_MAX–50Ω=123V / 0.022A–50Ω=5.54kΩ

(2)

Each individual RGB output has a separate maximum current programming. The control bits are in registers

RGB1 max current and RGB2 max current (12H and 13H) and programming is shown in table below. The

default value after reset is 00b.

IR1[1:0], IG1[1:0],

Maximum

IB1[1:0], IR2[1:0],

current/output

IG2[1:0], IB2[1:0]

00

01

10

11

0.25 × I_MAX

0.50 × I_MAX

0.75 × I_MAX

1.00 × I_MAX

SWITCH MODE

The switch mode is used if there is a need to connect parallel LEDs to output or if the RGB output current needs

to be increased.

Please note that the switch mode requires an external ballast resistors at each output to limit the LED current.

The switch/current mode and on/off controls for RGB are in the RGB_ctrl register (00H).

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Table 1. RGB_ctrl register (00H)

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

R1, G1 and B1 are switches → limit current with ballast resistor

CC_RGB1

CC_RGB2

r1sw

bit7

bit6

bit5

bit4

bit3

bit2

bit1

bit0

R1, G1 and B1 are constant current sinks, current limited internally

R2, G2 and B2 are switches → limit current with ballast resistor

R2, G2 and B2 are constant current sinks, current limited internally

R1 is on

R1 is off

G1 is on

G1 is off

B1 is on

B1 is off

R2 is on

R2 is off

G2 is on

G2 is off

B2 is on

B2 is off

g1sw

b1sw

r2sw

g2sw

b2sw

V

OUT

V

OUT

RR1

R1

G1

R1

G1

RR2

RG1

R1

control

R1

control

RG2

RB1

RB2

G1

control

G1

control

B1

control

B1

control

RGB1 output as a constant

current sink (CC)

RGB1 output as switch (SW)

Command Based Pattern Generator for Color LEDs

The LP39542 has an unique stand-alone command based pattern generator with 8 user controllable 16-bit

commands. Since registers are 8-bit long one command requires 2 write cycles. Each command has intensity

level for each LED, command execution time (CET) and transition time (TT) as seen in Figure 3.

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16 bits

RED[2:0]

GREEN[2:0]

CET [3:0]

BLUE[2:0]

TT[2:0]

16 bits

ADDESS[7:0]

RED[2:0]

GREEN[2:0]

CET[3:2]

NEXT ADDESS[7:0]

CET[1:0]

BLUE[2:0]

TT[2:0]

Figure 3.

COMMAND REGISTER WITH 8 COMMANDS

COMMAND 1

COMMAND 2

COMMAND 3

COMMAND 4

COMMAND 5

COMMAND 6

COMMAND 7

COMMAND 8

ADDRESS 50H

ADDRESS 51H

ADDRESS 52H

ADDRESS 53H

ADDRESS 54H

ADDRESS 55H

ADDRESS 56H

ADDRESS 57H

ADDRESS 58H

ADDRESS 59H

ADDRESS 5AH

ADDRESS 5BH

ADDRESS 5CH

ADDRESS 5DH

ADDRESS 5EH

ADDRESS 5FH

R2

CET1

R2

R1

CET0

R1

R0

B2

R0

B2

R0

B2

R0

B2

R0

B2

R0

B2

R0

B2

R0

B2

G2

B1

G2

B1

G2

B1

G2

B1

G2

B1

G2

B1

G2

B1

G2

B1

G1

B0

G1

B0

G1

B0

G1

B0

G1

B0

G1

B0

G1

B0

G1

B0

G0

TT2

G0

CET3

TT1

CET2

TT0

CET3

TT1

CET2

TT0

CET1

R2

CET0

R1

TT2

G0

CET3

TT1

CET2

TT0

CET1

R2

CET0

R1

TT2

G0

CET3

TT1

CET2

TT0

CET1

R2

CET0

R1

TT2

G0

CET3

TT1

CET2

TT0

CET1

R2

CET0

R1

TT2

G0

CET3

TT1

CET2

TT0

CET1

R2

CET0

R1

TT2

G0

CET3

TT1

CET2

TT0

CET1

R2

CET0

R1

TT2

G0

CET3

TT1

CET2

TT0

CET1

CET0

TT2

COLOR INTENSITY CONTROL

Each color has 3-bit intensity level. Level control is logarithmic, 2 curves are selectable. The LOG bit in register

11H defines the curve used as seen in the following table.

R[2:0], G[2:0],

B[2:0]

CURRENT

[% × I_MAX(COLOR)

]

LOG=0

0

LOG=1

000

001

010

011

100

101

110

111

0

1

7

14

2

21

4

32

10

21

46

100

46

71

100

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100

80

60

40

20

0

LOG=0

LOG=1

000 001 010 011 100 101 110 111

R[2:0], G[2:0], B[2:0]

COMMAND EXECUTION TIME (CET) AND TRANSITION TIME (TT)

The command execution CET time is the duration of one single command. Command execution times CET are

defined as follows, when R_T=82kΩ:

CET [3:0]

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

CET duration, ms

197

393

590

786

983

1180

1376

1573

1769

1966

2163

2359

2556

2753

2949

3146

Transition time TT is duration of transition from the previous RGB value to programmed new value. Transition

times TT are defined as follows:

TT [2:0]

000

Transition time, ms

0

001

55

010

110

221

442

885

1770

3539

011

100

101

110

111

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Figure 4 shows an example of RGB CET and TT times.

COMMAND EXECUTION TIME = CET

CET

TT

CET

3

1

2

TT

3

TRANSITION TIME = TT

2

1

BLUE

GREEN

RED

TT < CET

Figure 4.

The command execution time also may be less than the transition time – Figure 5 illuminates this case.

TRANSITION TIME = TT

1

COMMAND EXECUTION TIME = CET

CET

1

2

3

TT

2

TT

3

Target values

BLUE

GREEN

RED

TT > CET

TT < CET

3

1

2

3

Figure 5.

LOOP CONTROL

Pattern generator commands can be looped using the LOOP bit (D1) in Pattern gen ctrl register (11H). If

LOOP=1 the program will be looped from the command 8 register or if there is 0000 0000 and 0000 0000 in one

command register. The loop will start from command 1 and continue until stopped by writing rgb_start=0 or

loop=0. The example of loop is shown in Figure 6.

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IF 0000 0000 and 0000 0000 then ‰ LOOP

LOOP=1

ADDRESS 50H

COMMAND 1

COMMAND 2

ADDRESS 51H

ADDRESS 52H

ADDRESS 53H

ADDRESS 54H

ADDRESS 55H

0

COMMAND 3

Figure 6.

SINGLE PROGRAM

If control bit LOOP=0 the program will start from Command 1 and run to either last command or to empty “0000

0000 / 0000 0000” command.

IF 0000 0000 and 0000 0000 then ‰ STOP

LOOP=0

ADDRESS 50H

start

COMMAND 1

COMMAND 2

ADDRESS 51H

ADDRESS 52H

ADDRESS 53H

ADDRESS 54H

ADDRESS 55H

stop

0

COMMAND 3

Figure 7.

The LEDs maintain the brightness of the last command when the single program stops. Changes in command

register will not be effective in this phase. The RGB_START bit has to be toggled off and on to make changes

effective.

START BIT

Pattern_gen_ctrl register’s RGB_START bit will enable command execution starting from Command 1.

Pattern gen ctrl register (11H)

0 – Pattern generator disabled

1 – execution pattern starting from command 1

rgb_start

loop

Bit 2

Bit 1

Bit 0

0 – pattern generator loop disabled (single pattern)

1 – pattern generator loop enabled (execute until stopped)

0 – color intensity mode 0

1 – color intensity mode 1

log

Audio Synchronization

The color LEDs connected to RGB outputs can be synchronized to incoming audio with Audio Synchronization

feature. Audio Sync has 2 modes. Amplitude mode synchronizes color LEDs based on input signal’s peak

amplitude. In the amplitude mode the user can select between 3 different amplitude mapping modes and 4

different speed configurations. The frequency mode synchronizes the color LEDs based on bass, middle and

treble amplitudes (= low pass, band pass and high pass filters). User can select between 2 different frequency

responses and 4 different speed configurations for best audio-visual user experience. Programmable gain and

AGC function are also available for adjustment of input signal amplitude to light response. The Audio Sync

functionality is described more closely below.

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USING A DIGITAL PWM AUDIO SIGNAL AS AN AUDIO SYNCHRONIZATION SOURCE

If the input signal is a PWM signal, use a first or second order low pass filter to convert the digital PWM audio

signal into an analog waveform. There are two parameters that need to be known to get the filter to work

successfully: frequency of the PWM signal and the voltage level of the PWM signal. Suggested cut-off frequency

(-3 dB) should be around 2 kHz to 4 kHz and the stop-band attenuation at sampling frequency should be around

-48 dB or better. Use a resistor divider to reduce the digital signal amplitude to meet the specification of the

analog audio input. Because a low-order low-pass filter attenuates the high-frequency components from audio

signal, MODE_CTRL=01b selection is recommended when frequency synchronization mode is enabled.

Application example 5 shows an example of a second order RC-filter for 29 kHz PWM signal with 3.3V

amplitude. Active filters, such as a Sallen-Key filter, may also be applied. An active filter gives better stop-band

attenuation and cut-off frequency can be higher than for a RC-filter.

To make sure that the filter rolls off sufficiently quickly, connect your filter circuit to the audio input(s), turn on the

audio synchronization feature, set manual gain to maximum, apply the PWM signal to the filter input and keep an

eye on LEDs. If they are blinking without an audio signal (modulation), a sharper roll-off after the cut-off

frequency, more stop-band attenuation, or smaller amplitude of the PWM signal is required.

AUDIO SYNCHRONIZATION SIGNAL PATH

LP39542 audio synchronization is mainly done digitally and it consists of the following signal path blocks:

•

Input Buffers

AD Converter

DC Remover

Automatic Gain Control (AGC)

Programmable Gain

3 Band Digital Filter

Peak Detector

Look-up Tables (LUT)

Mode Selector

Integrators

PWM Generator

Output Drivers

MODE

HIGH / LOW

3 FILTERS

EN

GAIN

SPEED

INT

LUT

R

G

B

ASE

PW

M

DC

REMOVER

LED

DRIVER

ADC

AGC

BUFFER

PEAK

DETECTOR

Figure 8.

The digitized input signal has DC component that is removed by digital DC REMOVER (-3 dB @ 400 Hz). Since

the light response of input audio signal is very much amplitude dependent the AGC adjusts the input signal to

suitable range automatically. User can disable AGC and the gain can be set manually with PROGRAMMABLE

GAIN. LP39542 has 2 audio synchronization modes: amplitude and frequency. For amplitude based

synchronization the PEAK DETECTION method is used. For frequency based synchronization 3 BAND FILTER

separates high pass, low pass and band bass signals. For both modes the predefined LUT is used to optimize

the audio visual effect. MODE SELECTOR selects the synchronization mode. Different response times to music

beat can be selected using INTEGRATOR speed variables. Finally PWM GENERATOR sets the driver FET duty

cycles.

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INPUT SIGNAL TYPE AND BUFFERING

LP39542 supports single ended audio input as shown in Figure 9. The electric parameters of the buffer are

described in the Audio Synch table. The buffer is rail-to-rail input operational amplifier connected as a voltage

follower. DC level of the input signal is set by a simple resistor divider

V

DDA

1 MW

ASE

10 nF

1 MW

GNDA

Figure 9.

AUDIO SYNCHRONIZATION ELECTRICAL PARAMETERS

Symbol

Z_IN

Parameter

Conditions

Min

250

0.1

Typical

Max

Unit

kΩ

V

Input Impedance of ASE

500

A_IN

Audio Input Level Range

(peak-to-peak)

Gain = 21 dB

Gain = 0 dB

V_DDA-0.1

f_3dB

Crossover Frequencies (-3 dB)

Narrow Frequency Response

Low Pass

Band Pass

High Pass

Low Pass

Band Pass

High Pass

0.5

1.0 and 1.5

2.0

kHz

Wide Frequency Response

1.0

2.0 and 3.0

4.0

CONTROL OF ADC AND AUDIO SYNCHRONIZATION

The following table describes the controls required for audio synchronization.

Audio_sync_CTRL1 (2AH)

Input signal gain control. Range 0...21 dB, step 3 dB:

[000] = 0 dB (default) [011] = 9 dB

[110] = 18 dB

[111] = 21 dB

GAIN_SEL[2:0]

Bits 7-5

[001] = 3 dB

[010] = 6 dB

[100] = 12 dB

[101] = 15 dB

Synchronization mode selector.

SYNC_MODE

EN_AGC

Bit 4

Bit 3

SYNCMODE = 0 → Amplitude Mode (default)

SYNCMODE = 1 → Frequency Mode

Automatic Gain Control enable

1 = enabled

0 = disabled (Gain Select enabled) (default)

Audio synchronization enable

1 = Enabled

Note : If AGC is enabled, AGC gain starts from current GAIN_SEL gain value.

0 = Disabled (default)

EN_SYNC

Bit 2

[00] = Single ended input signal, ASE.

[01] = Temperature measurement

[10] = Ambient light measurement

[11] = No input (default)

INPUT_SEL[1:0]

Bits 1-0

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Audio_sync_CTRL2 (2BH)

0 – averaging disabled (not applicable in audio sync mode)

1 – averaging enabled (not applicable in audio sync mode)

EN_AVG

Bit 4

MODE_CTRL[1:0]

Bits 3-2

See below: Mode control

Sets the LEDs light response time to audio input.

[00] = FASTEST (default)

[01] = FAST

SPEED_CTRL[1:0]

Bits 1-0

[10] = MEDIUM

[11] = SLOW

(For SLOW setting in amplitude mode f_MAX= 3.8 Hz,

Frequency mode f_MAX= 7.6 Hz)

MODE CONTROL IN FREQUENCY MODE

Mode control has two setups based on audio synchronization mode select: the frequency mode and the

amplitude mode. During the frequency mode user can select two filter options by MODE_CTRL as shown

below. User can select the filters based on the music type and light effect requirements. In the first mode the

frequency range extends to 8 kHz in the secont to 4 kHz.

The lowpass filter is used for the red, the bandpass filter for the blue and the hipass filter for the green LED.

Figure 10. Higher frequency mode

MODE_CTRL = 00 and SYNC_MODE = 1

0

BANDPASS

LOWPASS

HIPASS

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

1.0 2.0 3.0 4.0 5.0 6.0 7.0

kHz

0

8.0

Figure 11. Lower frequency mode

MODE_CTRL = 01 and SYNC_MODE = 1

0

BANDPASS

LOWPASS

HIPASS

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

0.5 1.0 1.5 2.0 2.5 3.0 3.5

kHz

0

4.0

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MODE CONTROL IN AMPLITUDE MODE

During the amplitude synchronization mode user can select between three different amplitude mappings by

using MODE_CTRL select. These three mapping options give different light response. The modes are presented

in the following graphs.

Non-overlapping mode

MODE_CTRL[1:0] = [01]

Partly overlapping mode

MODE_CTRL[1:0] = [00]

100

90

80

70

60

50

40

30

20

10

0

100

90

80

70

60

50

40

30

20

10

0

BLUE

GREEN

RED

BLUE

GREEN

RED

0

10 20 30 40 50 60 70 80 90 100

INPUT AMPLITUDE (%)

0

10 20 30 40 50 60 70 80 90 100

INPUT AMPLITUDE (%)

Overlapping mode

MODE_CTRL[1:0] = [10]

Peak Input Signal Level

Range vs Gain Setting

5.00

100

90

80

70

60

50

40

30

20

10

0

BLUE

GREEN

3.00

2.50

2.00

1.50

1.00

0.50

0.30

0.25

0.20

0.15

0.10

RED

0.05

0

3

6

9

12

15

18

21

0

10 20 30 40 50 60 70 80 90 100

INPUT AMPLITUDE (%)

GAIN (dB)

RGB Output Synchronization to External Clock

The RGB pattern generator and high current flash driver timing can be synchronized to external clock with

following configuration.

1. Set PWM_SYNC bit in Enables register to 1

2. Feed SYNC/PWM pin with 5 MHz clock

By this the internal 5 MHz clock is disabled from pattern generator and flash timing circuitry.

The external clock signal frequency will fully determine the timings related to RGB and Flash.

Note: The boost converter will use internal 5 MHz clock even if the external clock is available.

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RGB LED Blinking Control

LP39542 has a possibility to drive indicator LEDs with RGB1 outputs with programmable blinking time. Blinking

function is enabled with RGB_SEL[1:0] bits set as 01b in 0BH register. R1_CYCLE_EN, G1_CYCLE_EN and

B1_CYCLE_EN bits in cycle registers (02H, 04H and 06H) enable/disable blinking function for corresponding

output. When EN_BLINK bit is written high in register 11H, the blinking sequences for all outputs (which has

CYCLE_EN bit enabled) starts simultaneously. EN_BLINK bit should be written high after selecting wanted

blinking sequences and enabling CYCLE_EN bits, to synchronize outputs to get desired lighting effect. R1SW,

G1SW and B1SW bits can be used to enable and disable outputs when wanted.

RGB1 blinking sequence is set with R1, G1 and B1 blink registers (01H, 03H and 05H) by setting the appropriate

OFF-ON times. Blinking cycle times are set with R1_CYCLE[2:0], G1_CYCLE[2:0] and B1_CYCLE[2:0] bits in

R1, G1 and B1 CYCLE registers (02H, 04H and 06H). OFF/ON time is a percentage of the selected cycle time.

Values for setting OFF/ON time can be seen in following table.

Table 2. R1, G1, and B1 Blink Registers (01H, 03H and 05H)

Name

Bit

Description

R1_ON[3:0], R1_OFF[3:0]

G1_ON[3:0], G1_OFF[3:0]

B1_ON[3:0], B1_OFF[3:0]

7-4, 3-0

RGB1 ON and OFF time

Bits

ON/OFF time

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

0%

1%

2.5%

5%

7.5%

10%

15%

20%

30%

40%

50%

60%

70%

80%

90%

100%

Blinking ON/OFF cycle is defined so that there will be first OFF-period then ON-period after which follows an off-

period for the remaining cycle time that can not be set. If OFF and ON times are together more than 100% the

first OFF time will be as set and the ON time is cut to meet 100%. For example, if 50% OFF time is set and ON

time is set greater than 50%, only 50% ON time is used, the exceeding ON time is ignored. If OFF and ON times

are together less than 100% the remaining cycle time output is OFF.

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Blinking cycle time

Remaining OFF time

100 - 10 - 10 = 80%

OFF ON

10%

OFF ON

10%

R1 output

10%

OFF

20%

OFF

20%

ON

20%

G1 output

B1 output

100 - 20 - 20 = 60%

OFF

40%

ON

100 - 40 - 10 = 50%

10%

R1SW bit

G1SW bit

B1SW bit

EN_BLINK bit

R1, G1, B1

CYCLE EN bits

Values for setting the blinking cycle for RGB1 can be seen in following table:

Table 3. R1, G1 and B1 Cycle Registers (02H, 04H and 06H)

Name

Bit

Decription

R1_CYCLE_EN

G1_CYCLE_EN

B1_CYCLE_EN

3

Blinking enable

0 = disabled

1 = enabled, output state is defined with blinking cycle

R1_CYCLE[2:0]

G1_CYCLE[2:0]

B1_CYCLE[2:0]

2-0

RGB1 cycle time

Bits

000

001

010

011

100

101

110

111

Blinking cycle time

Blinking frequency

10 Hz

0.1s

0.25s

0.5s

1s

4 Hz

2 Hz

1 Hz

2s

0.5 Hz

3s

0.33 Hz

0.25 Hz

0.2 Hz

4s

5s

Table 4. PATTERN_GEN_CTRL Register (11H):

Name

Bit

Description

EN_BLINK

3

Blinking sequence start bit

0 = disabled

1 = enabled

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RGB Driver Electrical Characteristics (R1, G1, B1, R2, G2, B2 Outputs)

Symbol

Parameter

Condition

Min

Typ

Max

1

Unit

I_LEAKAGE

R1, G1, B1, R2, G2, B2 pin

leakage current

0.1

μA

I_RGB

Maximum recommended sink

current⁽¹⁾

CC mode

40

50

mA

%

SW mode

Accuracy @ 37mA

Current mirror ratio

R_RGB=3.3 kΩ ±1%, CC mode

CC mode

±5

1:100

±5

RGB1 and RGB2 current

mismatch

I_RGB=37mA, CC mode

%

R_SW

f_RGB

Switch resistance

SW mode

2.5

20

5

Ω

RGB switching frequency

Accuracy proportional to internal

clock freq.

18.2

21.8

kHz

If SYNC to external 5 MHz clock

is in use

20

kHz

(1) Note: RGB current should be limited as follows:

constant current mode – limit by external R_RGBresistor;

switch mode – limit by external ballast resistors

Output Current vs Pin Voltage (Current Sink Mode)

Pin Voltage vs Output Current (Switch Mode)

Output Current vs R_RGB(Current Sink Mode)

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Single High Current Driver

LP39542 has internal constant current driver that is capable of driving high current LED, mainly targeted for

FLASH LED in camera phone applications.

MAXIMUM CURRENT SETUP FOR FLASH

The user sets the maximum current of FLASH with R_FLASHresistor based on following equation:

I_MAX= 300 × 1.23V / (R_FLASH+ 50Ω),

(3)

where

Imax = maximum flash current in Amps (ie. 0.3A)

1.23V = reference voltage

300 = internal current mirror multiplier

R_FLASH= Resistor value in Ohms

50Ω = Internal resistor in the I_FLASHinput

For example if 400mA is required for the maximum flash current, R_FLASHequals to

R_FLASH= 300 × 1.23V / I_MAX– 50Ω = 369V / 0.4A – 50Ω = 873Ω e.g. 910Ω resistor can be used

(4)

CURRENT CONTROL FOR FLASH

To minimize the internal current consumption, the flash function has an enable bit EN_HCFLASH in the

HC_Flash register.

EN_

HCFLASH

MODE

FLASH disabled, no extra current

consumption through R_FLASH

0

FLASH enabled, IFLASH set by

HC_SW[1:0] (see below)

1

HC[1:0] bits in the HC_Flash register control the FLASH current as show in following table.

HC[1:0]

00

I(FLASH)

0.25 × I_MAX(FLASH)

0.50 × I_MAX(FLASH)

0.75 × I_MAX(FLASH)

1.00 × I_MAX(FLASH)

01

10

11

Figure 12 shows the internal structure for the FLASH driver.

V

DD

V

OUT

FLASH

LED

1 mA

FLASH

1.23V

+

-

up to 400 mA

I

RFLASH

1 mA

R

FLASH

Figure 12.

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FLASH TIMING

Flash output is turned on in lower current View finder mode when the EN_HCFLASH bit is written high. The

actual flash at maximum current starts when the FLASH_EN digital input pin goes high. The Flash length can be

selected from 3 pre-defined values or the FLASH_EN pin pulse length can determine how long the flash pulse is.

After flash pulse the flash is shut down completely. To enable flash again, EN_HCFLASH bit must be set to 0

and then 1.The pulse length is controlled by the FT_T[1:0] bits in register 10H as show in the table below.

Current during view

FL_T[1:0]

Flash duration typ

Current during FLASH

finder/focusing

Set by HC[1:0]

00

01

10

11

200ms

400ms

HC[11] = I_MAX(FLASH)

600ms

EN_FLASH on duration

After the flash pulse the EN_HCFLASH bit has to be written low, the LP39542 does not clear this bit

automatically. If 11b is selected in the FL_T[1:0] register, then it is possible to use safety bit EN_SAFETY in

register 10H. When EN_SAFETY is 1, then the flash is shut down automatically, if the FLASH_EN pulse duration

is longer than 1.2 seconds (typ.). This prevents any damage to the application circuitry, if the FLASH_EN pin is

stuck high because of user or program error.

Figure 13 shows the functionality of the built-in flash

Current

HIGH CURRENT

FLASH

VIEW FINDER / FOCUS

HC[1:0] = 11

FL_T[1:0]

HC[1:0] = 10

HC[1:0] = 01

HC[1:0] = 00

HC[11] = I_MAX

HC[1:0]

For mode

FL_T[1:0]=11

Time

FLASH_EN input

EN_HCFLASH bit

Figure 13.

Flash LED can be controlled also with external PWM signal:

Table 5. HC_FLASH Register (10H):

Name

Bit

Description

Flash external PWM control

HC_PWM

5

0 = Flash external PWM control disabled

1 = Flash external PWM control enabled

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High Current Driver Electrical Characteristics

Symbol

Parameter

Condition

Min

Typ

Max

2

Unit

μA

I_LEAKAGE

I_MAX(FLASH)

FLASH pin leakage current

Maximum Sink Current

0.1

400

mA

-10

-5

10

5

Accuracy

R_FLASH= 910Ω

%

Current mirror ratio

Flash safety time

1:300

1.2

t_SAFETY

EN_SAFETY = 1, FL_T = 11b

s

Backlight Drivers

LP39542 has 2 independent backlight drivers. Both drivers are regulated constant current sinks. LED current for

both LED banks (WLED1…4 and WLED5…6) are controlled by 8-bit current mode DACs with 0.1 mA step.

WLED1…4 and WLED5…6 can be also controlled with one DAC for better matching allowing the use of larger

displays having up to 6 white LEDs in parallel.

Display configuration is controlled with DISPL bit as shown in the following table.

DISPL

Configuration

Matching

Main display up

to 4 LEDs

Good btw

WLED1…4

0

Sub display up

to 2 LEDs

Good btw

WLED5…6

Large display

up to 6 LEDs

Good btw

WLED 1…6

1

External PWM

&

WLED1-4_pwm

8-Bit IDAC

WLED1-4

WLED1-4[7:0]

EN_W1-4

Figure 14. Main display up to 4 LEDs (WLED1…4)

External PWM

&

WLED5-6_pwm

8-Bit IDAC

WLED5-6

WLED5-6[7:0]

EN_W5-6

Figure 15. Sub display driver up to 2 LEDs (WLED5…6)

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External PWM

WLED1-4_pwm

&

8-Bit IDAC

WLED1-4

WLED1-4[7:0]

EN_W1-4

Figure 16. Main display up to 6 LEDs (WLED1…6) (DISPL=1)

FADE IN / FADE OUT

LP39542 has an automatic fade in and out for main and sub backlight. The fade function is enabled to main and

sub backlights with EN_FADE_W1_4 and EN_FADE_W5_6 register bits. Register bits SLOPE_W1_4 and

SLOPE_W5_6 set the slope of the fade curve. The fading times are shown in the graphs, which corresponds the

full range current change (0-255). Note that when large display mode is selected (DISPL = 1), then

EN_FADE_W5_6 and SLOPE_W5_6 bits do not have any effect.

WLED dimming, SLOPE=0

WLED dimming, SLOPE=1

100

80

60

40

20

0

100

80

60

40

20

0

FADE OUT

FADE IN

FADE OUT

FADE IN

0

0.1

0.5 0.6 0.7

0

0.2

0.1 1.2 1.4

0.2 0.3 0.4

TIME (s)

0.4 0.6 0.8

TIME (s)

Table 6. WLED Control Register (08H)

Name

Bit

Description

Slope for WLED5-6

SLOPE_W5_6

6

0 = Full range fade execution time 1.30s

1 = Full range fade execution time 0.65s

Slope for WLED1-4

SLOPE_W1_4

EN_FADE_W5_6

EN_FADE_W1_4

DISPL

5

4

3

2

0 = Full range fade execution time 1.30s

1 = Full range fade execution time 0.65s

Enable fade for WLED5-6

0 = Fade disabled

1 = Fade enabled

Enable fade for WLED1-4

0 = Fade disabled

1 = Fade enabled

Large display mode enable

0 = WLED1-4 and WLED5-6 are controlled separately

1 = WLED1-4 and WLED5-6 are controlled with WLED1-4 controls

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Table 6. WLED Control Register (08H) (continued)

Enable WLED1-4

EN_W1_4

EN_W5_6

1

0

0 = WLED1-4 disabled

1 = WLED1-4 enabled

Enable WLED5-6

0 = WLED5-6 disabled

1 = WLED5-6 enabled

ADJUSTMENT

WLED1-4[7:0]

WLED5-6[7:0]

Driver current,

mA (typical)

0000 0000

0000 0001

0000 0010

0000 0011

…

0

0.1

0.2

0.3

…

1111 1101

1111 1110

1111 1111

25.3

25.4

25.5

Figure 17. WLED Output Current vs. Voltage

30

25^oC

25

85^oC

20

-40^oC

15

10

5

0

0.05 0.10 0.15 0.20 0.25 0.30

WLED OUTPUT VOLTAGE (V)

Backlight Driver Electrical Characteristics

Symbol

I_MAX

Parameter

Maximum Sink Current

Leakage Current

Conditions

Min

Typ

25.5

0.03

12.8

Max

29.4

1

Unit

mA

μA

mA

%

21.3

I_leakage

I_WLED1

WLED1 Current tolerance

I_WLED1set to 12.8 mA (80H)

10.52

-18

14.78

+16

I_match1-4

I_match5-6

I_match1-6

Sink Current Matching⁽¹⁾

Sink Current Matching

I_SINK= 13 mA, Between WLED1…4

I_SINK= 13 mA, Between WLED5…6

I_SINK= 13 mA, Between WLED1…6

0.2

0.3

%

(1) Note: Matching is the maximum difference from the average.

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Ambient Light and Temperature Measurement with LP39542

The Analog-to-Digital converter (ADC) in the Audio Syncronization block can be also used for ambient light

measurement or temperature measurement.

The selection between these modes is controlled with input selector bits INPUT_SEL[1:0] in register 2AH as

seen on the following table. Internal averaging function can be used to filter unwanted noise from the measured

signal. Averaging function can be enabled with EN_AVG bit in register 2BH.

INPUT_SEL[1:0]

Mode

00

Audio synchronization

Temperature measurement

(voltage input)

01

Ambient light measurement

(current input)

10

11

No input

EN_AVG = 0

Averaging disabled. f_sample= 122 Hz, data in register changes every 8.2 ms.

Averaging enabled. f_sample= 244 Hz, averaging of 64 samples, data in register changes

every 262 ms (3.2Hz).

EN_AVG = 1

AMBIENT LIGHT MEASUREMENT

The ambient light measurement requires only one external component: Ambient light sensor (photo transistor or

diode). The ADC reads the current level at ASE pin and converts the result into a digital word. User can read the

ADC output from the ADC output register. The known ambient light condition allows user to set the backlight

current to optimal level thus saving power especially in low light and bright sunlight condition.

V

DDA

I

BIAS

R

1 mA

S2

AMBIENT

LIGHT

ASE

ADC

DDA

SENSOR

-

+

S1

S3

V

Figure 18. ASE Input Configuration for Light Measurement

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FF

E0

C0

A0

80

60

40

20

00

0

1

2

3

4

5

6

7

INPUT CURRENT (mA)

Figure 19. ADC Code vs Input Current

in Light Measurement Mode

TEMPERATURE MEASUREMENT

The temperature measurement requires two external components: resistor and thermistor (resistor that has

known temperature vs resistance curve). The ADC reads the voltage level at ASE pin and converts the result into

a digital word. User can read the ADC output from register. The known temperature allows for example to

monitor the temperature inside the display module and decrease the current level of the LEDs if temperature

raises too high. This function may increase lifetime of LEDs in some applications.

R

ADC

-

+

V

DDA

TEMPERATURE

SENSOR

ASE

S1

S2

Figure 20. Temperature sensor connection example

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FF

E0

C0

A0

80

60

40

20

00

100

10

1

0.1

0.01

-40 -20

0

20 40 60 80 100 120

0

0.2

0.4

0.6

0.8

1

TEMPERATURE (°C)

INPUT VOLTAGE × V

DDA

Figure 21. ADC Code vs Input Voltage

in temperature measurement mode

Figure 22. Example curve for thermistor

EXAMPLE TEMP SENSOR READING AT DIFFERENT TEMPERATURES (R_25°C= 1MΩ)

T(°C)

-40

0

R(MΩ)

Rt(MΩ)

60

V(ASE)

2.7540984

2.24

1

4

25

1

1.4

60

0.2

0.04

0.4666667

0.1076923

100

7V Shielding

To shield LP39542 from high input voltages 6…7.2V the use of external 2.8V LDO is required. This 2.8V voltage

protects internally the device against high voltage condition. The recommended connection is as shown in the

picture below. Internally both logic and analog circuitry works at 2.8V supply voltage. Both supply voltage pins

should have separate filtering capacitors.

4.7 mH

BATTERY

C

IN

10 mF

SW

Digital

supply

voltage

V

DD1

DD2

V

DDA

2.8V

LDO

2.8V

LDO

C

VDDA

1 mF

C

VDD

100 nF

Analog

supply

voltage

LP3954

In cases where high voltage is not an issue the connection is as shown below

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4.7 ꢀH

BATTERY

C

IN

10 ꢀF

C

VDD

100 nF

SW

Digital

supply

voltage

V

DD1

DD2

V

DDA

2.8V

LDO

C

VDDA

1 mF

Analog

supply

voltage

LP3954

Logic Interface Electrical Characteristics

(1.65V ≤ V_DDIO≤ V_DD1,2V) (Unless otherwise noted).

Symbol

Parameter

Test Conditions

Min

Typ

Max

Unit

LOGIC INPUTS ADDR_SEL, NRST, SCL, SYNC_PWM, FLASH_EN, SDA

V_IL

V_IH

I_L

Input Low Level

Input High Level

Logic Input Current

Clock Frequency

0.2×V_DDIO

V

0.8×V_DDIO

−1.0

1.0

μA

kHz

f_SCL

400

LOGIC OUTPUT SDA

V_OL

I_L

Output Low Level

Output Leakage Current

I_SDA= 3 mA

V_SDA= 2.8V

0.3

0.5

1.0

V

μA

Note: Any unused digital input pin has to be connected to GND to avoid floating and extra current consumption.

I²C Compatible Interface

INTERFACE BUS OVERVIEW

The I²C compatible synchronous serial interface provides access to the programmable functions and registers on

the device. This protocol uses a two-wire interface for bi-directional communications between the devices

connected to the bus. The two interface lines are the Serial Data Line (SDA), and the Serial Clock Line (SCL).

These lines should be connected to a positive supply, via a pull-up resistor and remain HIGH even when the bus

is idle. Every device on the bus is assigned a unique address and acts as either a Master or a Slave depending

on whether it generates or receives the serial clock (SCL).

DATA TRANSACTIONS

One data bit is transferred during each clock pulse. Data is sampled during the high state of the serial clock

(SCL). Consequently, throughout the clock’s high period, the data should remain stable. Any changes on the

SDA line during the high state of the SCL and in the middle of a transaction, aborts the current transaction. New

data should be sent during the low SCL state. This protocol permits a single data line to transfer both

command/control information and data using the synchronous serial clock.

I²C DATA VALIDITY

The data on SDA line must be stable during the HIGH period of the clock signal (SCL). In other words, state of

the data line can only be changed when CLK is LOW.

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SCL

SDA

data

change

allowed

data

change

allowed

data

change

allowed

data

valid

data

valid

Figure 23. I²C Signals: Data Validity

I²C START AND STOP CONDITIONS

START and STOP bits classify the beginning and the end of the I²C session. START condition is defined as SDA

signal transitioning from HIGH to LOW while SCL line is HIGH. STOP condition is defined as the SDA

transitioning from LOW to HIGH while SCL is HIGH. The I²C master always generates START and STOP bits.

The I²C bus is considered to be busy after START condition and free after STOP condition. During data

transmission, I²C master can generate repeated START conditions. First START and repeated START

conditions are equivalent, function-wise.

SDA

SCL

S

P

START condition

STOP condition

TRANSFERRING DATA

Every byte put on the SDA line must be eight bits long, with the most significant bit (MSB) being transferred first.

Each byte of data has to be followed by an acknowledge bit. The acknowledge related clock pulse is generated

by the master. The transmitter releases the SDA line (HIGH) during the acknowledge clock pulse. The receiver

must pull down the SDA line during the 9^thclock pulse, signifying an acknowledge. A receiver which has been

addressed must generate an acknowledge after each byte has been received.

After the START condition, the I²C master sends a chip address. This address is seven bits long followed by an

eighth bit which is a data direction bit (R/W). The LP39542 address is 54h or 55H as selected with ADDR_SEL

pin. I²C address for LP39542 is 54H when ADDR_SEL=0 and 55H when ADDR_SEL=1. For the eighth bit, a

“0” indicates a WRITE and a “1” indicates a READ. The second byte selects the register to which the data will be

written. The third byte contains data to write to the selected register.

MSB

LSB

ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0 R/W

Bit7

bit6

2

bit5

bit4

bit3

bit2

bit1

bit0

I C SLAVE address (chip address)

Figure 24. I²C Chip Address

Register changes take an effect at the SCL rising edge during the last ACK from slave.

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ack from slave

msb Chip Address lsb

w

ack

msb Register Add lsb

ack

msb DATA lsb

ack

stop

start

SCL

SDA

start

Id = 54h

w

ack

addr = 02h

ack

address 02h data

ack

stop

w = write (SDA = “0”)

r = read (SDA = “1”)

ack = acknowledge (SDA pulled down by either master or slave)

rs = repeated start

id = 7-bit chip address, 54H (ADDR_SEL=0) or 55H (ADDR_SEL=1) for LP39542.

Figure 25. I²C Write Cycle

When a READ function is to be accomplished, a WRITE function must precede the READ function, as shown in

the Read Cycle waveform.

ack from slave

repeated start

ack from slave data from slave ack from master

ack from slave

start

msb Chip Address lsb

w

msb Register Add lsb

rs

msb Chip Address lsb

r

msb DATA lsb

stop

SCL

SDA

start

Id = 54h

w

ack

addr = h00

ack rs

Id = 54h

r

ack

Address 00h data ack stop

Figure 26. I²C Read Cycle

SDA

10

7

8

7

6

1

8

2

SCL

5

1

4

9

3

Figure 27. I²C Timing Diagram

I²C Timing Parameters

V_DD1,2= 3.0 to 4.5V, V_{DD_IO}= 1.65V to V_DD1,2

Symbol

Parameter

Limit⁽¹⁾

Unit

Min

Max

(1) Specified by design. Not production tested.

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1

2

Hold Time (repeated) START Condition

Clock Low Time

0.6

1.3

μs

ns

μs

pF

3

Clock High Time

600

4

Setup Time for a Repeated START Condition

Data Hold Time (Output direction, delay generated by LP39542)

Data Hold Time (Input direction, delay generated by the Master)

Data Setup Time

600

5

300

900

5

0

6

100

7

Rise Time of SDA and SCL

20+0.1C_b

15+0.1C_b

600

300

8

Fall Time of SDA and SCL

9

Set-up Time for STOP condition

10

C_b

Bus Free Time between a STOP and a START Condition

Capacitive Load for Each Bus Line

1.3

10

200

Autoincrement mode is available, with this mode it is possible to read or write bytes with autoincreasing

addresses. LP39542 has empty spaces in address register map, and it is recommended to use autoincrement

mode only for writing in pattern command registers.

Recommended External Components

OUTPUT CAPACITOR, C_OUT

The output capacitor C_OUTdirectly affects the magnitude of the output ripple voltage. In general, the higher the

value of C_OUT, the lower the output ripple magnitude. Multilayer ceramic capacitors with low ESR are the best

choice. At the lighter loads, the low ESR ceramics offer a much lower Vout ripple that the higher ESR tantalums

of the same value. At the higher loads, the ceramics offer a slightly lower Vout ripple magnitude than the

tantalums of the same value. However, the dv/dt of the Vout ripple with the ceramics is much lower than the

tantalums under all load conditions. Capacitor voltage rating must be sufficient, 10V or greater is recommended.

Some ceramic capacitors, especially those in small packages, exhibit a strong capacitance reduction

with the increased applied DC voltage, so called DC bias effect. The capacitance value can fall to below

half of the nominal capacitance. Too low output capacitance will increase noise and it can make the

boost converter unstable. Recommended maximum DC bias effect at 5V DC voltage is -50%.

INPUT CAPACITOR, C_IN

The input capacitor C_INdirectly affects the magnitude of the input ripple voltage and to a lesser degree the V_OUT

ripple. A higher value C_INwill give a lower V_INripple. Capacitor voltage rating must be sufficient, 10V or greater is

recommended.

OUTPUT DIODE, D₁

A schottky diode should be used for the output diode. Peak repetitive current rating of the schottky diode should

be larger than the peak inductor current (ca. 1A). Average current rating of the schottky diode should be higher

than maximum output current (400 mA). Schottky diodes with a low forward drop and fast switching speeds are

ideal for increasing efficiency in portable applications. Choose a reverse breakdown of the schottky diode larger

than the output voltage. Do not use ordinary rectifier diodes, since slow switching speeds and long recovery

times cause the efficiency and the load regulation to suffer.

INDUCTOR, L₁

The LP39542’s high switching frequency enables the use of the small surface mount inductor. A 4.7 μH shielded

inductor is suggested for 2 MHz operation, 10 μH should be used at 1 MHz. The inductor should have a

saturation current rating higher than the peak current it will experience during circuit operation (ca. 1A). Less

than 300 mΩ ESR is suggested for high efficiency. Open core inductors cause flux linkage with circuit

components and interfere with the normal operation of the circuit. This should be avoided. For high efficiency,

choose an inductor with a high frequency core material such as ferrite to reduce the core losses. To minimize

radiated noise, use a toroid, pot core or shielded core inductor. The inductor should be connected to the SW pin

as close to the IC as possible. Examples of suitable inductors are: TDK VLF4012AT-4R7M1R1 and Panasonic

ELLVEG4R7N.

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LIST OF RECOMMENDED EXTERNAL COMPONENTS

Symbol

C_VDD1

C_VDD2

C_VDDIO

C_VDDA

C_OUT

C_IN

Symbol explanation

Value

100

1

Unit

nF

μF

μH

nF

kΩ

V

Type

Ceramic, X7R / X5R

Ceramic, X7R / X5R, 10V

Ceramic, X7R / X5R

Shielded, low ESR, Isat 1A

Ceramic, X7R

C between VDD1 and GND

C between VDD2 and GND

C between VDDIO and GND

C between VDDA and GND

C between FB and GND

10

C between battery voltage and GND

L between SW and V_BATat 2 MHz

C between V_REFand GND

C between V_DDIOand GND

R between I_FLASHand GND

R between I_RGBand GND

10

L₁

4.7

100

1.2

5.6

82

C_VREF

C_VDDIO

R_FLASH

R_RBG

R_RT

Ceramic, X7R

±1%

R between I_RTand GND

±1%

D₁

Rectifying Diode (Vf @ maxload)

C between Audio input and ASE

0.3

100

Schottky diode

C_ASE

LEDs

D_LIGHT

nF

Ceramic, X7R / X5R

User defined

Light Sensor

TDK BSC2015

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Application Examples

EXAMPLE 1

www.ti.com

I

= 300...400 mA

= 4...5.3V

MAX

L1

4.7 éH

+

D1

V

OUT

C

OUT

10 éF

C

IN

10 éF

C

VDD1

100 nF

-

FB

SW

BATTERY

V

DD2

WLED1

DD1

WLED2

WLED3

MAIN

and

SUB

V

DDA

C

WLED4

BACKLIGHT

VDDA

V

REF

1 éF

C

REF

WLED5

WLED6

100 nF

IRGB

IRT

R1

R

RT

R

RGB

LP39542

ADDR_SEL

G1

B1

FUNLIGHTS

NRST

SCL

MCU

SDA

SYNC/PWM

VDDIO

VBAT

R2

G2

B2

C

VDDIO

RGB

INDICATION

LED

100 nF

FLASH_EN

ASE

CAMERA

AUDIO

SINGLE

WHITE

FLASH LED

300 mA

FLASH

IFLASH

GNDS

GND

R

FLASH

•

MAIN BACKLIGHT

SUB BACKLIGHT

AUDIO SYNCHRONIZED FUNLIGHTS

RGB INDICATION LIGHT

FLASH LED

Figure 28. FLIP PHONE

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EXAMPLE 2

I

= 300...400 mA

MAX

L1

4.7 éH

D1

V

OUT

= 4...5.3V

C

VDD1

C

OUT

10 éF

IN

10 éF 100 nF

FB

SW

BATTERY

V

DD2

WLED1

DD1

WLED2

WLED3

SMART

PHONE

BACKLIGHT

V

DDA

C

WLED4

WLED5

VDDA

REF

1 éF

C

REF

100 nF

WLED6

IRGB

IRT

R1

R

RGB

RT

LP39542

KEYPAD

LEDS

G1

B1

NRST

SCL

MCU

SDA

SYNC/PWM

VDDIO

VBAT

ADDR_SEL

R2

G2

B2

C

VDDIO

100 nF

RGB

INDICATION

LED

FLASH_EN

ASE

CAMERA

SINGLE

WHITE

FLASH LED

300 mA

LDO 2.8V

TEMPERATURE

SENSOR

FLASH

IFLASH

GNDS

R

FLASH

•

6 WHITE LED BACKLIGHT

KEYPAD LIGHTS

RGB INDICATION LED

WHITE SINGLE LED FLASH

TEMPERATURE SENSOR

Figure 29. SMART PHONE

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EXAMPLE 3

L1

4.7 éH

I

= 300...400 mA

= 4...5.3V

MAX

D1

V

OUT

C

VDD1

C

OUT

10 éF

IN

10 éF 100 nF

FB

SW

BATTERY

V

DD2

WLED1

DD1

WLED2

WLED3

MAIN

BACKLIGHT

V

DDA

C

WLED4

VDDA

V

REF

1 éF

C

REF

100 nF

WLED5

IRGB

IRT

KEYPAD

LEDS

R

RT

RGB

WLED6

LP39542

NRST

SCL

R1

G1

MCU

SDA

SYNC/PWM

VDDIO

AUDIO

SYNC

FUNLIGHTS

B1

R2

ADDR_SEL

C

VDDIO

100 nF

G2

B2

FLASH_EN

ASE

AUDIO

FLASH

IFLASH

VIBRA

GNDS

GND

R

FLASH

•

MAIN BACKLIGHT

KEYPAD LIGHTS

AUDIO SYNCHRONIZED FUNLIGHTS

VIBRA

Figure 30. CANDYBAR PHONE

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SNVS503B –APRIL 2007–REVISED MAY 2013

EXAMPLE 4

I

= 300...400 mA

= 4...5.3V

MAX

L1

4.7 éH

+

-

D1

V

OUT

C

IN

10 éF

C

OUT

10 éF

VDD1

100 nF

SW

FB

BATTERY

V

DD2

WLED1

WLED2

WLED3

C

DD1

DDA

VDDA

1 éF

V

C

REF

100 nF

V

REF

WLED4

R

RGB

IRGB

IRT

WLED5

WLED6

R

RT

NRST

SCL

R1

SDA

MCU

SYNC/PWM

VDDIO

G1

B1

ADDR_SEL

C

VDDIO

100 nF

FLASH_EN

R4

100k

R3

100k

V

DDA

VBAT

R2

G2

B2

AUDIO

LMV321

+

-

ASE

C2

10 nF

R1

10k

C1

100 nF

R2

100k

FLASH

IFLASH

GNDS

•

MAIN BACKLIGHT

SUB BACKLIGHT

AUDIO SYNCHRONIZED FUNLIGHTS

RGB INDICATION LIGHT

There may be cases where the audio input signal going into the LP39542 is too weak for audio synchronization. This

figure presents a single-supply inverting amplifier connected to the ASE input for audio signal amplification. The

amplification is +20 dB, which is well enough for 20 mVp-p audio signal. Because the amplifier (LMV321) is operating

in single supply voltage, a voltage divider using R3 and R4 is implemented to bias the amplifier so the input signal is

within the input common-mode voltage range of the amplifier. The capacitor C1 is placed between the inverting input

and resistor R1 to block the DC signal going into the audio signal source. The values of R1 and C1 affect the cutoff

frequency, fc = 1/(2π*R1*C1), in this case it is around 160 Hz. As a result, the LMV321 output signal is centered

around mid-supply, that is V_DDA/2. The output can swing to both rails, maximizing the signal-to-noise ratio in a low

voltage system

Figure 31. USING EXTRA AMPLIFIER

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EXAMPLE 5

I

= 300...400 mA

= 4...5.3V

L1

4.7 mH

MAX

+

D1

V

OUT

C

OUT

10 mF

IN

VDD1

100 nF

-

10 mF

SW

FB

BATTERY

V

DD2

WLED1

WLED2

WLED3

C

VDDA

DD1

DDA

1 mF

V

C

REF

100 nF

WLED4

V

REF

R

RGB

IRGB

IRT

WLED5

WLED6

R

RT

NRST

SCL

R1

SDA

MCU

SYNC/PWM

VDDIO

G1

B1

ADDR_SEL

C

VDDIO

100 nF

FLASH_EN

PWM

AUDIO

SIGNAL

VBAT

C1

10 nF

R2

10k

R1

10k

R2

G2

B2

ASE

C2

10 nF

C3

10 nF

FLASH

IFLASH

GNDS

•

MAIN BACKLIGHT

SUB BACKLIGHT

AUDIO SYNCHRONIZED FUNLIGHTS

RGB INDICATION LIGHT

Here, a second order RC-filter is used on the ASE input to convert a PWM signal to an analog waveform.

Figure 32. USING PWM SIGNAL

More application information is available in the document "LP39542 Evaluation Kit".

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SNVS503B –APRIL 2007–REVISED MAY 2013

LP39542 Registers

Table 7. LP39542 Control Register Names and Default Values

ADDR

(HEX)

REGISTER

D7

D6

D5

D4

D3

D2

D1

D0

cc_rgb1

cc_rgb2

r1sw

g1sw

b1sw

r2sw

g2sw

b2sw

00

RGB Ctrl

R1 blink

R1 cycle

G1 blink

G1 cycle

B1 blink

B1 cycle

1

r1_on[3]

0

1

r1_on[2]

0

r1_on[1]

0

r1_on[0]

0

r1_off[3]

r1_off[2]

r1_off[1]

r1_off[0]

01

02

03

04

05

06

0

r1_cycle en

r1_cycle[2]

r1_cycle[1]

r1_cycle[0]

0

g1_off[3]

0

g1_off[2]

0

g1_off[1]

0

g1_off[0]

0

g1_on[3]

g1_on[2]

g1_on[1]

g1_on[0]

0

g1_cycle en g1_cycle[2] g1_cycle[1] g1_cycle[0]

0

b1_off[3]

0

b1_off[2]

0

b1_off[1]

0

b1_off[0]

0

b1_on[3]

b1_on[2]

b1_on[1]

b1_on[0]

0

b1_cycle en b1_cycle[2] b1_cycle[1] b1_cycle[0]

0

b1_pwm

0

r2_pwm

0

wled1_4_pw wled5_6_pw

r1_pwm

g1_pwm

g2_pwm

b2_pwm

m

07

08

Ext. PWM control

WLED control

0

en_w1_4

0

en_w5_6

0

en_fade_w5 en_fade_w1

slope_w5_6 slope_w1_4

displ

0

_6

_4

0

wled1_4[7:0]

09

0A

0B

0C

0D

0E

10

11

12

13

2A

2B

50

51

WLED1-4

WLED5-6

0

1

wled5_6[7:0]

0

pwm_sync

0

nstby

0

en_boost

0

en_autoload

rgb_sel[1:0]

Enables

1

0

data[7:0]

ADC output

0

1

0

1

0

1

0

1

boost[7:0]

Boost output

Boost_frq

1

freq_sel[2:0]

1

en_safety

hc_pwm

fl_t[1:0]

hc[1:0]

en_hcflash

HC_Flash

0

rgb_start

0

loop

0

log

0

Pattern gen ctrl

RGB1 max current

RGB2 max current

Audio sync CTRL1

Audio sync CTRL2

Command 1A

Command 1B

ir1[1:0]

ig1[1:0]

ib1[1:0]

0

1

ir2[1:0]

ig2[1:0]

ib2[1:0]

0

en_agc

0

1

gain_sel[2:0]

sync_mode

en_sync

input_sel[1:0]

0

en_avg

0

mode_ctrl[1:0]

speed_ctrl[1:0]

0

g[2:0]

0

r[2:0]

cet[3:2]

0

b[2:0]

0

tt[2:0]

0

cet[1:0]

0

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Table 7. LP39542 Control Register Names and Default Values (continued)

ADDR

(HEX)

REGISTER

D7

D6

D5

D4

D3

D2

D1

D0

r[2:0]

g[2:0]

cet[3:2]

52

53

54

55

56

57

58

59

5A

5B

5C

5D

5E

Command 2A

0

b[2:0]

0

tt[2:0]

0

cet[1:0]

Command 2B

Command 3A

Command 3B

Command 4A

Command 4B

Command 5A

Command 5B

Command 6A

Command 6B

Command 7A

Command 7B

Command 8A

0

r[2:0]

0

g[2:0]

0

cet[3:2]

0

b[2:0]

0

tt[2:0]

0

r[2:0]

0

g[2:0]

0

b[2:0]

0

tt[2:0]

0

r[2:0]

0

g[2:0]

0

b[2:0]

0

tt[2:0]

0

r[2:0]

0

g[2:0]

0

b[2:0]

0

tt[2:0]

0

r[2:0]

0

g[2:0]

0

b[2:0]

0

tt[2:0]

0

r[2:0]

0

g[2:0]

0

b[2:0]

0

tt[2:0]

0

5F

60

Command 8B

Reset

0

Writing any data to Reset Register resets LP39542

REGISTER BIT EXPLANATIONS

Each register is shown with a key indicating the accessibility of the each individual bit, and the initial condition:

Register Bit Accessibility and Initial Condition

Key

rw

Bit Accessibility

Read/write

r

Read only

–0,–1

Condition after POR

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SNVS503B –APRIL 2007–REVISED MAY 2013

RGB CTRL (00H) – RGB LEDS CONTROL REGISTER

D7

cc_rgb1

rw-1

D6

cc_rgb2

rw-1

D5

D4

D3

D2

D1

D0

r1sw

rw-0

g1sw

rw-0

b1sw

rw-0

r2sw

rw-0

g2sw

rw-0

b2sw

rw-0

0 - R1, G1 and B1 are constant current sinks, current limited internally

1 - R1, G1 and B1 are switches, limit current with external ballast resistor

cc_rgb1

cc_rgb2

r1sw

Bit 7

Bit 6

Bit 5

0 – R2, G2 and B2 are constant current sinks, current limited internally

1 – R2, G2 and B2 are switches, limit current with external ballast resistor

0 – R1 disabled

1 – R1 enabled

0 – G1 disabled

1 – G1 enabled

g1sw

Bit 4

Bit 3

0 – B1 disabled

1 – B1 enabled

b1sw

0 – R2 disabled

1 – R2 enabled

r2sw

Bit 2

Bit 1

Bit 0

0 – G2 disabled

1 – G2 enabled

g2sw

0 – B2 disabled

1 – B2 enabled

b2sw

R1/G1/B1 BLINK (01H, 03H, 05H) – BLINKING ON/OFF TIME CONTROL REGISTER

D7

D6

D5

D4

D3

D2

D1

D0

R1/G1/B1_ON[3:0]

R1/G1/B1_OFF[3:0]

rw-0

RGB1 ON and OFF time

Bits

ON/OFF time

0%

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

1%

2.5%

5%

7.5%

10%

R1_ON[3:0], R1_OFF[3:0]

G1_ON[3:0], G1_OFF[3:0]

B1_ON[3:0], B1_OFF[3:0]

15%

Bits 7-4, 3-0

20%

30%

40%

50%

60%

70%

80%

90%

100%

R1/G1/B1 CYCLE(02H, 04H, 06H) – BLINKING CYCLE CONTROL REGISTER

D7

D6

D5

D4

D3

D2

D1

D0

R1/G1/B1_CYCL

E_EN

R1/G1/B1_CYCLE[2:0]

r-0

rw-0

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R1_CYCLE_EN

G1_CYCLE_EN

B1_CYCLE_EN

Bit 3

Blinking enable

0 = disabled, output state is defined with RGB registers

1 = enabled, output state is defined with blinking cycle

R1_CYCLE[2:0]

G1_CYCLE[2:0]

B1_CYCLE[2:0]

Bits 2-0

RGB1 cycle time

Bits

000

001

010

011

100

101

110

111

Blinking cycle time

Blinking frequency

0.1s

0.25s

0.5s

1s

10 Hz

4 Hz

2 Hz

1 Hz

2s

0.5 Hz

0.33 Hz

0.25 Hz

0.2 Hz

3s

4s

5s

EXT_PWM_CONTROL (07H) – EXTERNAL PWM CONTROL REGISTER

D7

wled1_4_pwm

rw-0

D6

wled5_6_pwm

rw-0

D5

r1_pwm

rw-0

D4

g1_pwm

rw-0

D3

b1_pwm

rw-0

D2

r2_pwm

rw-0

D1

g2_pwm

rw-0

D0

b2_pwm

rw-0

0 – WLED1…WLED4 PWM control disabled

1 – WLED1…WLED4 PWM control enabled

wled1_4_pwm

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0 – WLED5, WLED6 PWM control disabled

1 – WLED5, WLED6 PWM control enabled

wled5_6_pwm

r1_pwm

0 – R1 PWM control disabled

1 – R1 PWM control enabled

0 – G1 PWM control disabled

1 – G1 PWM control enabled

g1_pwm

b1_pwm

r2_pwm

0 – RB PWM control disabled

1 – B1 PWM control enabled

0 – R2 PWM control disabled

1 – R2 PWM control enabled

0 – G2 PWM control disabled

1 – G2 PWM control enabled

g2_pwm

b2_pwm

0 – B2 PWM control disabled

1 – B2 PWM control enabled

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SNVS503B –APRIL 2007–REVISED MAY 2013

WLED CONTROL (08H) – WLED CONTROL REGISTER

D7

r-0

D6

slope_w5_6

rw-0

D5

slope_w1_4

rw-0

D4

en_fade_w5_6

rw-0

D3

en_fade_w1_4

rw-0

D2

D1

en_w1_4

rw-0

D0

en_w5_6

rw-0

displ

rw-0

0 – WLED5-6 full range fade execution time 1.3s

1 – WLED5-6 full range fade execution time 0.65s

slope_w5_6

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0 – WLED1-4 full range fade execution time 1.3s

1 – WLED1-4 full range fade execution time 0.65s

slope_w1_4

en_fade_w5_6

en_fade_w1_4

displ

0 – disable fade for WLED5-6

1 – enable fade for WLED5-6

0 – disable fade for WLED1-4

1 – enable fade for WLED1-4

0 – WLED1-4 and WLED5-6 are controlled separately

1 – WLED1-4 and WLED5-6 are controlled with WLED1-4 controls

0 – WLED1-4 disabled

1 – WLED1-4 enabled

en_w1_4

0 – WLED5-6 disabled

1 – WLED5-6 enabled

en_w5_6

WLED1-4 (09H) – WLED1…WLED4 BRIGHTNESS CONTROL REGISTER

D7

D6

D5

D4

D3

D2

rw-0

D1

D0

wled1_4[7:0]

rw-0

Adjustment

wled1_4[7:0]

0000 0000

0000 0001

0000 0010

0000 0011

0000 0100

…

Typical driver current (mA)

0

0.1

0.2

0.3

0.4

…

wled1_4[7:0]

Bits 7-0

1111 1101

1111 1110

1111 1111

25.3

25.4

25.5

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WLED5-6 (0AH) – WLED5, WLED6 BRIGHTNESS CONTROL REGISTER

D7

D6

D5

D4

D3

D2

D1

D0

wled5_6[7:0]

rw-0

Adjustment

wled5_6[7:0]

0000 0000

0000 0001

0000 0010

0000 0011

0000 0100

…

Typical driver current (mA)

0

0.1

0.2

0.3

0.4

…

wled5_6[7:0]

Bits 7-0

1111 1101

1111 1110

1111 1111

25.3

25.4

25.5

ENABLES (0BH) – ENABLES REGISTER

D7

pwm_sync

rw-0

D6

D5

en_boost

rw-0

D4

r-0

D3

r-0

D2

en_autoload

rw-1

D1

D0

nstby

rw-0

rgb_sel[1:0]

rw-0

0 – synchronization to external clock disabled

1 – synchronization to external clock enabled

pwm_sync

nstby

Bit 7

0 – LP39542 standby mode

1 – LP39542 active mode

Bit 6

Bit 5

Bit 2

0 – boost converter disabled

1 – boost converter enabled

en_boost

en_autoload

0 – internal boost converter loader off

1 – internal boost converter loader on

Color LED control mode selection

rgb_sel[1:0]

Audio sync

Pattern generator

Blinking sequence

00

01

10

11

-

RGB1 & RGB2

-

rgb_sel[1:0]

Bits 1-0

-

RGB2

RGB1

-

RGB1

RGB2

-

RGB1 & RGB2

ADC_OUTPUT (0CH) – ADC DATA REGISTER

D7

D6

D5

r-0

D4

r-0

D3

D2

r-0

D1

r-0

D0

r-0

data[7:0]

r-0

data[7:0]

Bits 7-0

Data register ADC (Audio input, light or temperature sensors)

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SNVS503B –APRIL 2007–REVISED MAY 2013

BOOST_OUTPUT (0DH) – BOOST OUTPUT VOLTAGE CONTROL REGISTER

D7

D6

D5

D4

D3

D2

D1

D0

Boost[7:0]

rw-0

rw-1

Adjustment

Boost[7:0]

0000 0000

0000 0001

0000 0011

0000 0111

0000 1111

0001 1111

0011 1111

0111 1111

1111 1111

Typical boost output (V)

4.00

4.25

4.40

Boost[7:0]

Bits 7-0

4.55

4.70

4.85

5.00 (default)

5.15

5.30

BOOST_FRQ (0EH) – BOOST FREQUENCY CONTROL REGISTER

D7

r-0

D6

r-0

D5

r-0

D4

r-0

D3

r-0

D2

D1

freq_sel[2:0]

rw-1

D0

rw-1

Adjustment

freq_sel[2:0]

Frequency

freq_sel[2:0]

Bits 7-0

1xx

01x

00x

2.00 MHz

1.67 MHz

1.00 MHz

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HC_FLASH (10H) – HIGH CURRENT FLASH DRIVER CONTROL REGISTER

D7

r-0

D6

en_safety

rw-0

D5

hc_pwm

rw-0

D4

D3

D2

D1

D0

en_hcflash

rw-0

fl_t[1:0]

hc[1:0]

rw-0

0 - flash timeout feature disabled

1 - flash timeout feature enabled

en_safety

Bit 6

0 – ext. PWM for high current flash driver disabled

1 – ext. PWM for high current flash driver enabled

hc_pwm

Bit 5

Flash duration for high current driver

fl_t[1:0]

00

Typical flash duration

200 ms

400 ms

fl_t[1:0]

Bits 4-3

01

10

600 ms

11

EN_FLASH pin on duration

Current control for high current flash driver

current

hc[1:0]

00

0.25×I_MAX(FLASH)

hc[1:0]

Bits 2-1

Bit 0

01

0.50×I_MAX(FLASH)

10

0.75×I_MAX(FLASH)

11

1.00×I_MAX(FLASH)

0 – high current flash driver disabled

1 – high current flash driver enabled

en_hcflash

PATTERN_GEN_CTRL (11H) – PATTERN GENERATOR CONTROL REGISTER

D7

r-0

D6

r-0

D5

r-0

D4

r-0

D3

en_blink

rw-0

D2

rgb_start

rw-0

D1

D0

log

loop

rw-0

0 - blinking sequences start bit disabled

1 - blinking sequences start bit enabled

en_blink

rgb_start

loop

Bit 3

Bit 2

Bit 1

Bit 0

0 – pattern generator disabled

1 – execution pattern starting from command 1

0 – pattern generator loop disabled (single pattern)

1 – pattern generator loop enabled (execute until stopped)

0 – color intensity mode 0

1 – color intensity mode 1

log

52

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SNVS503B –APRIL 2007–REVISED MAY 2013

RGB1_MAX_CURRENT (12H) – RGB1 DRIVER INDIVIDUAL MAXIMUM CURRENT CONTROL REGISTER

D7

r-0

D6

r-0

D5

D4

D3

D2

D1

D0

ir1[1:0]

ig1[1:0]

ib1[1:0]

rw-0

Maximum current for R1 driver

ir1[2:0]

Maximum output current

0.25×I_MAX

00

01

10

11

ir1[1:0]

ig1[1:0]

ib1[1:0]

Bits 5-4

0.50×I_MAX

0.75×I_MAX

1.00×I_MAX

Maximum current for G1 driver

ig2[1:0]

00

Maximum output current

0.25×I_MAX

Bits 3-2

01

0.50×I_MAX

10

0.75×I_MAX

11

1.00×I_MAX

Maximum current for B1 driver

ib1[1:0]

00

Maximum output current

0.25×I_MAX

Bits 1-0

01

0.50×I_MAX

10

0.75×I_MAX

11

1.00×I_MAX

RGB2_MAX_CURRENT (13H) – RGB2 DRIVER INDIVIDUAL MAXIMUM CURRENT CONTROL REGISTER

D7

r-0

D6

r-0

D5

D4

D3

D2

D1

D0

ir2[1:0]

ig2[1:0]

ib2[1:0]

rw-0

Maximum current for R2 driver

ir2[2:0]

Maximum output current

0.25×I_MAX

00

01

10

11

ir2[1:0]

ig2[1:0]

ib2[1:0]

Bits 5-4

0.50×I_MAX

0.75×I_MAX

1.00×I_MAX

Maximum current for G2 driver

ig2[1:0]

00

Maximum output current

0.25×I_MAX

Bits 3-2

01

0.50×I_MAX

10

0.75×I_MAX

11

1.00×I_MAX

Maximum current for B2 driver

ib2[1:0]

00

Maximum output current

0.25×I_MAX

Bits 1-0

01

0.50×I_MAX

10

0.75×I_MAX

11

1.00×I_MAX

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AUDIO_SYNC_CTRL1 (2AH) – AUDIO SYNCHRONIZATION AND ADC CONTROL REGISTER 1

D7

D6

gain_sel[2:0]

rw-0

D5

D4

sync_mode

rw-0

D3

en_agc

rw-0

D2

en_sync

rw-0

D1

D0

input_sel[1:0]

rw-0

rw-1

Input signal gain control

gain, dB

gain_sel[2:0]

000

0 (default)

001

3

6

010

gain_sel[2:0]

Bits 7-5

011

9

100

12

15

18

21

101

110

111

Input filter mode control

sync_mode

Bit 4

0 – Amplitude mode

1 – Frequency mode

0 – automatic gain control disabled

1 – automatic gain control enabled

en_agc

Bit 3

Bit 2

0 – audio synchronization disabled

1 – audio synchronization enabled

en_sync

ADC input selector

Input

input_sel[1:0]

00

01

10

11

Single ended input signal (ASE)

input_sel[1:0]

Bits 1-0

Temperature measurement

Ambient light measurement

No input (default)

AUDIO_SYNC_CTRL2 (2BH) – AUDIO SYNCHRONIZATION AND ADC CONTROL REGISTER 2

D7

r-0

D6

r-0

D5

r-0

D4

en_avg

rw-0

D3

D2

D1

D0

mode_ctrl[1:0]

speed_ctrl[1:0]

rw-0

0 – averaging disabled. f_sample= 122 Hz, data in register changes every 8.2 ms.

1 – averaging enabled. f_sample= 244 Hz, averaging of 64 samples, data in register

changes every 262 ms (3.2Hz).

en_avg

Bit 4

mode_ctrl[1:0]

Bits 3-2

Filtering mode control

LEDs light response time to audio input

speed_ctrl[1:0]

Response

FASTEST (default)

FAST

00

01

10

11

speed_ctrl[1:0]

Bits 1-0

MEDIUM

SLOW

54

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SNVS503B –APRIL 2007–REVISED MAY 2013

PATTERN CONTROL REGISTERS

Command_[1:8]A – Pattern Control Register A

D7

D6

D5

D4

D3

D2

D1

D0

r[2:0]

rw-0

g[2:0]

rw-0

cet[3:2]

rw-0

Command_[1:8]B – Pattern Control Register B

D7

D6

D5

D4

D3

D2

D1

D0

cet[1:0]

b[2:0]

rw-0

tt[2:0]

rw-0

Red color intensity

current, %

r[2:0]

log=0

log=1

000

001

010

011

100

101

110

111

0×I_MAX

7%×I_MAX

1%×I_MAX

2%×I_MAX

Bits

7-5A

r[2:0]

14%×I_MAX

21%×I_MAX

32%×I_MAX

46%×I_MAX

71%×I_MAX

100%×I_MAX

Green color intensity

4%×I_MAX

10%×I_MAX

21%×I_MAX

46%×I_MAX

100%×I_MAX

g[2:0]

current, %

log=0

log=1

0×I_MAX

000

001

010

011

100

101

110

111

0×I_MAX

7%×I_MAX

14%×I_MAX

21%×I_MAX

32%×I_MAX

46%×I_MAX

71%×I_MAX

100%×I_MAX

1%×I_MAX

2%×I_MAX

4%×I_MAX

10%×I_MAX

21%×I_MAX

46%×I_MAX

100%×I_MAX

Bits

4-2A

g[2:0]

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Command execution time

CET duration, ms

cet[3:0]

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

197

393

590

786

983

1180

Bits

1376

cet[3:0]

1-0A

7-6B

1573

1769

1966

2163

2359

2556

2753

2949

3146

Blue color intensity

b[2:0]

current, %

log=0

log=1

0×I_MAX

000

001

010

011

100

101

110

111

0×I_MAX

7%×I_MAX

14%×I_MAX

21%×I_MAX

32%×I_MAX

46%×I_MAX

71%×I_MAX

100%×I_MAX

1%×I_MAX

2%×I_MAX

4%×I_MAX

10%×I_MAX

21%×I_MAX

46%×I_MAX

100%×I_MAX

Bits

5-3B

b[2:0]

Transition time

tt[2:0]

000

001

010

011

100

101

110

111

Transition time, ms

0

55

110

221

442

885

1770

3539

Bits

2-0B

tt[2:0]

RESET (60H) - RESET REGISTER

D7

D6

D5

D4

D3

D2

D1

D0

Writing any data to Reset Register in address 60H can reset LP39542

w-0 w-0 w-0 w-0

w-0

56

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SNVS503B –APRIL 2007–REVISED MAY 2013

REVISION HISTORY

Changes from Revision A (May 2013) to Revision B

Page

•

Changed layout of National Data Sheet to TI format .......................................................................................................... 56

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PACKAGE MATERIALS INFORMATION

www.ti.com

11-Oct-2013

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

LP39542RL/NOPB

LP39542RLX/NOPB

LP39542TL/NOPB

LP39542TLX/NOPB

DSBGA

YPG

YZR

36

250

1000

250

178.0

12.4

3.21

0.76

8.0

12.0

Q1

1000

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

11-Oct-2013

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

LP39542RL/NOPB

LP39542RLX/NOPB

LP39542TL/NOPB

LP39542TLX/NOPB

DSBGA

YPG

YZR

36

250

1000

250

210.0

185.0

35.0

1000

Pack Materials-Page 2

MECHANICAL DATA

YPG0036xxx

D

0.650±0.075

E

RLA36XXX (Rev A)

4214895/A

12/12

A. All linear dimensions are in millimeters. Dimensioning and tolerancing per ASME Y14.5M-1994.

B. This drawing is subject to change without notice.

NOTES:

www.ti.com

MECHANICAL DATA

YZR0036xxx

D

0.600±0.075

E

TLA36XXX (Rev D)

4215058/A

12/12

A. All linear dimensions are in millimeters. Dimensioning and tolerancing per ASME Y14.5M-1994.

B. This drawing is subject to change without notice.

NOTES:

www.ti.com

IMPORTANT NOTICE

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型号：	LP39542RLX/NOPB
厂家：	TEXAS INSTRUMENTS
描述：	Advanced Lighting Management Unit 36-DSBGA 驱动接口集成电路
文件：	总64页 (文件大小：1484K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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