LP39542TLX_技术文档

August 2007

LP39542

Advanced Lighting Management Unit

General Description

Features

LP39542 is an advanced lighting management unit for hand-

held devices. It drives any phone lights including display

backlights, RGB, keypad and camera flash LEDs. The boost

DC-DC converter drives high current loads with high efficien-

cy. White LED backlight drivers are high efficiency low voltage

structures with excellent matching and automatic fade in/ fade

out function. The stand-alone command based RGB con-

troller is feature rich and easy to configure. Built-in audio

synchronization feature allows user to synchronize the color

LEDs to audio input. Integrated high current driver can drive

camera flash LED or motor/vibra. Internal ADC can be used

for ambient light or temperature sensing. The flexible I²C in-

terface allows easy control of LP39542. Small micro SMD

package together with minimum number of external compo-

nents is a best fit for handheld devices.

Audio synchronization for color/RGB LEDs

■

Command based PWM controlled RGB LED drivers

■

Programmable ON/OFF blinking sequences for RGB LED

High current driver for flash LED with built-in timing and

safety feature.

4+2 or 6 low voltage constant current white LED drivers

with programmable 8-bit adjustment (0...25 mA/LED)

■

High efficiency Boost DC-DC converter

I²C compatible interface

■

Possibility for external PWM dimming control

Possibility for clock synchronization for RGB timing

Ambient light and temperature sensing possibility

Small package – microSMD-36, 3.0 x 3.0 x 0.6 mm

Applications

Cellular Phones

■

PDAs, MP3 players

Typical Applications

30008560

300085

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Connection Diagrams and Package Mark Information

CONNECTION DIAGRAMS

MicroSMD-36 Package, 3.0 x 3.0 x 0.6 mm, 0.5 mm pitch NS Package Number TLA36AAA or

MicroSMDxt-36 Package, 3.0 x 3.0 x 0.65 mm, 0.5 mm pitch NS Package Number RLA36AAA

30008503

30008504

PACKAGE MARK

30008505

Ordering Information

Order Number

LP39542TL

Package Marking

D58B

Supplied As

TNR 250

Spec/Flow

NoPb

LP39542TLX

LP39542RL

LP39542RLX

D58B

TNR 1000

TNR 250

NoPb

D58B

NoPb

D58B

TNR 1000

NoPb

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2

Pin Descriptions

Pin #

6F

6E

6D

6C

6B

6A

5F

5E

5D

5C

5B

5A

4F

4E

4D

4C

4B

4A

3F

3E

3D

3C

3B

3A

2F

2E

2D

2C

2B

2A

1F

1E

1D

1C

1B

1A

Name

SW

Type

Output

Input

Description

Boost Converter Power Switch

Boost Converter Feedback

High Current Flash Output

Red LED 1 Output

FB

FLASH

R1

Output

Ground

Power

G1

Green LED 1 Output

Blue LED 1 Output

B1

GND_SW

GND

Power Switch Ground

Ground

V_DDIO

Supply Voltage for Logic Input/Output Buffers and Drivers

SDA

Logic Input/Output Serial Data In/Out (I²C)

IRGB

Input

Ground

Input

Bias Current Set Resistor for RGB Drivers

GND_RGB

GND_WLED

IFLASH

SYNC_PWM

ADDR_SEL

NRST

R2

Ground for RGB Currents

Ground for WLED Currents

High Current Flash Current Set Resistor

External PWM Control for LEDs or External Clock for RGB Sync

Address Select (I²C)

Logic Input

Output

Reset Pin

Red LED 2 Output

WLED5

WLED6

V_DD1

Output

White LED 5 Output

Output

White LED 6 Output

Power

Supply Voltage

FLASH_EN

SCL

Logic Input

Output

Enable for High Current Flash

Clock (I²C)

G2

Green LED 2 Output

WLED3

WLED4

ASE

Output

White LED 3 Output

Output

White LED 4 Output

Input

Audio Synchronization Input

Oscillator Frequency Resistor

Ground

IRT

Input

GNDT

B2

Ground

Output

Blue LED 2 Output

WLED1

WLED2

GNDA

VREF

V_DDA

Output

White LED 1 Output

Output

White LED 2 Output

Ground

Output

Ground for Analog Circuitry

Reference Voltage

Power

Internal LDO Output

V_DD2

Power

Supply Voltage

3

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Absolute Maximum Ratings (Notes 1, 2)

Operating Ratings (Notes 1, 2)

V (SW, FB, WLED1-6, R1-2, G1-2,

B1-2, FLASH)

V_DD1,2with external LDO

V_DD1,2with internal LDO

V_DDA

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales Office/

Distributors for availability and specifications.

0 to 6.0V

2.7 to 5.5V

3.0 to 5.5V

V (SW, FB, R1-2, G1-2, B1-2,

FLASH, WLED1-6)(Notes 3, 4)

-0.3V to +7.2V

2.7 to 2.9V

V_DD1, V_DD2, V_DDIO, V_DDA

-0.3V to +6.0V

V_DDIO

1.65V to V_DD1

Voltage on ASE, IRT, IFLASH,

IRGB, VREF

-0.3V to V_DD1+0.3V

with 6.0V max

Voltage on ASE

0.1V to V_DDA–0.1V

0 mA to 400 mA

-30°C to +125°C

-30°C to +85°C

Recommended Load Current

Junction Temperature (T_J) Range

Voltage on Logic Pins

-0.3V to V_DDIO+0.3V

with 6.0V max

Ambient Temperature (T_A) Range

(Note 9)

V(all other pins): Voltage to GND

-0.3V to 6.0V

I (V_REF

)

10 μA

100 mA

400 mA

I(R1, G1, B1, R2, G2, B2)

I(FLASH)(Note 5)

Thermal Properties

Junction-to-Ambient Thermal

Resistance(θ_JA), TLA36AAA or

RLA36AAA Package

(Note 10)

60°C/W

Continuous Power Dissipation

(Note 6)

Internally Limited

Junction Temperature (T_J-MAX

Storage Temperature Range

)

150°C

-65°C to +150°C

260°C

Maximum Lead Temperature

(Soldering) (Note 7)

ESD Rating (Note 8)

Human Body Model:

2 kV

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4

Electrical Characteristics (Notes 2, 11)

Limits in standard typeface are for T_J= 25°C. Limits in boldface type apply over the operating ambient temperature range (-30°C

< T_A< +85°C). Unless otherwise noted, specifications apply to the LP39542 Block Diagram with: V_DD1= V_DD2= 3.6V, V_DDIO= 2.8V,

C_VDD= C_VDDIO= 100 nF, C_OUT= C_IN= 10 μF, C_VDDA= 1 μF, C_REF= 100 nF, L₁= 4.7 μH, R_FLASH= 910Ω, R_RGB= 5.6 kΩ and R_RT

= 82 kΩ (Note 12).

Symbol

Parameter

Standby supply current NSTBY (bit) = L, NRST (pin) = H

(V_DD1+ V_DD2SCL=H, SDA = H

No-boost supply current NSTBY (bit) = H,

Condition

Min

Typ

Max

8

Units

I_VDD

1

μA

)

450

μA

(V_DD1+ V_DD2

)

EN_BOOST(bit) = L

SCL = H, SDA = H

Audio sync and LEDs OFF

No-load supply current NSTBY (bit) = H,

1

mA

(V_DD1+ V_DD2

)

EN_BOOST (bit) = H

SCL = H, SDA = H

Audio sync and LEDs OFF

Autoload OFF

RGB drivers

(V_DD1+ V_DD2

CC mode at R1, G1, B1 and R2, G2, B2 set to 15 mA

SW mode

150

500

μA

)

WLED drivers

(V_DD1+ V_DD2

Audio synchronization

4+2 banks I_OUT= 25.5 mA per LED

)

Audio sync ON

V_DD1,2= 2.8V

V_DD1,2= 3.6V

(V_DD1+ V_DD2

)

390

700

2

μA

Flash

I(R_FLASH) = 1 mA

mA

(V_DD1+ V_DD2

)

Peak current during flash

I_VDDIO

V_DDIOStandby Supply

current

NSTBY (bit)=L

SCL = H, SDA = H

1

μA

I_{EXT_LDO}External LDO output

current

7V tolerant application only

I_BOOST= 300 mA

6.5

mA

(V_DD1, V_DD2, V_DDA

)

V_DDA

Output voltage of internal (Note 13)

LDO for analog parts

2.72

-3

2.80

2.88

+3

V

%

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under which operation

of the device is guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed performance limits and associated test conditions,

see the Electrical Characteristics tables.

Note 2: All voltages are with respect to the potential at the GND pins.

Note 3: Battery/Charger voltage should be above 6V no more than 10% of the operational lifetime.

Note 4: Voltage tolerance of LP39542 above 6.0V relies on fact that V_DD1and V_DD2(2.8V) are available (ON) at all conditions. If V_DD1and V_DD2are not available

(ON) at all conditions, National Semiconductor does not guarantee any parameters or reliability for this device.

Note 5: The total load current of the boost converter in worst-case conditions is limited to 300 mA (min. input and max. output voltage).

Note 6: Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at T_J=160°C (typ.) and disengages at

T_J=140°C (typ.).

Note 7: For detailed soldering specifications and information, please refer to National Semiconductor Application Note AN1112 : Micro SMD Wafer Level Chip

Scale Package or Application note AN1412: Micro SMDxt Wafer Lever Chip Scale Package

Note 8: The Human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin.

Note 9: In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may have to be

derated. Maximum ambient temperature (T_A-MAX) is dependent on the maximum operating junction temperature (T_J-MAX-OP= 125°C), the maximum power

dissipation of the device in the application (P_D-MAX), and the junction-to ambient thermal resistance of the part/package in the application (θ_JA), as given by the

following equation: T_A-MAX= T_J-MAX-OP– (θ_JA× P_D-MAX).

Note 10: Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power dissipation exists,

special care must be paid to thermal dissipation issues in board design.

Note 11: Min and Max limits are guaranteed by design, test, or statistical analysis. Typical numbers are not guaranteed, but do represent the most likely norm.

Note 12: Low-ESR Surface-Mount Ceramic Capacitors (MLCCs) used in setting electrical characteristics.

Note 13: V_DDAoutput is not recommended for external use.

5

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Block Diagram

30008506

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6

Modes of Operation

RESET:

In the RESET mode all the internal registers are reset to the default values and the chip goes to STANDBY

mode after reset. NSTBY control bit is low after reset by default. Reset is active always if NRST input pin is

low or internal Power On Reset is active. LP39542 can be also reset by writing any data to Reset Register

in address 60H. Power On Reset (POR) will activate during the chip startup or when the supply voltage

V_DD2falls below 1.5V. Once V_DD2rises above 1.5V, POR will inactivate and the chip will continue to the

STANDBY mode.

STANDBY:

STARTUP:

The STANDBY mode is entered if the register bit NSTBY is LOW. This is the low power consumption mode,

when all circuit functions are disabled. Registers can be written in this mode and the control bits are effective

immediately after power up.

When NSTBY bit is written high, the INTERNAL STARTUP SEQUENCE powers up all the needed internal

blocks (Vref, Bias, Oscillator etc..). To ensure the correct oscillator initialization, a 10 ms delay is generated

by the internal state-machine. If the chip temperature rises too high, the Thermal Shutdown (TSD) disables

the chip operation and STARTUP mode is entered until no thermal shutdown event is present.

BOOST STARTUP:

NORMAL:

Soft start for boost output is generated in the BOOST STARTUP mode. The boost output is raised in PFM

mode during the 10 ms delay generated by the state-machine. The Boost startup is entered from Internal

Startup Sequence if EN_BOOST is HIGH or from Normal mode when EN_BOOST is written HIGH. During

the 10 ms Boost Startup time all LED outputs are switched off to ensure smooth start-up.

During NORMAL mode the user controls the chip using the Control Registers. The registers can be written

in any sequence and any number of bits can be altered in a register in one write

30008507

7

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Magnetic Boost DC/DC Converter

The LP39542 Boost DC/DC Converter generates a 4.0 – 5.3V

voltage for the LEDs from single Li-Ion battery (3V…4.5V).

The output voltage is controlled with an 8-bit register in 9

steps. The converter is a magnetic switching PWM mode DC/

DC converter with a current limit. The converter has three op-

tions for switching frequency, 1 MHz, 1.67 MHz and 2 MHz

(default), when timing resistor RT is 82 kΩ. Timing resistor

defines the internal oscillator frequency and thus directly af-

fects boost frequency and all circuit's internally generated

timing (RGB, Flash, WLED fading).

The topology of the magnetic boost converter is called CPM

control, current programmed mode, where the inductor cur-

rent is measured and controlled with the feedback. The user

can program the output voltage of the boost converter. The

output voltage control changes the resistor divider in the feed-

back loop.

The following figure shows the boost topology with the pro-

tection circuitry. Four different protection schemes are imple-

mented:

1. Over voltage protection, limits the maximum output

voltage

The LP39542 Boost Converter uses pulse-skipping elimina-

tion to stabilize the noise spectrum. Even with light load or no

load a minimum length current pulse is fed to the inductor. An

active load is used to remove the excess charge from the

output capacitor at very light loads. At very light load and when

input and output voltages are very close to each other, the

pulse skipping is not completely eliminated. Output voltage

should be at least 0.5V higher than input voltage to avoid

pulse skipping. Reducing the switching frequency will also

reduce the required voltage difference.

Keeps the output below breakdown voltage.

—

Prevents boost operation if battery voltage is much

higher than desired output.

2. Over current protection, limits the maximum inductor

current

Voltage over switching NMOS is monitored; too high

voltages turn the switch off.

—

3. Feedback break protection. Prevents uncontrolled

operation if FB pin gets disconnected.

Active load can be disabled with the en_autoload bit. Dis-

abling will increase the efficiency at light loads, but the down-

side is that pulse skipping will occur. The Boost Converter

should be stopped when there is no load to minimise the cur-

rent consumption.

4. Duty cycle limiting, done with digital control.

30008508

Boost Converter Topology

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8

Magnetic Boost DC/DC Converter Electrical Characteristics

Symbol

I_LOAD

Parameter

Load Current

Conditions

Min

Typ

Max

Units

3.0V ≤ V_IN

0

300

V_OUT= 5V

mA

3.0V ≤ V_IN

V_OUT= 4V

0

400

V_OUT

Output Voltage Accuracy

(FB Pin)

3.0V ≤ V_IN≤ V_OUT- 0.5

−5

+5

%

V

V_OUT= 5.0V

Output Voltage

(FB Pin)

1 mA ≤ I_LOAD≤ 300 mA

V_IN> 5V + V_(SCHOTTKY)

V_IN–V_(SCHOTTKY)

RDS_ON

f_boost

Switch ON Resistance

V_DD1,2= 2.8V, I_SW= 0.5A

0.4

2

0.8

Ω

PWM Mode Switching

Frequency

RT = 82 kΩ

freq_sel[2:0] = 1XX

MHz

Frequency Accuracy

−6

±3

+6

2.7 ≤ VDDA ≤ 2.9

RT = 82 kΩ

no load

%

−9

+9

t_PULSE

Switch Pulse Minimum

Width

25

ns

t_STARTUP

I_{SW_MAX}

Startup Time

Boost startup from STANDBY

10

ms

SW Pin Current Limit

700

800

900

mA

550

950

Boost Output Voltage Control

BOOST STANDBY MODE

User can stop the Boost Converter operation by writing the

Enables register bit EN_BOOST low. When EN_BOOST is

written high, the converter starts for 10 ms in PFM mode and

then goes to PWM mode.

BOOST OUTPUT VOLTAGE CONTROL

User can control the boost output voltage by boost output 8-

bit register.

Boost Output [7:0]

Register 0DH

Boost Output

Voltage (typical)

Bin

Hex

00

01

03

07

0F

1F

3F

7F

FF

0000 0000

0000 0001

0000 0011

0000 0111

0000 1111

0001 1111

0011 1111

0111 1111

1111 1111

4.00

4.25

4.40

4.55

4.70

30008509

4.85

BOOST FREQUENCY CONTROL

5.00 Default

5.15

freq_sel[2:0]

1XX

frequency

2.00 MHz

1.67 MHz

1.00 MHz

5.30

01X

001

Register ‘boost freq’ (address 0EH). Register default value

after reset is 07H.

9

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Boost Converter Typical Performance Characteristics

Vin = 3.6V, Vout = 5.0V if not otherwise stated

Boost Converter Efficiency

Battery Current vs Voltage

Boost Line Regulation

Boost Typical Waveforms at 100mA Load

30008511

30008510

Battery Current vs Voltage

30008512

30008513

Boost Startup with No Load

30008514

30008515

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10

Boost Load Transient, 50 mA–100 mA

Boost Switching Frequency

30008516

30008517

Output Voltage vs Load Current

Efficiency at Low Load vs Autoload

30008562

30008561

11

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Functionality of Color LED Outputs (R1, G1, B1; R2, G2, B2)

LP39542 has 2 sets of RGB/color LED outputs. Both sets

have 3 outputs and the sets can be controlled in 4 different

ways:

CURRENT CONTROL OF COLOR LED OUTPUTS (R1, R2,

G1, G2, B1, B2)

Both RGB output sets can be separately controlled as con-

stant current sinks or as switches. This is done using

cc_rgb1/2 bits in the RGB control register. In constant current

mode one or both RGB output sets are controlled with con-

stant current sinks (no external ballast resistors required).

The maximum output current for both drivers is set by one

external resistor R_RGB. User can decrease the maximum cur-

rent for an individual LED driver by programming as shown

later.

1. Command based pattern generator control (internal

PWM)

2. Audio synchronization control

3. Programmable ON/OFF blinking sequences for RGB1

4. External PWM control

By using command based pattern generator user can pro-

gram any kind of color effect patterns. LED intensity, blinking

cycles and slopes are independently controlled with 8 16-bit

commands. Also real time commands are possible as well as

loops and step by step control. If analog audio is available on

system, the user can use audio synchronization for syn-

chronizing LED blinking to the music. The different modes

together with the various sub modes generate very colorful

and interesting lighting effects. Direct ON/OFF control is

mainly for switching on and off LEDs. External PWM con-

trol is for applications where external PWM signal is available

and required to control the color LEDs. PWM signal can be

connected to any color LED separately as shown later.

The maximum current for all RGB drivers is set with R_RGB

The equation for calculating the maximum current is

.

I_MAX= 100 × 1.23V / (R_RGB+ 50Ω)

where

I_MAX- maximum RGB current in any RGB output in constant

current mode

1.23V - reference voltage

100 - internal current mirror multiplier

R_RGB- resistor value in Ohms

50Ω - internal resistor in the I_RGBinput

For example if 22mA is required for maximum RGB current

R_RGBequals to

COLOR LED CONTROL MODE SELECTION

The RGB_SEL[1:0] bits in the Enables register (08H) control

the output modes for RGB1 (R1, G1, B1) and RGB2 (R2, G2,

B2) outputs as seen in the following table.

R_RGB=100×1.23V / I_MAX–50Ω=123V / 0.022A–50Ω=5.54kΩ

Each individual RGB output has a separate maximum current

programming. The control bits are in registers RGB1 max

current and RGB2 max current (12H and 13H) and pro-

gramming is shown in table below. The default value after

reset is 00b.

RGB_SEL

[1:0]

Audio sync

Pattern

generator

Blinking

control

00

01

10

11

-

RGB1 & RGB2

-

RGB2

RGB1

-

RGB1

IR1[1:0], IG1[1:0],

Maximum

RGB2

-

IB1[1:0], IR2[1:0],

current/output

IG2[1:0], IB2[1:0]

RGB1 & RGB2

RGB Control register (00H) has control bits for direct on/off

control of all color LEDs. Note that the LEDs have to be turned

on in order to control them with audio synchronization or pat-

tern generator.

00

01

10

11

0.25 × I_MAX

0.50 × I_MAX

0.75 × I_MAX

1.00 × I_MAX

The external PWM signal can control any LED depending on

the control register setup. External PWM signal is connected

to PWM/SYNC pin. The controls are in the Ext. PWM Control

register (address 07H) except the FLASH control in HC_Flash

(10H) register as follows:

SWITCH MODE

The switch mode is used if there is a need to connect parallel

LEDs to output or if the RGB output current needs to be in-

creased.

Ext. PWM Control (07H)

Please note that the switch mode requires an external bal-

last resistors at each output to limit the LED current.

The switch/current mode and on/off controls for RGB are in

the RGB_ctrl register (00H).

wled1-4_pwm

wled5-6_pwm

r1_pwm

bit 7 PWM controls WLED 1-4

bit 6 PWM controls WLED 5-6

bit 5 PWM controls R1 output

bit 4 PWM controls G1 output

bit 3 PWM controls B1 output

bit 2 PWM controls R2 output

bit 1 PWM controls G2 output

bit 0 PWM controls B2 output

HC_Flash (10H)

g1_pwm

b1_pwm

r2_pwm

g2_pwm

b2_pwm

hc_pwm

bit 5 PWM controls FLASH

Note: If DISPL=1, wled1-4pwm controls WLED1-6

Note: Maximum external PWM frequency is 1kHz. If during the external

PWM control the internal PWM is on, the result will be product of both

functions.

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12

RGB_ctrl register (00H)

1

R1, G1 and B1 are switches → limit current with ballast resistor

R1, G1 and B1 are constant current sinks, current limited internally

CC_RGB1

bit7

0

1

R2, G2 and B2 are switches → limit current with ballast resistor

R2, G2 and B2 are constant current sinks, current limited internally

CC_RGB2

r1sw

bit6

bit5

bit4

bit3

bit2

bit1

bit0

0

1

0

1

0

1

0

1

0

1

0

1

0

R1 is on

R1 is off

G1 is on

G1 is off

B1 is on

B1 is off

R2 is on

R2 is off

G2 is on

G2 is off

B2 is on

B2 is off

g1sw

b1sw

r2sw

g2sw

b2sw

30008518

13

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Since registers are 8-bit long one command requires 2 write

cycles. Each command has intensity level for each LED, com-

mand execution time (CET) and transition time (TT) as seen

in the following figures.

Command Based Pattern Generator

for Color LEDs

The LP39542 has an unique stand-alone command based

pattern generator with 8 user controllable 16-bit commands.

30008519

COMMAND REGISTER WITH 8 COMMANDS

COMMAND 1

COMMAND 2

COMMAND 3

COMMAND 4

COMMAND 5

COMMAND 6

COMMAND 7

COMMAND 8

ADDRESS 50H

ADDRESS 51H

ADDRESS 52H

ADDRESS 53H

ADDRESS 54H

ADDRESS 55H

ADDRESS 56H

ADDRESS 57H

ADDRESS 58H

ADDRESS 59H

ADDRESS 5AH

ADDRESS 5BH

ADDRESS 5CH

ADDRESS 5DH

ADDRESS 5EH

ADDRESS 5FH

R2

CET1

R2

R1

CET0

R1

R0

B2

R0

B2

R0

B2

R0

B2

R0

B2

R0

B2

R0

B2

R0

B2

G2

B1

G2

B1

G2

B1

G2

B1

G2

B1

G2

B1

G2

B1

G2

B1

G1

B0

G1

B0

G1

B0

G1

B0

G1

B0

G1

B0

G1

B0

G1

B0

G0

TT2

G0

CET3

TT1

CET2

TT0

CET3

TT1

CET2

TT0

CET1

R2

CET0

R1

TT2

G0

CET3

TT1

CET2

TT0

CET1

R2

CET0

R1

TT2

G0

CET3

TT1

CET2

TT0

CET1

R2

CET0

R1

TT2

G0

CET3

TT1

CET2

TT0

CET1

R2

CET0

R1

TT2

G0

CET3

TT1

CET2

TT0

CET1

R2

CET0

R1

TT2

G0

CET3

TT1

CET2

TT0

CET1

R2

CET0

R1

TT2

G0

CET3

TT1

CET2

TT0

CET1

CET0

TT2

COLOR INTENSITY CONTROL

Each color has 3-bit intensity level. Level control is logarith-

mic, 2 curves are selectable. The LOG bit in register 11H

defines the curve used as seen in the following table.

R[2:0], G[2:0],

B[2:0]

CURRENT

[% × I_MAX(COLOR)

]

LOG=0

0

LOG=1

000

001

010

011

100

101

110

111

0

1

7

14

2

21

4

32

10

21

46

100

46

71

100

30008520

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14

COMMAND EXECUTION TIME (CET) AND TRANSITION TIME (TT)

The command execution CET time is the duration of one sin-

gle command. Command execution times CET are defined as

follows, when R_T=82kΩ:

CET [3:0]

1110

CET duration, ms

2949

3146

1111

CET [3:0]

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

CET duration, ms

197

Transition time TT is duration of transition from the previous

RGB value to programmed new value. Transition times TT

are defined as follows:

393

590

TT [2:0]

000

Transition time, ms

786

0

983

001

55

1180

1376

1573

1769

1966

2163

2359

2556

2753

010

110

221

442

885

1770

3539

011

100

101

110

111

The figure below shows an example of RGB CET and TT

times.

30008521

The command execution time also may be less than the transition time – the figure below illuminates this case.

30008522

15

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LOOP CONTROL

is 0000 0000 and 0000 0000 in one command register. The

loop will start from command 1 and continue until stopped by

writing rgb_start=0 or loop=0. The example of loop is shown

in following figure:

Pattern generator commands can be looped using the LOOP

bit (D1) in Pattern gen ctrl register (11H). If LOOP=1 the pro-

gram will be looped from the command 8 register or if there

30008523

SINGLE PROGRAM

If control bit LOOP=0 the program will start from Command 1

and run to either last command or to empty “0000 0000 / 0000

0000” command.

30008524

The LEDs maintain the brightness of the last command when

the single program stops. Changes in command register will

not be effective in this phase. The RGB_START bit has to be

toggled off and on to make changes effective.

START BIT

Pattern_gen_ctrl register’s RGB_START bit will enable

command execution starting from Command 1.

Pattern gen ctrl register (11H)

0 – Pattern generator disabled

1 – execution pattern starting from command 1

rgb_start

loop

Bit 2

Bit 1

Bit 0

0 – pattern generator loop disabled (single pattern)

1 – pattern generator loop enabled (execute until stopped)

0 – color intensity mode 0

1 – color intensity mode 1

log

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16

Audio Synchronization

The color LEDs connected to RGB outputs can be synchro-

nized to incoming audio with Audio Synchronization feature.

Audio Sync has 2 modes. Amplitude mode synchronizes

color LEDs based on input signal’s peak amplitude. In the

amplitude mode the user can select between 3 different am-

plitude mapping modes and 4 different speed configurations.

The frequency mode synchronizes the color LEDs based on

bass, middle and treble amplitudes (= low pass, band pass

and high pass filters). User can select between 2 different

frequency responses and 4 different speed configurations for

best audio-visual user experience. Programmable gain and

AGC function are also available for adjustment of input signal

amplitude to light response. The Audio Sync functionality is

described more closely below.

PWM signal with 3.3V amplitude. Active filters, such as a

Sallen-Key filter, may also be applied. An active filter gives

better stop-band attenuation and cut-off frequency can be

higher than for a RC-filter.

To make sure that the filter rolls off sufficiently quickly, con-

nect your filter circuit to the audio input(s), turn on the audio

synchronization feature, set manual gain to maximum, apply

the PWM signal to the filter input and keep an eye on LEDs.

If they are blinking without an audio signal (modulation), a

sharper roll-off after the cut-off frequency, more stop-band

attenuation, or smaller amplitude of the PWM signal is re-

quired.

AUDIO SYNCHRONIZATION SIGNAL PATH

LP39542 audio synchronization is mainly done digitally and it

consists of the following signal path blocks:

USING A DIGITAL PWM AUDIO SIGNAL AS AN AUDIO

SYNCHRONIZATION SOURCE

•

Input Buffers

AD Converter

DC Remover

If the input signal is a PWM signal, use a first or second order

low pass filter to convert the digital PWM audio signal into an

analog waveform. There are two parameters that need to be

known to get the filter to work successfully: frequency of the

PWM signal and the voltage level of the PWM signal. Sug-

gested cut-off frequency (-3 dB) should be around 2 kHz to 4

kHz and the stop-band attenuation at sampling frequency

should be around -48 dB or better. Use a resistor divider to

reduce the digital signal amplitude to meet the specification

of the analog audio input. Because a low-order low-pass filter

attenuates the high-frequency components from audio signal,

MODE_CTRL=01b selection is recommended when frequen-

cy synchronization mode is enabled. Application example 5

shows an example of a second order RC-filter for 29 kHz

Automatic Gain Control (AGC)

Programmable Gain

3 Band Digital Filter

Peak Detector

Look-up Tables (LUT)

Mode Selector

Integrators

PWM Generator

Output Drivers

30008525

The digitized input signal has DC component that is removed

by digital DC REMOVER (-3 dB @ 400 Hz). Since the light

response of input audio signal is very much amplitude de-

pendent the AGC adjusts the input signal to suitable range

automatically. User can disable AGC and the gain can be set

manually with PROGRAMMABLE GAIN. LP39542 has 2 au-

dio synchronization modes: amplitude and frequency. For

amplitude based synchronization the PEAK DETECTION

method is used. For frequency based synchronization 3

BAND FILTER separates high pass, low pass and band bass

signals. For both modes the predefined LUT is used to opti-

mize the audio visual effect. MODE SELECTOR selects the

synchronization mode. Different response times to music

beat can be selected using INTEGRATOR speed variables.

Finally PWM GENERATOR sets the driver FET duty cycles.

scribed in the Audio Synch table. The buffer is rail-to-rail input

operational amplifier connected as a voltage follower. DC lev-

el of the input signal is set by a simple resistor divider

INPUT SIGNAL TYPE AND BUFFERING

LP39542 supports single ended audio input as shown in the

figure below. The electric parameters of the buffer are de-

30008526

17

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AUDIO SYNCHRONIZATION ELECTRICAL PARAMETERS

Symbol Parameter

Conditions

Min

250

0.1

Typical

Max

Units

kΩ

Z_IN

A_IN

Input Impedance of ASE

500

Audio Input Level Range

(peak-to-peak)

Gain = 21 dB

Gain = 0 dB

V

V_DDA-0.1

f_3dB

Crossover Frequencies (-3 dB)

Narrow Frequency Response

Low Pass

Band Pass

High Pass

Low Pass

Band Pass

High Pass

0.5

1.0 and 1.5

2.0

kHz

Wide Frequency Response

1.0

2.0 and 3.0

4.0

CONTROL OF ADC AND AUDIO SYNCHRONIZATION

The following table describes the controls required for audio synchronization.

Audio_sync_CTRL1 (2AH)

Input signal gain control. Range 0...21 dB, step 3 dB:

[000] = 0 dB (default)

[001] = 3 dB

[011] = 9 dB

[100] = 12 dB

[101] = 15 dB

[110] = 18 dB

[111] = 21 dB

GAIN_SEL[2:0]

Bits 7-5

[010] = 6 dB

Synchronization mode selector.

SYNC_MODE

EN_AGC

Bit 4

Bit 3

SYNCMODE = 0 → Amplitude Mode (default)

SYNCMODE = 1 → Frequency Mode

Automatic Gain Control enable

1 = enabled

0 = disabled (Gain Select enabled) (default)

Audio synchronization enable

1 = Enabled

Note : If AGC is enabled, AGC gain starts from current GAIN_SEL gain value.

0 = Disabled (default)

EN_SYNC

Bit 2

[00] = Single ended input signal, ASE.

[01] = Temperature measurement

[10] = Ambient light measurement

[11] = No input (default)

INPUT_SEL[1:0]

Bits 1-0

Audio_sync_CTRL2 (2BH)

0 – averaging disabled (not applicable in audio sync mode)

1 – averaging enabled (not applicable in audio sync mode)

EN_AVG

Bit 4

MODE_CTRL[1:0]

Bits 3-2 See below: Mode control

Sets the LEDs light response time to audio input.

[00] = FASTEST (default)

[01] = FAST

[10] = MEDIUM

Bits 1-0

SPEED_CTRL[1:0]

[11] = SLOW

(For SLOW setting in amplitude mode f_MAX= 3.8 Hz,

Frequency mode f_MAX= 7.6 Hz)

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18

MODE CONTROL IN FREQUENCY MODE

based on the music type and light effect requirements. In the

first mode the frequency range extends to 8 kHz in the secont

to 4 kHz.

Mode control has two setups based on audio synchronization

mode select: the frequency mode and the amplitude mode.

During the frequency mode user can select two filter options

by MODE_CTRL as shown below. User can select the filters

The lowpass filter is used for the red, the bandpass filter for

the blue and the hipass filter for the green LED.

Higher frequency mode

MODE_CTRL = 00 and SYNC_MODE = 1

Lower frequency mode

MODE_CTRL = 01 and SYNC_MODE = 1

30008527

30008528

MODE CONTROL IN AMPLITUDE MODE

MODE_CTRL select. These three mapping options give dif-

ferent light response. The modes are presented in the follow-

ing graphs.

During the amplitude synchronization mode user can se-

lect between three different amplitude mappings by using

Non-overlapping mode

MODE_CTRL[1:0] = [01]

Partly overlapping mode

MODE_CTRL[1:0] = [00]

30008529

30008530

19

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Overlapping mode

MODE_CTRL[1:0] = [10]

Peak Input Signal Level

Range vs Gain Setting

30008532

30008531

2. Feed SYNC/PWM pin with 5 MHz clock

RGB Output Synchronization to

External Clock

By this the internal 5 MHz clock is disabled from pattern gen-

erator and flash timing circuitry.

The external clock signal frequency will fully determine the

timings related to RGB and Flash.

The RGB pattern generator and high current flash driver tim-

ing can be synchronized to external clock with following con-

figuration.

Note: The boost converter will use internal 5 MHz clock even

if the external clock is available.

1. Set PWM_SYNC bit in Enables register to 1

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20

synchronize outputs to get desired lighting effect. R1SW,

G1SW and B1SW bits can be used to enable and disable

outputs when wanted.

RGB LED Blinking Control

LP39542 has a possibility to drive indicator LEDs with RGB1

outputs with programmable blinking time. Blinking function is

enabled with RGB_SEL[1:0] bits set as 01b in 0BH register.

R1_CYCLE_EN, G1_CYCLE_EN and B1_CYCLE_EN bits in

cycle registers (02H, 04H and 06H) enable/disable blinking

function for corresponding output. When EN_BLINK bit is

written high in register 11H, the blinking sequences for all

outputs (which has CYCLE_EN bit enabled) starts simulta-

neously. EN_BLINK bit should be written high after selecting

wanted blinking sequences and enabling CYCLE_EN bits, to

RGB1 blinking sequence is set with R1, G1 and B1 blink reg-

isters (01H, 03H and 05H) by setting the appropriate OFF-ON

times. Blinking cycle times are set with R1_CYCLE[2:0],

G1_CYCLE[2:0] and B1_CYCLE[2:0] bits in R1, G1 and B1

CYCLE registers (02H, 04H and 06H). OFF/ON time is a per-

centage of the selected cycle time. Values for setting OFF/

ON time can be seen in following table.

R1, G1 and B1 Blink Registers (01H, 03H and 05H):

Name

Bit

Description

R1_ON[3:0], R1_OFF[3:0]

G1_ON[3:0], G1_OFF[3:0]

B1_ON[3:0], B1_OFF[3:0]

7-4, 3-0

RGB1 ON and OFF time

Bits

ON/OFF time

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

0%

1%

2.5%

5%

7.5%

10%

15%

20%

30%

40%

50%

60%

70%

80%

90%

100%

Blinking ON/OFF cycle is defined so that there will be first

OFF-period then ON-period after which follows an off-period

for the remaining cycle time that can not be set. If OFF and

ON times are together more than 100% the first OFF time will

be as set and the ON time is cut to meet 100%. For example,

if 50% OFF time is set and ON time is set greater than 50%,

only 50% ON time is used, the exceeding ON time is ignored.

If OFF and ON times are together less than 100% the re-

maining cycle time output is OFF.

30008570

21

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Values for setting the blinking cycle for RGB1 can be seen in

following table:

R1, G1 and B1 Cycle Registers (02H, 04H and 06H):

Name

Bit

Decription

R1_CYCLE_EN

G1_CYCLE_EN

B1_CYCLE_EN

3

Blinking enable

0 = disabled

1 = enabled, output state is defined with blinking

cycle

R1_CYCLE[2:0]

G1_CYCLE[2:0]

B1_CYCLE[2:0]

2-0

RGB1 cycle time

Bits

Blinking cycle

time

Blinking

frequency

000

001

010

011

100

101

110

111

0.1s

0.25s

0.5s

1s

10 Hz

4 Hz

2 Hz

1 Hz

2s

0.5 Hz

0.33 Hz

0.25 Hz

0.2 Hz

3s

4s

5s

PATTERN_GEN_CTRL Register (11H):

Name

Bit

Description

EN_BLINK

3

Blinking sequence start bit

0 = disabled

1 = enabled

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22

RGB Driver Electrical Characteristics (R1, G1, B1, R2, G2, B2 Outputs)

Symbol

Parameter

Condition

Min

Typ

Max

1

Units

I_LEAKAGE

R1, G1, B1, R2, G2, B2 pin leakage

current

0.1

μA

I_RGB

Maximum recommended sink current

CC mode

40

50

mA

%

SW mode

Accuracy @ 37mA

±5

R_RGB=3.3 kΩ ±1%, CC mode

CC mode

Current mirror ratio

1:100

±5

RGB1 and RGB2 current mismatch

Switch resistance

I_RGB=37mA, CC mode

SW mode

%

R_SW

f_RGB

2.5

5

Ω

kHz

RGB switching frequency

Accuracy proportional to internal clock 18.2

20

21.8

freq.

If SYNC to external 5 MHz clock is in

use

20

kHz

Note: RGB current should be limited as follows:

constant current mode – limit by external R_RGBresistor;

switch mode – limit by external ballast resistors

Output Current vs Pin Voltage (Current Sink Mode)

Pin Voltage vs Output Current (Switch Mode)

30008566

30008568

Output Current vs R_RGB(Current Sink Mode)

30008567

23

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Single High Current Driver

LP39542 has internal constant current driver that is capable

of driving high current LED, mainly targeted for FLASH LED

in camera phone applications.

HC[1:0] bits in the HC_Flash register control the FLASH cur-

rent as show in following table.

HC[1:0]

00

I(FLASH)

MAXIMUM CURRENT SETUP FOR FLASH

0.25 × I_MAX(FLASH)

0.50 × I_MAX(FLASH)

0.75 × I_MAX(FLASH)

1.00 × I_MAX(FLASH)

The user sets the maximum current of FLASH with R_FLASH

resistor based on following equation:

01

10

I_MAX= 300 × 1.23V / (R_FLASH+ 50Ω),

11

where

The figure below shows the internal structure for the FLASH

driver.

Imax = maximum flash current in Amps (ie. 0.3A)

1.23V = reference voltage

300 = internal current mirror multiplier

R_FLASH= Resistor value in Ohms

50Ω = Internal resistor in the I_FLASHinput

For example if 400mA is required for the maximum flash cur-

rent, R_FLASHequals to

R_FLASH= 300 × 1.23V / I_MAX– 50Ω = 369V / 0.4A – 50Ω =

873Ω e.g. 910Ω resistor can be used

CURRENT CONTROL FOR FLASH

To minimize the internal current consumption, the flash func-

tion has an enable bit EN_HCFLASH in the HC_Flash regis-

ter.

EN_

HCFLASH

MODE

30008533

FLASH disabled, no extra current

consumption through R_FLASH

FLASH TIMING

0

Flash output is turned on in lower current View finder mode

when the EN_HCFLASH bit is written high. The actual flash

at maximum current starts when the FLASH_EN digital input

pin goes high. The Flash length can be selected from 3 pre-

defined values or the FLASH_EN pin pulse length can deter-

mine how long the flash pulse is. After flash pulse the flash is

shut down completely. To enable flash again, EN_HCFLASH

bit must be set to 0 and then 1.The pulse length is controlled

by the FT_T[1:0] bits in register 10H as show in the table be-

low.

FLASH enabled, IFLASH set by

HC_SW[1:0] (see below)

1

Current during view finder/

FL_T[1:0]

Flash duration typ

Current during FLASH

focusing

00

01

10

11

200ms

400ms

Set by HC[1:0]

HC[11] = I_MAX(FLASH)

600ms

EN_FLASH on duration

After the flash pulse the EN_HCFLASH bit has to be written

low, the LP39542 does not clear this bit automatically. If 11b

is selected in the FL_T[1:0] register, then it is possible to use

safety bit EN_SAFETY in register 10H. When EN_SAFETY

is 1, then the flash is shut down automatically, if the

FLASH_EN pulse duration is longer than 1.2 seconds (typ.).

This prevents any damage to the application circuitry, if the

FLASH_EN pin is stuck high because of user or program er-

ror.

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24

The following figure shows the functionality of the built-in flash

30008534

Flash LED can be controlled also with external PWM signal:

HC_FLASH Register (10H):

Description

Name

Bit

Flash external PWM control

HC_PWM

5

0 = Flash external PWM control disabled

1 = Flash external PWM control enabled

High Current Driver Electrical Characteristics

Symbol

I_LEAKAGE

I_MAX(FLASH)

Parameter

Condition

Min

Typ

Max

2

Units

μA

FLASH pin leakage current

Maximum Sink Current

0.1

400

mA

-10

-5

10

5

Accuracy

R_FLASH= 910Ω

%

s

Current mirror ratio

Flash safety time

1:300

1.2

t_SAFETY

EN_SAFETY = 1, FL_T = 11b

25

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Backlight Drivers

LP39542 has 2 independent backlight drivers. Both drivers

are regulated constant current sinks. LED current for both

LED banks (WLED1…4 and WLED5…6) are controlled by 8-

bit current mode DACs with 0.1 mA step.

DISPL

Configuration

Matching

Main display up

to 4 LEDs

Good btw

WLED1…4

Good btw

0

Sub display up

to 2 LEDs

WLED1…4 and WLED5…6 can be also controlled with one

DAC for better matching allowing the use of larger displays

having up to 6 white LEDs in parallel.

WLED5…6

Large display

up to 6 LEDs

Good btw

WLED 1…6

1

Display configuration is controlled with DISPL bit as shown in

the following table.

30008535

30008536

Main display up to 4 LEDs (WLED1…4)

Sub display driver up to 2 LEDs (WLED5…6)

30008537

Main display up to 6 LEDs (WLED1…6) (DISPL=1)

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26

FADE IN / FADE OUT

slope of the fade curve. The fading times are shown in the

graphs, which corresponds the full range current change

(0-255). Note that when large display mode is selected (DIS-

PL = 1), then EN_FADE_W5_6 and SLOPE_W5_6 bits do not

have any effect.

LP39542 has an automatic fade in and out for main and sub

backlight. The fade function is enabled to main and sub back-

lights with EN_FADE_W1_4 and EN_FADE_W5_6 register

bits. Register bits SLOPE_W1_4 and SLOPE_W5_6 set the

WLED dimming, SLOPE=0

WLED dimming, SLOPE=1

30008539

30008540

WLED Control Register (08H):

Name

Bit

Description

Slope for WLED5-6

SLOPE_W5_6

6

0 = Full range fade execution time 1.30s

1 = Full range fade execution time 0.65s

Slope for WLED1-4

SLOPE_W1_4

EN_FADE_W5_6

EN_FADE_W1_4

5

4

3

0 = Full range fade execution time 1.30s

1 = Full range fade execution time 0.65s

Enable fade for WLED5-6

0 = Fade disabled

1 = Fade enabled

Enable fade for WLED1-4

0 = Fade disabled

1 = Fade enabled

Large display mode enable

0 = WLED1-4 and WLED5-6 are controlled

separately

DISPL

2

1 = WLED1-4 and WLED5-6 are controlled with

WLED1-4 controls

Enable WLED1-4

EN_W1_4

EN_W5_6

1

0

0 = WLED1-4 disabled

1 = WLED1-4 enabled

Enable WLED5-6

0 = WLED5-6 disabled

1 = WLED5-6 enabled

27

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WLED Output Current vs. Voltage

ADJUSTMENT

WLED1-4[7:0]

Driver current,

mA (typical)

WLED5-6[7:0]

0000 0000

0000 0001

0000 0010

0000 0011

…

0

0.1

0.2

0.3

…

1111 1101

1111 1110

1111 1111

25.3

25.4

25.5

30008538

Backlight Driver Electrical Characteristics

Symbol

I_MAX

Parameter

Maximum Sink Current

Leakage Current

Conditions

Min Typical Max

Units

21.3

25.5

0.03

12.8

29.4

1

mA

I_leakage

I_WLED1

μA

mA

%

WLED1 Current tolerance

I_WLED1set to 12.8 mA (80H)

10.52

-18

14.78

+16

I_match1-4

I_match5-6

I_match1-6

Sink Current Matching

I_SINK= 13 mA, Between WLED1…4

I_SINK= 13 mA, Between WLED5…6

I_SINK= 13 mA, Between WLED1…6

0.2

0.3

%

Note: Matching is the maximum difference from the average.

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28

Ambient Light and Temperature Measurement with LP39542

The Analog-to-Digital converter (ADC) in the Audio Syn-

cronization block can be also used for ambient light measure-

ment or temperature measurement.

The selection between these modes is controlled with input

selector bits INPUT_SEL[1:0] in register 2AH as seen on the

following table. Internal averaging function can be used to fil-

ter unwanted noise from the measured signal. Averaging

function can be enabled with EN_AVG bit in register 2BH.

INPUT_SEL[1:0]

Mode

00

Audio synchronization

Temperature measurement

(voltage input)

01

Ambient light measurement

(current input)

10

11

No input

30008564

Averaging disabled. f_sample= 122 Hz,

data in register changes every 8.2 ms.

EN_AVG = 0

EN_AVG = 1

ADC Code vs Input Current

in Light Measurement Mode

Averaging enabled. f_sample= 244 Hz,

averaging of 64 samples, data in

register changes every 262 ms

(3.2Hz).

TEMPERATURE MEASUREMENT

The temperature measurement requires two external compo-

nents: resistor and thermistor (resistor that has known tem-

perature vs resistance curve). The ADC reads the voltage

level at ASE pin and converts the result into a digital word.

User can read the ADC output from register. The known tem-

perature allows for example to monitor the temperature inside

the display module and decrease the current level of the LEDs

if temperature raises too high. This function may increase

lifetime of LEDs in some applications.

AMBIENT LIGHT MEASUREMENT

The ambient light measurement requires only one external

component: Ambient light sensor (photo transistor or diode).

The ADC reads the current level at ASE pin and converts the

result into a digital word. User can read the ADC output from

the ADC output register. The known ambient light condition

allows user to set the backlight current to optimal level thus

saving power especially in low light and bright sunlight con-

dition.

30008542

Temperature sensor connection example

30008541

ASE Input Configuration for Light Measurement

29

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EXAMPLE TEMP SENSOR READING AT DIFFERENT

TEMPERATURES (R_25°C= 1MΩ)

T(°C)

-40

0

V(ASE)

2.7540984

2.24

R(MΩ)

Rt(MΩ)

60

1

4

25

1

1.4

60

0.2

0.04

0.4666667

0.1076923

100

30008563

ADC Code vs Input Voltage

in temperature measurement mode

30008543

Example curve for thermistor

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30

ommended connection is as shown in the picture below.

Internally both logic and analog circuitry works at 2.8V supply

voltage. Both supply voltage pins should have separate filter-

ing capacitors.

7V Shielding

To shield LP39542 from high input voltages 6…7.2V the use

of external 2.8V LDO is required. This 2.8V voltage protects

internally the device against high voltage condition. The rec-

30008544

In cases where high voltage is not an issue the connection is

as shown below

30008545

31

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Logic Interface Electrical Characteristics

(1.65V ≤ V_DDIO≤ V_DD1,2V) (Unless otherwise noted).

Symbol

Parameter

Conditions

Min

Typ

Max

Units

LOGIC INPUTS ADDR_SEL, NRST, SCL, SYNC_PWM, FLASH_EN, SDA

V_IL

V_IH

I_L

Input Low Level

Input High Level

Logic Input Current

Clock Frequency

0.2×V_DDIO

V

0.8×V_DDIO

−1.0

1.0

μA

kHz

f_SCL

400

LOGIC OUTPUT SDA

V_OL

I_L

I_SDA= 3 mA

Output Low Level

0.3

0.5

1.0

V

Output Leakage Current V_SDA= 2.8V

μA

Note: Any unused digital input pin has to be connected to GND to avoid floating and extra current consumption.

I²C Compatible Interface

INTERFACE BUS OVERVIEW

STOP condition is defined as the SDA transitioning from LOW

to HIGH while SCL is HIGH. The I²C master always generates

START and STOP bits. The I²C bus is considered to be busy

after START condition and free after STOP condition. During

data transmission, I²C master can generate repeated START

conditions. First START and repeated START conditions are

equivalent, function-wise.

The I²C compatible synchronous serial interface provides ac-

cess to the programmable functions and registers on the

device. This protocol uses a two-wire interface for bi-direc-

tional communications between the devices connected to the

bus. The two interface lines are the Serial Data Line (SDA),

and the Serial Clock Line (SCL). These lines should be con-

nected to a positive supply, via a pull-up resistor and remain

HIGH even when the bus is idle. Every device on the bus is

assigned a unique address and acts as either a Master or a

Slave depending on whether it generates or receives the se-

rial clock (SCL).

DATA TRANSACTIONS

One data bit is transferred during each clock pulse. Data is

sampled during the high state of the serial clock (SCL). Con-

sequently, throughout the clock’s high period, the data should

remain stable. Any changes on the SDA line during the high

state of the SCL and in the middle of a transaction, aborts the

current transaction. New data should be sent during the low

SCL state. This protocol permits a single data line to transfer

both command/control information and data using the syn-

chronous serial clock.

30008550

TRANSFERRING DATA

Every byte put on the SDA line must be eight bits long, with

the most significant bit (MSB) being transferred first. Each

byte of data has to be followed by an acknowledge bit. The

acknowledge related clock pulse is generated by the master.

The transmitter releases the SDA line (HIGH) during the ac-

knowledge clock pulse. The receiver must pull down the SDA

line during the 9^thclock pulse, signifying an acknowledge. A

receiver which has been addressed must generate an ac-

knowledge after each byte has been received.

I²C DATA VALIDITY

The data on SDA line must be stable during the HIGH period

of the clock signal (SCL). In other words, state of the data line

can only be changed when CLK is LOW.

After the START condition, the I²C master sends a chip ad-

dress. This address is seven bits long followed by an eighth

bit which is a data direction bit (R/W). The LP39542 address

is 54h or 55H as selected with ADDR_SEL pin. I²C address

for LP39542 is 54H when ADDR_SEL=0 and 55H when

ADDR_SEL=1. For the eighth bit, a “0” indicates a WRITE

and a “1” indicates a READ. The second byte selects the reg-

ister to which the data will be written. The third byte contains

data to write to the selected register.

30008549

I²C Signals: Data Validity

I²C START AND STOP CONDITIONS

START and STOP bits classify the beginning and the end of

the I²C session. START condition is defined as SDA signal

transitioning from HIGH to LOW while SCL line is HIGH.

30008551

I²C Chip Address

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32

Register changes take an effect at the SCL rising edge during the last ACK from slave.

30008552

w = write (SDA = “0”)

r = read (SDA = “1”)

ack = acknowledge (SDA pulled down by either master or slave)

rs = repeated start

id = 7-bit chip address, 54H (ADDR_SEL=0) or 55H (ADDR_SEL=1) for LP39542.

I²C Write Cycle

When a READ function is to be accomplished, a WRITE function must precede the READ function, as shown in the Read Cycle

waveform.

30008553

I²C Read Cycle

30008554

I²C Timing Diagram

33

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I²C Timing Parameters

V_DD1,2= 3.0 to 4.5V, V_{DD_IO}= 1.65V to V_DD1,2

Symbol

Parameter

Limit

Units

Min

0.6

1.3

600

300

0

Max

1

2

Hold Time (repeated) START Condition

μs

ns

μs

pF

Clock Low Time

3

Clock High Time

4

Setup Time for a Repeated START Condition

Data Hold Time (Output direction, delay generated by LP39542)

Data Hold Time (Input direction, delay generated by the Master)

Data Setup Time

5

900

5

6

100

7

Rise Time of SDA and SCL

20+0.1C_b

15+0.1C_b

600

300

8

Fall Time of SDA and SCL

9

Set-up Time for STOP condition

10

C_b

Bus Free Time between a STOP and a START Condition

Capacitive Load for Each Bus Line

1.3

10

200

NOTE: Data guaranteed by design

Autoincrement mode is available, with this mode it is possible to read or write bytes with autoincreasing addresses. LP39542 has

empty spaces in address register map, and it is recommended to use autoincrement mode only for writing in pattern command

registers.

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34

Recommended External Components

OUTPUT CAPACITOR, C_OUT

than the peak inductor current (ca. 1A). Average current rating

of the schottky diode should be higher than maximum output

current (400 mA). Schottky diodes with a low forward drop

and fast switching speeds are ideal for increasing efficiency

in portable applications. Choose a reverse breakdown of the

schottky diode larger than the output voltage. Do not use or-

dinary rectifier diodes, since slow switching speeds and long

recovery times cause the efficiency and the load regulation to

suffer.

The output capacitor C_OUTdirectly affects the magnitude of

the output ripple voltage. In general, the higher the value of

C_OUT, the lower the output ripple magnitude. Multilayer ce-

ramic capacitors with low ESR are the best choice. At the

lighter loads, the low ESR ceramics offer a much lower Vout

ripple that the higher ESR tantalums of the same value. At the

higher loads, the ceramics offer a slightly lower Vout ripple

magnitude than the tantalums of the same value. However,

the dv/dt of the Vout ripple with the ceramics is much lower

than the tantalums under all load conditions. Capacitor volt-

age rating must be sufficient, 10V or greater is recommended.

INDUCTOR, L₁

The LP39542’s high switching frequency enables the use of

the small surface mount inductor. A 4.7 μH shielded inductor

is suggested for 2 MHz operation, 10 μH should be used at 1

MHz. The inductor should have a saturation current rating

higher than the peak current it will experience during circuit

operation (ca. 1A). Less than 300 mΩ ESR is suggested for

high efficiency. Open core inductors cause flux linkage with

circuit components and interfere with the normal operation of

the circuit. This should be avoided. For high efficiency,

choose an inductor with a high frequency core material such

as ferrite to reduce the core losses. To minimize radiated

noise, use a toroid, pot core or shielded core inductor. The

inductor should be connected to the SW pin as close to the

IC as possible. Examples of suitable inductors are: TDK

VLF4012AT-4R7M1R1 and Panasonic ELLVEG4R7N.

Some ceramic capacitors, especially those in small pack-

ages, exhibit a strong capacitance reduction with the

increased applied DC voltage, so called DC bias effect.

The capacitance value can fall to below half of the nom-

inal capacitance. Too low output capacitance will in-

crease noise and it can make the boost converter

unstable. Recommended maximum DC bias effect at 5V

DC voltage is -50%.

INPUT CAPACITOR, C_IN

The input capacitor C_INdirectly affects the magnitude of the

input ripple voltage and to a lesser degree the V_OUTripple. A

higher value C_INwill give a lower V_INripple. Capacitor voltage

rating must be sufficient, 10V or greater is recommended.

OUTPUT DIODE, D₁

A schottky diode should be used for the output diode. Peak

repetitive current rating of the schottky diode should be larger

LIST OF RECOMMENDED EXTERNAL COMPONENTS

Symbol

C_VDD1

C_VDD2

C_VDDIO

C_VDDA

C_OUT

C_IN

Symbol explanation

Value

100

1

Unit

nF

Type

Ceramic, X7R / X5R

Ceramic, X7R / X5R, 10V

Ceramic, X7R / X5R

Shielded, low ESR, Isat 1A

Ceramic, X7R

C between VDD1 and GND

C between VDD2 and GND

C between VDDIO and GND

C between VDDA and GND

C between FB and GND

nF

μF

μH

nF

10

C between battery voltage and GND

L between SW and V_BATat 2 MHz

C between V_REFand GND

C between V_DDIOand GND

R between I_FLASHand GND

R between I_RGBand GND

10

L₁

4.7

100

1.2

5.6

82

C_VREF

C_VDDIO

R_FLASH

R_RBG

R_RT

Ceramic, X7R

±1%

kΩ

V

±1%

R between I_RTand GND

±1%

D₁

Rectifying Diode (Vf @ maxload)

C between Audio input and ASE

0.3

100

Schottky diode

C_ASE

nF

Ceramic, X7R / X5R

LEDs

D_LIGHT

User defined

TDK BSC2015

Light Sensor

35

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Application Examples

EXAMPLE 1

30008555

MAIN BACKLIGHT

—

SUB BACKLIGHT

AUDIO SYNCHRONIZED FUNLIGHTS

RGB INDICATION LIGHT

FLASH LED

—

FLIP PHONE

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36

EXAMPLE 2

30008556

6 WHITE LED BACKLIGHT

—

KEYPAD LIGHTS

RGB INDICATION LED

WHITE SINGLE LED FLASH

TEMPERATURE SENSOR

SMART PHONE

37

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EXAMPLE 3

30008557

MAIN BACKLIGHT

—

KEYPAD LIGHTS

AUDIO SYNCHRONIZED FUNLIGHTS

VIBRA

CANDYBAR PHONE

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38

EXAMPLE 4

30008565

MAIN BACKLIGHT

—

SUB BACKLIGHT

AUDIO SYNCHRONIZED FUNLIGHTS

RGB INDICATION LIGHT

There may be cases where the audio input signal going into the LP39542 is too weak for audio synchronization. This figure presents a single-supply inverting

amplifier connected to the ASE input for audio signal amplification. The amplification is +20 dB, which is well enough for 20 mVp-p audio signal. Because the

amplifier (LMV321) is operating in single supply voltage, a voltage divider using R3 and R4 is implemented to bias the amplifier so the input signal is within the

input common-mode voltage range of the amplifier. The capacitor C1 is placed between the inverting input and resistor R1 to block the DC signal going into the

audio signal source. The values of R1 and C1 affect the cutoff frequency, fc = 1/(2π*R1*C1), in this case it is around 160 Hz. As a result, the LMV321 output

signal is centered around mid-supply, that is V_DDA/2. The output can swing to both rails, maximizing the signal-to-noise ratio in a low voltage system

USING EXTRA AMPLIFIER

39

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EXAMPLE 5

30008569

MAIN BACKLIGHT

—

SUB BACKLIGHT

AUDIO SYNCHRONIZED FUNLIGHTS

RGB INDICATION LIGHT

Here, a second order RC-filter is used on the ASE input to convert a PWM signal to an analog waveform.

USING PWM SIGNAL

More application information is available in the document "LP39542 Evaluation Kit".

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40

41

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42

43

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LP39542 Registers

REGISTER BIT EXPLANATIONS

Each register is shown with a key indicating the accessibility of the each individual bit, and the initial condition:

Register Bit Accessibility and Initial Condition

Key

rw

Bit Accessibility

Read/write

r

Read only

–0,–1

Condition after POR

RGB CTRL (00H) – RGB LEDS CONTROL REGISTER

D7

cc_rgb1

rw-1

D6

cc_rgb2

rw-1

D5

D4

D3

D2

D1

D0

r1sw

rw-0

g1sw

rw-0

b1sw

rw-0

r2sw

rw-0

g2sw

rw-0

b2sw

rw-0

0 - R1, G1 and B1 are constant current sinks, current limited internally

1 - R1, G1 and B1 are switches, limit current with external ballast resistor

cc_rgb1 Bit 7

cc_rgb2 Bit 6

0 – R2, G2 and B2 are constant current sinks, current limited internally

1 – R2, G2 and B2 are switches, limit current with external ballast resistor

0 – R1 disabled

1 – R1 enabled

r1sw

g1sw

b1sw

r2sw

g2sw

b2sw

Bit 5

Bit 4

0 – G1 disabled

1 – G1 enabled

Bit 3 0 – B1 disabled

1 – B1 enabled

0 – R2 disabled

Bit 2

1 – R2 enabled

0 – G2 disabled

Bit 1

1 – G2 enabled

0 – B2 disabled

Bit 0

1 – B2 enabled

R1/G1/B1 BLINK (01H, 03H, 05H) – BLINKING ON/OFF TIME CONTROL REGISTER

D7

D6

R1/G1/B1_ON[3:0]

rw-0 rw-0

D5

D4

D3

D2

R1/G1/B1_OFF[3:0]

rw-0 rw-0

D1

D0

rw-0

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44

RGB1 ON and OFF time

Bits

ON/OFF time

0%

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

1%

2.5%

5%

7.5%

10%

15%

20%

30%

40%

50%

60%

70%

80%

90%

100%

R1_ON[3:0],

R1_OFF[3:0]

G1_ON[3:0],

G1_OFF[3:0]

B1_ON[3:0],

B1_OFF[3:0]

Bits 7-4, 3-0

R1/G1/B1 CYCLE(02H, 04H, 06H) – BLINKING CYCLE CONTROL REGISTER

D7

D6

D5

D4

D3

D2

D1

D0

R1/G1/

R1/G1/B1_CYCLE[2:0]

B1_CYCLE_EN

r-0

rw-0

R1_CYCLE_EN

G1_CYCLE_EN

B1_CYCLE_EN

Bit 3

Blinking enable

0 = disabled, output state is defined with RGB registers

1 = enabled, output state is defined with blinking cycle

R1_CYCLE[2:0]

G1_CYCLE[2:0]

B1_CYCLE[2:0]

Bits 2-0

RGB1 cycle time

Bits

000

001

010

011

100

101

110

111

Blinking cycle time

Blinking frequency

10 Hz

0.1s

0.25s

0.5s

1s

4 Hz

2 Hz

1 Hz

2s

0.5 Hz

3s

0.33 Hz

0.25 Hz

0.2 Hz

4s

5s

45

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EXT_PWM_CONTROL (07H) – EXTERNAL PWM CONTROL REGISTER

D7

wled1_4_pwm wled5_6_pwm

rw-0 rw-0

D6

D5

r1_pwm

rw-0

D4

g1_pwm

rw-0

D3

b1_pwm

rw-0

D2

r2_pwm

rw-0

D1

g2_pwm

rw-0

D0

b2_pwm

rw-0

0 – WLED1…WLED4 PWM control disabled

1 – WLED1…WLED4 PWM control enabled

wled1_4_pwm

wled5_6_pwm

r1_pwm

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0 – WLED5, WLED6 PWM control disabled

1 – WLED5, WLED6 PWM control enabled

0 – R1 PWM control disabled

1 – R1 PWM control enabled

0 – G1 PWM control disabled

1 – G1 PWM control enabled

g1_pwm

0 – RB PWM control disabled

1 – B1 PWM control enabled

b1_pwm

0 – R2 PWM control disabled

1 – R2 PWM control enabled

r2_pwm

0 – G2 PWM control disabled

1 – G2 PWM control enabled

g2_pwm

0 – B2 PWM control disabled

1 – B2 PWM control enabled

b2_pwm

WLED CONTROL (08H) – WLED CONTROL REGISTER

D7

r-0

D6

D5

D4

D3

D2

D1

en_w1_4

rw-0

D0

en_w5_6

rw-0

slope_w5_6 slope_w1_4 en_fade_w5_6 en_fade_w1_4

displ

rw-0

0 – WLED5-6 full range fade execution time 1.3s

1 – WLED5-6 full range fade execution time 0.65s

slope_w5_6

slope_w1_4

en_fade_w5_6

en_fade_w1_4

displ

Bit 6

0 – WLED1-4 full range fade execution time 1.3s

1 – WLED1-4 full range fade execution time 0.65s

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0 – disable fade for WLED5-6

1 – enable fade for WLED5-6

0 – disable fade for WLED1-4

1 – enable fade for WLED1-4

0 – WLED1-4 and WLED5-6 are controlled separately

1 – WLED1-4 and WLED5-6 are controlled with WLED1-4 controls

0 – WLED1-4 disabled

1 – WLED1-4 enabled

en_w1_4

0 – WLED5-6 disabled

1 – WLED5-6 enabled

en_w5_6

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WLED1-4 (09H) – WLED1…WLED4 BRIGHTNESS CONTROL REGISTER

D7

D6

D5

D4

D3

D2

D1

D0

wled1_4[7:0]

rw-0

Adjustment

wled1_4[7:0]

0000 0000

0000 0001

0000 0010

0000 0011

0000 0100

…

Typical driver current (mA)

0

0.1

0.2

0.3

0.4

…

wled1_4[7:0] Bits 7-0

1111 1101

1111 1110

1111 1111

25.3

25.4

25.5

WLED5-6 (0AH) – WLED5, WLED6 BRIGHTNESS CONTROL REGISTER

D7

D6

D5

D4

D3

D2

D1

D0

wled5_6[7:0]

rw-0

Adjustment

wled5_6[7:0]

0000 0000

0000 0001

0000 0010

0000 0011

0000 0100

…

Typical driver current (mA)

0

0.1

0.2

0.3

0.4

…

wled5_6[7:0] Bits 7-0

1111 1101

1111 1110

1111 1111

25.3

25.4

25.5

47

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ENABLES (0BH) – ENABLES REGISTER

D7

pwm_sync

rw-0

D6

D5

en_boost

rw-0

D4

r-0

D3

r-0

D2

en_autoload

rw-1

D1

D0

nstby

rw-0

rgb_sel[1:0]

rw-0

0 – synchronization to external clock disabled

1 – synchronization to external clock enabled

pwm_sync

Bit 7

Bit 6

Bit 5

Bit 2

0 – LP39542 standby mode

1 – LP39542 active mode

nstby

0 – boost converter disabled

1 – boost converter enabled

en_boost

en_autoload

0 – internal boost converter loader off

1 – internal boost converter loader on

Color LED control mode selection

rgb_sel[1:0]

Audio sync

Pattern generator

Blinking sequence

00

01

10

11

-

RGB1 & RGB2

-

rgb_sel[1:0]

Bits 1-0

-

RGB2

RGB1

-

RGB1

RGB2

-

RGB1 & RGB2

ADC_OUTPUT (0CH) – ADC DATA REGISTER

D7

r-0

D6

r-0

D5

r-0

D4

r-0

D3

D2

r-0

D1

r-0

D0

r-0

data[7:0]

r-0

data[7:0]

Bits 7-0

Data register ADC (Audio input, light or temperature sensors)

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BOOST_OUTPUT (0DH) – BOOST OUTPUT VOLTAGE CONTROL REGISTER

D7

D6

D5

D4

D3

D2

D1

D0

Boost[7:0]

rw-0

rw-1

Adjustment

Boost[7:0]

Typical boost output (V)

0000 0000

0000 0001

0000 0011

0000 0111

0000 1111

0001 1111

0011 1111

0111 1111

1111 1111

4.00

4.25

4.40

Boost[7:0]

Bits 7-0

4.55

4.70

4.85

5.00 (default)

5.15

5.30

BOOST_FRQ (0EH) – BOOST FREQUENCY CONTROL REGISTER

D7

r-0

D6

r-0

D5

r-0

D4

r-0

D3

r-0

D2

D1

D0

freq_sel[2:0]

rw-1

Adjustment

freq_sel[2:0]

Frequency

2.00 MHz

1.67 MHz

1.00 MHz

freq_sel[2:0]

Bits 7-0

1xx

01x

00x

49

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HC_FLASH (10H) – HIGH CURRENT FLASH DRIVER CONTROL REGISTER

D7

r-0

D6

en_safety

rw-0

D5

hc_pwm

rw-0

D4

D3

D2

D1

D0

en_hcflash

rw-0

fl_t[1:0]

hc[1:0]

rw-0

0 - flash timeout feature disabled

1 - flash timeout feature enabled

en_safety

Bit 6

Bit 5

0 – ext. PWM for high current flash driver disabled

1 – ext. PWM for high current flash driver enabled

hc_pwm

Flash duration for high current driver

fl_t[1:0]

00

Typical flash duration

200 ms

fl_t[1:0]

Bits 4-3

01

400 ms

10

600 ms

11

EN_FLASH pin on duration

Current control for high current flash driver

hc[1:0]

current

00

01

10

11

0.25×I_MAX(FLASH)

0.50×I_MAX(FLASH)

0.75×I_MAX(FLASH)

1.00×I_MAX(FLASH)

hc[1:0]

Bits 2-1

Bit 0

0 – high current flash driver disabled

1 – high current flash driver enabled

en_hcflash

PATTERN_GEN_CTRL (11H) – PATTERN GENERATOR CONTROL REGISTER

D7

r-0

D6

r-0

D5

r-0

D4

r-0

D3

en_blink

rw-0

D2

rgb_start

rw-0

D1

D0

log

loop

rw-0

0 - blinking sequences start bit disabled

1 - blinking sequences start bit enabled

en_blink

rgb_start

loop

Bit 3

0 – pattern generator disabled

1 – execution pattern starting from command 1

Bit 2

Bit 1

Bit 0

0 – pattern generator loop disabled (single pattern)

1 – pattern generator loop enabled (execute until stopped)

0 – color intensity mode 0

1 – color intensity mode 1

log

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50

RGB1_MAX_CURRENT (12H) – RGB1 DRIVER INDIVIDUAL MAXIMUM CURRENT CONTROL REGISTER

D7

r-0

D6

r-0

D5

D4

D3

D2

D1

D0

ir1[1:0]

ig1[1:0]

ib1[1:0]

rw-0

Maximum current for R1 driver

ir1[2:0]

00

Maximum output current

0.25×I_MAX

ir1[1:0]

ig1[1:0]

ib1[1:0]

Bits 5-4

Bits 3-2

Bits 1-0

01

0.50×I_MAX

10

0.75×I_MAX

11

1.00×I_MAX

Maximum current for G1 driver

ig2[1:0]

Maximum output current

00

01

10

11

0.25×I_MAX

0.50×I_MAX

0.75×I_MAX

1.00×I_MAX

Maximum current for B1 driver

ib1[1:0]

00

Maximum output current

0.25×I_MAX

01

0.50×I_MAX

10

0.75×I_MAX

11

1.00×I_MAX

51

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RGB2_MAX_CURRENT (13H) – RGB2 DRIVER INDIVIDUAL MAXIMUM CURRENT CONTROL REGISTER

D7

r-0

D6

r-0

D5

D4

D3

D2

D1

D0

ir2[1:0]

ig2[1:0]

ib2[1:0]

rw-0

Maximum current for R2 driver

ir2[2:0]

00

Maximum output current

0.25×I_MAX

ir2[1:0]

ig2[1:0]

ib2[1:0]

Bits 5-4

Bits 3-2

Bits 1-0

01

0.50×I_MAX

10

0.75×I_MAX

11

1.00×I_MAX

Maximum current for G2 driver

ig2[1:0]

Maximum output current

00

01

10

11

0.25×I_MAX

0.50×I_MAX

0.75×I_MAX

1.00×I_MAX

Maximum current for B2 driver

ib2[1:0]

00

Maximum output current

0.25×I_MAX

01

0.50×I_MAX

10

0.75×I_MAX

11

1.00×I_MAX

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AUDIO_SYNC_CTRL1 (2AH) – AUDIO SYNCHRONIZATION AND ADC CONTROL REGISTER 1

D7

D6

gain_sel[2:0]

rw-0

D5

D4

sync_mode

rw-0

D3

en_agc

rw-0

D2

en_sync

rw-0

D1

D0

input_sel[1:0]

rw-0

rw-1

Input signal gain control

gain_sel[2:0]

000

gain, dB

0 (default)

001

3

6

010

gain_sel[2:0]

Bits 7-5

011

9

100

12

15

18

21

101

110

111

Input filter mode control

0 – Amplitude mode

sync_mode

Bit 4

1 – Frequency mode

0 – automatic gain control disabled

1 – automatic gain control enabled

en_agc

Bit 3

Bit 2

0 – audio synchronization disabled

1 – audio synchronization enabled

en_sync

ADC input selector

input_sel[1:0]

Input

00

01

10

11

Single ended input signal (ASE)

Temperature measurement

Ambient light measurement

No input (default)

input_sel[1:0]

Bits 1-0

AUDIO_SYNC_CTRL2 (2BH) – AUDIO SYNCHRONIZATION AND ADC CONTROL REGISTER 2

D7

r-0

D6

r-0

D5

r-0

D4

en_avg

rw-0

D3

D2

D1

D0

mode_ctrl[1:0]

speed_ctrl[1:0]

rw-0

0 – averaging disabled. f_sample= 122 Hz, data in

register changes every 8.2 ms.

en_avg

Bit 4

1 – averaging enabled. f_sample= 244 Hz, averaging of

64 samples, data in register changes every 262 ms

(3.2Hz).

mode_ctrl[1:0]

speed_ctrl[1:0]

Bits 3-2 Filtering mode control

LEDs light response time to audio input

speed_ctrl[1:0]

Response

FASTEST (default)

FAST

00

01

10

11

Bits 1-0

MEDIUM

SLOW

53

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PATTERN CONTROL REGISTERS

Command_[1:8]A – Pattern Control Register A

D7

D6

D5

D4

D3

D2

D1

D0

r[2:0]

rw-0

g[2:0]

rw-0

cet[3:2]

rw-0

Command_[1:8]B – Pattern Control Register B

D7

D6

D5

D4

D3

D2

D1

D0

cet[1:0]

b[2:0]

rw-0

tt[2:0]

rw-0

Red color intensity

current, %

r[2:0]

log=0

log=1

000

001

010

011

100

101

110

111

0×I_MAX

1%×I_MAX

2%×I_MAX

4%×I_MAX

10%×I_MAX

21%×I_MAX

46%×I_MAX

100%×I_MAX

7%×I_MAX

Bits

7-5A

14%×I_MAX

21%×I_MAX

32%×I_MAX

46%×I_MAX

71%×I_MAX

100%×I_MAX

Green color intensity

r[2:0]

g[2:0]

current, %

log=0

log=1

0×I_MAX

000

001

010

011

100

101

110

111

0×I_MAX

7%×I_MAX

14%×I_MAX

21%×I_MAX

32%×I_MAX

46%×I_MAX

71%×I_MAX

100%×I_MAX

1%×I_MAX

2%×I_MAX

4%×I_MAX

10%×I_MAX

21%×I_MAX

46%×I_MAX

100%×I_MAX

Bits

4-2A

g[2:0]

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54

Command execution time

cet[3:0] CET duration, ms

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

197

393

590

786

983

1180

Bits

1-0A

7-6B

1376

cet[3:0]

1573

1769

1966

2163

2359

2556

2753

2949

3146

Blue color intensity

b[2:0]

current, %

log=0

log=1

0×I_MAX

000

001

010

011

100

101

110

111

0×I_MAX

7%×I_MAX

14%×I_MAX

21%×I_MAX

32%×I_MAX

46%×I_MAX

71%×I_MAX

100%×I_MAX

1%×I_MAX

2%×I_MAX

4%×I_MAX

10%×I_MAX

21%×I_MAX

46%×I_MAX

100%×I_MAX

Bits

5-3B

b[2:0]

Transition time

tt[2:0]

000

001

010

011

100

101

110

111

Transition time, ms

0

55

110

221

442

885

1770

3539

Bits

2-0B

tt[2:0]

RESET (60H) - RESET REGISTER

D7

D6

D5

D4

D3

D2

D1

D0

Writing any data to Reset Register in address 60H can reset LP39542

w-0 w-0 w-0 w-0

w-0

55

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Physical Dimensions inches (millimeters) unless otherwise noted

The dimension for X1 ,X2 and X3 are as given:

X1=3.00 mm ±0.03 mm

—

X2=3.00 mm ±0.03 mm

X3=0.60 mm ±0.075 mm

36-bump micro SMD Package, 3 x 3 x 0.6 mm, 0.5 mm pitch

NS Package Number TLA36AAA

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56

The dimension for X1 ,X2 and X3 are as given:

X1=3.00 mm ±0.03 mm

—

X2=3.00 mm ±0.03 mm

X3=0.65 mm ±0.075 mm

36-bump micro SMDxt Package, 3 x 3 x 0.65 mm, 0.5 mm pitch

NS Package Number RLA36AAA

See Application notes AN–1112 and AN–1412 for PCB design and assembly instructions.

57

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Notes

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IMPLIED, ARISING BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS

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Life support devices or systems are devices which (a) are intended for surgical implant into the body, or (b) support or sustain life and

whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected

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型号：	LP39542TLX
厂家：	National Semiconductor
描述：	Advanced Lighting Management Unit 先进的照明管理单元
文件：	总58页 (文件大小：2935K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LP39542TLX [NSC]

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