LP3954TL_技术文档

July 2007

LP3954

Advanced Lighting Management Unit

General Description

Features

LP3954 is an advanced lighting management unit for hand-

held devices. It drives any phone lights including display

backlights, RGB, keypad and camera flash LEDs. The boost

DC-DC converter drives high current loads with high efficien-

cy. White LED backlight drivers are high efficiency low voltage

structures with excellent matching and automatic fade in/ fade

out function. The new stand-alone command based RGB

controller is feature rich and easy to configure. Built-in audio

synchronization feature allows user to synchronize the color

LEDs to audio input. Integrated high current driver can drive

camera flash LED or motor/vibra. Internal ADC can be used

for ambient light or temperature sensing. The flexible SPI/I²C

interface allows easy control of LP3954. Small micro SMD

package together with minimum number of external compo-

nents is a best fit for handheld devices.

Audio synchronization for color/RGB LEDs

■

Command based PWM controlled RGB LED drivers

High current driver for flash LED with built-in timing.

■

4+2 or 6 low voltage constant current white LED drivers

with programmable 8-bit adjustment (0…25mA/LED)

High efficiency Boost DC-DC converter

SPI / I²C compatible interface

■

Possibility for external PWM dimming control

Possibility for clock synchronization for RGB timing

Ambient light and temperature sensing possibility

Small package – micro SMD or micro SMDxt, 3.0 x 3.0 x

0.6mm

Applications

Cellular Phones

■

PDAs, MP3 players

Typical Applications

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Connection Diagrams and Package Mark Information

CONNECTION DIAGRAMS

Micro SMD Package, 3.0 x 3.0 x 0.6mm, 0.5mm pitch NS Package Number TLA36AAA or

Micro SMDxt Package, 3.0 x 3.0 x 0.65mm, 0.5mm pitch NS Package Number RLA36AAA

20132203

20132204

PACKAGE MARK

20132205

ORDERING INFORMATION

Order Number

LP3954TL

Package Marking

D49B

Supplied As

TNR 250

Spec/Flow

NoPB

LP3954TLX

LP3954RL

D49B

TNR 1000

TNR 250

NoPB

D49B

NoPB

LP3954RLX

D49B

TNR 1000

NoPB

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2

PIN DESCRIPTIONS

Pin #

6F

6E

6D

6C

6B

6A

5F

5E

5D

5C

5B

5A

4F

4E

4D

4C

4B

4A

3F

3E

3D

3C

3B

3A

2F

2E

2D

2C

2B

2A

1F

1E

1D

1C

1B

1A

Name

SW

Type

Output

Input

Description

Boost Converter Power Switch

Boost Converter Feedback

High Current Flash Output

Red LED 1 Output

FB

FLASH

R1

Output

Ground

Power

G1

Green LED 1 Output

Blue LED 1 Output

B1

GND_SW

GND

Power Switch Ground

Ground

VDDIO

SS/SDA

IRGB

Supply Voltage for Input/output Buffers and Drivers

Logic Input/Output Slave Select (SPI), Serial Data In/Out (I²C)

Input

Ground

Input

Bias Current Set Resistor for RGB Drivers

Ground for RGB Currents

Ground for WLED Currents

High Current Flash Current Set Resistor

External PWM Control for LEDs or External Clock for RGB Sync

Serial Input (SPI), Address Select (I²C)

Serial Data Out (SPI)

GND_RGB

GND_WLED

IFLASH

SYNC_PWM

SI

Logic Input

Logic Output

Output

SO

R2

Red LED 2 output

WLED5

WLED6

VDD1

EN_FLASH

SCK/SCL

G2

Output

White LED 5 output

Output

White LED 6 output

Power

Supply voltage

Logic Input

Output

Enable for High Current Flash

Clock (SPI/I²C)

Green LED 2 Output

WLED3

WLED4

ASE

Output

White LED 3 output

Output

White LED 4 output

Input

Audio Synchronization Input

Oscillator Frequency Resistor

Interface (SPI or I²C compatible) Selection (IF_SEL = 1 for SPI)

Blue LED 2 Output

IRT

Input

IF_SEL

B2

Logic Input

Output

WLED1

WLED2

GNDA

VREF

VDDA

VDD2

Output

White LED 1 Output

Output

White LED 2 Output

Ground

Output

Ground for Analog Circuitry

Reference Voltage

Power

Internal LDO Output

Power

Supply Voltage

3

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Operating Ratings (Notes 1, 2)

Absolute Maximum Ratings (Notes 1, 2)

V (SW, FB, WLED1-6, R1-2, G1-2,

B1-2, FLASH)

0 to 6.0V

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales Office/

Distributors for availability and specifications.

V_DD1,2with external LDO

V_DD1,2with internal LDO

V_DDA

2.7 to 5.5V

3.0 to 5.5V

V (SW, FB, R1-2, G1-2, B1-2,

FLASH, WLED1-6)(Notes 3, 4)

-0.3V to +7.2V

2.7 to 2.9V

V_{DD_IO}

1.65V to V_DD1

V_DD1, V_DD2, V_{DD_IO}, V_DDA

-0.3V to +6.0V

Voltage on ASE

0.1V to V_DDA–0.1V

0mA to 300mA

Voltage on ASE, IRT, IFLASH,

IRGB, VREF

-0.3V to V_DD1+0.3V

with 6.0V max

-0.3V to V_{DD_IO}+0.3V

with 6.0V max

-0.3V to 6.0V

Recommended Load Current

Junction Temperature (T_J) Range

Voltage on Logic Pins

-30°C to +125°C

-30°C to +85°C

Ambient Temperature (T_A) Range

(Note 9)

V(all other pins): Voltage to GND

I (V_REF

)

10µA

Thermal Properties

I(R1, G1, B1, R2, G2, B2)

I(FLASH)(Note 5)

Continuous Power Dissipation

(Note 6)

Junction Temperature (T_J-MAX

Storage Temperature Range

Maximum Lead Temperature

(Soldering) (Note 7)

100mA

400mA

Internally Limited

Junction-to-Ambient Thermal

Resistance(θ_JA), TLA36AAA or

RLA36AAA Package

(Note 10)

60°C/W

)

150°C

-65°C to +150°C

260ºC

ESD Rating (Note 8)

Human Body Model:

2kV

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Electrical Characteristics (Notes 2, 11)

Limits in standard typeface are for T_J= 25° C. Limits in boldface type apply over the operating ambient temperature range (-30°

C < T_A< +85°C). Unless otherwise noted, specifications apply to the LP3954 Block Diagram with: V_DD1= V_DD2= 3.6V, V_DDIO

=

2.8V, C_VDD= C_VDDIO= 100nF, C_OUT= C_IN= 10µF, C_VDDA= 1µF, C_REF= 100nF, L₁= 4.7µH, R_FLASH=1.2k, R_RGB=5.6k and R_RT

=82k (Note 12).

Symbol

Parameter

Standby supply current

(V_DD1, V_DD2

No-boost supply current

(V_DD1, V_DD2

Condition

NSTBY = L

SCK, SS, SI

Min

Typ

Max Units

I_VDD

1

8

µA

)

NSTBY = H,

EN_BOOST = L

SCK, SS, SI

400

µA

)

Audio sync and LEDs OFF

No-load supply current

(V_DD1, V_DD2

NSTBY = H,

EN_BOOST = H

SCK, SS, SI

1

mA

)

Audio sync and LEDs OFF

Autoload OFF

RGB drivers

(V_DD1, V_DD2

CC mode at R1, G1, B1 and

R2, G2, B2 set to 15mA

SW mode

150

µA

)

150

500

WLED drivers

(V_DD1, V_DD2

Audio synchronization

4+2 banks I_OUT/LED 25mA

)

Audio sync ON

V_DD1,2= 2.8V

V_DD1,2= 3.6V

(V_DD1, V_DD2

)

390

700

2

µA

mA

µA

Flash

I(R_FLASH)=1mA

(V_DD1, V_DD2

)

Peak current during flash

I_VDDIO

V_DDIOStandby Supply

current

NSTBY = L

SCK, SS, SI = H

1

V_DDIOsupply current

1MHz SCK frequency in SPI

mode, C_L= 50pF at SO pin

20

µA

I_{EXT_LDO}

V_DDA

External LDO output current

7V tolerant application only

I_BOOST= 300mA

6.5

mA

(V_DD1, V_DD2, V_DDA

)

Output voltage of internal

LDO for analog parts

(Note 13)

2.72

-3

2.80

2.88

+3

V

%

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under which operation

of the device is guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed performance limits and associated test conditions,

see the Electrical Characteristics tables.

Note 2: All voltages are with respect to the potential at the GND pins.

Note 3: Battery/Charger voltage should be above 6V no more than 10% of the operational lifetime.

Note 4: Voltage tolerance of LP3954 above 6.0V relies on fact that V_DD1and V_DD2(2.8V) are available (ON) at all conditions. If V_DD1and V_DD2are not available

(ON) at all conditions, National Semiconductor does not guarantee any parameters or reliability for this device.

Note 5: The total load current of the boost converter in worst-case conditions should be limited to 300mA (min. input and max. output voltage).

Note 6: Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at T_J=160°C (typ.) and disengages at

T_J=140°C (typ.).

Note 7: For detailed soldering specifications and information, please refer to National Semiconductor Application Note AN1112 : Micro SMD Wafer Level Chip

Scale Package or Application Note AN1412 : Micro SMDxt Wafer Level Chip Scale Package.

Note 8: The Human body model is a 100pF capacitor discharged through a 1.5kΩ resistor into each pin. The machine model is a 200pF capacitor discharged

directly into each pin. MIL-STD-883 3015.7

Note 9: In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may have to be

derated. Maximum ambient temperature (T_A-MAX) is dependent on the maximum operating junction temperature (T_J-MAX-OP= 125°C), the maximum power

dissipation of the device in the application (P_D-MAX), and the junction-to ambient thermal resistance of the part/package in the application (θ_JA), as given by the

following equation: T_A-MAX= T_J-MAX-OP– (θ_JA× P_D-MAX).

Note 10: Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power dissipation exists,

special care must be paid to thermal dissipation issues in board design.

Note 11: Min and Max limits are guaranteed by design, test, or statistical analysis. Typical numbers are not guaranteed, but do represent the most likely norm.

Note 12: Low-ESR Surface-Mount Ceramic Capacitors (MLCCs) used in setting electrical characteristics.

Note 13: V_DDAoutput is not recommended for external use.

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Block Diagram

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Modes of Operation

RESET:

In the RESET mode all the internal registers are reset to the default values and the chip goes to STANDBY

mode after reset. NSTBY control bit is low after reset by default. Reset is entered always if Reset Register

is written or internal Power On Reset is active. There is no dedicated Reset pin available. LP3954 can be

reset by writing any data to Reset Register in address 60H. Power On Reset (POR) will activate during the

chip startup or when the supply voltage VDD2 falls below 1.5V. Once VDD2 rises above 1.5V, POR will

inactivate and the chip will continue to the STANDBY mode.

STANDBY:

STARTUP:

The STANDBY mode is entered if the register bit NSTBY is LOW. This is the low power consumption mode,

when all circuit functions are disabled. Registers can be written in this mode and the control bits are effective

immediately after power up.

When NSTBY bit is written high, the INTERNAL STARTUP SEQUENCE powers up all the needed internal

blocks (Vref, Bias, Oscillator etc..). To ensure the correct oscillator initialization, a 10ms delay is generated

by the internal state-machine. If the chip temperature rises too high, the Thermal Shutdown (THSD) disables

the chip operation and STARTUP mode is entered until no thermal shutdown event is present.

BOOST STARTUP:

NORMAL:

Soft start for boost output is generated in the BOOST STARTUP mode. The boost output is raised in PFM

mode during the 10ms delay generated by the state-machine. The Boost startup is entered from Internal

Startup Sequence if EN_BOOST is HIGH or from Normal mode when EN_BOOST is written HIGH. During

the 10ms Boost Startup time all LED outputs are switched off to ensure smooth start-up.

During NORMAL mode the user controls the chip using the Control Registers. The registers can be written

in any sequence and any number of bits can be altered in a register in one write

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The topology of the magnetic boost converter is called CPM

control, current programmed mode, where the inductor cur-

rent is measured and controlled with the feedback. The user

can program the output voltage of the boost converter. The

output voltage control changes the resistor divider in the feed-

back loop.

Magnetic Boost DC/DC Converter

The LP3954 Boost DC/DC Converter generates a 4.0 – 5.3V

voltage for the LEDs from single Li-Ion battery (3V…4.5V).

The output voltage is controlled with an 8-bit register in 9

steps. The converter is a magnetic switching PWM mode DC/

DC converter with a current limit. The converter has three op-

tions for switching frequency, 1MHz, 1.67MHz and 2MHz

(default), when timing resistor RT is 82kohm. Timing resistor

defines the internal oscillator frequency and thus directly af-

fects boost frequency and all circuit's internally generated

timing (RGB, Flash, WLED fading).

The following figure shows the boost topology with the pro-

tection circuitry. Four different protection schemes are imple-

mented:

1. Over voltage protection, limits the maximum output

voltage

The LP3954 Boost Converter uses pulse-skipping elimination

to stabilize the noise spectrum. Even with light load or no load

a minimum length current pulse is fed to the inductor. An ac-

tive load is used to remove the excess charge from the output

capacitor at very light loads. At very light load and when input

and output voltages are very close to each other, the pulse

skipping is not completely eliminated. Output voltage should

be at least 0.5V higher than input voltage to avoid pulse skip-

ping. Reducing the switching frequency will also reduce the

required voltage difference.

Keeps the output below breakdown voltage.

—

Prevents boost operation if battery voltage is much

higher than desired output.

2. Over current protection, limits the maximum inductor

current

Voltage over switching NMOS is monitored; too high

voltages turn the switch off.

—

3. Feedback break protection. Prevents uncontrolled

operation if FB pin gets disconnected.

Active load can be disabled with the en_autoload bit. Dis-

abling will increase the efficiency at light loads, but the down-

side is that pulse skipping will occur. The Boost Converter

should be stopped when there is no load to minimise the cur-

rent consumption.

4. Duty cycle limiting, done with digital control.

20132208

Boost Converter Topology

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MAGNETIC BOOST DC/DC CONVERTER ELECTRICAL CHARACTERISTICS

Symbol

I_LOAD

Parameter

Load Current

Conditions

Min

Typ

Max

Units

3.0V ≤ V_IN

0

300

V_OUT= 5V

mA

3.0V ≤ V_IN

V_OUT= 4V

0

400

V_OUT

Output Voltage Accuracy

(FB Pin)

3.0V ≤ V_IN≤ V_OUT- 0.5

−5

+5

%

V

V_OUT= 5.0V

Output Voltage

(FB Pin)

1 mA ≤ I_LOAD≤ 300 mA

V_IN> 5V + V_(SCHOTTKY)

V_IN–V_(SCHOTTKY)

RDS_ON

f_PWF

Switch ON Resistance

V_DD1,2= 2.8V, I_SW= 0.5A

0.4

2

0.8

Ω

PWM Mode Switching

Frequency

RT = 82 kΩ

freq_sel[2:0] = 1XX

MHz

Frequency Accuracy

−6

±3

+6

2.7 ≤ VDDA ≤ 2.9

RT = 82 kΩ

no load

%

−9

+9

t_PULSE

Switch Pulse Minimum

Width

25

ns

t_STARTUP

I_{SW_MAX}

Startup Time

Boost startup from STANDBY

10

ms

SW Pin Current Limit

700

800

900

mA

550

950

Boost Output Voltage Control

BOOST STANDBY MODE

User can stop the Boost Converter operation by writing the

Enables register bit EN_BOOST low. When EN_BOOST is

written high, the converter starts for 10ms in PFM mode and

then goes to PWM mode.

BOOST OUTPUT VOLTAGE CONTROL

User can control the boost output voltage by boost output 8-

bit register.

Boost Output [7:0]

Register 0DH

Boost Output

Voltage (typical)

Bin

Hex

00

01

03

07

0F

1F

3F

7F

FF

0000 0000

0000 0001

0000 0011

0000 0111

0000 1111

0001 1111

0011 1111

0111 1111

1111 1111

4.00

4.25

4.40

4.55

4.70

20132209

4.85

BOOST FREQUENCY CONTROL

5.00 Default

5.15

freq_sel[2:0]

1XX

frequency

2.00 MHz

1.67 MHz

1.00 MHz

5.30

01X

001

Register ‘boost freq’ (address 0EH). Register default value

after reset is 07H.

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Boost Converter Typical Performance Characteristics

Vin = 3.6V, Vout = 5.0V if not otherwise stated

Boost Converter Efficiency

Battery Current vs Voltage

Boost Line Regulation

Boost Typical Waveforms at 100mA Load

20132211

20132210

Battery Current vs Voltage

20132212

20132213

Boost Startup with No Load

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20132215

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Boost Load Transient, 50 mA–100 mA

Boost Switching Frequency

20132216

20132217

Output Voltage vs Load Current

Efficiency At Low Load vs Autoload

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HC_Flash

Functionality of Color LED Outputs

(R1, G1, B1; R2, G2, B2)

hc_pwm

bit 5 PWM controls High

Current FLASH

LP3954 has 2 sets of RGB/color LED outputs. Both sets have

3 outputs and the sets can be controlled in 4 different ways:

Note: If DISPL=1, wled1-4pwm controls WLED1-6

Note: Maximum external PWM frequency is 1kHz. If during the external

PWM control the internal PWM is on the result will be product of both

functions.

1. Command based pattern generator control (internal

PWM)

CURRENT CONTROL OF COLOR LED OUTPUTS (R1, R2,

G1, G2, B1, B2)

2. Audio synchronization control

3. Direct ON/OFF control

4. External PWM control

Both RGB output sets can be separately controlled as con-

stant current sinks or as switches. This is done using

cc_rgb1/2 bits in the RGB control register. In constant current

mode one or both RGB output sets are controlled with con-

stant current sinks (no external ballast resistors required).

The maximum output current for both drivers is set by one

external resistor R_RGB. User can decrease the maximum cur-

rent for an individual LED driver by programming as shown

later.

By using command based pattern generator user can pro-

gram any kind of color effect patterns. LED intensity, blinking

cycles and slopes are independently controlled with 8 16-bit

commands. Also real time commands are possible as well as

loops and step by step control. If analog audio is available on

system, the user can use audio synchronization for syn-

chronizing LED blinking to the music. The different modes

together with the various sub modes generate very colorful

and interesting lighting effects. Direct ON/OFF control is

mainly for switching on and off LEDs. External PWM con-

trol is for applications where external PWM signal is available

and required to control the color LEDs. PWM signal can be

connected to any color LED separately as shown later.

The maximum current for all RGB drivers is set with R_RGB

The equation for calculating the maximum current is

.

I_MAX= 100 ×1.23V / (R_RGB+ 50Ω)

where

I_MAX- maximum RGB current in any RGB output in constant

current mode

COLOR LED CONTROL MODE SELECTION

1.23V - reference voltage

The RGB_SEL[1:0] bits in the Enables register (08H) control

the output modes for RGB1 (R1, G1, B1) and RGB2 (R2, G2,

B2) outputs. The following table shows the RGB_SEL func-

tionality.

100 - internal current mirror multiplier

R_RGB- resistor value in Ohms

50Ω - internal resistor in the I_RGBinput

For example if 22mA is required for maximum RGB current

R_RGBequals to

RGB_SEL[1:0]

Audio sync

Command based

pattern

connected to

generator

connected to

R_RGB= 100 × 1.23V / I_MAX–50Ω = 123V / 0.022A –50Ω =

5.54kΩ

00

01

10

11

none

RGB1

RGB1 & RGB2

RGB2

Each individual RGB output has a separate maximum current

programming. The control bits are in registers RGB1 max

current and RGB2 max current (12H and 13H) and pro-

gramming is shown in table below. The default value after

reset is 00.

RGB2

RGB1

RGB1 & RGB2

none

RGB Control register (00H) has control bits for direct on/off

control of all color LEDs. Note that the LEDs have to be turned

on in order to control them with audio synchronization or pat-

tern generator.

IR1[1:0], IG1[1:0],

IB1[1:0], IR2[1:0],

IG2[1:0], IB2[1:0]

Maximum

current/output

00

01

10

11

0.25 × I_MAX

0.50 × I_MAX

0.75 × I_MAX

1.00 × I_MAX

The external PWM signal controls any LED depending on the

control register setup. The controls are in the Ext. PWM Con-

trol register (address 07H) except the FLASH control in

HC_Flash (10H) register as follows:

Ext. PWM Control

SWITCH MODE

wled1-4_pwm

wled5-6_pwm

r1_pwm

bit 7 PWM controls WLED 1-4

bit 6 PWM controls WLED 5-6

bit 5 PWM controls R1 output

bit 4 PWM controls G1 output

bit 3 PWM controls B1 output

bit 2 PWM controls R2 output

bit 1 PWM controls G2 output

bit 0 PWM controls B2 output

The switch mode is used if there is a need to connect parallel

LEDs to output or if the RGB output current needs to be in-

creased.

g1_pwm

Please note that the switch mode requires an external bal-

last resistors at each output to limit the LED current.

The switch/current mode and on/off controls for RGB are in

the RGB_ctrl register (00H) as follows:

b1_pwm

r2_pwm

g2_pwm

b2_pwm

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12

RGB_ctrl register (00H)

CC_RGB1

1

R1, G1 and B1 are switches → limit current with ballast resistor

R1, G1 and B1 are constant current sinks, current limited internally

bit7

0

1

R2, G2 and B2 are switches → limit current with ballast resistor

R2, G2 and B2 are constant current sinks, current limited internally

CC_RGB2

r1sw

bit6

bit5

bit4

bit3

bit2

bit1

bit0

0

1

0

1

0

1

0

1

0

1

0

1

0

R1 is on

R1 is off

G1 is on

G1 is off

B1 is on

B1 is off

R2 is on

R2 is off

G2 is on

G2 is off

B2 is on

B2 is off

g1sw

b1sw

r2sw

g2sw

b2sw

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Command Based Pattern Generator for Color LEDs

The LP3954 has a unique stand-alone command based pattern generator with 8 user controllable 16-bit wide commands. Since

write registers are 8-bit long one command requires 2 write cycles. Each command has intensity level for each LED, command

execution time (CET) and transition time (TT). The command structure is shown in following two figures.

20132219

COMMAND REGISTER WITH 8 COMMANDS

COMMAND 1

COMMAND 2

COMMAND 3

COMMAND 4

COMMAND 5

COMMAND 6

COMMAND 7

COMMAND 8

ADDRESS 50H

ADDRESS 51H

ADDRESS 52H

ADDRESS 53H

ADDRESS 54H

ADDRESS 55H

ADDRESS 56H

ADDRESS 57H

ADDRESS 58H

ADDRESS 59H

ADDRESS 5AH

ADDRESS 5BH

ADDRESS 5CH

ADDRESS 5DH

ADDRESS 5EH

ADDRESS 5FH

R2

CET1

R2

R1

CET0

R1

R0

B2

R0

B2

R0

B2

R0

B2

R0

B2

R0

B2

R0

B2

R0

B2

G2

B1

G2

B1

G2

B1

G2

B1

G2

B1

G2

B1

G2

B1

G2

B1

G1

B0

G1

B0

G1

B0

G1

B0

G1

B0

G1

B0

G1

B0

G1

B0

G0

TT2

G0

CET3

TT1

CET2

TT0

CET3

TT1

CET2

TT0

CET1

R2

CET0

R1

TT2

G0

CET3

TT1

CET2

TT0

CET1

R2

CET0

R1

TT2

G0

CET3

TT1

CET2

TT0

CET1

R2

CET0

R1

TT2

G0

CET3

TT1

CET2

TT0

CET1

R2

CET0

R1

TT2

G0

CET3

TT1

CET2

TT0

CET1

R2

CET0

R1

TT2

G0

CET3

TT1

CET2

TT0

CET1

R2

CET0

R1

TT2

G0

CET3

TT1

CET2

TT0

CET1

CET0

TT2

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14

COLOR INTENSITY CONTROL

CET [3:0]

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

CET duration, ms

197

Each color, Red, Green and Blue, has 3-bit intensity levels.

The level control is logarithmic. 2 logarithmic curves are avail-

able. The LOG bit in Pattern_gen_ctrl register (11H) defines

the curve used. The values for both logarithmic curves are

shown in following table.

393

590

786

R[2:0], G[2:0],

B[2:0]

CURRENT

983

[% × I_MAX(COLOR)

]

1180

1376

1573

1769

1966

2163

2359

2556

2753

2949

3146

LOG=0

0

LOG=1

000

001

010

011

100

101

110

111

0

1

7

14

2

21

4

32

10

21

46

100

46

71

100

Transition time TT is duration of transition from the previous

RGB value to programmed new value. Transition times TT

are defined as follows:

TT [2:0]

000

Transition time, ms

0

001

55

010

110

221

442

885

1770

3539

011

100

101

110

111

The figure below shows an example of RGB CET and TT

times.

20132220

COMMAND EXECUTION TIME (CET) AND TRANSITION

TIME (TT)

The command execution CET time is the duration of one sin-

gle command. Command execution times CET are defined as

follows, when R_T=82k:

20132221

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The command execution time also may be less than the transition time – the figure below illuminates this case.

20132222

LOOP CONTROL

Pattern generator commands can be looped using the LOOP bit (D1) in Pattern gen ctrl register (11H). If LOOP=1 the program

will be looped from the command 8 register or if there is 0000 0000 and 0000 0000 in one command register. The loop will start

from command 1 and continue until stopped by writing rgb_start=0 or loop=0. The example of loop is shown in following figure:

20132223

SINGLE PROGRAM

If control bit LOOP=0 the program will start from Command 1 and run to either last command or to empty “0000 0000 / 0000 0000”

command.

20132224

The LEDs maintain the brightness of the last command when the single program stops. Changes in command register will not be

effective in this phase. The RGB_START bit has to be toggled off and on to make changes effective.

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16

START BIT

Pattern_gen_ctrl register’s RGB_START bit will enable command execution starting from Command 1.

Pattern gen ctrl register (11H)

0 – Pattern generator disabled

1 – execution pattern starting from command 1

rgb_start

loop

Bit 2

Bit 1

Bit 0

0 – pattern generator loop disabled (single pattern)

1 – pattern generator loop enabled (execute until stopped)

0 – color intensity mode 0

1 – color intensity mode 1

log

HARDWARE ON/OFF CONTROL AND DIMMING

PWM_LED input can be used as direct ON/OFF control or PWM dimming control for selected RGB outputs or the WLED groups.

PWM_LED control can be enabled with the control bits in the Ext. PWM Control register.

17

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ple 5 shows an example of a second order RC-filter for 29 kHz

PWM signal with 3.3V amplitude. Active filters, such as a

Sallen-Key filter, may also be applied. An active filter gives

better stop-band attenuation and cut-off frequency can be

higher than for a RC-filter.

Audio Synchronization

The color LEDs connected to RGB outputs can be synchro-

nized to incoming audio with Audio Synchronization feature.

Audio Sync has 2 modes. Amplitude mode synchronizes

color LEDs based on input signal’s peak amplitude. In the

amplitude mode the user can select between 3 different am-

plitude mapping modes and 4 different speed configurations.

The frequency mode synchronizes the color LEDs based on

bass, middle and treble amplitudes (= low pass, band pass

and high pass filters). User can select between 2 different

frequency responses and 4 different speed configurations for

best audio-visual user experience. Programmable gain and

AGC function are also available for adjustment of input signal

amplitude to light response. The Audio Sync functionality is

described more closely below.

To make sure that the filter rolls off sufficiently quickly, con-

nect your filter circuit to the audio input(s), turn on the audio

synchronization feature, set manual gain to maximum, apply

the PWM signal to the filter input and keep an eye on LEDs.

If they are blinking without an audio signal (modulation), a

sharper roll-off after the cut-off frequency, more stop-band

attenuation, or smaller amplitude of the PWM signal is re-

quired.

AUDIO SYNCHRONIZATION SIGNAL PATH

LP3954 audio synchronization is mainly done digitally and it

consists of the following signal path blocks:

USING A DIGITAL PWM AUDIO SIGNAL AS AN AUDIO

SYNCHRONIZATION SOURCE

•

Input Buffers

AD Converter

DC Remover

If the input signal is a PWM signal, use a first or second order

low pass filter to convert the digital PWM audio signal into an

analog waveform. There are two parameters that need to be

known to get the filter to work successfully: frequency of the

PWM signal and the voltage level of the PWM signal. Sug-

gested cut-off frequency (-3dB) should be around 2 kHz to 4

kHz and the stop-band attenuation at sampling frequency

should be around -48dB or better. Use a resistor divider to

reduce the digital signal amplitude to meet the specification

of the analog audio input. Because a low-order low-pass filter

attenuates the high-frequency components from audio signal,

MODE_CONTROL=[01] selection is recommended when fre-

quency synchronization mode is enabled. Application exam-

Automatic Gain Control (AGC)

Programmable Gain

3 Band Digital Filter

Peak Detector

Look-up Tables (LUT)

Mode Selector

Integrators

PWM Generator

Output Drivers

20132225

The digitized input signal has DC component that is removed

by digital DC REMOVER (-3dB @ 400Hz). Since the light re-

sponse of input audio signal is very much amplitude depen-

dent the AGC adjusts the input signal to suitable range

automatically. User can disable AGC and the gain can be set

manually with PROGRAMMABLE GAIN. LP3954 has 2 au-

dio synchronization modes: amplitude and frequency. For

amplitude based synchronization the PEAK DETECTION

method is used. For frequency based synchronization 3

BAND FILTER separates high pass, low pass and band bass

signals. For both modes the predefined LUT is used to opti-

mize the audio visual effect. MODE SELECTOR selects the

synchronization mode. Different response times to music

beat can be selected using INTEGRATOR speed variables.

Finally PWM GENERATOR sets the driver FET duty cycles.

scribed in the Audio Synch table. The buffer is rail-to-rail input

operational amplifier connected as a voltage follower. DC lev-

el of the input signal is set by a simple resistor divider

20132226

INPUT SIGNAL TYPE AND BUFFERING

LP3954 supports single ended audio input as shown in the

figure below. The electric parameters of the buffer are de-

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18

AUDIO SYNC ELECTRICAL PARAMETERS

Symbol Parameter

Conditions

Min

250

0.1

Typical

Max

Units

kOhm

V

Z_IN

A_IN

Input Impedance of ASE

500

Audio Input Level Range

(peak-to-peak)

Gain = 21dB

Gain = 0 dB

V_DDA-0.1

f_3dB

Crossover Frequencies (-3

dB)

Narrow Frequency

Response

Low Pass

Band Pass

High Pass

0.5

1.0 and 1.5

2.0

kHz

Wide Frequency Response Low Pass

1.0

Band Pass

High Pass

2.0 and 3.0

4.0

CONTROL OF AUDIO SYNCHRONIZATION

The following table describes the controls required for audio synchronization.

Audio_sync_CTRL1 (2AH)

Input signal gain control. Range 0...21 dB, step 3 dB:

[000] = 0 dB (default)

[001] = 3 dB

[011] = 9 dB

[100] = 12 dB

[101] = 15 dB

[110] = 18 dB

[111] = 21 dB

GAIN_SEL[2:0]

Bits 7-5

[010] = 6 dB

Synchronization mode selector.

SYNC_MODE

EN_AGC

Bit 4

Bit 3

SYNCMODE = 0 → Amplitude Mode (default)

SYNCMODE = 1 → Frequency Mode

Automatic Gain Control enable

1 = enabled

0 = disabled (Gain Select enabled) (default)

Audio synchronization enable

1 = Enabled

Note : If AGC is enabled, AGC gain starts from current GAIN_SEL gain value.

0 = Disabled (default)

EN_SYNC

Bit 2

[00] = Single ended input signal, ASE.

[01] = Temperature measurement

[10] = Ambient light measurement

[11] = No input (default)

INPUT_SEL[1:0]

Bits 1-0

Audio_sync_CTRL2 (2BH)

0 – average disabled (not applicable in audio synchronization mode)

1 – average enabled (not applicable in audio synchronization mode)

EN_AVG

Bit 4

MODE_CTRL[1:0]

Bits 3-2 See below: Mode control

Sets the LEDs light response time to audio input.

[00] = FASTEST (default)

[01] = FAST

[10] = MEDIUM

SPEED_CTRL[1:0]

Bits 1-0

[11] = SLOW

(For SLOW setting in amplitude mode f_MAX=3.8Hz,

Frequency mode f_MAX=7.6Hz)

19

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MODE CONTROL IN FREQUENCY MODE

Mode control has two setups based on audio synchronization mode select: the frequency mode and the amplitude mode. During

the frequency mode user can select two filter options by MODE_CTRL as shown below. User can select the filters based on the

music type and light effect requirements. In the first mode the frequency range extends to 8 kHz in the secont to 4 kHz.

The lowpass filter is used for the red, the bandpass filter for the blue and the hipass filter for the green LED.

Higher frequency mode

MODE_CTRL = 00 and SYNC_MODE = 1

Lower frequency mode

MODE_CTRL = 01 and SYNC_MODE = 1

20132227

20132228

MODE CONTROL IN AMPLITUDE MODE

During the amplitude synchronization mode user can select between three different amplitude mappings by using

MODE_CTRL select. These three mapping option gives different light response. The modes are shown in the tables below.

Non-overlapping mode

MODE_CTRL[1:0] = [01]

Partly overlapping mode

MODE_CTRL[1:0] = [00]

20132229

20132230

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20

Overlapping mode

MODE_CTRL[1:0] = [10]

Peak Input Signal Level

Range vs Gain Setting

20132232

20132231

RGB OUTPUT SYNCHRONIZATION TO EXTERNAL CLOCK

The RGB pattern generator and high current flash driver timing can be synchronized to external clock with following configuration.

1. Set PWM_SYNC bit in Enables register to 1

2. Feed PWM_SYNC pin with 5 MHz clock

By this the internal 5 MHz clock is disabled from pattern generator and flash timing circuitry.

The external clock signal frequency will fully determine the timings related to RGB and Flash.

Note: The boost converter will use internal 5 MHz clock even if the external clock is available.

RGB Driver Typical Performance Characteristics

RGB DRIVER ELECTRICAL CHARACTERISTICS (R1, G1, B1, R2, G2, B2 OUTPUTS)

Symbol

I_LEAKAGE

I_MAX(RGB)

Parameter

Condition

Min Typ Max Units

R1, G1, B1, R2, G2, B2 pin leakage current

Maximum recommended sink current

0.1

1

µA

mA

%

CC mode

40

50

SW mode

Accuracy @ 37mA

±5

R_RGB=3.3 kΩ ±1%, CC mode

CC mode

Current mirror ratio

1:100

±5

RGB1 and RGB2 current mismatch

Switch resistance

I_RGB=37mA, CC mode

SW mode

%

R_SW

2.5

4

Ω

ƒ_RGB

RGB switching frequency

Accuracy proportional to internal clock 18.2

20

21.8

kHz

freq.

If external SYNC 5MHz is in use

20

kHz

Note: RGB current should be limited as follows:

constant current mode – limit by external R_RGBresistor;

switch mode – limit by external ballast resistors

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Output Current vs Pin Voltage (Current Sink Mode)

Pin Voltage vs Output Current (Switch Mode)

20132266

20132268

Output Current vs R_RGB(Current Sink Mode)

20132267

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22

HC[1:0]

00

I(FLASH)

Single High Current Driver

0.25 × I_MAX(FLASH)

0.50 × I_MAX(FLASH)

0.75 × I_MAX(FLASH)

1.00 × I_MAX(FLASH)

LP3954 has internal constant current driver that is capable for

driving high current mainly targeted for FLASH LED in camera

phone applications.

01

10

MAXIMUM CURRENT SETUP FOR FLASH

11

The user sets the maximum current of FLASH with R_FLASH

resistor based on following equation:

The figure below shows the internal structure for the FLASH

driver.

I_MAX= 300 × 1.23V / (R_FLASH+ 50Ω),

where

Imax = maximum flash current in Amps (ie. 0.3A)

1.23V = reference voltage

300 = internal current mirror multiplier

R_FLASH= Resistor value in Ohms

50Ω = Internal resistor in the I_FLASHinput

For example if 300mA is required for maximum flash current

R_FLASHequals to

R_FLASH= 300 × 1.23V / I_MAX– 50Ω = 369V / 0.3A – 50Ω =

1.18kΩ

CURRENT CONTROL FOR FLASH

To minimize the internal current consumption, the flash func-

20132233

tion has an enable bit EN_HCFLASH in the HC_Flash regis-

ter.

FLASH TIMING

Flash output is turned on in lower current View finder mode

when the EN_HCFLASH bit is written high. The actual Flash

at maximum current starts when the EN_FLASH i/o-pin goes

high. The Flash length can be selected from 3 pre-defined

values or EN_FLASH pin pulse length can determine the

length. The pulse length is controlled by the FT_T[1:0] bits as

show in the table below.

EN_

HCFLASH

0

1

FLASH disabled, no extra current

consumption through R_FLASH

FLASH enabled, IFLASH set by

HC_SW[1:0] (see below)

HC[1:0] bits in the HC_Flash register control the FLASH cur-

rent as show in following table.

FL_T[1:0]

Flash duration typ

Current during view finder/

Current during FLASH

focusing

00

01

10

11

200ms

400ms

Set by HC[1:0]

HC[11] = I_MAX(FLASH)

600ms

EN_FLASH on duration

23

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The following figure shows the functionality of the built-in flash

20132234

HIGH CURRENT DRIVER ELECTRICAL CHARACTERISTICS

Symbol

I_LEAKAGE

I_MAX(FLASH)

Parameter

Condition

Min

Typ

Max Units

FLASH pin leakage current

Maximum Sink Current

Accuracy @ 300 mA

0.1

2

µA

400

±10

mA

%

±5

R_FLASH=1.18 kΩ ±1%

Current mirror ratio

1:300

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24

DISPL

Configuration

Matching

Backlight Drivers

Main display up

to 4 LEDs

Good btw

WLED1…4

Good btw

LP3954 has 2 independent backlight drivers. Both drivers are

regulated constant current sinks. LED current for both LED

banks (WLED1…4 and WLED5…6) are controlled by 8-bit

current mode DACs with 0.1 mA step.

0

Sub display up

to 2 LEDs

WLED5…6

WLED1…4 and WLED5…6 can be also controlled with one

DAC for better matching allowing the use of larger displays

having up to 6 white LEDs in parallel.

Large display

up to 6 LEDs

Good btw

WLED 1…6

1

Display configuration is controlled with DISPL bit as shown

below.

Display backlight enables

1

0

1

0

WLED1-4 enabled

EN_W1-4

EN_W5-6

WLED1-4 disabled

WLED5-6 enabled

WLED5-6 disabled

20132235

20132236

Main display up to 4 LEDs (WLED1…4)

Sub display driver up to 2 LEDs (WLED5…6)

20132237

Main display up to 6 LEDs (WLED1…6) (DISPL=1)

BACKLIGHT DRIVER ELECTRICAL CHARACTERISTICS

Symbol

I_MAX

I_Leakage

I_WLED1

Parameter

Maximum Sink Current

Conditions

Min Typical Max

Units

mA

21.3

25.5

0.03

12.8

29.4

1

Leakage Current

V_FB=5V

µA

WLED1 Current tolerance

I_WLED1set to 12.8mA (80H)

10.52

-18

14.78

+16

mA

%

I_Match1-4

I_Match5-6

I_Match1-6

Sink Current Matching

I_SINK=13mA, Between WLED1…4

I_SINK=13mA, Between WLED5…6

I_SINK=13mA, Between WLED1…6

0.2

0.3

%

Note: Matching is the maximum difference from the average.

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ADJUSTMENT

FADE IN / FADE OUT

LP3954 has an automatic fade in and out for main and sub

backlight. The fade function is enabled with EN_FADE bit.

The slope of the fade curve is set by the SLOPE bit. Fade

control for main and sub display is set by FADE_SEL bit.

WLED1-4[7:0]

WLED5-6[7:0]

Driver current,

ma (typical)

0000 0000

0000 0001

0000 0010

0000 0011

…

0

0.1

0.2

0.3

…

0

1

0

1

0

1

Automatic fade disabled

Automatic fade enabled

Fade execution time 1.3s

Fade execution time 0.65s

Fade controls WLED1-4

Fade controls WLED5-6

EN_FADE

SLOPE

…

FADE_SEL

1111 1101

1111 1110

1111 1111

25.3

25.4

25.5

Note: if DISPL=1 and FADE_SEL=0, Fade effects to WLED1-6

Recommended fading sequence:

WLED Output Current vs. Voltage

1. ASSUMPTION: Current WLED value in register

2. Set SLOPE

3. Set FADE_SEL

4. Set EN_FADE = 1

5. Set target WLED value

6. Fading will be done either within 0.5s or 1s based on

Slope selection

20132238

WLED dimming, SLOPE=0

WLED dimming, SLOPE=1

20132239

20132240

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26

TEMPERATURE MEASUREMENT

Ambient Light and Temperature

Measurement with LP3954

The temperature measurement requires two external compo-

nents: resistor and thermistor (resistor that has known tem-

perature vs resistance curve). The ADC reads the voltage

level at ASE pin and converts the result in digital word. User

can read the ADC output from register. The known tempera-

ture allows for example to monitor the temperature inside the

display module and decrease the current level of the LEDs if

temperature raises too high. This function may increase life-

time of LEDs in some applications.

The Analog-to-Digital converter (ADC) in the Audio Syn-

cronization block can be also used for ambient light measure-

ment or temperature measurement.

The selection between these modes is controlled with input

selector bits INPUT_SEL[1:0] as follows

INPUT_SEL[1:0]

Mode

00

Audio synchronization

Temperature measurement

(voltage input)

01

Ambient light measurement

(current input)

10

11

No input

AMBIENT LIGHT MEASUREMENT

The ambient light measurement requires only one external

component: Ambient light sensor (photo transistor or diode).

The ADC reads the current level at ASE pin and converts the

result in digital word. User can read the ADC output from the

ADC output register. The known ambient light condition al-

lows user to set the backlight current to optimal level thus

saving power especially in low light and bright sunlight con-

dition.

20132242

Temperature sensor connection example

20132241

20132263

ADC Code vs Input Voltage

in temperature measurement mode

20132264

ADC Code vs Input Current

in light measurement mode

27

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EXAMPLE TEMP SENSOR READING AT DIFFERENT

TEMPERATURES (R(25°C)=1MΩ)

T°C

-40

0

V(ASE)

2.7540984

2.24

R(MΩ)

Rt(MΩ)

60

1

4

25

1

1.4

60

0.2

0.04

0.4666667

0.1076923

100

20132243

Example curve for thermistor

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28

7V Shielding

To shield LP3954 from high input voltages 6…7.2V the use of external 2.8V LDO is required. This 2.8V voltage protects internally

the device against high voltage condition. The recommended connection is as shown in the picture below. Internally both logic and

analog circuitry works at 2.8V supply voltage. Both supply voltage pins should have separate filtering capacitors.

20132244

In cases where high voltage is not an issue the connection is as shown below

20132245

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Logic Interface Characteristics

(1.65V ≤ V_DDIO≤ V_DD1,2V) (Unless otherwise noted).

Symbol

Parameter

Conditions

Min

Typ

Max

Units

LOGIC INPUTS SS, SI, SCK/SCL, SYNC/PWM, IF_SEL, EN_FLASH

V_IL

V_IH

I_I

Input Low Level

Input High Level

Logic Input Current

0.2×V_DDIO

V

0.8×V_DDIO

−1.0

1.0

µA

kHz

I²C Mode

400

SPI Mode,

V_DDIO> 1.8V

13

5

MHz

f_SCL

Clock Frequency

SPI Mode,

1.65V ≤ V_DDIO< 1.8V

LOGIC OUTPUT SO

I_SO= 3 mA

0.3

0.5

V_DDIO> 1.8V

V_OL

Output Low Level

Output High Level

V

I_SO= 2 mA

0.3

1.65V ≤ V_DDIO< 1.8V

I_SO= −3 mA

V_DDIO− 0.5

V_DDIO− 0.3

V_DDIO> 1.8V

V_OH

I_SO= -2 mA

1.65V ≤ V_DDIO< 1.8V

I_L

LOGIC OUTPUT SDA

V_OLOutput Low Level

Output Leakage Current V_SO= 2.8V

1.0

0.5

µA

V

I_SDA= 3 mA

0.3

Control Interface

The LP3954 supports two different interface modes:

User can define the serial interface by IF_SEL pin. IF_SEL=0

selects the I²C mode.

•

SPI interface (4 wire, serial)

I²C compatible interface (2 wire, serial)

SPI INTERFACE

LP3954 is compatible with SPI serial bus specification and it operates as a slave. The transmission consists of 16-bit Write and

Read Cycles. One cycle consists of 7 Address bits, 1 Read/Write (RW) bit and 8 Data bits. RW bit high state defines a Write Cycle

and low defines a Read Cycle. SO output is normally in high-impedance state and it is active only when Data is sent out during a

Read Cycle. A pull-up resistor may be needed in SO line if a floating logic signal can cause unintended current consumption in the

input circuits where SO is connected.The Address and Data are transmitted MSB first. The Slave Select signal SS must be low

during the Cycle transmission. SS resets the interface when high and it has to be taken high between successive Cycles. Data is

clocked in on the rising edge of the SCK clock signal, while data is clocked out on the falling edge of SCK.

20132246

SPI Write Cycle

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30

20132247

SPI Read Cycle

20132248

SPI Timing Diagram

SPI Timing Parameters

V_DD= V_{DD_IO}= 2.775V

Limit

Symbol

Parameter

Units

Min

70

35

20

0

Max

1

2

Cycle Time

ns

Enable Lead Time

Enable Lag Time

Clock Low Time

Clock High Time

Data Setup Time

Data Hold Time

Data Access Time

Disable Time

3

4

5

6

7

8

20

10

20

9

10

11

Data Valid

Data Hold Time

0

Note: Data guaranteed by design.

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I²C COMPATIBLE INTERFACE

I²C Signals

In I²C mode the LP3954 pin SCK is used for the I²C clock SCL

and the pin SS is used for the I²C data signal SDA. Both these

signals need a pull-up resistor according to I²C specification.

SI pin is the address select pin. I²C address for LP3954 is 54h

when SI = 0 and 55h when SI = 1. Unused pin SO can be left

unconnected.

20132250

Transferring Data

I²C Data Validity

Every byte put on the SDA line must be eight bits long, with

the most significant bit (MSB) being transferred first. Each

byte of data has to be followed by an acknowledge bit. The

acknowledge related clock pulse is generated by the master.

The transmitter releases the SDA line (HIGH) during the ac-

knowledge clock pulse. The receiver must pull down the SDA

line during the 9^thclock pulse, signifying an acknowledge. A

receiver which has been addressed must generate an ac-

knowledge after each byte has been received.

The data on SDA line must be stable during the HIGH period

of the clock signal (SCL). In other words, state of the data line

can only be changed when CLK is LOW.

After the START condition, the I²C master sends a chip ad-

dress. This address is seven bits long followed by an eighth

bit which is a data direction bit (R/W). The LP3954 address is

54h or 55H as selected with SI pin. For the eighth bit, a “0”

indicates a WRITE and a “1” indicates a READ. The second

byte selects the register to which the data will be written. The

third byte contains data to write to the selected register.

20132249

I²C Signals: Data Validity

I²C Start and Stop Conditions

START and STOP bits classify the beginning and the end of

the I²C session. START condition is defined as SDA signal

transitioning from HIGH to LOW while SCL line is HIGH.

STOP condition is defined as the SDA transitioning from LOW

to HIGH while SCL is HIGH. The I²C master always generates

START and STOP bits. The I²C bus is considered to be busy

after START condition and free after STOP condition. During

data transmission, I²C master can generate repeated START

conditions. First START and repeated START conditions are

equivalent, function-wise.

20132251

I²C Chip Address

Register changes take an effect at the SCL rising edge during

the last ACK from slave.

20132252

w = write (SDA = “0”)

r = read (SDA = “1”)

ack = acknowledge (SDA pulled down by either master or slave)

rs = repeated start

id = 7-bit chip address, 54h (SI=0) or 55h (SI=1) for LP3954.

I²C Write Cycle

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32

When a READ function is to be accomplished, a WRITE function must precede the READ function, as shown in the Read Cycle

waveform.

20132253

I²C Read Cycle

20132254

I²C Timing Diagram

I²C Timing Parameters (V_DD1,2= 3.0 to 4.5V, V_{DD_IO}= 1.65V

to V_DD1,2

)

Symbol

Parameter

Hold Time (repeated) START Condition

Limit

Units

Min

0.6

1.3

600

300

0

Max

1

2

µs

ns

µs

pF

Clock Low Time

3

Clock High Time

4

Setup Time for a Repeated START Condition

Data Hold Time (Output direction, delay generated by LP3954)

Data Hold Time (Input direction, delay generated by the Master)

Data Setup Time

5

900

5

6

100

7

Rise Time of SDA and SCL

20+0.1C_b

15+0.1C_b

600

300

8

Fall Time of SDA and SCL

9

Set-up Time for STOP condition

10

C_b

Bus Free Time between a STOP and a START Condition

Capacitive Load for Each Bus Line

1.3

10

200

NOTE: Data guaranteed by design

Autoincrement mode is available, with this possible read or write few byte with autoincreasing addresses, but LP3954 has holes

in address register map, and is recommended to use autoincrement mode only for the pattern command registers.

33

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OUTPUT DIODE, D_OUT

Recommended External

Components

A Schottky diode should be used for the output diode. To

maintain high efficiency the average current rating of the

schottky diode should be larger than the peak inductor current

(1A). Schottky diodes with a low forward drop and fast switch-

ing speeds are ideal for increasing efficiency in portable ap-

plications. Choose a reverse breakdown of the schottky diode

larger than the output voltage. Do not use ordinary rectifier

diodes, since slow switching speeds and long recovery times

cause the efficiency and the load regulation to suffer.

OUTPUT CAPACITOR, C_OUT

The output capacitor C_OUTdirectly affects the magnitude of

the output ripple voltage. In general, the higher the value of

C_OUT, the lower the output ripple magnitude. Multilayer ce-

ramic capacitors with low ESR are the best choice. At the

lighter loads, the low ESR ceramics offer a much lower Vout

ripple that the higher ESR tantalums of the same value. At the

higher loads, the ceramics offer a slightly lower Vout ripple

magnitude than the tantalums of the same value. However,

the dv/dt of the Vout ripple with the ceramics is much lower

that the tantalums under all load conditions. Capacitor voltage

rating must be sufficient, 10V or greater is recommended.

INDUCTOR, L₁

The LP3954’s high switching frequency enables the use of

the small surface mount inductor. A 4.7 µH shielded inductor

is suggested for 2 MHz operation, 10 µH should be used at 1

MHz. The inductor should have a saturation current rating

higher than the peak current it will experience during circuit

operation (1A). Less than 300 mΩ ESR is suggested for high

efficiency. Open core inductors cause flux linkage with circuit

components and interfere with the normal operation of the

circuit. This should be avoided. For high efficiency, choose an

inductor with a high frequency core material such as ferrite to

reduce the core losses. To minimize radiated noise, use a

toroid, pot core or shielded core inductor. The inductor should

be connected to the SW pin as close to the IC as possible.

Some ceramic capacitors, especially those in small pack-

ages, exhibit a strong capacitance reduction with the

increased applied voltage. The capacitance value can fall

to below half of the nominal capacitance. Too low output

capacitance will increase the noise and it can make the

boost converter unstable.

INPUT CAPACITOR, C_IN

The input capacitor C_INdirectly affects the magnitude of the

input ripple voltage and to a lesser degree the V_OUTripple. A

higher value C_INwill give a lower V_INripple. Capacitor voltage

rating must be sufficient, 10V or greater is recommended.

LIST OF RECOMMENDED EXTERNAL COMPONENTS

Symbol

C_VDD1

C_VDD2

C_VDDIO

C_VDDA

C_OUT

Symbol explanation

Value

100

1

Unit

nF

µF

µH

nF

Type

Ceramic, X7R / X5R

Ceramic, X7R / X5R, 10V

Ceramic, X7R / X5R

Shielded,low ESR, Isat 1A

Ceramic, X7R

C between VDD1 and GND

C between VDD2 and GND

C between VDDIO and GND

C between VDDA and GND

C between FB and GND

10

C_IN

C between battery voltage and GND

L between SW and V_BATat 2 MHz

C between V_REFand GND

C between V_DDIOand GND

R between I_FLASHand GND

R between I_RGBand GND

10

L_BOOST

C_VREF

C_VDDIO

R_FLASH

R_RBG

4.7

100

1.2

5.6

82

Ceramic, X7R

±1%

kΩ

V

±1%

R_RT

R between I_RTand GND

±1%

D_OUT

Rectifying Diode (Vf @ maxload)

C between Audio input and ASE

0.3

100

Schottky diode

C_ASE

nF

Ceramic, X7R / X5R

LEDs

D_LIGHT

User defined

TDK BSC2015

Light Sensor

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34

Application Examples

EXAMPLE 1

20132255

MAIN BACKLIGHT

—

SUB BACKLIGHT

AUDIO SYNCHRONIZED FUNLIGHTS

RGB INDICATION LIGHT

FLASH LED

—

FLIP PHONE

35

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EXAMPLE 2

20132256

6 WHITE LED BACKLIGHT

—

KEY PAD LIGHTS

RGB INDICATION LED

WHITE SINGLE LED FLASH

TEMPERATURE SENSOR

SMART PHONE

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36

EXAMPLE 3

20132257

MAIN BACKLIGHT

—

KEYPAD LIGHTS

AUDIO SYNCHRONIZED FUNLIGHTS

VIBRA

CANDYBAR PHONE

37

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EXAMPLE 4

20132265

MAIN BACKLIGHT

—

SUB BACKLIGHT

AUDIO SYNCHRONIZED FUNLIGHTS

RGB INDICATION LIGHT

There may be cases where the audio input signal going into the LP3954 is too weak for audio synchronization. This figure presents a single-supply inverting

amplifier connected to the ASE input for audio signal amplification. The amplification is +20 dB, which is well enough for 20 mVp-p audio signal. Because the

amplifier (LMV321) is operating in single supply voltage, a voltage divider using R3 and R4 is implemented to bias the amplifier so the input signal is within the

input common-mode voltage range of the amplifier. The capacitor C1 is placed between the inverting input and resistor R1 to block the DC signal going into the

audio signal source. The values of R1 and C1 affect the cutoff frequency, fc = 1/(2*Pi*R1*C1), in this case it is around 160 Hz. As a result, the LMV321 output

signal is centered around mid-supply, that is V_DDA/2. The output can swing to both rails, maximizing the signal-to-noise ratio in a low voltage system

USING EXTRA AMPLIFIER

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38

EXAMPLE 5

20132269

MAIN BACKLIGHT

—

SUB BACKLIGHT

AUDIO SYNCHRONIZED FUNLIGHTS

RGB INDICATION LIGHT

Here, a second order RC-filter is used on the ASE input to convert a PWM signal to an analog waveform.

USING PWM SYGNAL

More application information is available in the document "LP3954 Evaluation Kit".

39

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40

41

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LP3954 Registers

REGISTER BIT EXPLANATIONS

Each register is shown with a key indicating the accessibility of the each individual bit, and the initial condition:

Register Bit Accessibility and Initial Condition

Key

rw

Bit Accessibility

Read/write

r

Read only

–0,–1

Condition after POR

RGB CTRL (00H) – RGB LEDS CONTROL REGISTER

D7

cc_rgb1

rw-1

D6

cc_rgb2

rw-1

D5

D4

D3

D2

D1

D0

r1sw

rw-0

g1sw

rw-0

b1sw

rw-0

r2sw

rw-0

g2sw

rw-0

b2sw

rw-0

0 - R1, G1 and B1 are constant current sinks, current limited internally

1 - R1, G1 and B1 are switches, limit current with external ballast resistor

cc_rgb1 Bit 7

cc_rgb2 Bit 6

0 – R2, G2 and B2 are constant current sinks, current limited internally

1 – R2, G2 and B2 are switches, limit current with external ballast resistor

0 – R1 disabled

1 – R1 enabled

r1sw

g1sw

b1sw

r2sw

g2sw

b2sw

Bit 5

Bit 4

0 – G1 disabled

1 – G1 enabled

Bit 3 0 – B1 disabled

1 – B1 enabled

0 – R2 disabled

Bit 2

1 – R2 enabled

0 – G2 disabled

Bit 1

1 – G2 enabled

0 – B2 disabled

Bit 0

1 – B2 enabled

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42

EXT_PWM_CONTROL (07H) – EXTERNAL PWM CONTROL REGISTER

D7

wled1_4_pwm

rw-0

D6

wled5_6_pwm

rw-0

D5

r1_pwm

rw-0

D4

g1_pwm

rw-0

D3

b1_pwm

rw-0

D2

r2_pwm

rw-0

D1

g2_pwm

rw-0

D0

b2_pwm

rw-0

0 – WLED1…WLED4 PWM control disabled

1 – WLED1…WLED4 PWM control enabled

wled1_4_pwm

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0 – WLED5, WLED6 PWM control disabled

1 – WLED5, WLED6 PWM control enabled

wled5_6_pwm

r1_pwm

0 – R1 PWM control disabled

1 – R1 PWM control enabled

0 – G1 PWM control disabled

1 – G1 PWM control enabled

g1_pwm

b1_pwm

r2_pwm

0 – RB PWM control disabled

1 – B1 PWM control enabled

0 – R2 PWM control disabled

1 – R2 PWM control enabled

0 – G2 PWM control disabled

1 – G2 PWM control enabled

g2_pwm

b2_pwm

0 – B2 PWM control disabled

1 – B2 PWM control enabled

WLED CONTROL (08H) – WLED CONTROL REGISTER

D7

r-0

D6

r-0

D5

D4

fade_sel

rw-0

D3

en_fade

rw-0

D2

D1

D0

en_w5_6

rw-0

slope

rw-0

displ

rw-0

en_w1_4

rw-0

0 – fade execution time 1.3 sec

1 – fade execution time 0.65 sec

slope

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0 – fade control for WLED1… WLED4

1 – fade control for WLED5, WLED6

fade_sel

en_fade

displ

0 – automatic fade disabled

1 – automatic fade enabled

0 – WLED1-4 and WLED5-6 are controlled separately

1 – WLED1-4 and WLED5-6 are controlled with WLED1-4 controls

0 – WLED1…WLED4 disabled

1 – WLED1…WLED4 enabled

en_w1_4

en_w5_6

0 – WLED5,WLED6 disabled

1 – WLED5,WLED6 enabled

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WLED1-4 (09H) – WLED1…WLED4 BRIGHTNESS CONTROL REGISTER

D7

D6

D5

D4

D3

D2

D1

D0

wled1_4[7:0]

rw-0

Adjustment

wled1_4[7:0]

0000 0000

0000 0001

0000 0010

0000 0011

0000 0100

…

Typical driver current (ma)

0

0.1

0.2

0.3

0.4

…

wled1_4[7:0]

Bits 7-0

1111 1101

1111 1110

1111 1111

25.3

25.4

25.5

WLED5-6 (0AH) – WLED5, WLED6 BRIGHTNESS CONTROL REGISTER

D7

D6

D5

D4

D3

D2

D1

D0

wled5_5[7:0]

rw-0

Adjustment

wled5_6[7:0]

0000 0000

0000 0001

0000 0010

0000 0011

0000 0100

…

Typical driver current (ma)

0

0.1

0.2

0.3

0.4

…

wled5_6[7:0]

Bits 7-0

1111 1101

1111 1110

1111 1111

25.3

25.4

25.5

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44

ENABLES (0BH) – ENABLES REGISTER

D7

pwm_sync

rw-0

D6

D5

en_boost

rw-0

D4

r-0

D3

r-0

D2

en_autoload

rw-1

D1

D0

nstby

rw-0

rgb_sel[1:0]

rw-0

0 – synchronization to external clock disabled

1 – synchronization to external clock enabled

pwm_sync

nstby

Bit 7

Bit 6

Bit 5

Bit 2

0 – LP3954 standby mode

1 – LP3954 active mode

0 – boost converter disabled

1 – boost converter enabled

en_boost

en_autoload

0 – internal boost converter active load off

1 – internal boost converter active load on

Color LED control mode selection

rgb_sel[1:0]

Audio sync

connected to

Pattern generator

connected to

00

01

10

11

none

RGB1

RGB1 & RGB2

RGB2

rgb_sel[1:0]

Bits 1-0

RGB2

RGB1

RGB1 & RGB2

none

ADC_OUTPUT (0CH) – ADC DATA REGISTER

D7

r-0

D6

r-0

D5

r-0

D4

D3

r-0

D2

r-0

D1

r-0

D0

r-0

data[7:0]

r-0

data[7:0]

Bits 7-0

Data register ADC (Audio input, light or temperature sensors)

45

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BOOST_OUTPUT (0DH) – BOOST OUTPUT VOLTAGE CONTROL REGISTER

D7

D6

D5

D4

D3

D2

D1

D0

Boost[7:0]

rw-0

rw-1

Adjustment

Boost[7:0]

Typical boost output (V)

0000 0000

0000 0001

0000 0011

0000 0111

0000 1111

0001 1111

0011 1111

0111 1111

1111 1111

4.00

4.25

4.40

Boost[7:0]

Bits 7-0

4.55

4.70

4.85

5.00 (default)

5.15

5.30

BOOST_FRQ (0EH) – BOOST FREQUENCY CONTROL REGISTER

D7

r-0

D6

r-0

D5

r-0

D4

r-0

D3

r-0

D2

D1

D0

freq_sel[2:0]

rw-1

Adjustment

freq_sel[2:0]

Frequency

2.00 MHz

1.67 MHz

1.00 MHz

freq_sel[2:0]

Bits 7-0

1xx

01x

00x

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46

HC_FLASH (10H) – HIGH CURRENT FLASH DRIVER CONTROL REGISTER

D7

r-0

D6

r-0

D5

hc_pwm

rw-0

D4

D3

D2

D1

D0

en_hcflash

rw-0

fl_t[1:0]

hc[1:0]

rw-0

0 – PWM for high current flash driver disabled

1 – PWM for high current flash driver enabled

hc_pwm

fl_t[1:0]

Bit 5

Flash duration for high current driver

fl_t[1:0]

00

Typical flash duration

200 ms

Bits 4-3

01

400 ms

10

600 ms

11

According EN_FLASH pin on duration

Current control for high current flash driver

hc[1:0]

current

00

01

10

11

0.25×I_MAX(FLASH)

0.50×I_MAX(FLASH)

0.75×I_MAX(FLASH)

1.00×I_MAX(FLASH)

hc[1:0]

Bits 2-1

Bit 0

0 – high current flash driver disabled

1 – high current flash driver enabled

en_hcflash

PATTERN_GEN_CTRL (11H) – PATTERN GENERATOR CONTROL REGISTER

D7

r-0

D6

r-0

D5

r-0

D4

r-0

D3

r-0

D2

rgb_start

rw-0

D1

D0

log

loop

rw-0

0 – Pattern generator disabled

1 – execution pattern starting from command 1

rgb_start

loop

Bit 2

Bit 1

Bit 0

0 – pattern generator loop disabled (single patter)

1 – pattern generator loop enabled (execute until stopped)

0 – color intensity mode 0

1 – color intensity mode 1

log

47

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RGB1_MAX_CURRENT (12H) – RGB1 DRIVER INDIVIDUAL MAXIMUM CURRENT CONTROL REGISTER

D7

r-0

D6

r-0

D5

D4

D3

D2

D1

D0

ir1[1:0]

ig1[1:0]

ib1[1:0]

rw-0

Maximum current for R1 driver

ir1[2:0]

00

Maximum output current

0.25×I_MAX

ir1[1:0]

Bits 5-4

Bits 3-2

Bits 1-0

01

0.50×I_MAX

10

0.75×I_MAX

11

1.00×I_MAX

1aximum current for G1 driver

ig2[1:0]

Maximum output current

00

01

10

11

0.25×I_MAX

0.50×I_MAX

ig1[1:0]

ib1[1:0]

0.75×I_MAX

1.00×I_MAX

Maximum current for B1 driver

ib1[1:0]

00

Maximum output current

0.25×I_MAX

01

0.50×I_MAX

10

0.75×I_MAX

11

1.00×I_MAX

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48

RGB2_MAX_CURRENT (13H) – RGB2 DRIVER INDIVIDUAL MAXIMUM CURRENT CONTROL REGISTER

D7

D6

D5

D4

D3

D2

D1

D0

ir2[1:0]

ig2[1:0]

ib2[1:0]

rw-0

Maximum current for R2 driver

ir2[2:0]

00

Maximum output current

0.25×I_MAX

ir2[1:0]

Bits 5-4

Bits 3-2

Bits 1-0

01

0.50×I_MAX

10

0.75×I_MAX

11

1.00×I_MAX

Maximum current for G2 driver

ig2[1:0]

Maximum output current

00

01

10

11

0.25×I_MAX

0.50×I_MAX

ig2[1:0]

ib2[1:0]

0.75×I_MAX

1.00×I_MAX

Maximum current for B2 driver

ib2[1:0]

00

Maximum output current

0.25×I_MAX

01

0.50×I_MAX

10

0.75×I_MAX

11

1.00×I_MAX

49

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AUDIO_SYNC_CTRL1 (2AH) – AUDIO SYNCHRONIZATION AND ADC CONTROL REGISTER 1

D7

D6

gain_sel[2:0]

rw-0

D5

D4

sync_mode

rw-0

D3

en_agc

rw-0

D2

en_sync

rw-0

D1

D0

input_sel[1:0]

rw-0

rw-1

Input signal gain control

gain_sel[2:0]

000

gain, db

0 (default)

001

3

6

010

gain_sel[2:0]

sync_mode

Bits 7-5

011

9

100

12

15

18

21

101

110

111

Input filter mode control

0 – Amplitude mode

Bit 4

1 – Frequency mode

0 – automatic gain control disabled

1 – automatic gain control enabled

en_agc

Bit 3

Bit 2

0 – audio synchronization disabled

1 – audio synchronization enabled

en_sync

ADC input selector

input_sel[1:0]

Input

00

01

10

11

Single ended input signal (ASE)

Temperature measurement

Ambient light measurement

No input (default)

input_sel[1:0]

Bits 1-0

AUDIO_SYNC_CTRL2 (2BH) – AUDIO SYNCHRONIZATION AND ADC CONTROL REGISTER 2

D7

r-0

D6

r-0

D5

r-0

D4

en_avg

rw-0

D3

D2

D1

D0

mode_ctrl[1:0]

speed_ctrl[1:0]

rw-0

0 – averaging disabled

1 – averaging enabled

en_avg

Bit 4

mode_ctrl[1:0]

Bits 3-2

Filtering mode control

LEDs light response time to audio input

speed_ctrl[1:0]

Response

FASTEST (default)

FAST

00

01

10

11

speed_ctrl[1:0]

Bits 1-0

MEDIUM

SLOW

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50

PATTERN CONTROL REGISTERS

Command_[1:8]A – Pattern Control Register A

D7

D6

D5

D4

D3

D2

D1

D0

r[2:0]

rw-0

g[2:0]

rw-0

cet[3:2]

rw-0

Command_[1:8]B – Pattern Control Register B

D7

D6

D5

D4

D3

D2

D1

D0

cet[1:0]

b[2:0]

rw-0

tt[2:0]

rw-0

Red color intensity

current, %

r[2:0]

log=0

log=1

000

001

010

011

100

101

110

111

0×I_MAX

1%×I_MAX

2%×I_MAX

4%×I_MAX

10%×I_MAX

21%×I_MAX

46%×I_MAX

100%×I_MAX

7%×I_MAX

14%×I_MAX

21%×I_MAX

32%×I_MAX

46%×I_MAX

71%×I_MAX

100%×I_MAX

Bits

7-5A

r[2:0]

^*log bit is in pattern_gen_ctrl register

Green color intensity

current, %

g[2:0]

log=0

log=1

0×I_MAX

000

001

010

011

100

101

110

111

0×I_MAX

7%×I_MAX

14%×I_MAX

21%×I_MAX

32%×I_MAX

46%×I_MAX

71%×I_MAX

100%×I_MAX

1%×I_MAX

2%×I_MAX

4%×I_MAX

10%×I_MAX

21%×I_MAX

46%×I_MAX

100%×I_MAX

Bits

4-2A

g[2:0]

^*log bit is in pattern_gen_ctrl register

51

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Command execution time

cet[3:0] CET duration, ms

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

197

393

590

786

983

1180

Bits

1-0A

7-6B

1376

cet[3:0]

1573

1769

1966

2163

2359

2556

2753

2949

3146

Blue color intensity

b[2:0]

current, %

log=0

log=1

0×I_MAX

000

001

010

011

100

101

110

111

0×I_MAX

7%×I_MAX

14%×I_MAX

21%×I_MAX

32%×I_MAX

46%×I_MAX

71%×I_MAX

100%×I_MAX

1%×I_MAX

2%×I_MAX

4%×I_MAX

10%×I_MAX

21%×I_MAX

46%×I_MAX

100%×I_MAX

Bits

5-3B

b[2:0]

^*log bit is in pattern_gen_ctrl register

Transition time

tt[2:0]

000

001

010

011

100

101

110

111

Transition time, ms

0

55

110

221

442

885

1770

3539

Bits

2-0B

tt[2:0]

RESET (60H) - RESET REGISTER

D7

r-0

D6

r-0

D5

D4

D3

D2

D1

D0

r-0

Writing any data to Reset Register in address 60H can reset LP3954

r-0 r-0 r-0 r-0

r-0

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52

Physical Dimensions inches (millimeters) unless otherwise noted

The dimension for X1 ,X2 and X3 are as given:

X1=3.00mm ±0.03mm

—

X2=3.00mm ±0.03mm

X3=0.60mm ±0.075mm

36-bump micro SMD Package, 3 x 3 x 0.6mm, 0.5mm pitch

NS Package Number TLA36AAA

53

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The dimension for X1 ,X2 and X3 are as given:

X1=3.00mm ±0.03mm

—

X2=3.00mm ±0.03mm

X3=0.65mm ±0.075mm

36-bump micro SMDxt Package, 3 x 3 x 0.65mm, 0.5mm pitch

NS Package Number RLA36AAA

See Application note AN1112 for micro SMD and AN1412 for micro SMDxt PCB design and assembly instructions.

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54

Notes

55

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Notes

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型号：	LP3954TL
厂家：	National Semiconductor
描述：	Advanced Lighting Management Unit 先进的照明管理单元显示驱动器驱动程序和接口接口集成电路
文件：	总56页 (文件大小：6162K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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