LP3958TL [NSC]
Lighting Management Unit with High Voltage Boost Converter; 高电压升压转换器的照明管理单元
| 型号： | LP3958TL |
| 厂家： | 
National Semiconductor |
| 描述： | Lighting Management Unit with High Voltage Boost Converter |
| 文件： | 总28页 (文件大小：1091K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
February 2006
LP3958
Lighting Management Unit with High Voltage Boost
Converter
General Description
Features
n High efficiency boost converter with programmable
output voltage
LP3958 is a Lighting Management Unit for portable applica-
tions. It is used to drive display backlight and keypad LEDs.
The device can drive 5 separately connected strings of LEDs
with high voltage boost converter.
n 2 individual drivers for serial display backlight LEDs
n 3 drivers for serial keypad LEDs
n Automatic dimming controller
n Stand alone serial keypad LEDs controller
n 3 general purpose IO pins
The keypad LED driver allows driving LEDs from high volt-
age boost converter or separate supply voltage.The MAIN
and SUB outputs are high resolution current mode drivers.
Keypad LED outputs can be used in switch mode and cur-
rent mode. External PWM control can be used for any se-
lected outputs.
n 25-bump micro SMD Package: (2.54mm x 2.54mm x
0.6mm)
The device is controlled through 2-wire low voltage I2C
compatible interface that reduces the number of required
connections.
Applications
n Cellular Phones and PDAs
n MP3 Players
LP3958 is offered in a tiny 25-bump micro-SMD package.
n Digital Cameras
Typical Application
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© 2006 National Semiconductor Corporation
DS201755
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Connection Diagrams and Package Mark Information
CONNECTION DIAGRAMS
25-Bump Thin Micro SMD Package, Large Bump
NS Package Number TLA25CCA
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20175571
Bottom View
Top View
PACKAGE MARK
20175596
ORDERING INFORMATION
Order Number
LP3958TL
Package Marking
SJHB
Supplied As
TNR 250
Spec/Flow
NoPb
NoPb
LP3958TLX
SJHB
TNR 3000
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2
Connection Diagrams and Package Mark Information (Continued)
PIN DESCRIPTIONS
Pin #
5E
5D
5C
5B
5A
4E
4D
4C
4B
4A
3E
3D
3C
3B
3A
2E
2D
2C
2B
2A
1E
1D
1C
1B
1A
Name
SW
Type
Output
Description
Boost Converter Power Switch
Boost Converter Feedback
FB
Input
KEY1
Output
Keypad LED Output 1 (Current Sink)
Keypad LED Output 2 (Current Sink)
Keypad LED Output 3 (Current Sink)
Power Switch Ground
KEY2
Output
KEY3
Output
GND_SW
NRST
Ground
Input
External Reset, Active Low
SCL
Logic Input
Input
Clock Input for I2C Compatible Interface
External Keypad LED Maximum Current Set Resistor
Ground for KEY LED Currents
IKEY
GND_KEY
VDD2
Ground
Power
Supply Voltage 3.0...5.5 V
VDDIO
SDA
Power
Supply Voltage for Digital Input/Output Buffers and Drivers
Data Input/Output for I2C Compatible Interface
General Purpose Logic Input/Output
General Purpose Logic Input/Output / External PWM Input
Ground for White LED Currents (MAIN and SUB Outputs)
Ground
Logic Input/Output
Logic Input/Output
Logic Input/Output
Ground
GPIO[2]
GPIO[0] / PWM
GND_WLED
GNDT
VDD1
Ground
Power
Supply Voltage 3.0...5.5 V
VREF
Output
Reference Voltage (1.23V)
GPIO[1]
MAIN
Logic Input/Output
Output
General Purpose Logic Input/Output
MAIN Display White LED Current Output (Current Sink)
SUB Display White LED Current Output (Current Sink)
Internal LDO Output (2.80V)
SUB
Output
VDDA
GND
Output
Ground
Ground for Core Circuitry
IRT
Input
Oscillator Frequency Set Resistor
3
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Absolute Maximum Ratings (Notes 1,
2)
Operating Ratings (Notes 1, 2)
V (SW, FB, MAIN, SUB)
0 to +19V
3.0 to 5.5V
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
VDD1,2
VDDIO
1.65V to VDD1
Recommended Load Current
V (SW, FB, MAIN, SUB, KEY1,
KEY2, KEY3)
-0.3V to +20V
(KEY1, KEY2, KEY3) CC Mode
Recommended Total Boost
Converter Load Current
0mA to 15mA/driver
VDD1, VDD2, VDDIO, VDDA
Voltage on IKEY, IRT, VREF
-0.3V to +6.0V
-0.3V to VDD1+0.3V
with 6.0V max
-0.3V to VDDIO +0.3V
with 6.0V max
10µA
0mA to 70mA
-30oC to +125oC
Junction Temperature (TJ) Range
Ambient Temperature (TA) Range
(Note 6)
-30oC to +85oC
Voltage on Logic Pins
I (VREF
)
Thermal Properties
Junction-to-Ambient Thermal
Resistance(θJA), TLA25 Package
(Note 7)
I(KEY1, KEY2, KEY3)
Continuous Power Dissipation
(Note 3)
100mA
Internally Limited
125oC
-65oC to +150oC
60 - 100oC/W
Junction Temperature (TJ-MAX
Storage Temperature Range
Maximum Lead Temperature
(Soldering) (Note 4)
)
260oC
ESD Rating (Note 5)
Human Body Model:
2kV
Machine Model:
200V
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4
Electrical Characteristics (Notes 2, 8)
Limits in standard typeface are for TJ = 25o C. Limits in boldface type apply over the operating ambient temperature range
o
o
<
<
(-30 C TA +85 C). Unless otherwise noted, specifications apply to the LP3958 Block Diagram with: VDD1,2 = 3.0 ... 5.5V,
CVDD = CVDDIO = 100nF, COUT = 2 x 4.7µF, CIN = 10µF, CVDDA = 1µF, CVREF = 100nF, L1 = 10µH, RKEY = 8.2kΩ and RRT
82kΩ (Note 9).
=
Symbol
Parameter
Condition
Min
Typ
Max
7
Units
IVDD
Standby supply current
NSTBY = L
1.7
µA
(VDD1, VDD2
No-boost supply current
(VDD1, VDD2
No-load supply current
(VDD1, VDD2
)
Register 0DH=08H (Note 10)
NSTBY = H,
300
750
800
µA
uA
)
EN_BOOST = L
NSTBY = H,
1300
)
EN_BOOST = H
Autoload OFF
VDDA
VREF
Output voltage of internal LDO
IVDDA = 1mA
2.80
1.23
V
%
V
-3
+3
Reference voltage (Note 11)
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under which operation of
the device is guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed performance limits and associated test conditions, see the
Electrical Characteristics tables.
Note 2: All voltages are with respect to the potential at the GND pins.
Note 3: Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at T =150oC (typ.) and disengages at
J
T =130oC (typ.).
J
Note 4: For detailed soldering specifications and information, please refer to National Semiconductor Application Note AN1112 : Micro SMD Wafer Level Chip Scale
Package
Note 5: The Human body model is a 100pF capacitor discharged through a 1.5kΩ resistor into each pin. The machine model is a 200pF capacitor discharged
directly into each pin. MIL-STD-883 3015.7
Note 6: In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may have to be
derated. Maximum ambient temperature (T
) is dependent on the maximum operating junction temperature (T
= 125oC), the maximum power
A-MAX
J-MAX-OP
dissipation of the device in the application (P
), and the junction-to ambient thermal resistance of the part/package in the application (θ ), as given by the
D-MAX
JA
following equation: T
= T
J-MAX-OP
– (θ x P
).
A-MAX
JA
D-MAX
Note 7: Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power dissipation exists,
special care must be paid to thermal dissipation issues in board design.
Note 8: Min and Max limits are guaranteed by design, test, or statistical analysis. Typical numbers are not guaranteed, but do represent the most likely norm.
Note 9: Low-ESR Surface-Mount Ceramic Capacitors (MLCCs) used in setting electrical characteristics.
Note 10: Boost output voltage set to 8V (08H in register 0DH) to prevent any unneccessary current consumption.
Note 11: No external loading allowed for V
pin.
REF
5
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Block Diagram
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6
Modes of Operation
RESET:
In the RESET mode all the internal registers are reset to the default values. Reset is entered always if input
NRST is LOW or internal Power On Reset is active. Power On Reset (POR) will activate during the chip
startup or when the supply voltages VDD1 and VDD2 fall below 1.5V. Once VDD1 and VDD2 rises above 1.5V,
POR will inactivate and the chip will continue to the STANDBY mode. NSTBY control bit is low after POR
by default.
STANDBY:
STARTUP:
The STANDBY mode is entered if the register bit NSTBY is LOW and Reset is not active. This is the low
power consumption mode, when all circuit functions are disabled. Registers can be written in this mode and
the control bits are effective immediately after start up.
When NSTBY bit is written high, the INTERNAL STARTUP SEQUENCE powers up all the needed internal
blocks (VREF, Bias, Oscillator etc.). To ensure the correct oscillator initialization, a 10ms delay is generated
by the internal state-machine. If the chip temperature rises too high, the Thermal Shutdown (THSD)
disables the chip operation and STARTUP mode is entered until no thermal shutdown event is present.
BOOST STARTUP: Soft start for boost output is generated in the BOOST STARTUP mode. The boost output is raised in low
current PWM mode during the 20ms delay generated by the state-machine. All LED outputs are off during
the 20ms delay to ensure smooth startup. The Boost startup is entered from Internal Startup Sequence if
EN_BOOST is HIGH or from Normal mode when EN_BOOST is written HIGH.
NORMAL:
During NORMAL mode the user controls the chip using the Control Registers. The registers can be written
in any sequence and any number of bits can be altered in a register in one write.
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fed to the inductor. An active load is used to remove the
excess charge from the output capacitor at very light loads.
Active load can be disabled with the EN_AUTOLOAD bit.
Disabling active load will increase slightly the efficiency at
light loads, but the downside is that pulse skipping will occur.
The Boost Converter should be stopped when there is no
load to minimise the current consumption.
Power-Up Sequence
When powering up the device, VDD1 and VDD2 should be
greater than VDDIO to prevent any damage to the device.
The topology of the magnetic boost converter is called CPM
control, current programmed mode, where the inductor cur-
rent is measured and controlled with the feedback. The user
can program the output voltage of the boost converter. The
output voltage control changes the resistor divider in the
feedback loop. The following figure shows the boost topol-
ogy with the protection circuitry. Four different protection
schemes are implemented:
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Magnetic Boost DC/DC Converter
The LP3958 Boost DC/DC Converter generates an 8…18V
supply voltage for the LEDs from single Li-Ion battery
(3V…4.5V). The output voltage is controlled with an 8-bit
register in 10 steps. The converter is a magnetic switching
PWM mode DC/DC converter with a current limit. Switching
frequency is 1MHz, when timing resistor RT is 82kΩ. Timing
resistor defines the internal oscillator frequency and thus
directly affects boost frequency and KEY timings.
1. Over voltage protection, limits the maximum output volt-
age
— Keeps the output below breakdown voltage.
— Prevents boost operation if battery voltage is much
higher than desired output.
2. Over current protection, limits the maximum inductor
current
— Voltage over switching NMOS is monitored; too high
voltages turn the switch off.
EMI filter (RSW and CSW) on the SW pin can be used to
suppress EMI caused by fast switching. These components
should be as near as possible to the SW pin to ensure
reliable operation. The LP3958 Boost Converter uses pulse-
skipping elimination to stabilize the noise spectrum. Even
with light load or no load a minimum length current pulse is
3. Feedback break protection. Prevents uncontrolled op-
eration if FB pin gets disconnected.
4. Duty cycle limiting, done with digital control.
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Boost Converter Topology
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8
Magnetic Boost DC/DC Converter (Continued)
MAGNETIC BOOST DC/DC CONVERTER ELECTRICAL CHARACTERISTICS
Symbol
Parameter
Maximum Continuous Load
Current
Conditions
Min
Typ
Max
Units
ILOAD
3.0V = VIN
70
mA
VOUT = 18V
VOUT
Output Voltage Accuracy
(FB Pin)
3.0V ≤ VIN ≤ 5.5V
VOUT = 18V
ISW = 0.5A
−3.5
+3.5
0.3
%
Ω
RDSON
fPWM
Switch ON Resistance
PWM Mode Switching
Frequency
0.15
1.0
RT = 82 kΩ
MHz
Frequency Accuracy
RT = 82 kΩ
−7
+7
%
−9
+9
tPULSE
Switch Pulse Minimum
Width
no load
45
ns
tSTARTUP Startup Time
IMAX SW Pin Current Limit
BOOST STANDBY MODE
Boost startup from STANDBY to VOUT
= 18V, no load
15
ms
800
1150
mA
User can set the Boost Converter to STANDBY mode by
writing the register bit EN_BOOST low. When EN_BOOST is
written high, the converter starts for 20ms in low current
PWM mode and then goes to normal PWM mode. All LED
outputs are off during the 20ms delay to ensure smooth
startup.
BOOST OUTPUT VOLTAGE CONTROL
User can control the boost output voltage by Boost Output
8-bit register.
Boost Output Voltage Control
Boost Output [7:0]
Boost Output
Register 0DH
Voltage (typical)
Bin
Dec
8
0000 1000
0000 1001
0000 1010
0000 1011
0000 1100
0000 1101
0000 1110
0000 1111
0001 0000
0001 0001
0001 0010
8.0V
9.0V
9
10
11
12
13
14
15
16
17
18
10.0V
11.0V
12.0V
13.0V
14.0V
15.0V
16.0V
17.0V
18.0V
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If register value is lower than 8, then value of 8 is used
internally.
If register value is higher than 18, then value of 18 is used
internally.
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Boost Converter Typical Performance Characteristics
Vin = 3.6V, Vout = 18.0V if not otherwise stated
Boost Converter Efficiency
Boost Typical Waveforms at 70mA Load
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20175580
Battery Current vs Voltage
Boost Output Voltage vs. Current
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Boost Line Regulation 3.0V - 3.6V, no load
Boost Turn On Time with No Load
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Boost Converter Typical Performance Characteristics (Continued)
Boost Load Transient Response 25mA – 70mA
Autoload Effect on Input Current, No Load
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20175586
Boost Maximum Current vs. Output Voltage
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Brightness control is logarithmic and is programmed as fol-
lows:
Functionality of Keypad LED
Outputs (KEY1, KEY2, KEY3)
LP3958 has three individual keypad LED output pins. Output
pins can be used in switch mode or constant current mode.
Output mode can be selected with the control register (ad-
dress 00H) bit CC_SW. If the bit is set high, then keypad
LED outputs are in switch mode, otherwise in constant cur-
rent mode. These modes are described later in separate
chapters.
Bright[2:0]
Brightness [%]
Ratio to max
brightness
0
000
001
010
011
100
101
110
111
0
1.56
3.12
6.25
12.5
25
1/64
1/32
1/16
1/8
Keypad LED output control can be done in three ways:
1/4
1. Defining the expected balance and brightness in Keypad
register (address 01H)
50
1/2
2. Direct setting each LED ON/OFF via Keypad control
register (address 00H)
100
1/1
The LED balance can be selected as follows. This is valid
only in non-overlapping mode.
3. External PWM control
BRIGHTNESS CONTROL WITH KEYPAD REGISTER
Balance
[2:0]
000
KEY1
active [%]
KEY2
active [%]
KEY3
active [%]
If the keypad LED output is used by defining the balance and
brightness in the Keypad register, then one needs to set
EN_KEYP bit high and KEYP_PWM bit high in the Control
register (address 00H). K1SW, K2SW and K3SW are used
to enable each LED output, enabled when written high.
CC_SW defines the LED output mode. A single register is
used for defining the balance and brightness for keypad LED
output:
100
0
0
100
0
0
0
001
010
0
100
0
011
50
0
50
50
0
100
50
50
33
25
101
50
33
50
KEYPAD REGISTER (01H)
110
33
25
Name
Bit Description
111
BALANCE[2:0]
6:4 Balance of KEY1, KEY2 and
KEY3 outputs
BRIGHT[2:0]
OVL
3:1 Brightness control
0
Overlapping mode selection:
0 = non-overlapping mode
1 = overlapping mode
OVERLAPPING MODE
The brightness is controlled using PWM duty cycle based control method as the following figure shows.
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Overlapping Mode
Since KEY outputs are on simuneltaneously, the maximum load peak current is:
IMAX = I(KEY1)MAX + I(KEY2)MAX + I(KEY3)MAX
NON-OVERLAPPING MODE
The timing diagram shows the splitted KEY1, KEY2 and KEY3 and brightness control effect to splitted parts. Full brightness is
used in the diagram. If for example 1⁄
brightness is used, the frame is still 50µs, but all LED outputs’ ON time is 50% shorter and
at the last 25µs all LED outputs are OFF.
2
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12
Functionality of Keypad LED Outputs (KEY1, KEY2, KEY3) (Continued)
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Non-overlapping Mode
The non-overlapping mode has 8-programmed balance ra-
Maximum current for each LED output is adjusted with the
Keypad max current register in following way:
tios. Since the KEY1, KEY2 and KEY3 are split in to non-
overlapping slots the output current through the keypad LED
can be calculated by following equation:
IK1[1:0], IK2[1:0], IK3[1:0] Maximum current / output
00
01
10
11
0.25 x IMAX
0.50 x IMAX
0.75 x IMAX
1.00 x IMAX
IAVG=(CKEY1xIKEY1+CKEY2xIKEY2+CKEY3xIKEY3)xB
where
C = Balance [%] (see table of balance control earlier)
B = Brightness [%] (see table of Brightness Control)
External ballast resistors are not needed in this mode. The
LED ON/OFF CONTROL WITH KEYPAD CONTROL
REGISTER
maximum current for all keypad LED drivers is set with RKEY
The equation for calculating the maximum current is:
.
Each LED output can be set ON by writing the corresponding
bit high in the control register. K1SW controls KEY1, K2SW
controls KEY2 and K3SW controls KEY3 output. Note that
EN_KEYP bit must be high and KEYP_PWM bit low. In this
mode, the KEYPAD register does not have any effect.
CC_SW bit in control register defines the LED output mode.
IMAX = 100 x 1.23V / (RKEY + 50 Ω)
where
IMAX = maximum KEY current in any KEY output (during
constant current mode)
1.23V = reference voltage
100 = internal current mirror multiplier
RKEY = resistor value in Ohms
Switch Mode / Constant Current Mode
Each keypad LED output can be set to act as a switch or a
constant current sink. Selection of mode is done with the
CC_SW bit in the Control Register. If bit is set high, then the
switch mode is selected. Default is switch mode.
50 Ω = Internal resistor in the IKEY input
Table with example resistance values and corresponding
output currents:
Maximum current / output
KEY resistor RKEY (kΩ)
1. SWITCH MODE
IMAX (mA)
In switch mode, the keypad LED outputs are low ohmic
switches to ground. Resistance is typically 3.5Ω. External
ballast resistors must be used to limit the current
through the LED.
8.2
9.1
10
12
15
18
24
14.9
13.4
12.2
10.2
8.2
2. CONSTANT CURRENT MODE
In constant current mode, the maximum output current is
defined with a single external resistor (RKEY) and the maxi-
mum current control register (address 02H).
6.8
5.1
KEYPAD MAX CURRENT REGISTER (02H)
Note that the LED output requires a minimum saturation
voltage in order to act as a true constant current sink. The
saturation voltage minimum is typically 100mV. If the LED
output voltage drops below 100mV, then the current will
decrease significantly.
Name
IK1[1:0]
IK2[1:0]
IK3[1:0]
Bit
5:4
3:2
1:0
Description
KEY1 maximum current
KEY2 maximum current
KEY3 maximum current
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Functionality of Keypad LED Outputs (KEY1, KEY2, KEY3) (Continued)
External PWM Control
The GPIO[0]/PWM pin can be used to control the KEY
output. PWM function for the pin is selected by writing EN-
_PWM_PIN high in GPIO control register (address 06H).
Note, that EN_KEYP bit must be set high. Each LED output
can be enabled with K1SW, K2SW and K3SW bits.
polarity of external PWM control is active high i.e. when high,
then LED output is enabled. If KEYP_PWM is set low, then
each selected LED output is controlled directly with external
PWM input. If KEYP_PWM is set high, then internal PWM
control is modulated by the external PWM input. In latter
case, internal PWM control is passed to LED when external
PWM input is high.
EN_EXT_K1_PWM,
EN_EXT_K2_PWM
and
EN_EXT_K3_PWM bits are used to select, which LED out-
puts are controlled with the external PWM input. Note that
Keypad LEDs Driver Performance Characteristics
Symbol
ILEAKAGE
IMAX(KEY)
Parameter
Condition
Min Typ
Max Units
KEY1, KEY2, KEY3 pin leakage current
Maximum recommended sink current
1
µA
mA
mA
%
CC mode
15
60
SW mode
@
Accuracy 15mA
CC mode
5
Current mirror ratio
CC mode
1:100
KEY current matching error
Switch resistance
IKEY set to 15mA, CC mode
SW mode
3
%
Ω
RSW
ƒKEY
3.5
20
KEY internal PMW switching frequency
Accuracy same as internal clock
frequency accuracy
IKEY set to 15mA
kHz
VSAT
Saturation voltage (current drop 10%)
100 500
mV
Note: KEY current should be limited as follows:
constant current mode – limited by external R
resistor
KEY
switch mode – limited by external ballast resistors
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Backlight Drivers
LP3958 has 2 independent backlight drivers. Both drivers are regulated constant current sinks. LED current for both LED strings
are controlled by the 8-bit current mode DACs with 0.1 mA step. MAIN and SUB LEDs can be also controlled with one DAC
(MAIN) for better matching allowing the use of larger displays having up to 8 white LEDs by setting DISPL bit to 1.
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SUB output for 2 LEDs (DISPL = 0)
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MAIN output for 4 LEDs (DISPL = 0)
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MAIN and SUB outputs for 8 LEDs (DISPL = 1)
PWM CONTROL
External PWM control is enabled by writing 1 to EN_MAIN_PWM and/or EN_SUB_PWM bits in register address 2BH. GPIO[0]
pin is used as external PWM input when EN_PWM_PIN is set high. PWM input is active high, i.e. LED is activated when in high
state.
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Adjustment is made with 04H (main current) and with 05H
(sub current) registers:
Backlight Drivers (Continued)
FADE IN / FADE OUT
MAIN CURRENT [7:0]
SUB CURRENT [7:0]
0000 0000
0000 0001
0000 0010
0000 0011
…
Driver current,
mA (typical)
LP3958 has an automatic fade in and out for main and sub
backlight. The fade function is enabled with EN_FADE bit.
The slope of the fade curve is set by the SLOPE bit. Fade
control for main and sub display is set by FADE_SEL bit.
0
0.1
0.2
0.3
…
Recommended fading sequence:
1. ASSUMPTION: Current WLED value in register
2. Set SLOPE
3. Set FADE_SEL
…
…
4. Set EN_FADE = 1
1111 1101
25.3
25.4
25.5
5. Set target WLED value
1111 1110
6. Fading will be done either within 0.65s or 1.3s based on
SLOPE selection
1111 1111
Fading times apply to full scale change i.e. from 0 to 100% or
vice versa. If the current change does not correspond to full
scale change, the time will be respectively shorter. See
WLED Dimming diagrams for typical fade times.
WLED CONTROL REGISTER (03H)
Name
Bit
Description
FADE execution time:
SLOPE
5
0 = 1.3s (full scale)
1 = 0.65s (full scale)
FADE selection:
FADE_SEL
EN_FADE
DISPL
4
3
2
0 = FADE controls MAIN
1 = FADE controls SUB
FADE enable
0 = FADE disabled
1 = FADE enabled
Display mode:
0 = MAIN and SUB individual control
1 = MAIN and SUB controlled with
MAIN DAC
EN_MAIN
EN_SUB
1
0
MAIN enable:
0 = disable
1 = enable
SUB enable:
0 = disable
1 = enable
Note: if DISPL=1 and FADE_SEL=0 then FADE effects MAIN and SUB
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16
Backlight Driver Electrical Characteristics
Symbol
IMAX
ILEAKAGE
IMAIN
Parameter
Conditions
Min
Typical
25.5
Max
30
Units
mA
Maximum Sink Current
Leakage Current
VSUB, MAIN =18V
0.03
1
µA
MAIN Current tolerance
SUB Current tolerance
Sink Current Matching Error
Sink Current Matching Error
95% Saturation Voltage
IMAIN and ISUB set to 12.8mA (80H)
11.1
12.8
14.1
mA
ISUB
MatchMAIN-SUB
MatchMAIN-SUB
VSAT
ISINK=12.8mA, DISPL=1
ISINK=12.8mA, DISPL=0
ISINK=25mA
0.2
5
%
%
400
600
mV
800
Note: Matching is the maximum difference from the average.
WLED Dimming, SLOPE=0
WLED Dimming, SLOPE=1
20175539
20175540
WLED Output Current vs. Voltage
20175592
17
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General Purpose I/O Functionality
GPIO DATA (07H)
LP3958 has three general purpose I/O pins: GPIO[0]/PWM,
GPIO[1] and GPIO[2]. GPIO[0]/PWM can also be used as a
PWM input for the external LED PWM controlling. GPIO
bi-directional drivers are operating from the VDDIO supply
domain.
Name
Bit
Description
Data bits
DATA[2:0]
2:0
GPIO control register is used to set the direction of each
GPIO pin. For example, by setting OEN0 bit high the
GPIO[0]/PWM pin acts as a logic output pin with data de-
fined DATA0 in GPIO data register. Note, that the EN_PW-
M_PIN bit overrides OEN0 state by forcing GPIO[0]/PWM to
act as PWM input. GPIO[1] and GPIO[2] pins can be se-
lected to be inputs or outputs, defined by OEN1 and OEN2
bit status. PWM functionality is valid only for GPIO[0]/PWM
pin. GPIO data register contains the data of GPIO pins.
When output direction is selected to GPIO pin, then GPIO
data register defines the output pin state. When GPIO data
register is read, it contains the state of the pin despite of the
pin direction.
Registers for GPIO are as follows:
GPIO CONTROL (06H)
Name
Bit
Description
Enable PWM pin
0 = disable
EN_PWM_PIN
4
1 = enable
OEN[2:0]
2:0
GPIO pin direction
0 = input
1 = output
Logic Interface Characteristics
(VDDIO = 1.65V...VDD1,2 unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
LOGIC INPUT SCL, SDA, GPIO[0:2]
VIL
VIH
II
Input Low Level
Input High Level
Logic Input Current
Clock Frequency
0.2xVDDIO
V
V
0.8xVDDIO
−1.0
1.0
µA
kHz
fSCL
400
LOGIC INPUT NRST
VIL
VIH
II
Input Low Level
0.5
1.0
V
V
Input High Level
Input Current
1.2
-1.0
10
µA
µs
tNRST
Reset Pulse Width
LOGIC OUTPUT SDA
VOL
VOH
IL
Output Low Level
ISDA = 3mA
ISDA = -3mA
VSDA = 2.8V
0.3
0.5
1.0
0.5
1.0
V
Output High Level
VDDIO − 0.5
VDDIO − 0.3
Output Leakage Current
µA
LOGIC OUTPUT GPIO[0:2]
VOL
VOH
IL
Output Low Level
IGPIO = 3 mA
IGPIO = −3 mA
VGPIO = 2.8V
0.3
V
V
Output High Level
VDDIO − 0.5
VDDIO − 0.3
Output Leakage Current
µA
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18
I2C Compatible Interface
I2C SIGNALS
The SCL pin is used for the I2C clock and the SDA pin is
used for bidirectional data transfer. Both these signals need
a pull-up resistor according to I2C specification.
TRANSFERRING DATA
Every byte put on the SDA line must be eight bits long, with
the most significant bit (MSB) being transferred first. Each
byte of data has to be followed by an acknowledge bit. The
acknowledge related clock pulse is generated by the master.
The transmitter releases the SDA line (HIGH) during the
acknowledge clock pulse. The receiver must pull down the
SDA line during the 9th clock pulse, signifying an acknowl-
edge. A receiver which has been addressed must generate
an acknowledge after each byte has been received.
I2C DATA VALIDITY
The data on SDA line must be stable during the HIGH period
of the clock signal (SCL). In other words, state of the data
line can only be changed when CLK is LOW.
After the START condition, the I2C master sends a chip
address. This address is seven bits long followed by an
eighth bit which is a data direction bit (R/W). The LP3958
address is 59H (101 1001b). For the eighth bit, a “0” indi-
cates a WRITE and a “1” indicates a READ. This means that
the first byte is B2H for WRITE and B3H for READ. The
second byte selects the register to which the data will be
written. The third byte contains data to write to the selected
register.
20175549
I2C Signals: Data Validity
I2C START AND STOP CONDITIONS
START and STOP bits classify the beginning and the end of
the I2C session. START condition is defined as SDA signal
transitioning from HIGH to LOW while SCL line is HIGH.
STOP condition is defined as the SDA transitioning from
LOW to HIGH while SCL is HIGH. The I2C master always
generates START and STOP bits. The I2C bus is considered
to be busy after START condition and free after STOP con-
dition. During data transmission, I2C master can generate
repeated START conditions. First START and repeated
START conditions are equivalent, function-wise.
20175551
I2C Chip Address
Register changes take an effect at the SCL rising edge
during the last ACK from slave.
20175550
I2C Start and Stop Conditions
19
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I2C Compatible Interface (Continued)
20175593
w = write (SDA = “0”)
r = read (SDA = “1”)
ack = acknowledge (SDA pulled down by either master or slave)
rs = repeated start
id = 7-bit chip address, 59H (101 1001b) for LP3958.
I2C Write Cycle
When a READ function is to be accomplished, a WRITE function must precede the READ function, as shown in the Read
Cycle waveform.
20175594
I2C Read Cycle
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20
I2C Compatible Interface (Continued)
20175554
I2C Timing Diagram
I2C TIMING PARAMETERS (VDD1,2 = 3.0 to 4.5V, VDDIO = 1.8V to VDD1,2
)
Limit
Symbol
Parameter
Units
Min
0.6
1.3
600
600
300
0
Max
1
2
Hold Time (repeated) START Condition
Clock Low Time
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
µs
pF
3
Clock High Time
4
Setup Time for a Repeated START Condition
5
Data Hold Time (Output direction, delay generated by LP3958)
Data Hold Time (Input direction, delay generated by Master)
Data Setup Time
900
900
5
6
100
7
Rise Time of SDA and SCL
20+0.1Cb
15+0.1Cb
600
300
300
8
Fall Time of SDA and SCL
9
Set-up Time for STOP condition
10
Cb
Bus Free Time between a STOP and a START Condition
1.3
Capacitive Load for Each Bus Line
10
200
NOTE: Data guaranteed by design
21
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Recommended External Components
OUTPUT CAPACITOR, COUT
rent (800mA) to ensure reliable operation. Schottky diodes
with a low forward drop and fast switching speeds are ideal
for increasing efficiency in portable applications. Choose a
reverse breakdown voltage of the schottky diode signifi-
The output capacitor COUT directly affects the magnitude of
the output ripple voltage. In general, the higher the value of
COUT, the lower the output ripple magnitude. Multilayer ce-
ramic capacitors with low ESR are the best choice. At the
lighter loads, the low ESR ceramics offer a much lower VOUT
ripple that the higher ESR tantalums of the same value. At
the higher loads, the ceramics offer a slightly lower VOUT
ripple magnitude than the tantalums of the same value.
However, the dv/dt of the VOUT ripple with the ceramics is
much lower that the tantalums under all load conditions.
Capacitor voltage rating must be sufficient, 25V or greater is
recommended. Examples of suitable capacitors are: TDK
~
cantly larger ( 30V) than the output voltage. Do not use
ordinary rectifier diodes, since slow switching speeds and
long recovery times cause the efficiency and the load regu-
lation to suffer. Example of suitable diode is: Central Semi-
conductor CMMSH1-40.
EMI FILTER COMPONENTS CSW, RSW
EMI filter (RSW and CSW) on the SW pin can be used to
suppress EMI caused by fast switching. These components
should be as near as possible to the SW pin to ensure
reliable operation. 50V or greater voltage rating is recom-
mended for capacitor.
C3216X5R1E475K,
Panasonic
ECJ3YB1E475K,
ECJMFB1E475K and ECJ4YB1E475K.
Some ceramic capacitors, especially those in small
packages, exhibit a strong capacitance reduction with
the increased applied voltage (DC bias effect). The ca-
pacitance value can fall below half of the nominal ca-
pacitance. Too low output capacitance can make the
boost converter unstable. Output capacitors DC bias
effect should be better than –50% at 18V.
INDUCTOR, L1
A 10uH shielded inductor is suggested for LP3958 boost
converter. The inductor should have a saturation current
rating higher than the rms current it will experience during
circuit operation (600mA). Less than 300mΩ ESR is sug-
gested for high efficiency and sufficient output current. Open
core inductors cause flux linkage with circuit components
and interfere with the normal operation of the circuit. This
should be avoided. For high efficiency, choose an inductor
with a high frequency core material such as ferrite to reduce
the core losses. To minimize radiated noise, use a toroid, pot
core or shielded core inductor. The inductor should be con-
nected to the SW pin as close to the IC as possible. Ex-
amples of suitable inductors are: TDK VLF4012AT-
100MR79, VLF4018BT-100MR90, VLF5014AT-100MR92,
Coilcraft LPS4018-103ML.
INPUT CAPACITOR, CIN
The input capacitor CIN directly affects the magnitude of the
input ripple voltage and to a lesser degree the VOUT ripple. A
higher value CIN will give a lower VIN ripple. Capacitor volt-
age rating must be sufficient, 10V or greater is recom-
mended.
OUTPUT DIODE, D1
A schottky diode should be used for the output diode. Peak
repetitive current should be greater than inductor peak cur-
LIST OF RECOMMENDED EXTERNAL COMPONENTS
Symbol
CVDD
Symbol explanation
Value
Unit
nF
nF
µF
µF
%
Type
Ceramic, X7R / X5R
C between VDD1,2 and GND
C between VDDIO and GND
C between VDDA and GND
C between FB and GND
100
CVDDIO
CVDDA
100
Ceramic, X7R / X5R
Ceramic, X7R / X5R
1
2 x 4.7 or 1 x 10
COUT
CIN
L1
Ceramic, X7R / X5R, tolerance +/-10%
Ceramic, X7R / X5R
@
Maximum DC bias effect 18V
-50
10
C between battery voltage and GND
L between SW and VBAT
Saturation current
µF
µH
mA
nF
kΩ
kΩ
V
10
Shielded inductor, low ESR
600
100
8.2
CVREF
RKEY
RRT
C between VREF and GND
R between IKEY and GND
R between IRT and GND
Ceramic, X7R / X5R
1%
1%
82
@
Rectifying diode (Vf maxload)
0.3-0.5
30
D1
Reverse voltage
Repetitive peak current
C in EMI filter
V
Schottky diode
800
100
390
mA
pF
Ω
CSW
RSW
Ceramic, X7R / X5R, 50V
R in EMI filter
1%
LEDs
User Defined
Note: See Application Note AN-1436 "Design and Programming Examples for Lighting Management Unit LP3958" for more
information on how to design with LP3958
www.national.com
22
23
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LP3958 Register Bit Explanations
Each register is shown with a key indicating the accessibility of the each individual bit, and the initial condition:
Register Bit Accessibility and Initial Condition
Key
RW
R
Bit Accessibility
Read/write
Read only
–0,–1
Condition after POR
CONTROL REGISTER (00H) – KEYPAD LEDS CONTROL REGISTER
D7
D6
D5
D4
D3
D2
D1
D0
KEYP_PWM
RW - 0
EN_KEYP
RW - 0
CC_SW
RW - 1
K1SW
RW - 0
K2SW
RW - 0
K3SW
RW - 0
R - 0
R - 0
0 - Internal KEYPAD PWM control disabled
1 - Internal KEYPAD PWM control enabled
0 – KEYPAD outputs disabled
1 – KEYPAD outputs enabled
0 – Constant current sink mode
1 – Switch mode
KEYP_PWM
Bit 7
EN_KEYP
CC_SW
K1SW
Bit 6
Bit 5
0 – KEYPAD1 disabled
Bit 3
Bit 2
1 – KEYPAD1 enabled
0 – KEYPAD2 disabled
K2SW
1 – KEYPAD2 enabled
0 – KEYPAD3 disabled
K3SW
Bit 1
1 – KEYPAD3 enabled
KEYPAD (01H) – KEYPAD BALANCE AND BRIGHTNESS CONTROL REGISTER
D7
D6
D5
D4
D3
D2
D1
RW - 0
D0
BALANCE[2:0]
RW - 0
BRIGHT[2:0]
RW - 0
OVL
R - 0
RW - 0
RW - 0
RW - 0
RW - 0
BALANCE[2:0]
BRIGHT[2:0]
Bits 6-4
Bits 3-1
PWM balance for KEYPAD outputs
PWM brightness control for KEYPAD outputs
0 – Overlapping mode disabled
OVL
Bit 0
1 – Overlapping mode enabled
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24
LP3958 Register Bit Explanations (Continued)
KEYPAD MAX CURRENT (02H) – MAXIMUM KEYPAD CURRENT CONTROL REGISTER
D7
D6
D5
D4
D3
D2
D1
D0
IK1[1:0]
IK2[1:0]
IK3[1:0]
R - 0
R - 0
RW - 0
RW - 0
RW - 0
RW - 0
RW - 0
RW - 0
Maximum current for KEY1,2,3 driver
IK1,2,3[1:0]
Maximum output current
0.25 x IMAX
00
01
10
11
0.50 x IMAX
0.75 x IMAX
1.00 x IMAX
WLED CONTROL (03H) – WLED CONTROL REGISTER
D7
D6
D5
D4
D3
D2
D1
D0
SLOPE
RW - 0
FADE_SEL
RW - 0
EN_FADE
RW - 0
DISPL
RW - 0
EN_MAIN
RW - 0
EN_SUB
R - 0
R - 0
RW - 0
0 – fade execution time 0.65 sec (full scale)
1 – fade execution time 1.3 sec (full scale)
0 – fade control for MAIN
SLOPE
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
FADE_SEL
EN_FADE
DISPL
1 – fade control for SUB
0 – automatic fade disabled
1 – automatic fade enabled
0 - MAIN and SUB individual control
1 - MAIN and SUB controlled with MAIN DAC
0 – MAIN output disabled
EN_MAIN
EN_SUB
1 – MAIN output enabled
0 – SUB output disabled
1 – SUB output enabled
25
www.national.com
LP3958 Register Bit Explanations (Continued)
MAIN CURRENT (04H) – MAIN CURRENT CONTROL REGISTER
D7
D6
D5
D4
D3
D2
D1
D0
MAIN[7:0]
RW - 0
RW - 0
RW - 0
RW - 0
RW - 0
RW - 0
RW - 0
RW - 0
SUB CURRENT (05H) – SUB CURRENT CONTROL REGISTER
D7
D6
D5
D4
D3
D2
D1
D0
SUB[7:0]
RW - 0
RW - 0
RW - 0
RW - 0
RW - 0
RW - 0
RW - 0
RW - 0
MAIN, SUB current adjustment
MAIN[7:0],
Typical driver current (mA)
SUB[7:0]
0000 0000
0000 0001
0000 0010
0000 0011
0000 0100
…
0
0.1
0.2
0.3
0.4
…
1111 1101
1111 1110
1111 1111
25.3
25.4
25.5
GPIO CONTROL (06H) – GPIO CONTROL REGISTER
D7
D6
D5
D4
D3
D2
RW - 0
D1
D0
EN_PWM_PIN
RW - 0
OEN[2:0]
RW - 0
R - 0
R - 0
R - 0
R - 0
RW - 0
0 – External PWM pin disabled
1 – External PWM pin enabled
0 – GPIO pin set as a input
1 – GPIO pin set as a output
EN_PWM_PIN
OEN[2:0]
Bit 4
Bits 2-0
GPIO DATA (07H) – GPIO DATA REGISTER
D7
D6
D5
D4
D3
D2
RW - 0
D1
D0
DATA[2:0]
RW - 0
R - 0
R - 0
R - 0
R - 0
R - 0
RW - 0
DATA[2:0]
Bits 2-0
GPIO data register bits
www.national.com
26
LP3958 Register Bit Explanations (Continued)
ENABLES (0BH) – ENABLES REGISTER
D7
D6
D5
D4
D3
D2
D1
D0
NSTBY
RW - 0
EN_BOOST
RW - 0
EN_AUTOLOAD
RW - 1
R - 0
R - 0
R - 0
R - 0
R - 0
0 – LP3958 standby mode
1 – LP3958 active mode
NSTBY
Bit 6
Bit 5
Bit 2
0 – Boost converter disabled
1 – Boost converter enabled
0 – Boost active load disabled
1 – Boost active load enabled
EN_BOOST
EN_AUTOLOAD
BOOST OUTPUT (0DH) – BOOST OUTPUT VOLTAGE CONTROL REGISTER
D7
D6
D5
D4
D3
D2
D1
RW - 0
D0
BOOST[7:0]
RW - 0
RW - 0
RW - 0
RW - 0
RW - 1
RW - 0
RW - 0
BOOST output voltage adjustment
BOOST[7:0]
0000 1000
0000 1001
0000 1010
0000 1011
0000 1100
0000 1101
0000 1110
0000 1111
0001 0000
0001 0001
0001 0010
Typical boost output voltage (V)
8.00
9.00
10.00
11.00
12.00
13.00
14.00
15.00
16.00
17.00
18.00
PWM ENABLE (2BH) – EXTERNAL PWM CONTROL REGISTER
D7 D6 D5 D4 D3
D2
D1
D0
EN_EXT_K1_PWM EN_EXT_K2_PWM EN_EXT_K3_PWM EN_MAIN_PWM EN_SUB_PWM
R - 0 R - 0 R - 0
RW - 0
RW - 0
RW - 0
RW - 0
RW - 0
0 – External PWM control for KEY1 disabled
1 – External PWM control for KEY1 enabled
0 – External PWM control for KEY2 disabled
1 – External PWM control for KEY2 enabled
0 – External PWM control for KEY3 disabled
1 – External PWM control for KEY3 enabled
0 – External PWM control for MAIN disabled
1 – External PWM control for MAIN enabled
0 – External PWM control for SUB disabled
1 – External PWM control for SUB enabled
EN_EXT_K1_PWM
EN_EXT_K2_PWM
EN_EXT_K3_PWM
EN_EXT_MAIN_PWM
EN_EXT_SUB_PWM
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
27
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Physical Dimensions inches (millimeters) unless otherwise noted
The dimension for X1 ,X2 and X3 are as given:
•
•
•
X1=2.543mm 0.03mm
X2=2.543mm 0.03mm
X3=0.60mm 0.075mm
25-bump micro SMD Package, 2.54 x 2.54 x 0.6mm, 0.5mm pitch
NS Package Number TLA25CCA
See Application note AN–1112 for PCB design and assembly instructions.
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves
the right at any time without notice to change said circuitry and specifications.
For the most current product information visit us at www.national.com.
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