LM9617CCEA-2_技术文档

March 2001

LM9617 Monochrome CMOS Image Sensor VGA 30 FPS

General Description

Applications

The LM9617 is a high performance, low power, third inch VGA

CMOS Active Pixel Sensor capable of capturing grey-scale digi-

tal still or motion images and converting them to a digital data

stream.

• Security Cameras

• Toys

• Machine Vision

• Biometrics

• Infrared Camera

• Barcode Scanner

In addition to the active pixel array, an on-chip 12 bit A/D conver-

tor, fixed pattern noise elimination circuits and a video gain is

provided. Furthermore, an integrated programmable smart tim-

ing and control circuit allows the user maximum flexibility in

adjusting integration time, active window size, gain and frame

rate. Various control, timing and power modes are also provided.

Key Specifications

• Array Format

Total: 664H x 504V

Active: 648H x 488V

Total: 4.98mm x 3.78 mm

Active: 4.86 mm x 3.66 mm

• Effective Image Area

Features

• Supplied with micro lenses

• Optical Format

• Pixel Size

1/3“

7.5mm x 7.5mm

8,10 & 12 Bit Digital

57dB

• Video Outputs

• Dynamic Range

• FPN

• Video or snapshot operations

• Progressive scan and interlace read out modes.

• Programmable pixel clock, inter-frame and inter-line delays.

• Programmable partial or full frame integration

• Programmable gain

• Horizontal & vertical sub-sampling (2:1 & 4:2)

• Windowing

• External snapshot trigger & event synchronisation signals

• Auto black level compensation

• Flexible digital video read-out supporting programmable:

0.35%

Sensitivity

28.7 Kilo LSBs / lux.s

27%

• Quantum Efficiency

• Fill Factor

47% (no micro lens)

48 LCC

• Package

• Single Supply

• Power Consumption

• Operating Temp

3.3 V

90 mW

0 to 50^oC

-

polarity for synchronisation and pixel clock signals

-

leading edge adjustment for horizontal synchronization

• Programmable via 2 wire I²C compatible serial interface

• Power on reset & power down mode

System Block Diagram

Storage

LM9617

lens

12bit digital image

Digital Image

Processor

I²C compatible

event trigger

snapshot

ã 2000 National Semiconductor Corporation

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Overall Chip Block Diagram

d[11:0]

pclk

AMP

12 Bit A/D

Row Address

Decoder

hsync

vsync

APS Array

POR

Vertical

Timing

Horizontal

Timing

Reset

Gen

Gain

Control

Row Address

Gen

sda

sclk

2

I C Compatible

Serial I/F

Register Bank

Power

Control

Controller

(sequencer)

Clock Gen

sadr

Master Timer

irq

mclk

extsync snapshot

pdwn

Figure 1. Chip Block Diagram

Connection Diagram

6

5

4

3

2

1

48 47 46 45 44 43

42

NC

sclk

7

fine_i

snapshot

resetb

41

40

39

38

37

36

35

34

33

32

31

8

gnd

9

pdwn

fine_ctrl

offset

10

11

12

13

14

15

16

17

18

vss_dig

vdd_dig

hsync

LM9617

48 PIN LCC

vdd_ana1

vss_ana1

vsync

pclk

mclk

d0

vref_adc

vss_ana2

vdd_ana2

vss_od2

vdd_od2

NC

19 20 21 22 23 24 25 26 27 28 29 30

Ordering Information

Temperature

(0°C £ T_A£ +50°C)

NS Package

LM9617 CCEA

LCC

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Typical Application Circuit

System Control

Camera Control

Serial Control Bus

16

9

10

4

8

48

7

6

5

3.3V analog

37

36

33

34

vdd_ana1

vss_ana1

vdd_ana2

vss_ana2

0.1mF

3.3V digital

47

46

31

vdd_od2

vdd_od1

vss_od1

0.1mF

vss_od2 32

3.3Vdigital

3.3V digital

44

45

12

vdd_od3

vss_od3

vdd_dig

0.1mF

11

vss_dig

3.3Vanalog

3

2

LM9617

1

vdd_pix

vrl

vsrvdd

0.1

m

F

1.0mF

3.3V analog

vdd_ana

1.5k

W

22kW

1%

35

vref_adc

41

39

fine_i

820W

1N4148

0.1mF

fine_ctrl

2N3904

10kW

1%

1.2kW

1%

18

19

42

43

NC

38

40

offset

gnd

4.7m F

470W

1%

13 14 15 30 29 28 27 26 25 24 23 22 21 20 17

Digital Video Bus

Figure 2. Typical Application Diagram

Scan Read Out Direction

pin 1

(0,0)

digital

out

(0,0)

horizontal scan

CMOS Image Sensor

lens

Figure 3. Scan directions and position of origin in imaging system

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Pin Descriptions

Name

I/O

Typ

Description

Analog bidirectional, it should be connect to ground via a 1.0mf capacitor. This pin is the

internal charge pump voltage source.

1

vsrvdd

I0

P

2

3

vrl

I

A

P

Anti blooming pin. This pin is normally tied to ground.

3.3 volt supply for the pixel array.

vdd_pix

Digital output, the interrupt request pin. This pin generates interrupts during snapshot

mode.

4

5

6

irq

O

I

D

Digital input with pull down resistor. This pin is used to program different slave addresses

for the sensor in an I²C compatible system.

sadr

sda

I²C compatible serial interface data bus. The output stage of this pin has an open drain

driver.

IO

7

8

sclk

I

D

I²C compatible serial interface clock.

snapshot

Digital input with pull down resistor used to activate (trigger) a snapshot sequence.

Digital input with pull up resistor. When forced to a logic 0 the sensor is reset to its default

power up state. The resetb signal is internally synchronized to mclk which must be run-

ning for a reset to occur.

9

resetb

pdwn

I

D

Digital input with pull down resistor. When forced to a logic 1 the sensor is put into power

down mode.

10

11

12

vss_dig

vdd_dig

I

P

0 volt power supply for the digital circuits.

3.3 volt power supply for the digital circuits.

Digital Bidirectional. This is a dual mode pin. When the sensor’s digital video port is con-

figured to be a master, (the default), this pin is an output and is the horizontal synchroni-

zation pulse. When the sensor’s digital video port is configured to be a slave, this pin is

an input and is the row trigger.

13

14

hsync

vsync

IO

D

Digital Bidirectional. This is a dual mode pin. When the sensor’s digital video port is con-

figured to be a master, (the default), this pin is an output and is the vertical synchroniza-

tion pulse. When the sensor’s digital video port is configured to be a slave, this pin is an

input and is the frame trigger.

15

16

pclk

O

I

D

Digital output. The pixel clock.

mclk

Digital input. The sensor’s master clock input.

Digital output. Bit 0 of the digital video output bus. This output can be put into tri-state

mode.

17

d0

O

D

18

19

NC

Pin not used, do not connect.

Digital output. Bit 1 of the digital video output bus. This output can be put into tri-state

mode.

20

21

22

23

24

25

d1

d2

d3

d4

d5

d6

O

D

Digital output. Bit 2 of the digital video output bus. This output can be put into tri-state

mode.

Digital output. Bit 3 of the digital video output bus. This output can be put into tri-state

mode.

Digital output. Bit 4 of the digital video output bus. This output can be put into tri-state

mode.

Digital output. Bit 5 of the digital video output bus. This output can be put into tri-state

mode.

Digital output. Bit 6 of the digital video output bus. This output can be put into tri-state

mode.

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Pin Descriptions (Continued)

Name

I/O

Typ

Description

Digital output. Bit 7 of the digital video output bus. This output can be put into tri-state

mode.

26

d7

O

D

Digital output. Bit 8 of the digital video output bus. This output can be put into tri-state

mode.

27

28

29

30

d8

O

D

Digital output. Bit 9 of the digital video output bus. This output can be put into tri-state

mode.

d9

Digital output. Bit 10 of the digital video output bus. This output can be put into tri-state

mode.

d10

d11

Digital output. Bit 11 of the digital video output bus. This output can be put into tri-state

mode.

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

vdd_od2

vss_od2

vdd_ana2

vss_ana2

vref_adc

vss_ana1

vdd_ana1

offset

I

P

A

P

A

3.3 volt supply for the digital IO buffers.

0 volt supply for the digital IO buffers

3.3 volt supply for analog circuits.

I

0 volt supply for analog circuits.

I

A/D reference resistor ladder voltage. See figure 4 for equivalent circuit.

0 volt supply for analog circuits.

I

3.3 volt supply for analog circuits.

I

Analog input used to adjust the offset of the sensor. See figure 4 for equivalent circuit.

Analog output used to drive the offset pin.

This pin must be tied to ground.

fine_ctrl

gnd

O

fine_i

I

A

Bias current for the fine offset adjust.

Pin not used, do not connect.

NC

Pin not used, do not connect.

vdd_od3

vss_od3

vss_od1

vdd_od1

I

P

3.3 volt supply for the sensor.

0 volt supply for the sensor.

0 volt supply for the digital IO buffers

3.3 volt supply for the digital IO buffers.

Digital output. The external event synchronization signal is used to synchronize external

events in snapshot mode.

48

extsync

O

D

Legend: (I=Input), (O=Output), (IO=Bi-directional), (P=Power), (D=Digital), (A=Analog).

1KW

adc_vref

offset

800W

200W

Figure 4. Equivalent Circuits For adc_ref and offset pins

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Absolute Maximum Ratings (Notes 1 & 2)

Operating Ratings (Notes 1 & 2)

Any Positive Supply Voltage

6.5V

-0.5V to 6.5V

±25mA

Operating Temperature Range

All VDD Supply Voltages

Voltage Range on vref_adc pin

Voltage Range on offset pin

0°C£T£+50°C

+3.15V to +3.6V

+0.6V to +1.0V

+0.04V to +0.4V

Voltage On Any Input or Output Pin

Input Current at any pin (Note 3)

ESD Susceptibility (Note 5)

Human Body Model

2000V

200V

Machine Model

Package Input Current (Note 3)

Package Power Dissipation @ T_A(Note 4)

Soldering Temperature Infrared,

10 seconds (Note 6)

±50mA

2.5W

220°C

Storage Temperature

-40°C to 125°C

DC and logic level specifications

The following specifications apply for all VDD pins= +3.3V. Boldface limits apply for TA = T_MINto T_MAX: all other limits T_A= 25^oC

(Note 7)

Min

note 9

Typical

note 8

Max

note 9

Units

Symbol

Parameter

Conditions

sclk, sda, sadr, Digital Input/Output Characteristics

VIH

VIL

Logical “1” Input Voltage

Logical “0” Input Voltage

Logical “0” Output Voltage

0.7_*vdd_od

-0.5

vdd_od+0.5

0.3_*vdd_od

0.5

V

VOL

vdd_od = +3.15V, Iout=3.0mA

vdd_od = +3.15V

0.05_*vdd_o

d

V_hys

I_leak

Hysteresis (SCLK pin only)

V

Input Leakage Current

Vin=vss_od

-1

mA

mclk, snapshot, pdwn, resetb, hsync, vsync Digital Input Characteristics

VIH

VIL

IIH

IIL

Logical “1” Input Voltage

Logical “0” Input Voltage

Logical “1” Input Current

Logical “0” Input Current

vdd_dig = +3.6V

vdd_dig = +3.15V

VIH = vdd_dig

VIL = vss_dig

2.0

V

0.8

0.1

-1

mA

d0 - d11, pclk, hsync, vsync, extsync, irq, Digital Output Characteristics

VOH

VOL

Logical “1” Output Voltage

Logical “0” Output Voltage

vdd_od=3.15V, Iout=-1.6mA

vdd_od=3.15V, Iout =-1.6mA

2.2

V

0.5

VOUT = vss_od

VOUT = vdd_od

-0.1

0.1

mA

IOZ

IOS

TRI-STATE Output Current

Output Short Circuit Current

+/-17

mA

Power Supply Characteristics

Power down mode, no clock.

Operational mode in dark

700

19

mA

IA

ID

Analog Supply Current

Digital Supply Current

Power down mode, no clock.

Operational mode in dark

300

7

mA

Power Dissipation Specifications

The following specifications apply for All VDD pins = +3.3V. Boldface limits apply for TA = T_MINto T_MAX: all other limits T_A= 25^oC.

Min

note 9

Typical

note 8

Max

note 9

Units

Symbol

P_dwn

Parameter

Power Down

Average Power Dissipation

Conditions

no clock running

5

mW

mclk = 48Mhz & sensors default set-

tings in dark.

PWR

90

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Video Amplifier Specifications

The following specifications apply for all VDD pins= +3.3V. Boldface limits apply for TA = T_MINto T_MAX: all other limits T_A= 25^oC.

Min

note 9

Typical

note 8

Max

note 9

Units

Symbol

Parameter

Conditions

64 linear steps

Video Amplifier Nominal Gain

0-15

dB

AC Electrical Characteristics

The following specifications apply for All VDD pins = +3.3V. Boldface limits apply for T_A= T_MINto T_MAX: all other limits T_A= 25^oC.

Min

note 9

Typical

note 8

Max

note 9

Units

Symbol

Parameter

Conditions

F_mclk

T_ch

Input Clock Frequency

Clock High Time

12

10

48

45

MHz

ns

@ CLK_max

T_cl

Clock Low Time

@ CLK_max

10

45

ns

Clock Duty Cycle

45/55

55/45

min/max

ns

T_rc, T_fc

F_hclk

Clock Input Rise and Fall Time

3

Internal System Clock Fre-

quency

1.0

14.0

MHz

T_reset

Reset pulse width

Frame Rate

1.0

1

ms

FRM_rate

30

fps

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate con-

ditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications

and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions

listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions.

Note 2: All voltages are measured with respect to VSS = vss_ana = vss_od = vss_dig = 0V, unless otherwise specified.

Note 3: When the voltage at any pin exceeds the power supplies (VIN < VSS or VIN > VDD), the current at that pin should be lim-

ited to 25mA. The 50mA maximum package input current rating limits the number of pins that can safely exceed the power

supplies with an input current of 25mA.

Note 4: The absolute maximum junction temperature (TJmax) for this device is 125^oC. The maximum allowable power dissipation

is dictated by TJmax, the junction-to-ambient thermal resistance (QJA), and the ambient temperature (T_A), and can be cal-

culated using the formula PDMAX = (TJmax - T_A)/QJA. In the 48-pin LCC, QJA is 38.5^oC/W, so PDMAX = 2.5W at 25^oC

and 1.94W at the maximum operating ambient temperature of 50^oC. Note that the power dissipation of this device under

normal operation will be well under the PDMAX of the package.

Note 5: Human body model is 100pF capacitor discharged through a 1.5kW resistor. Machine model is 220pF discharged through

ZERO Ohms.

Note 6: See AN450, “Surface Mounting Methods and Their Effect on Product Reliability”, or the section entitled “Surface Mount”

found in any post 1986 National Semiconductor Linear Data Book, for other methods of soldering surface mount devices.

Note 7: The analog inputs are protected as shown below. Input voltage magnitude up to 500mV beyond the supply rails will not

damage this device. However, input errors will be generated If the input goes above AV+ and below AGND.

VDD

IOP

Internal Circuits

Pad

VSS

Note 8: Typical figures are at TJ = 25^oC, and represent most likely parametric norms.

Note 9: Test limits are guaranteed to National's AOQL (Average Outgoing Quality Level).

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CMOS Active Pixel Array Specifications

Parameter

Value

Units

Number of pixels (column, row)

664 x 504

648 x 488

Total

Active

pixels

Array size (x,y Dimensions)

4.98 x 3.78

4.86 x 3.66

Total

Active

mm

Pixel Pitch

7.5

47

m

Fill Factor (without micro-lens)

%

Image Sensor Specifications

The following specifications apply for All VDD pins = +3.3V, T_A= 25^oC, Illumination Color Temperature = 2850^oK, IR cutoff filter at

700nm, mclk = 48MHz, frame rate = 30Hz, vref_adc = 0.6 volt, video gain 0dB.

Min

Typical

note 1

Max

Units

Parameter

Conditions

Optical Sensitivity @ A/D output

Optical Sensitivity @ A/D input

28.7

4.13

kLSBs/(lux.s)

volt/(lux.s)

Dynamic Range

Read Noise

57

dB

5.3

LSBs

RMS value of pixel FPN in dark

as a percentage of full scale.

Offset Fixed Pattern Noise

0.35

1

%

RMS variation of pixel sensitivi-

ties as a percentage of the aver-

age sensitivity.

Sensitivity Fixed Pattern Noise

Note 1: Typical figures are at TJ = 25^oC, and represent most likely parametric norms.

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Sensor Response Curves

1.20E+03

1.00E+03

8.00E+02

6.00E+02

4.00E+02

2.00E+02

0.00E+00

370

420

470

520

570

620

670

720

770

820

wavelength [nm]

Figure 5. Spectral Response Curve

4500

4000

3500

3000

2500

2000

1500

1000

500

0

0.05

0.1

0.15

0.2

0.25

0.3

Exposure (lux.sec)

Figure 6. Linearity Response Curve

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Functional Description

0-15dB

1.0 OVERVIEW

Video

AMP

1.1

Light Capture and Conversion

12 Bit A/D

The LM9617 contains a CMOS active pixel array consisting of

648 rows by 488 columns. This active region is surrounded by 8

columns and 8 rows of optically shielded (black) pixels as shown

in Figure.

Analog pixel values

Digital pixel data

8 columns, 8 rows

Figure 9: Analog Signals In, Digital Data Out.

648 columns, 488 rows

mono-chrome active pixels

black pixels

The digital pixel data is further processed to:

• remove defects due to bad pixels,

• compensate black level, before being framed and presented

on the digital output port. (see Figure 10).

do[11:0]

pclk

hsync

vsync

8 columns, 8 rows

black pixels

Figure 10. Digital Pixel Processing.

1.2

Program and Control Interfaces

The programming, control and status monitoring of the LM9617

Figure 7: CMOS APS region of the LM9617

2

is achieved through a two wire I C compatible serial bus. In

addition, a slave address pin is provided (see Figure 11).

At the beginning of a given integration time the on-board timing

and control circuit will reset every pixel in the array one row at a

time as shown in Figure 8. Note that all pixels in the same row

are simultaneously reset, but not all pixels in the array.

sda

2

I C Compatible

Serial I/F

a

b

c

d

e

f

g

h

i

j

k l m n o p q r

Register Bank

0

1

sclk

2

3

4

5

6

7

8

9

sadr

10

11

Figure 11. Control Interface to the LM9617.

12

13

14

15

Additional control and status pins: snapshot and external event

synchronization are provided allowing the latency of the serial

control port to be bypassed during single frame capture. An

interrupt request pin is also available allowing complex snapshot

operations to be controlled via an external micro-processor (see

Figure 12).

Analog Data Out

CDS/Shift Register

Figure 8: CMOS APS Row and Column addressing scheme

irq

At the end of the integration time, the timing and control circuit

will address each row and simultaneously transfer the integrated

value of the pixel to a correlated double sampling circuit and

then to a shift register as shown in Figure 8.

Timing

Generator

extsyn

snapshot

Figure 12. Snapshot & External Event Trigger Signals

Once the correlated double sampled data has been loaded into

the shift register, the timing and control circuit will shift them out

one pixel at a time starting with column “a”.

The pixel data is then fed into an analog video amplifier, where a

user programmed gain is applied .

After gain adjustment the analog value of each pixel is con-

verted to a 12 bit digital data as shown in Figure 9.

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Functional Description (continued)

Column/Horizontal

a b c d e f g h i j k l mn o p q r

2.0 WINDOWING

0

1

2

3

4

5

The integrated timing and control circuit allows any size window

in any position within the active region of the array to be read out

with a 1x1 pixel resolution. The window read out is called the

“Display Window”.

6

7

8

A “Scan Window” must be defined first, by programing the start

and end row addresses as shown in Figure 13. Four coordinates

(start row address, start column address, end row address &

end column address) are programmed to define the size and

location of the “Display Window” to be read out (see Figure 13).

display col

9

10

11

12

display col

scan row

13

end address

start address

14

15

16

17

18

19

20

display row

start address

Display Window

Figure 14: Progressive Scan Read Out Mode

display row

end address

Scan Window

3.2

Interlaced Readout Mode

In interlaced readout mode, pixels are read out in two fields, an

Odd Field followed by an Even Field.

Active Pixel Array

scan row

end address

Figure 13. Windowing

The Odd Field, consisting of all even rows contained within the

display window, is read out first. Each pixel in the “Odd Field” is

consecutively read out, one pixel at a time, starting with the left

most pixel in the top most even row.

Notes:

• The “Display Window” must always be defined within the

“Scan Window”.

• A “Display Window” can only be read out in the progressive

scan mode.

• By default the “Display Window” is the complete array.

The Even Field, consisting of all odd rows contained within the

display window, is then read out. Each pixel in the “Even Field”

is consecutively read out, one pixel at a time, starting with the

left most pixel in the top most odd row.

2.1

Programming the scan window

Column/Horizontal

a b c d e f g h i j k l m n o p q r

Two registers (SROWS & SROWE) are provided to program the

size of the scan window. The start and end row address of the

scan window is given by:

0

2

4

6

8

scan row start address = (2* SwStartRow) + SwLsb

scan row end address = (2* SwEndRow) + 1 + SwLsb

10

12

14

16

18

20

Where:

SwStartRow

is the contents of the Scan Window start row

register (SROWS)

Odd Field

Column/Horizontal

a b c d e f g h i j k l m n o p q r

SwEndROW

is the contents of the Scan Window end row reg-

ister (SROWE)

1

3

5

SwLsb

is bit 6 of the Display Window LSB register

(DWLSB)

7

9

11

13

15

17

19

2.2

Programming the display window

Five register (DROWS, DROWE, DCOLS, DCOLE and DWLSB)

are provided to program the display window as described in the

register section of this datasheet.

Even Field

3.0 READ OUT MODES

Figure 15: Interlace Read Out Mode

Hence, for the example shown in Figure , the display window is

broken up into two fields, as shown in Figure . Pixels a0,b0,...,r0

followed by a2,b2,...,r2 and so on until pixels a20,b20,...r20 in

the even field are read out first. The even field read out is fol-

lowed by pixels in the odd field, a1,b1,...,r1 then a3,b3,...,r3 until

pixels a19,b19,...,r19.

3.1

Progressive Scan Readout Mode

In progressive scan readout mode, every pixel in every row in

the display window is consecutively read out, one pixel at a time,

starting with the left most pixel in the top most row. Hence, for

the example shown in Figure 13, the read out order will be

a0,b0,...,r0 then a1,b1,...,r1 and so on until pixel r20 is read out.

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Functional Description (continued)

4.0 SUBSAMPLING MODES

4.2

4:2 Sub-Sampling

4.1

2:1 Sub-Sampling

The timing and control circuit can be programmed to sub-sam-

ple pixels in the display window vertically, horizontally or both,

with an aspect ratio of 4:2 as illustrated in Figure17.

The timing and control circuit can be programmed to sub-sam-

ple pixels in the display window vertically, horizontally or both,

with an aspect ratio of 2:1 as illustrated in Figure16

Column/Horizontal

a b c d e f g h i j k l m n o p q r

q

a b c d e f g h i j k l m n o p

r

0

1

2

3

4

0

1

2

3

4

5

6

7

8

9

5

6

7

8

9

a) Horizontal Sub-sampling

a) Horizontal Sub-Sampling

Column/Horizontal

a b c d e f g h i j k l m n o p q r

Column/Horizontal

a b c d e f g h i j k l m n o p q r

0

1

2

3

4

5

6

7

8

1

2

3

4

5

6

7

8

9

b) Vertical Sub-sampling

b) Vertical Sub-Sampling

Column/Horizontal

a b c d e f g h i j k l m n o p q r

Column/Horizontal

a b c d e f g h i j k l l n o p q r

0

1

0

1

2

3

4

2

3

4

5

6

7

8

9

5

6

7

8

9

c) Horizontal & Vertical Sub-sampling

c) Horizontal & Vertical Sub-Sampling

Not Read Out

Read Out

Not Read Out

Read Out

Figure 17: 4:2 Horizontal and Vertical Sub-Sampling

Figure 16: 2:1 Horizontal and Vertical Sub-Sampling

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Functional Description (continued)

5.3

Auto Snapshot Mode

5.0 SNAPSHOT MODE

In auto snapshot mode (see figure 20), upon the receipt of a

snapshot or FTriggerNow trigger signal, the integrated timing and

control circuit will set the FTriggerEN bit and generate an inter-

nal TRIGGER signal (see figure 19), thus resetting the array one

row at a time. At end of the reset cycle the timing and control cir-

cuit will signal the shutter to open via extsync pin or FtSync bit.

At the end of the programmed integration time the shutter will be

signalled to close, and the pixel read-out will commence as

shown in figure 18a. At the end of the read-out sequence the

FTriggerEN will be automatically reset and the sensor will return

to video capture mode as shown in figure 20.

The LM9617 is capable of capturing a single frame of an image

under hardware or software control, with or without the aid of an

external shutter. Two registers, SNAPSHOTMODE0

&

SNAPSHOTMODE1, are provided to program, monitor and con-

trol all snapshot sequences.

5.1

Software Controlled Snapshots

The snapshot mode events can be software controlled by writing

2

to and reading from the snapshot mode registers over the I C

compatible interface.

5.2

Hardware Controlled Snapshots

If an external shutter is not available then at least two frames

need to be taken so that the pixels can be integrated over one

frame as shown in Figure 18b.

Two dedicated pins are provided on the LM9617, snapshot &

extsync, allowing the snapshot mode events to be controlled by

hardware. The snapshot pin must be enabled by writing to the

SnapEnable bit of the MCFG0 register.

To use auto snapshot mode the SsEngage bit of the

SNAPSHOTMODE1 register must be set to zero.

Array reset,

programmable 1 to 4 frames

Capture Data

image

read-out

note1

snapshot or FTriggerNow

note2

note 3

irq

FTriggerEn

extsync or FtSync

FtBusy

Start Snapshot Sequence

Start of Array Reset Frames

Open Shutter

Close shutter & start read-out

Read-out complete

a) With External Shutter

Array reset,

programmable 1 to 4 frames

Capture Data

image

read-out

note 1

snapshot or FTriggerNow

note 2

irq

note 3

FTriggerEn

extsync or FtSync

FtBusy

Start Snapshot sequence

Start of Array Reset Frames

Integration Start

Start Read-out

Bold external pins

italicregister bits

Read-out Complete

b) Without External Shutter

Note 1:

Note 2:

Note 3:

This wave form shows the snapshot pin programmed to the default pulse mode.

The irq pulse is taken low when the snapshot trigger interrupt flag (SsTrigFlag) in the snapshot mode1 (SNAPMODE1) register is read.

The irq pulse is taken low when the snapshot trigger interrupt flag (SsRdFlag) in the snapshot mode1 (SNAPMODE1) register is read.

Figure 18. Snapshot Mode

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Functional Description (continued)

snapshot

SnapShotPol

TRIGGER

VIDEO

SnapEnable

FTriggerNow

Figure 19. Snapshot Trigger Generation Logic

c:TRIGGER==1

VIDEO

a:SsTrigFlag=1

IRQ

c:TRIGGER==1

c:FTriggerEn==1

SNAP

a:FTriggerEn=1

SNAP

a:FTriggerEn=0

PREVIEW

a: SsRdFlag = 1

a: FtTriggerEn = 0

PREVIEW

Figure 20. Auto Snapshot Mode State Diagram

CPU Snapshot Mode

5.4

Figure 21. CPU Snapshot Mode State Diagram

In CPU snapshot mode, the FTriggerEN is not set automatically

and an Interrupt generator can be enabled.

When an interrupt is generated by a TRIGGER event, the

SsTrigFlag bit in the SNAPSHOTMODE1 register is set. Simi-

larly when an interrupt is generated at the completion of a read-

out the SsRdFlag in the SNAPSHOTMODE1 register is set.

Hence, upon the receipt of a snapshot or FTriggerNow trigger

signal, the integrated timing and control circuit will generate an

internal TRIGGER signal as shown in figure 19 and then wait in

the IRQ state for the FTriggerEN bit to be manually set as shown

in figure 21.

The polarity of the irq pin can be programmed. The interrupt can

only be cleared by reading SsTrigFlag and the SsRdFlag as

shown in figure 22.

Once the FtriggerEn bit is set the integrated timing and control

circuit will start resetting the array one row at a time. At end of

the reset cycle the timing and control circuit will signal the shut-

ter to open via extsync pin or FtSync bit. At the end of the pro-

grammed integration time the shutter will be signalled to close,

and the pixel read-out will commence as shown in figure 18a. At

the end of the read-out sequence the FTriggerEN will be auto-

matically disabled and the sensor will return to video capture

mode as shown in figure 20.

SsTrigFlag

SsRdFlag

irq

SnapIntEn

IrqPol

Figure 22. Interrupt Request Generation Logic

5.5

Pulse & Level Trigger Mode

If an external shutter is not available then at least two frames

need to be taken so that the pixels can be integrated over one

frame as shown in Figure 18b.

The snapshot pin can be programmed to operate in pulse trig-

ger mode where one snapshot sequence is executed per active

pulse or in level trigger mode where by snapshot sequences are

repeated as long as the level on the snapshot pin is held active.

(see figures 20 and 21).

To use CPU snapshot mode the SsEngage bit of the

SNAPSHOTMODE1 register must be set to one.

Pulse and level trigger modes can be set by programming the

SnapshotMod bit in the SNAPSHOTMODE0 register.

An interrupt generator can be enabled in CPU snapshot mode

by setting the SnapIntEn bit of SNAPSHOTMODE1 register. An

interrupt will be generated on the external interrupt pin, irq,

when a snapshot sequence is triggered (TRIGGER=1) or when

the array readout is complete at the end of the snapshot

sequence as shown figure 21.

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Functional Description (continued)

The number of rows in a scan window is given by:

6.0 CLOCK GENERATION MODULE

The LM9617 contains a clock generation module that will create

two clocks as follows:

SWN_rows= (RAD_end- RAD_start) + 1

Hclk,

the horizontal clock. This is an internal system

clock and can be programmed to be the input

clock (mclk) or mclk divided by any number

between 1 and 255.

Where:

RAD_endis the end row address of the defined scan win-

dow. (See section 2.1)

CLK

the pixel clock. This is the external pixel clock

RAD_startis the start row address of the defined scan win-

pixel

that appears at the digital video port. It can be

Hclk or Hclk divided by 2. This clock cannot be

programed.

dow. (Scan section 2.1).

The number of Hclk clocks required to process a full frame is

given by:

7.0 FRAME RATE PROGRAMING

A frame is defined as the time it takes to reset every pixel in the

array, integrate the incident light, convert it to digital data and

present it on the digital video port. This is not a concurrent pro-

cess and is characterized in a series of events each needing a

certain amount of time as shown in Figure 23.

FN_Hclk= [(M_{factor *}SWN_rows) + F_delay

] RN_Hclk

*

Where:

M_factor

is a Mode Factor which must be applied. It is

dependent on the selected mode of operation as

shown in the table below:

Start

Progressive Scan

1

Sub-sampling or Interlace/

Interlace

Row address = 0

0.5

SWN_rowsis the Number of Rows in Selected Scan Win-

dow.

Row delay time

F_delay

a programmable value between 0 & 4097 repre-

senting the Inter Frame Delay in multiples of

RN_Hclk. This parameter allows the frame time to

Transfer all pixels to CDS

Reset all pixels in row

be extended. (See the Frame Delay High and

Frame Delay Low registers).

The frame rate is given by:

Shift all pixels out of row

Row address + 1

Hclk

FN_Hclk

Frame Rate =

7.2

Partial Frame Integration

In some cases it is desirable to reduce the time during which the

pixels in the array are allowed to integrate incident light without

changing the frame rate.

Yes

No

Last row?

This is known as Partial Fame Integration and can be achieved

by resetting pixels in a given row ahead of the row being

selected for readout as shown in Figure 24. The number of Hclk

clocks required to process a partial frame is given by:

Figure 23. Frame Readout Flow Diagram

Full Frame Integration

7.1

Full frame integration is when each pixel in the array integrates

light incident on it for the duration of a frame (see Figure 24).

FP_Hclk= RN_{Hclk *}I_time

Where:

The number of Hclk clock cycles required to process & shift out

one row of pixels is given by:

RN_Hclk

is the number of Hclk clock cycles required to

process & shift out one row of pixels.

I_time

is the number of rows ahead of the current row

RN_Hclk= R_opcycle+ R_delay

to be reset. (See the Integration Time High and

Low registers).

Where:

The Integration time is subject to the following limits:

R_opcycleis a fixed integer value of 780 representing the

Row Operation Cycle Time in multiples of Hclk

clock cycles. It is the time required to carry out

all fixed row operations outlined in Figure 23.

Mode

Progressive Scan

Interlace

Limit

I_{time <=}SWN_{rows +}F_delay

I_{time <=}SWN_{rows +}2_*F_delay

I_{time <=}SWN_{rows +}0.5_*F_delay

R_delay

a programmable value between 0 & 2047 repre-

senting the Row Delay Time in multiples of Hclk.

This parameter allows the Row Operation Cycle

time to be extended. (See the Row Delay High

and Row Delay Low registers).

Sub-Sampled

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Functional Description (continued)

Full Integration Time

Partial Integration

Time

Frame

Delay

Frame

Delay

Row n

Row 2

Row 0 Row 1

Row x

Row x+

D

Row n

Row 0

Programmable Row Delay Row CDS, Reset Row x & Shift

Full Frame integration

Programmable Row Delay Row CDS, Reset Row x+D & Shift

Partial Frame Integration

Frame N

Figure 24. Partial and Full Frame Integration

7.3

Frame Rate Programming Guide

The table bellow can be used as a guide for programming the sensor. Note that it is assumed that the sensor is being driven with a

48MHz clock. All programmed values are given in decimal.

register

address

fps

vclkgen

rdelayh

rdelayl

16hex

[7:0]

0

fdelayh

fdelayl

18hex

[7:0]

9

srows

srowe

0Chex

[8:1]

251

dwlsb

05hex

15hex

17hex

[11:8]

0

0Bhex

12hex

[10:8]

[8:1]

0

30

4

5

4

5

6

0

3

0

2

0

3

50

15

0

2

40

0

251

7.5

3.75

25

0

6

12

0

251

12

6

12

0

251

172

0

251

12.5

6.25

3.125

5

1

226

188

14

0

251

0

5

0

251

156

255

0

14

4

0

251

23

0

251

4

10

14

13

15

12

0

251

3

0

14

0

251

2

200

241

248

126

0

251

1

0

251

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10.0 ANALOG GAIN ADJUSTMENT

Functional Description (continued)

The integrated analog programmable gain amplifier is capable

of applying a linear gain 1X to 5.6X in 64 linear steps. This can

be programmed using the VGAIN register as shown in the table

8.0 SIGNAL PROCESSING

8.1

Bad Pixel Detection & Correction

below:

The LM9617 has a built-in bad pixel detection and correction

block that operates on the fly. This block can be switched off by

the user.

VidGain

Dec

Code

VidGain

Hex

Code

VidGain

Dec

Code

VidGain

Hex

Code

Gain

Amp

Value

Gain

Amp

Value

8.2

Black Level Compensation

0

00

01

02

03

04

05

06

07

08

09

0A

0B

0C

0D

0E

0F

10

11

1

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

20

21

22

23

24

25

26

27

28

29

2A

2B

2C

2D

2E

2F

30

31

32

33

34

35

36

37

38

39

3A

3B

3C

3D

3E

3F

3.34

3.41

3.48

3.56

3.63

3.7

In addition to the programmable gain the LM9617 has a built in

black level compensation block as illustrated in Figure 25. This

block can be switched off.

1

2

1.07

1.15

1.22

1.29

1.37

1.44

1.51

1.58

1.66

1.73

1.8

only enabled for black pixels

input signal

3

_*a

+

-1

z

4

S

-

+

S

+

5

_*(1-a)

6

3.77

3.85

3.92

3.99

4.07

4.14

4.21

4.29

4.36

4.43

4.5

7

Figure 25. Digital Black Level Compensation.

The black level compensation block will subtract the average

signal level of the black pixels around the array from the digital

video output to compensate for the temperature and integration

time dependent dark signal level of the pixels. The exponential

averaging circuit shown in figure 25 only operates on the least

significant 8 bits of the video data.

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

9.0 POWER MANAGMENT

1.88

1.95

2.02

2.1

9.1

Power Up and Down

The LM9617 is equipped with an on-board power management

system allowing the analog and digital circuitry to be switched

off (power down) and on (power up) at any time.

The sensor can be put into power down mode by asserting a

logic one on the “pdwn” pin or by writing to the power down bit in

2.17

2.24

2.31

2.39

2.46

2.53

2.61

2.68

2.75

2.83

2.9

2

the main configuration register via the I C compatible serial

interface.

4.58

4.65

4.72

4.8

12

13

14

15

16

17

18

19

1A

1B

1C

1D

1E

1F

To power up the sensor a logic zero can be asserted on the

“pdwn” pin or write to the power down bit in the main configura-

tion register via the I²C compatible serial interface.

It will take a few milli seconds for all the circuits to power up. The

power management register contains a bit indicating when the

sensor is ready for use. During this time the sensor cannot be

used for capturing images. A status bit in the power manage-

ment register will indicate when the sensor is ready for use.

4.87

4.94

5.02

5.09

5.16

5.23

5.31

5.38

5.45

5.53

5.6

9.2

Advanced Power Features

In addition to the power up/power down features of the sensor,

sections of the analog video processing chain can be powered

down and re-routed during normal operation. This flexibility

allows power dissipation to be traded of with signal gain as

shown in the table below:

2.97

3.04

3.12

3.19

3.26

PGA Amp

Power Saving

0mW

on

off

10mW

Figure 26. Power Control

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Functional Description (continued)

11.0 OFFSET ADJUSTMENT

12.0 OFFSET & GAIN

For maximum image quality over a wide range of light conditions

it is necessary to set an appropriate offset voltage before using

the sensor to capture images. This offset voltage must be

applied to the offset pin (38) of the sensor, and is used to adjust

the analogue video signal being fed to the internal A/D.

The fine offset adjustment and calibration method described in

section 11.0 will ensure that the sensor’s black level is optimized

for a fixed analog gain setting. However, when the analog gain is

changed substantially, the black level of the sensor will shift

resulting in a white washed image.

To stop this effect from occurring, the black level needs to be re-

calibrated. This can be done as part of the contrast adjustment

which is carried out by most digital image processors. If this is

not possible then the following method can be used.

The relationship between the gain and the offset can be

described with the following equation.

The level of the offset voltage determines the black level of the

image and has a direct impact on the image quality. Too high an

offset results in a white washed or hazy looking image, while too

low of an offset results in a dark image with low contrast even

though the light conditions are good.

Offset(G) = Offset(0) + C * G^0.4

A fine offset adjustment should be applied to each part by pro-

gramming the offset voltage via the I²C compatible serial inter-

face. To program an offset voltage the following procedure

should be followed:

where:

Offset(G) is the offset that needs to be programmed in

the OCR1, OCR2 & OCR3 registers to ensure

the correct black level setting for an analog

gain setting of G.

The sensor’s offset, fine_i & fine_ctrl pins should be connected

as shown in figure 2.

Offset(0) is the offset that needs to be programmed in

the OCR1, OCR2 & OCR3 registers to ensure

the correct black level setting for unity analog

gain, (G=0).

The following procedure should be followed to calibrate the off-

set

• Disable the black level compensation block by writing a logic

1 to bit 4 of the Main Configuration Register 0(MCFG0:

address 02Hex).

• The offset can be adjusted by writing to the Offset Compen-

sation Registers (OCR: addresses 1F, 22 & 25 hex). Writing

00hex will give the largest voltage, while writing FF hex will

give the smallest value.

• Run the following binary search algorithm

• For n=7 to 0 step -1

C

is a constant and will vary from sensor to sen-

sor

G

is the value programmed in the VGAIN regis-

ter of the sensor which determines the sen-

sor’s analog gain.

The following procedure should be used to calculate the value of

C:

Use the calibration procedure described in section 11.0 to deter-

mine the offset at unity gain, offset(0). Note the VGAIN register

should be set to 0.

• {

Set bit n in the OCR registers (addresses 1F, 22 & 25

Set the sensor’s analog gain register (VGAIN) to its max setting,

31, and repeat the calibration procedure described in section

11.0. This will allow the offset at full gain, 31, that needs to be

programmed in the OCR1, OCR2 & OCR3 registers to ensure

the correct black level setting to be determined.

The value of C for a particular sensor can be calculated using

the following formula:

Hex) to a logic one by writing over the I²C compatible

interface.

Read a full frame and calculate the average black level

(BL_average) of the first and last 5 black pixels in the every

row of the array

If (BL_average< 100) then

Reset bit n in the OCR registers (addresses 1F, 22 &

25 Hex) to 0

Offset(31) - Offset(0)

C =

else

3.95

Keep bit n set to one.

Once the value of C has been calculated, offset values for differ-

ent gain settings can be calculated using equation 1. It is recom-

mended that a two decimal point accuracy for C is maintained.

}

• Enable the black level compensation block (if desired) by writ-

ing a logic 0 to bit 4 of the Main Configuration Register 0

(MCFG0: address 02Hex).

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Functional Description (continued)

13.4 Data Valid

13.0 SERIAL BUS

The master must ensure that data is stable during the logic 1

state of the sclk pin. All transitions on the sda pin can only occur

when the logic level on the sclk pin is “0” as shown in Figure 29.

The serial bus interface consists of the sda (serial data), sclk

(serial clock) and sadr (device address select) pins. The

LM9617 can operate only as a slave.

The sclk pin is an input, it only and controls the serial interface,

all other clock functions within LM9617 use the master clock pin,

mclk.

sda

sclk

data line

stable;

data valid

data line

stable;

data valid

change

of data

allowed

13.1

Start/Stop Conditions

The serial bus will recognize a logic 1 to logic 0 transition on the

sda pin while the sclk pin is at logic 1 as the start condition. A

logic 0 to logic 1 transition on the sda pin while the sclk pin is at

logic 1 is interrupted as the stop condition as shown in Figure

27.

Figure 29. Data Validity

13.5 Byte Format

Every byte consists of 8 bits. Each byte transferred on the bus

must be followed by an Acknowledge. The most significant bit of

the byte is should always be transmitted first. See Figure 30.

sda

sclk

13.6 Write Operation

A write operation is initiated by the master with a Start Condition

followed by the sensor’s Device Address and Write bit. When

the master receives an Acknowledge from the sensor it can

transmit 8 bit internal register address. The sensor will respond

with a second Acknowledge signaling the master to transmit 8

write data bits. A third Acknowledge is issued by the sensor

when the data has been successfully received.

S

P

start condition

stop condition

Figure 27. Start/Stop Conditions

13.2

Device Address

The serial bus Device Address of the LM9617 is set to 1010101

when sadr is tied low and 0110011 when sadr is tied high. The

value for sadr is set at power up.

The write operation is completed when the master asserts a

Stop Condition or a second Start Condition. See Figure 31.

13.3

Acknowledgment

The LM9617 will hold the value of the sda pin to a logic 0 during

the logic 1 state of the Acknowledge clock pulse on sclk as

shown in Figure 28.

13.7 Read Operation

A read operation is initiated by the master with a Start Condition

followed by the sensor’s Device Address and Write bit. When

the master receives an Acknowledge from the sensor it can

transmit the internal Register Address byte. The sensor will

respond with a second Acknowledge. The master must then

issue a new Start Condition followed by the sensor’s Device

Address and read bit. The sensor will respond with an Acknowl-

edged followed by the Read Data byte.

sda

MSB

from master

ACK

sda

from sensor

sclk

S

7

8

1

2

9

The read operation is completed when the master asserts a Not

Acknowledge followed by Stop Condition or a second Start Con-

dition. See Figure 32.

Clock pulse

for ACK

START

Figure 28. Acknowledge

MSB

sda

sclk

ack signal

from receiver

ack signal

from receiver

byte complete

7

9

1

8

2

8

9

ACK

1

2

ACK

clock line

held low

S

P

Figure 30. Serial Bus Byte Format

Register

Address

Data

Byte

Device

Address

S

W

A

R

P

bold sensor action

Figure 31. Serial Bus Write Operation

Device

Address

Register

Address

Device

Address

Data

Byte

_

A

S

W

A

S

A

P

bold sensor action

Figure 32. Serial Bus Read Operation

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Functional Description (continued)

This feature allows a programmable digital gain to be imple-

mented when connecting the sensor to 8 or 10 bit digital video

processing systems as illustrated in Figure 34. The unused bits

on the digital video bus can be optionally tri-stated.

14.0 DIGITAL VIDEO PORT

The captured image is placed onto a flexible 12-bit digital port as

shown in Figure 10. The digital video port consists of a program-

mable 12-bit digital Data Out Bus (d[11:0]) and three program-

mable synchronisation signals (hsync, vsync, pclk).

d11

d10

d9

d8

d7

d6

d5

d4

d3

d2

d1

d0

d9

d8

d7

d6

d5

d4

d3

d2

d1

d0

By default the synchronisation signals are configured to operate

in “master” mode. They can be programed to operate in “slave”

mode.

10 bit

Digital

Image

LM9617

Processor

The following sections are a detailed description of the timing

and programming modes of digital video port.

Pixel data is output on a 12-bit digital video bus. This bus can be

tri-stated by asserting the TriState bit in the VIDEOMODE1 reg-

ister.

a) LM9617 Connected to a 10 bit Digital Image Processors

14.1

Digital Video Data Out Bus (d[11:0])

A programmable matrix switch is provided to map the output of

the internal pixel framer to the pins of the digital video bus as

illustrated in Figure 33.

d11

d10

d9

d8

d7

d6

d5

d4

d3

d2

d1

d7

d6

d5

d4

d3

d2

d1

d0

8 bit

Digital

Image

Internal Pixel Framer Output Register

11 10

9

8

7

6

5

4

3

2

1

0

LM9617

Processor

d0

d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0

b) LM9617 Connected to a 8 bit Digital Image Processors

a) MSB Bit 11, Switch Mode (default)

Figure 34. Example of connection to 10/8 bit systems

Internal Pixel Framer Output Register

11 10

9

8

7

6

5

4

3

2

1

0

Synchronisation Signals in Master Mode

By default the sensor’s digital video port’s synchronisation sig-

nals are configured to operate in master mode. In master mode

the integrated timing and control block controls the flow of data

onto the 12-bit digital port, three synchronisation outputs are

provided:

pclk

is the pixel clock output pin.

hsync

vsync

is the horizontal synchronisation output signal.

is the vertical synchronisation output signal.

d11d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0

b) MSB Bit 10, Switch Mode

14.2 Pixel Clock Output Pin (pclk) (Master Mode)

Internal Pixel Framer Output Register

The pixel clock output pin, pclk, is provided to act as a synchro-

nisation reference for the pixel data appearing at the digital

video out bus pins d[11:0]. This pin can be programmed to oper-

ate in two modes:

9

8

7

6

5

4

3

2

1

0

11 10

• In free running mode the pixel clock output pin, pclk, is always

running with a fixed period. Pixel data appearing on the digital

video bus d[11:0] are synchronized to a specified active edge

of the clock as shown in Figure 35.

pclk

d11d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0

d[11:0]

c) MSB bit 9, Switch Mode

a) pclk active edge negative

Internal Pixel Framer Output Register

9

8

7

6

5

4

3

2

1

0

11 10

pclk

d[11:0]

b) pclk active edge positive (default)

invalid pixel data

Figure 35. pclk in Free Running Mode

• In data ready mode, the pixel clock output pin (pclk) will pro-

duce a pulse with a specified level every time valid pixel data

appears on the digital video bus d[11:0] as shown in Figure

36.

d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0

d) MSB bit 8, Switch Mode

Figure 33. Digital Video Bus Switching Modes

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Functional Description (continued)

,

14.4 Vertical/Horizontal Synchronisation Pin (vsync)

The vertical synchronisation output pin, vsync, is used as an

indicator for pixel data within a frame. The vsync output pin can

be programmed to operate in two modes as follows:

pclk

d[11:0]

a) pclk active edge negative

• Level mode should be used when the pixel clock, pclk, is pro-

grammed to operate in free running mode. In level mode the

vsync output pin will go to the specified level (high or low) at

the start of each frame and remain at that level until the last

pixel of that row in the frame is placed on d[11:0] as shown in

Figure 39. The hsync level is always synchronized to the

active edge of pclk.

pclk

d[11:0]

b) pclk active edge positive

invalid pixel data

Figure 36. pclk in Data Ready Mode

By default the pixel clock is a free running active low (pixel data

changes on the positive edge of the clock) with a period equal to

the internal hclk. The active edge of the clock can be pro-

grammed such that pixel data changes on the positive or nega-

tive edge of the clock.

pclk

d[11:0]

vsync

Frame n+1

Frame n

14.3

Horizontal Synchronisation Output Pin (hsync)

a) vsync programmed to be active high

pclk

The horizontal synchronisation output pin, hsync, is used as an

indicator for row data. The hsync output pin can be programmed

to operate in two modes as follows:

d[11:0]

vsync

• Level mode should be used when the pixel clock, pclk, is pro-

grammed to operate in free running mode. In level mode the

hsync output pin will go to the specified level (high or low) at

the start of each row and remain at that level until the last

pixel of that row is read out on d[11:0] as shown in Figure 37.

The hsync level is always synchronized to the active edge of

pclk.

Frame n+1

Frame n

b) vsync programmed to be active low

invalid pixel data

Figure 39. vsync in Level Mode

• Pulse mode should be used when the pixel clock,pclk, is pro-

grammed to operate in data ready mode. In pulse mode the

vsync output pin will produce a pulse at the end of each

frame. The width of the pulse will be a minimum of four hclk

cycles and its polarity can be programmed as shown in Figure

40. The vsync level is always synchronized to the active edge

of pclk.

pclk

d[11:0]

hsync

Row n+1

Row n

a) hsync programmed to be active high (default)

pclk

d[11:0]

hsync

d[11:0]

Row n+1

Row n

vsync

Frame n+1

Frame n

b) hsync programmed to be active low

invalid pixel data

a) vsync programmed to be active high

pclk

Figure 37. hsyncin Level Mode

• Pulse mode should be used when the pixel clock, pclk, is pro-

grammed to operate in data ready mode. In pulse mode the

hsync output pin will produce a pulse at the end of each row.

The width of the pulse will be a minimum of four pclk cycles

and its polarity can be programmed as shown in Figure 38.

The hsync level is always synchronized to the active edge of

pclk

d[11:0]

Frame n

Frame n+

vsync

b) vsync programmed to be active low (default)

invalid pixel data

Figure 40. vsync in pulse mode

14.5 Odd/Even Mode

pclk

In odd/even mode the vsync signal is used to indicate when

pixel data from an odd and even field is being placed on the dig-

ital video bus d[11:0]. The polarity of vsync can still be pro-

grammed in this mode as shown in Figure 41

d[11:0]

hsync

Row n+1

Row n

a) hsync programmed to be active high

pclk

d[11:0]

vsync

d[11:0]

Even Field

Odd Field

Row n

Row n+1

hsync

a) vsync programmed to be active high (default)

b) hsync programmed to be active low

invalid pixel data

Figure 38. hsync in Pulse Mode

pclk

d[11:0]

vsync

By default the first pixel data at the beginning of each row is

placed on the digital video bus as soon as hsync is activated. It

is possible to program up to 15 dummy pixels to be readout at

the beginning of each row before the real pixel data is readout.

This feature is supported for both level and pulse mode.

Even Field

Odd Field

b) vsync programmed to be active low

invalid pixel data

Figure 41. vsync in odd/even Mode

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Functional Description (continued)

pclk

vsync

hsync

d[11:0]

c0 c1

c2

c3 c4 c5

c6

c7 c8 c9

c0

c 1 c2

c3

c 4 c5

c6

c7

c 8 c9

c0

c1

c2

c3

c4

c5

c 6 c7

c8 c9

c0

c1

c2

c3

c4

c5

c 6 c7

c8 c9

row 2

row1

row 1

row 2

frame 1

frame 2

Programmable hsync to 1st valid pixel delay

Programmable inter-frame delay

Programmable row delay

Figure 42. Example of Digital Video Port Timing in Progressive Scan Mode

pclk

vsync

hsync

d[11:0]

c0

c1 c2 c3 c4

c5

c6

c7

c8 c9

c0 c1

c2 c3 c4

c5

c6

c7 c8 c9

c0 c1

c2

c3 c4

c5

c6

c7 c8 c9

c0 c1

c2

c3 c4 c5

c6

c7 c8 c9

row1

row 3

row 2

row 4

Odd Field

Even Field

Programmable hsync to 1st valid pixel delay

Programmable inter-frame delay

Programmable row delay

Figure 43. Example of Digital Video Port Timing in Interlaced Mode

pclk

vsync

hysync

d[11:0]

c 0

c2

c4

c6

c8

c0

c2

c4

c6

c8

c0

c2

c 4

c6

c8

c0

c2

c4

c6

c8

row 1

row 3

row 1

row 3

frame 1

frame 2

Programmable hsync to 1st valid pixel delay

Programmable inter-frame delay

Programmable inter-row delay

Figure 44. Example of Digital Video Port Timing in 2:1 Sub-sampling Mode

pclk

vsync

hsync

d[11:0]

c0

c2

c4

c6

c8

c0

c2

c4

c6

c8

c0

c2

c4

c6

c8

c0

c2

c4

c5

c8

row 1

row 2

row 1

row 2

frame 1

frame 2

Programmable hsync to 1st valid pixel delay

Programmable inter-frame delay

Programmable inter-row delay

Figure 45. Example of Digital Video Port Timing in 4:2 Sub-sampling Mode

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Functional Description (continued)

14.6

Synchronisation Signals in Slave Mode

14.7 Row Trigger Input Pin (hsync)

The sensor’s digital video port’s synchronisation signals can be

programmed to operate in slave mode. In slave mode the inte-

grated timing and control block will only start frame and row pro-

cessing upon the receipt of triggers from an external source.

The row trigger input pin, hsync, is used to trigger the process-

ing of a given row. It must be activated for at least two “mclk”

cycle. The first pixel data will appear at d[11:0] “X_mclk“periods

after the assertion of the row trigger, were X_mclkis given by:

X_mclk= 124 + DW_StAd

Only two synchronization signals are used in slave mode as fol-

lows:

Where:

hsync

vsync

is the row trigger input signal.

is the frame trigger input signal.

DW_StAdis the value of the display window column start

address.

Figure 46 shows the LM9617’s digital video port in slave mode

connected to a digital video processor master DVP.

The polarity of the active level of the row trigger is programma-

ble. By default it is active high.

d[11:0]

hsync

vsync

din[11:0]

RowTrig

FrameTrig

14.8 Frame Trigger Input Pin (vsync)

The frame trigger input pin, vsync, is used to reset the row

address counter and prepare the array for row processing. It

must be activated for at least one “mclk” cycle and no more than

96 mclk cycles after the activation of hsync as illustrated in Fig-

ure 48.

pclk

mclk

MasterClock

DVP

LM9617

The polarity of the active level of the row trigger is programma-

ble. By default it is active high.

Figure 46. LM9617 in slave mode

780 clock cycles per line

hsync

pixel 12

pixel11

pixel 652

d[11:0]

642 valid pixels

776 777 778 779

0

1

2

3

...

134 135 136 136 137

...

774 775 776 777 778 779

0

1

mclk

count

mclk

Figure 47. hsync slave mode timing diagram for centred display window of 642 pixels

780 clock cycles per line

hsync

vsync

No more than

96 clock cycles

line502

line503

line 0

line 502

internal row

counter

776 777 778 779

0

1

2

3

...

774 775 776 777 778 779

0

1

774 775 776 777 778 779

0

1

mclk

count

...

mclk

Figure 48. vsync slave mode timing diagram for scan window of 504 rows.

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MEMORY MAP

ADDR

Register

Reset Value

Description

Reserved for future use.

00h

01h

02h

03h

04h

05h

06h

07h

08h

09h

0Ah

0Bh

0Ch

0Dh

0Eh

0Fh

10h

11h

12h

13h

14h

15h

16h

17h

18h

19h

1Fh

22h

25h

26h

27h

28h

29h

2Ah

REV

02h

Revision Register

MCFG0

00h

04h

00h

FBh

Main Configuration Register 0

Main Configuration Register 1

Power Control Register.

MCFG1

PCR

VCLKGEN

VMODE0

VMODE1

VMODE2

SNAPMODE0

SNAPMODE1

SROWS

Video Clock Generator

Video Mode 0 Register

Video Mode 1 Register

Video Mode 2 Register

Snapshot Mode 0 Register

Snapshot Mode 1 Register

Scan Window Row Start Register

Scan Window Row End Register

Reserved for future use.

SROWE

DROWS

DROWE

DCOLS

DCOLE

DWLSB

ITIMEH

ITIMEL

00h

FBh

00h

A5h

32h

00h

Display Window Row Start Register

Display Window Row End Register

Display Window Column Start Register

Display Window Column End Register

Display Window LSB Register.

Integration Time High Register

Integration Time Low Register

Row Delay High Register

RDELAYH

RDELAYL

FDELAYH

FDELAYL

VGAIN

Row Delay Low Register

Frame Delay High Register

Frame Delay Low Register

Video Gain Register

OCR1

Offset Compensation Register 1

Offset Compensation Register 2

Black Level Compensation Coefficient Register

Bad pixel Threshold 0 High Register

Bad pixel Threshold 0 Low Register

Bad pixel Threshold 1 High Register

Bad pixel Threshold 1 Low Register

OCR1

OCR2

BLCOEFF

BPTH0H

BPTH0L

BPTH1H

BPTH1L

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Register Set

The following section describes all available registers in the

LM9617 register bank and their function.

Register Name Main Configuration 1

Address

Mnemonic

Type

03 Hex

MCFG1

Read/Write

00 Hex

Register Name Device Rev Register

Mnemonic

Address

Type

REV

01 Hex

Read Only.

Reset Value

Bit

Bit Symbol

ColorMode

Description

Bit

Bit Symbol

SiRev

Description

7

Assert when using a mono-

chrome sensor. When this bit is

at a logic 1, Sub-Sampling is set

to 2:1 and every other row is

read out during interlace mode.

Clear (the default) when using a

color sensor. When this bit is at

logic 0, sub-sampling is set to

4:2 and every other row pair is

read out during interlace mode.

7:0

The silicon revision register.

Register Name Main Configuration 0

Address

Mnemonic

Type:

02 Hex

MCFG0

Read/Write

Reset Value

00 Hex

Bit

Bit Symbol

Description

(Read Only Bit)

Indicates that power on initializa-

tion is in progress. The sensor is

ready for use when this bit is at

logic 0.

6

ScanMode

Assert to set the sensor to inter-

lace readout mode. Clear (the

default) to set the sensor to pro-

gressive scan read out mode.

7

PwrUpBusy

PwrDown

5

4

HSubSamEn

VSubSamEn

Assert to enable horizontal sub-

sampling. Clear (the default) to

disable horizontal sub-sampling.

6

Assert to power down the sensor.

Writing a logic 1 to this register bit

has the same effect as taking the

pdwn pin high. Clear (the default)

this bit to power up the sensor.

Assert to enable vertical sub-

sampling. Clear (the default) to

disable vertical sub-sampling.

5

4

3

BPCorrection

BlkLComp

Assert to enable the bad pixel

detection and correction circuit.

Clear (the default) to switch it off.

3

2

Reserved

SlaveMode

Use to configure the digital

video port’s synchronisation sig-

nal to operate in slave mode. By

default the digital video’s port’s

synchronization signals are con-

figured to operate in master

mode.

Assert to disable the black level

compensation circuit. Clear (the

default) to switch it on.

SnapEnable

Assert to enable the external

snapshot pin. Clear (the default)

to disable the external snapshot

pin.

1:0

Reserved

Register Name Power Control Register 1

Address

Mnemonic

Type

04 Hex

PCR

Read/Write

2:0

Reserved

Reset Value

00 Hex

Bit

Bit Symbol

Description

7

ByPassGain

Assert to route the analog video

signal from the output of the CDS

to the input of the 12 bit A/D. Clear

(the default) to route the signal to

the video gain amplifier.

6:4

3

Reserved

PwdnPGA

PwDnADC

Assert to power down the pro-

grammable video gain amplifier.

Clear (the default) to power up the

video gain amplifiers.

2:1

0

Reserved

Assert to power down the 12 bit

analog to digital convertor. Clear

(the default) to power up the 12 bit

analog to digital convertor.

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Register Name Digital Video Mode 1

Register Set (continued)

Register Name Hclk Generator Register

Address

Mnemonic

Type

07 Hex

VMODE1

Read/Write

00 Hext

Address

Mnemonic

Type

05 Hex

VCLKGEN

Read/Write

04 Hex.

Reset Value

Bit

Bit Symbol

Description

Reset Value

7

6

PixClkMode

Assert to set the pclk to “data

ready mode”. Clear, the default, to

set pclk to “free running mode”.

Assert to set the vsync pin to

“pulse mode”. Clear (the default)

to set the vsync signal to “level

mode”.

Bit

Bit Symbol

HclkGen

Description

VsyncMode

7:0

Use to divide the frequency of

the sensors master clock input,

mclk to generate the internal

sensor clock, Hclk.

Program 00 Hex (the default) for

Hclk to equal mclk or divide

mclk by any number between 1

and FF Hex.

5

HsyncMode

Assert to force the hsync signal to

pulse for a minimum of four pixel

clocks at the end of each row.

Clear (the default) to force the

hsync signal to a level indicating

valid data within a row.

Register Name Digital Video Mode 0

Address

Mnemonic

Type

06 Hex

4

3

PixClkPol

VsynPol

Assert to set the active edge of

the pixel clock to negative. Clear

(the default) to set the active edge

of the clock to positive.

VMODE0

Read/Write

00 Hex

Reset Value

Assert to force the vsync signal to

generate a logic 0 during a frame

readout (Level Mode), or a nega-

tive pulse at the end of a frame

readout (Pulse Mode). Clear (the

default) to force the vsync signal

to generate a logic 1 during a

frame readout (Level Mode), or a

negative pulse at the end of a

frame readout (Pulse Mode).

Assert to force the hsync signal to

generate a logic 0 during a row

readout (Level Mode), or a nega-

tive pulse at the end of a row

readout (Pulse Mode). Clear (the

default) to force the hsync signal

to generate a logic 1 during a row

readout (Level Mode), or a nega-

tive pulse at the end of a readout

(Pulse Mode).

Bit

Bit Symbol

PixDataSel

Description

7:6

Use to program the number of

active bits on the digital video bus

d[11:0], starting from the MSB

(d[11]). Inactive bits are tri-stated.:

00 12 bit mode, bits

d[11:0] of the digital

video bus are active.

This is the default.

2

HsynPol

01 10 bit mode, bits

d[11:2] of the digital

video bus are active.

10 8 bit mode, bits

d[11:4] of the digital

video bus are active.

11 Reserved.

1

0

OddEvenEn

TriState

Assert to force the vsync pin to act

as an odd/even field indicator.

Clear (the default) to force the

vsync pin to act as a vertical syn-

chronization signal.

Assert to tri-state all output signals

(data and control) on the digital

video port. Clear (default) to

enable all signals (data and con-

trol) on the digital video port.

5:4

PixDataMsb

Use to program the routing of the

MSB output of the internal video

A/D to a bit on the digital video

bus.

00 A/D [11:0] -> d[11:0].

01 A/D [10:0] -> d[11:1]

10 A/D [9:0] -> d[11:2]

11 A/D [8:0] -> d[11:3]

Register Name Digital Video Mode 2

3:0

Reserved

Address

Mnemonic

Type

08 Hex

VMODE2

Read/Write

00 Hex

Reset Value

Bit

Bit Symbol

HsyncAdjust

Description

7:4

Use to program the leading edge

of hsync to the first valid pixel at

the beginning of each row. This

can be 0-hex to F-hex corre-

sponding to 0 - 15 pixel clocks.

Default 0.

3:0

Reserved

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Register Set (continued)

Register Name Snapshot Mode Configuration Register 0

Register Name Snapshot Mode Configuration Register 1

Address

Mnemonic

Type

09 Hex

Address

Mnemonic

Type

0A Hex

SNAPMODE0

Read/Write

00 Hex

SNAPMODE1

Read/Write

00 Hex.

Reset Value

Bit

Bit Symbol

Description

Bit

Bit Symbol

SsFrames

Description

7

6

SnapIntEn

SsTrigFlag

Assert to enable the snapshot

interrupt generator. Clear (the

default) to disable the interrupt

generator.

7.6

Program to set the number of

frames required before readout

during a snapshot with no external

shutter, (see Figure 18). By

default these two bits are set to 00

resulting in one frame before

readout:

(Read Only Bit)

Snapshot trigger interrupt flag.

A logic 1 in this bit indicates that

the generated interrupt on the

irq pin is due to a snapshot trig-

ger. This bit is cleared when

read.

0

one frame

01 two frames

10 three frames

11 four frames

5

SsRdFlag

(Read Only Bit)

Snapshot read done interrupt

flag. A logic 1 in this bit indicates

that the generated interrupt on

the irq pin is due to the comple-

5

4

ShutterEn

Assert to indicate that an external

shutter will be used during snap-

shot mode. Clear (the default) to

indicate that snapshot mode will

be carried out without the aid of an

external shutter.

tion of

a snapshot readout

sequence. This bit is cleared

when read.

4

SsEngage

Assert to allow a CPU controlled

snapshot sequence. In this

mode the snapshot trigger will

only generate an interrupt to the

CPU and the CPU must manu-

ally start the snapshot sequence

by asserting the FTriggerEnbit

of this register.

Clear (the default) engage an

automatic snapshot sequence.

In auto mode the snapshot

sequence is started as soon as

a snapshot trigger is asserted.

ExtSynPol

Assert to set the active level of the

extsync signal to 0. Clear (the

default) to set the active level of

the extsync signal to 1.

3

2

Reserved

SnapshotMod

Assert to set the snapshot pin to

level mode. In level mode the sen-

sor will continually run snapshot

sequences as long as the snap-

shot pin is held to the active level.

Clear (the default) to set the snap-

shot signal to pulse mode. In

pulse mode the sensor will only

carry out one snapshot sequence

per pulse applied to the snapshot

pin.

3

2

FtSync

FtBusy

(Read Only Bit)

The internal synchronisation

signal. A logic 1 on this bit indi-

cates a synchronization event is

required. This bit is functionally

equivalent to the external

extsync pin.

1

0

SnapShotPol

Assert to set the snapshot pin to

be active on the positive edge.

Clear (the default) to set the snap-

shot pin to be active on the nega-

tive edge.

(Read Only Bit)

The Frame Trigger Busy bit. A

logic 1 on this bit indicates that

the sensor is busy reading out

pixel data as shown in Figure

18.

IrqPol

Assert to set the active level of the

irq signal to 0, Clear (the default)

to set the active level of the irq

signal to 1.

1

0

FTriggerNow

FTriggerEn

Assert to start a snapshot

sequence. The frame trigger

now is functionally equivalent to

the external snapshot pin. The

default is 0.

Assert to enable a snapshot

sequence (see the SsEngage

bit of this register). The default

is 0.

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Register Set (continued)

Register Name Scan Window Row Start Register

Register Name Display Window Column Start Register

Address

Mnemonic

Type

0B Hex

Address

Mnemonic

Type

10 Hex

SROWS

Read/Write

00 Hex

DCOLS

Read/Write

00 Hex

Reset Value

Bit

Bit Symbol

SwStartRow

Description

Bit

Bit Symbol

DwStartCol

Description

7:0

Use to program the scan window’s

start row address MSBs. If bit 6 of

register DWLSB is set to 1 the

start row address is incremented

by 1 else the raw value is used.

7:0

Use to program the display win-

dow’s start column address

MSBs. The two LSBs can be pro-

grammed using the DWLSB regis-

ter.

Register Name Scan Window Row End Register

Register Name Display Window Column End Register

Address

Mnemonic

Type

0C Hex

Address

Mnemonic

Type

11 Hex

DCOLE

Read/Write

A5 Hex

SROWE

Read/Write

FB Hex

Reset Value

Bit

Bit Symbol

SwEndRow

Description

Bit

Bit Symbol

DwEndCol

Description

7:0

Use to program the scan window’s

end row address MSBs. If bit 6 of

register DWLSB is set to 1 the end

row address is incremented by 1.

else the raw value is used.

7:0

Use to program the scan window’s

end column address MSBs. The

two LSBs can be programmed

using the DWLSB register.

Register Name Display Window LSB register

Register Name Display Window Row Start Register

Address

Mnemonic

Type

12 Hex

Address

Mnemonic

Type

0E Hex

DROWS

Read/Write

DWLSB

Read/Write

32 Hex

Reset Value

00 Hex

Bit

Bit Symbol

Description

Bit

Bit Symbol

DwStartRow

Description

7

Reserved

7:0

Use to program the display win-

dow’s start row address MSBs.

The LSB can be programmed

using the DWLSB register.

6

SwLsb

Assert to increment the value of

the scan window start and end

row addresses by 1. Clear (the

default) to use the raw values.

Register Name Display Row End Register

5

4

3

2

1

0

DwCel[1]

DwCel[0]

DwCSL[1]

DwCSL [0]

DwERLsb

DwSRLsb

Use to program bit 1 of the display

window’s end column address.

Default is 1.

Address

Mnemonic

Type

0F Hex

DROWE

Read/Write

FB Hex

Reset Value

Use to program bit 0 of the display

window’s end column address.

Default is 1.

Bit

Bit Symbol

DwEndRow

Description

7:0

Use to program the scan window’s

end row address. The LSB can be

programmed using the DWLSB

register.

Use to program bit 1 of the display

window’s start column address.

Default is 0.

Use to program bit 0 of the display

window’s start column address.

Default is 0.

Use to program bit 0 of the display

window’s end row address.

Default is 1.

Use to program bit 0 of the display

window’s start row address.

Default is 0.

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Register Set (continued)

Register Name Integration Time High Register

Register Name Frame Delay Low Register

Address

Mnemonic

Type

13 Hex

ITIMEH

Read/Write

00 Hex.

Address

Mnemonic

Type

18 Hex

FDELAYL

Read/Write

00 Hex

Reset Value

Bit

Bit Symbol

Description

Bit

Bit Symbol

FDelay [7:0]

Description

7:4

Reserved

7:0

Use to program the LSBs of

the frame delay.

3:0

Itime[11:8]

Program to set the integration

time of the array. The value pro-

grammed in the register is the

number of rows ahead of the

selected row to be reset.

Register Name Video Gain Register

Address

Mnemonic

Type

19 Hex

VGAIN

Read/Write

00 Hex

Reset Value

Register Name Integration Time Low Register

Address

Mnemonic

Type

14 Hex

ITIMEL

Read/Write

00 Hex.

Bit

Bit Symbol

Description

7:6

Reserved

Reset Value

5:0

VidGain

Use to program the overall video

gain. 00hex corresponds to a gain

of 0dB while 3Fhex corresponds

to a gain of 15dB. Steps are in lin-

ear increments.

Bit

Bit Symbol

Itime[7:0]

Description

7:0

Program to set the integration

time of the array. The value pro-

grammed in the register is the

number of rows ahead of the

selected row to be reset.

Register Name Offset Compensation Register 0

address

Mnemonic

Type

1FHex

OCR0

Read/Write

00 Hex

Register Name Row Delay High Register

Address

Mnemonic

Type

15 Hex

Reset Value

RDELAYH

Read/Write

00 Hex.

Bit

Bit Symbol

OffsetVol

Description

Reset Value

7:0

This register defines the volt-

age level appearing on the

offset_ctrl pin.

Bit

Bit Symbol

Description

7:3

Reserved

Register Name Offset Compensation Register 1

address

Mnemonic

Type

22 Hex

OCR1

Read/Write

00 Hex

2:0

Rdelay[10:8]

Use to program the MSBs of the

row delay.

Register Name Row Delay Low Register

Reset Value

Address

Mnemonic

Type

16 Hex

RDELAYL

Read/Write

00 Hex

Bit

Bit Symbol

OffsetVol

Description

Reset Value

7:0

This register defines the volt-

age level appearing on the

offset_ctrl pin.

Bit

Bit Symbol

Rdelay[7:0]

Description

Register Name Offset Compensation Register 2

7:0

Use to program the LSBs of the

row delay.

address

Mnemonic

Type

25 Hex

OCR2

Read/Write

00 Hex

Register Name Frame Delay High Register

Address

Mnemonic

Type

17

Reset Value

FDELAYH

Read/Write

00 Hex

Bit

Bit Symbol

OffsetVol

Description

Reset Value

7:0

This register defines the volt-

age level appearing on the

offset_ctrl pin.

Bit

Bit Symbol

Description

7:4

Reserved

3:0

FDelay[11:8]

Use to program the MSBs of the

frame delay.

Confidential

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Register Set (continued)

Register Name Black Level Compensation Coefficient

Register

Address

Mnemonic

Type

26 Hex

BLCOEFF

Read/Write

00 Hex

Reset Value

Bit

Bit Symbol

Alpha[7:0]

Description

7:0

Exponential averaging coeffi-

cient for black pixels

Register Name Threshold 0 High Register

Address

Mnemonic

Type

27 Hex

BPTH0H

Read/Write

00 Hex.

Reset Value

Bit

Bit Symbol

BpT0 [11:4]

Description

7:0

Use to program the MSBs of

the bad pixel correction

threshold 0.

Register Name Threshold 0 Low Register

Address

Mnemonic

Type

28 Hex

BPTH0L

Read/Write

00 Hex

Reset Value

Bit

Bit Symbol

BpT0 [3.0]

Description

7:4

Use to program the LSBs of

the bad pixel correction

threshold 0.

3:0

Reserved

Register Name Threshold 1 High Register

Address

Mnemonic

Type

29 Hex

BPTH1H

Read/Write

00 Hex

Reset Value

Bit

Bit Symbol

THR1[11.4]

Description

7:0

Use to program the MSBs of

the bad pixel correction

threshold 1.

Register Name Threshold 1 Low Register

Address

Mnemonic

Type

2A Hex

BPTH1L

Read/Write

00 Hex

Reset Value

Bit

Bit Symbol

THR1 [3.0]

Description

7:4

3:0

Use to program the LSBs of

the bad pixel correction

threshold 1.

Reserved

Confidential

30

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Timing Information

1.0 DIGITAL VIDEO PORT MASTER MODE TIMING

pclk

hsync

t2

t1

d[11:0]

P0

P1

Pn

t3

Figure 49. Row Timing Diagram

pclk

vsync

t6

t5

hsync

R2

R3

Rn

t1

t2

Figure 50. Frame Timing

pclk

vsync

t6

t5

hsync

R0

R1

R2

t2

Rn

F

n-1

F

n-2

F

n

delay

t1

Inter Frame Delay

Frame (n)

Figure 51. Frame Delay Timing (With Inter Frame Delay).

Label

Descriptions

Min

Typ

Max

t0

pclk period

74.4ns

83.3ns

1.0ms

hsync low

hsync high

level mode

pulse mode

(116-HsyncAdjust) _*pclk

16 _*pclk

(see note a & b)

t1

level mode

pulse mode

(664 -HsyncAdjust) _*pclk

764 _*pclk

t2

t3

t5

first valid pixel data after hsync active

HsyncAdjust _*pclk

(see note a & b)

vsync low

vsync high

level mode

pulse mode

116 _*pclk

16 _*pclk

level mode

pulse mode

(FN_Hclk- 116) _*pclk

16 _*pclk

(see note a & b)

t6

Note a: See Frame Rate Programming section for more details

Note b: See Digital Video Port Registers for more details

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Timing Information (continued)

d[11:0]

hsync

vsync

pclk

t1

t2

Figure 52. d[11:0], hsync & vsync to Active High pclk Timing

d[11:0]

hsync

vsync

pclk

t3

t4

Figure 53. d[11:0], hsync & vsync to Active Low pclk Timing

The following specifications apply for all supply pins = +3.3V and C_L= 10pF unless otherwise noted. Boldface limits apply for TA =

T_MINto T_MAX: all other limits T_A= 25^oC (Note 7)

Label

t1

Descriptions

Min

Typ

Max

Rising pclk to Rising hsync, vsync or d[11:0]

Rising pclkto Falling hsync, vsync or d[11:0]

Falling pclk to rising hsync, vsync or d[11:0]

Falling pclk to falling hsync, vsync or d[11:0]

25ns

23ns

25ns

23ns

t2

t3

t4

Confidential

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Timing Information (continued)

2.0 DIGITAL VIDEO PORT SLAVE MODE TIMING

t1

t3

trigger row n

hsync

trigger row n+1

t2

d[11:0]

P654

P655

P640

P652

P653

P652

P653

P654

P1

mclk

Row n-1

Row n

Figure 54. Slave Mode Row Trigger and Readout Timing

trigger last row

in frame n

hsync

t5

trigger Frame n+1

vsync

mclk

t4

Figure 55. Slave Mode d[11:0], hsync & vsync to pclk Timing

d[11:0]

mclk

t6

Figure 56. Rising Edge of mclk to Valid Pixel Data

The following specifications apply for all supply pins = +3.0V & C_L= 10pF unless otherwise noted. Boldface limits apply for TA =

T_MINto T_MAX: all other limits T_A= 25^oC (Note 7)

Label

t1

Descriptions

Min

Typ

Max

Pulse width of row trigger

2 _*mclk

124 _*mclk

780 _*mclk

t2

First pixel out after rising edge of row trigger

Minimum time between row triggers.

124 _*mclk

t3

Max time to assert next frame trigger after last row

trigger.

t4

96 _*mclk

t5

t6

Pulse width of Frame trigger

2 _*mclk

Time to valid pixel data after rising edge of mclk

44ns

Confidential

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Timing Information (continued)

3.0 DIGITAL VIDEO PORT SINGLE FRAME CAPTURE (SNAPSHOT MODE) TIMING

t1

snapshot or FTriggerNow

irq

FTriggerEn

extsync or FtSync

FtBusy

t4

t3

t2

Figure 57. Snapshot Mode Timing With External Shutter

t1

snapshot or FTriggerNow

irq

FTriggerEn

extsync or FtSync

FtBusy

t3

t2

t4

Figure 58. Snapshot Timing Without External Shutter

Label

t1

Descriptions

Equation

Minimum Snapshot Trigger Pulse Width

Minimum time from Snapshot Pulse to extsync

Array Integration Time

2 _*mclk

FN_Hclk

(see notes a & b)

t2

t3

t4

Pixel Read Out

Note a: See 7.0Frame Rate Programming section for more details

Note b: See Snapshot Mode for more details

Confidential

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Timing Information (continued)

4.0 SERIAL BUS TIMING

Sr

P

Sr

t_fDA

SDA

t

HD;DAT

t

SU;STA

HD;STA

SU;STO

t

SU;DAT

SCLK

t_rCL

t_rCL1

t_rCL

t_rCL1

(1)

= Rp resistor pull-up

= MCS current source pull-up

(1) Rising edge of the first SCLK pulse after an acknowledge bit.

Figure 59. I²C Compatible Serial Bus Timing.

t_LOW

t_HIGH

t_LOW

The following specifications apply for all supply pins = +3.3V, C_L= 10pF, and sclk = 400KHz unless otherwise noted. Boldface limits

apply for TA = T_MINto T_MAX: all other limits T_A= 25^oC (Note 7)

PARAMETER

SYMBOL

f_SCLH

MIN

0

MAX

UNIT

KHz

mS

sclk clock frequency

400

Set-up time (repeated) START condition

Hold time (repeated) START condition

LOW period of the sclk clock

HIGH period of the sclk clock

Data set-up time

t_SU;STA

t_HD;STA

t_LOW

0.6

1.3

0.6

180

0

-

mS

-

mS

t_HIGH

-

mS

t_SU;DAT

t_HD;DAT

t_SU;STO

C_b

-

nS

Data hold time

0.9

mS

Set-up time for STOP condition

Capacitive load for sda and sclk lines

0.6

mS

400

pF

Confidential

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Array Mechanical Information

.440 +/-.005 TYP

[11.18 +/- 0.12]

.040 +/-.003 TYP

[1.02 +/- 0.07]

.060 +.010 TYP

-.005

[1.52 + 0.25]

[- 0.12]

43

6

1

48

.085 +/-.010

[2.16 +/- 0.25]

7

42

distance from pixel (die surface) to top surface of

glass lid= 0.894 mm

R.0075 +/-.0050

[0.191+/- 0.127]

TYP

.020 +/-.003

[0.51 +/- 0.07]

TYP

0.328

[8.325]

Note 3

31

18

30

19

(4X R.0075)

[0.19]

0.281

[7.131]

Note 3

.040 +/-.007 TYP

[1.02 +/- 0.17]

Optical Center of

Sensor Array

.560 +.012

-.005

[14.22 + 0.30]

.102 MAX

[2.58]

[ - 0.12]

Notes:

1. Controlling dimensions are in inches, values in [] are in millimeters

2. All Exposed metallized areas shall be gold plated 60 micro-inches [1.52 micrometers] minimum thickness over nickel plate

3. Reference dimensions only. Tolerance will depend on die placement [+/-0.1 mm].

4. Reference JEDEC registration MS-009, variation AF issue A, dated 9/29/1980.

Confidential

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NATIONAL'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL

COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or systems

which, (a) are intended for surgical implant into the body, or

(b) support or sustain life, and whose failure to perform when

properly used in accordance with instructions for use pro-

vided in the labeling, can be reasonably expected to result in

a significant injury to the user.

2. A critical component is any component of a life support

device or system whose failure to perform can be reasonably

expected to cause the failure of the life support device or

system, or to affect its safety or effectiveness.

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Corporation

Americas

Tel: 1-800-272-9959

Fax: 1-800-737-7018

Email: support @ nsc.com

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Fax: +49 (0) 1 80-530 85 86

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Response Group

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Tel: 81-3-5639-7560

Fax: 81-3-5639-7507

Email: europe.support @ nsc.com

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Tel: 65-2544466

Fax: 65-2504466

Email: ap.support@nsc.com

www.national.com

National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.

See Interface Products

Products > Imaging > CMOS Imaging Sensor > LM9617

LM9617 Product Folder

Monochrome CMOS Image Sensor VGA 30 FPS

Generic P/N 9617

General

Description

Package

& Models

Samples

& Pricing

Design

Tools

Features

Datasheet

Parametric Table

Monochrome or Color

Microlenses

Parametric Table

Monochrome

Optical Format

1/3 in.

30

Yes

Max Frame Rate at Full Resolution (FPS)

Maximum Sensitivity (V/lux.s)

System Dynamic Range (dB)

Total Size of Image Array (pixels)

664x504

4.13

57

Datasheet

Title

Size in Kbytes Date

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4-May-01

LM9617 Monochrome CMOS Image

Sensor VGA 30 FPS

366 Kbytes

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Package Availability, Models, Samples & Pricing

Budgetary

Pricing

Samples &

Electronic

Orders

Std

Pack

Size

Package

Models

Package

Marking

Part Number

Status

Type Pins MSL

SPICE IBIS

Qty $US each

Full

production

LM9617-5SENSORS

LM9617EVAL-KIT

LM9617HEADBOARD

LM9617CCEA

kit/group

N/A

1+ $40.0000

1

-

Buy Now

evaluation

board

Full production

1+ $2600.0000

1+ $200.0000

1K+ $19.5000

1K+ $16.5000

-

evaluation

board

tray [logo]¢U¢Z¢2¢T¢P

of

96

LCC

MSL

48

LM9617

CCEA

tray [logo]¢U¢Z¢2¢T

of

96

LM9617CCEA-2

LM9617

CCEA

General Description

The LM9617 is a high performance, low power, one-third inch VGA CMOS Active Pixel Sensor capable of

capturing grey-scale digital still or motion images and converting them to a digital data stream.

In addition to the active pixel array, an on-chip 12 bit A/D convertor, fixed pattern noise elimination circuit,

and a video gain amplifier is provided. Furthermore, an integrated programmable smart timing and control

circuit allows the user maximum flexibility in adjusting integration time, active window size, gain and frame

rate. Various control, timing and power modes are also provided.

Features

●

Supplied with micro lenses

Video or snapshot operations

Progressive scan and interlace read out modes.

Programmable pixel clock, inter-frame and inter-line delays.

Programmable partial or full frame integration

Programmable gain

Horizontal & vertical sub-sampling (2:1 & 4:2)

Windowing

External snapshot trigger & event synchronisation signals

Auto black level compensation

Flexible digital video read-out supporting programmable polarity (for synchronisation and pixel clock

signals) and leading edge adjustment (for horizontal synchronization)

Programmable via 2 wire I2C compatible serial interface

Power on reset & power down mode

●

Key Specification

Total:

Active: 648H x 488V

664H x 504V

ò Array Format

Total: 4.98mm x 3.78 mm

Active: 4.86 mm x 3.66 mm

ò Effective Image Area

ò Optical Format

ò Pixel Size

1/3"

7.5um x 7.5um

8, 10, 12 Bit Digital

57dB

ò Video Outputs

ò Dynamic Range

ò FPN

0.35%

ò Sensitivity

28.7 kLSBs/lux.sec

27%

ò Quantum Efficiency

ò Fill Factor

47% (no micro lens)

48LCC

ò Package

ò Single Supply

3.3 V

ò Power Consumption 90mW

ò Operating Temp

0 to 50 C

Applications

●

Biometrics

Infrared Camera

Barcode Scanner

Security Camera

Toys

Machine Vision

Design Tools

Title

Size in Kbytes

Date

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View Online

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Buy LM96XX-LENS-KIT

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[Information as of 5-Aug-2002]

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型号：	LM9617CCEA-2
厂家：	TEXAS INSTRUMENTS
描述：	SPECIALTY ANALOG CIRCUIT, CQCC48
文件：	总40页 (文件大小：408K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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