LM96194CISQ_技术文档

March 2007

LM96194

TruTherm™ Hardware Monitor with PI Fan Control for

Workstation Management

1.0 General Description

2 PWM fan speed control outputs

■

4 fan tachometer inputs

The LM96194 hardware monitor has a two wire digital inter-

Processor thermal throttling (PROCHOT) monitoring

face compatible with SMBus 2.0. Using a ΣΔ ADC, the

LM96194 measures the temperature of four remote diode

connected transistors as well as its own die and 9 power sup-

ply voltages. The LM96194 has new TruTherm technology

that supports precision thermal diode measurements of pro-

cessors on sub-micron processes.

Dynamic VID monitoring (6/7 VIDs per processor)

supports VRD10.2/11

8 general purpose I/Os:

■

4 can be configured as fan tachometer inputs

—

2 can be configured to connect to processor

THERMTRIP

To set fan speed, the LM96194 has two PWM outputs that

are each controlled by up to six temperature zones. The fan-

control algorithm can be based on a lookup table, PI (propor-

tional/integral) control loop, or a combination of both. The

LM96194 includes digital filters that can be invoked to smooth

temperature readings for better control of fan speed such that

acoustical noise is minimized. The LM96194 has four

tachometer inputs to measure fan speed. Limit and status

registers for all measured values are included.

2 are standard GPIOs that could be used to monitor

IERR signal

—

A general purpose inputs that can be used to monitor the

7th VID signal for VRD11

Limit register comparisons of all monitored values

2-wire serial digital interface, SMBus 2.0 compliant

Supports byte/block read and write

■

Selectable slave address (tri-level pin selects 1 of 3

possible addresses)

ALERT output supports interrupt or comparator modes

LLP-48 package

The LM96194 includes most of the features of the LM94, dual

CPU motherboard server management ASIC, such as mea-

surement and control support for dynamic Vccp monitoring for

VRD10/11 and PROCHOT but is targeted for single proces-

sor systems.

■

XOR-tree test mode

2.0 Features

3.0 Key Specifications

ΣΔ ADC architecture

■

Voltage Measurement Accuracy

±2% FS (max)

9-bits, 0.5°C

±2.5 °C (max)

■

Monitors 9 power supplies

Temperature Resolution

Temperature Sensor Accuracy

Temperature Range:

■

Monitors 4 remote thermal diodes and 2 LM60

■

New TruTherm technology support for precision thermal

diode measurements

LM96194 Operational

Remote Temp Accuracy

-40°C to +85°C

-40°C to +125°C

+3.0V to +3.6V

1.6 mA

Internal ambient temperature sensing

■

Power Supply Voltage

Power Supply Current

■

Programmable autonomous fan control based on

temperature readings with fan boost support

Fan boost support on tachometer limit error event

■

4.0 Applications

Fan control based on 13-step lookup table or PI Control

Loop or combination of both

Servers

■

PI fan control loop supports Tcontrol

■

Workstations

Temperature reading digital filters

Processor based equipment

0.5°C digital temperature sensor resolution

0.0625°C filtered temperature resolution for fan control

TruTherm™ is a trademark of National Semiconductor Corporation.

201944

www.national.com

5.0 Ordering Information

Order Number

NS Package

Transport media

Number

LM96194CISQ

SQA48A

250 units in rail

LM96194CISQX

2500 units in tape-

and-reel

6.0 Block Diagram

The block diagram of LM96194 hardware is illustrated below. The hardware implementation is a single chip ASIC solution.

20194401

www.national.com

2

7.0 Application

The system diagram show in Figure 1 is a single processor

workstation example.

20194405

FIGURE 1. Workstation Management

3

www.national.com

8.0 Connection Diagram

56 Pin TSSOP

20194402

NS Package NSQ48A

Top View

NS Order Numbers:

LM96194CISQ (250 units per rail), or

LM96194CISQX (2500 units per tape-and-reel)

www.national.com

4

9.0 Pin Descriptions

Symbol

Pin #

Type

Function

PROCHOT

1

Digital I/O (Open-

Drain)

Connected to CPU1 PROCHOT (processor hot) signal through a

bidirectional level shifter. Supports TTL input logic levels and AGTL

compatible input logic levels.

GND

2

3

4

5

6

Ground

All grounds need to be tied together at the chip then taken to a low noise

system ground. A voltage difference between grounds may cause

erroneous results.

GND

All grounds need to be tied together at the chip then taken to a low noise

system ground. A voltage difference between grounds may cause

erroneous results.

GND

All grounds need to be tied together at the chip then taken to a low noise

system ground. A voltage difference between grounds may cause

erroneous results.

GND

All grounds need to be tied together at the chip then taken to a low noise

system ground. A voltage difference between grounds may cause

erroneous results.

GND

All grounds need to be tied together at the chip then taken to a low noise

system ground. A voltage difference between grounds may cause

erroneous results.

GPIO_0/TACH1

GPIO_1/TACH2

GPIO_2/TACH3

GPIO_3/TACH4

7

Digital I/O (Open-

Drain)

Can be configured as fan tach input or a general purpose open-drain digital

I/O.

8

Digital I/O (Open-

Drain)

Can be configured as fan tach input or a general purpose open-drain digital

I/O.

9

Digital I/O (Open-

Drain)

Can be configured as fan tach input or a general purpose open-drain digital

I/O.

10

Digital I/O (Open-

Drain)

Can be configured as fan tach input or a general purpose open-drain digital

I/O..

GPIO_4 / THERMTRIP 11

Digital I/O (Open-

Drain)

A general purpose open-drain digital I/O. Can be configured to monitor a

CPU's THERMTRIP signal to mask other errors. Supports TTL input logic

levels and AGTL compatible input logic levels.

GPIO_5

GPIO_6

12

13

Digital I/O (Open-

Drain)

A general purpose open-drain digital I/O. Supports TTL input logic levels

and AGTL compatible input logic levels.

Digital I/O (Open-

Drain)

Can be used to detect the state of CPU's IERR or a general purpose open-

drain digital I/O. Supports TTL input logic levels and AGTL compatible input

logic levels.

GPIO_7

VRD1_HOT

GND

14

15

16

Digital I/O (Open-

Drain)

A general purpose open-drain digital I/O. Supports TTL input logic levels

and AGTL compatible input logic levels.

Digital Input

CPU1 voltage regulator HOT. Supports TTL input logic levels and AGTL

compatible input logic levels.

Ground Input

All grounds need to be tied together at the chip then taken to a low noise

system ground. A voltage difference between grounds may cause

erroneous results.

VID6/GPI9

17

Digital Input

CPU VID6 input. Could also be used as a general purpose input to trigger

an error event. Supports TTL input logic levels and AGTL compatible input

logic levels.

SMBDAT

18

19

20

Digital I/O (Open-

Drain)

Bidirectional System Management Bus Data. Output configured as 5V

tolerant open-drain. SMBus 2.0 compliant.

SMBCLK

Digital Input

System Management Bus Clock. Driven by an open-drain output, and is 5V

tolerant. SMBus 2.0 Compliant.

ALERT/XtestOut

Digital Output (Open- Open-drain ALERT output used in an interrupt driven system to signal that

Drain)

an error event has occurred. Masked error events do not activate the

ALERT output. When in XOR tree test mode, functions as XOR Tree output.

5

www.national.com

Symbol

Pin #

Type

Function

RESET

21

Digital I/O (Open-

Drain)

Open-drain reset output when power is first applied to the LM96194. Used

as a reset for devices powered by 3.3V stand-by. After reset, this pin

becomes a reset input. See Section (TBD) for more information. If this pin

is not used, connection to an external resistive pull-up is required to prevent

LM96194 malfunction.

AGND

22

23

GROUND Input

Analog Ground. All grounds need to be tied together at the chip then taken

to a low noise system ground. A voltage difference between grounds may

cause erroneous results.

REMOTE1−

Remote Thermal

Diode_1- Input (CPU

THERMDC)

This is the negative input (current sink) from both of the CPU thermal

diodes. Connected to THERMDC pin of Pentium processor or the emitter

of a diode connected MMBT3904 NPN transistor. Serves as the negative

input into the A/D for thermal diode voltage measurements. A 100 pF

capacitor is optional and can be connected between REMOTE1− and

REMOTE1+.

REMOTE1a+

REMOTE2−

REMOTE2a+

24

25

26

Remote Thermal

Diode_1a+ I/O (CPU

THERMDA1)

This is a positive connection to the first CPU thermal diode. Serves as the

positive input into the A/D for thermal diode voltage measurements. It also

serves as a current source output that forward biases the thermal diode.

Connected to THERMDA pin of Pentium processor or the base of a diode

connected MMBT3904 NPN transistor. A 100 pF capacitor is optional and

can be connected between REMOTE1− and each REMOTE1+.

Remote Thermal

Diode_2 - Input

This is the negative input (current sink) from both of the CPU2 thermal

diodes. Connected to THERMDC pins of Pentium processor or the emitter

of a diode connected MMBT3904 NPN transistor. Serves as the negative

input into the A/D for thermal diode voltage measurements. A 100 pF

capacitor is optional and can be connected between REMOTE2− and each

REMOTE2+.

Remote Thermal

Diode_2a + I/O

This is a positive connection to the third thermal diode. Serves as the

positive input into the A/D for thermal diode voltage measurements. It also

serves as a current source output that forward biases the thermal diode.

Connected to THERMDA pin of Pentium processor or the base of a diode

connected MMBT3904 NPN transistor. A 100 pF capacitor is optional and

can be connected between REMOTE2− and REMOTE2+.

AD_IN1/REMOTE1b+ 27

AD_IN2/REMOTE2b+ 28

Analog Input (+12V1 or Analog Input for +12V Rail 1 monitoring, for CPU1 voltage regulator.

CPU1 THERMDA2)

External attenuation resistors required such that 12V is attenuated to

0.927V for nominal ¾ scale reading. This pin may also serve as the second

positive thermal diode input for the CPU.

Analog Input or

Remote Thermal

Diode_2b + I/O

Analog Input for +12V Rail 2 monitoring. External attenuation resistors

required such that 12V is attenuated to 0.927V for nominal ¾ scale reading.

This pin may also serve as the fourth positive thermal diode input.

AD_IN3

29

30

Analog Input (+12V3) Analog Input for +12V Rail 3, for Memory/3GIO slots. External attenuation

resistors required such that 12V is attenuated to 0.927V for nominal ¾ scale

reading.

AD_IN4 (Vccp)

Analog Input

(CPU1_Vccp)

Analog input for +Vccp (processor voltage) monitoring.

AD_IN5

GND

31

32

Analog Input (+3.3V)

Ground

Analog input for +3.3V monitoring, nominal ¾ scale reading

All grounds need to be tied together at the chip then taken to a low noise

system ground. A voltage difference between grounds may cause

erroneous results.

GND

33

34

Ground

All grounds need to be tied together at the chip then taken to a low noise

system ground. A voltage difference between grounds may cause

erroneous results.

All grounds need to be tied together at the chip then taken to a low noise

system ground. A voltage difference between grounds may cause

erroneous results.

www.national.com

6

Symbol

Pin #

Type

Function

AD_IN6

35

Analog Input

(Mem_Vtt)

Analog input for +0.984V monitoring, nominal ¾ scale reading.

AD_IN7

AD_IN8

36

37

Analog Input

(Gbit_Core)

Analog input for +0.984V S/B monitoring, nominal ¾ scale reading.

Analog Input (-12V)

Analog input for -12V monitoring. External resistors required to scale to

positive level. Full scale reading at 1.236V, , nominal ¾ scale reading. This

pin may also be used to monitor an analog temperature sensor such as the

LM60, since readings from this input can be routed to the fan control logic.

Address Select

38

39

3 level analog input

This input selects the lower two bits of the LM96194 SMBus slave address.

3.3V SB (AD_IN8)

POWER (V_DD) +3.3V V_DDpower input for LM96194. Generally this is connected to +3.3V standby

standby power

power.

The LM96194 can be powered by +3.3V if monitoring in low power states

is not required, but power should be applied to this input before any other

pins.

This pin also serves as the analog input to monitor the 3.3V stand-by (SB)

voltage. It is necessary to bypass this pin with a 0.1 µF in parallel with 100

pF. A bulk capacitance of 10 µF should be in the near vicinity. The 100 pF

should be closest to the power pin.

GND

40

Ground

Digital Ground. All grounds need to be tied together at the chip then taken

to a low noise system ground. A voltage difference between grounds may

cause erroneous results.

PWM1

PWM2

VID0/VID7

VID1

41

42

43

44

45

46

47

48

Digital Output (Open- Fan control output 1.

Drain)

Digital Output (Open- Fan control output 2

Drain)

Digital Input

Voltage Identification signal from the processor. Supports TTL input logic

levels and AGTL compatible input logic levels.

Voltage Identification signal from the processor. Supports TTL input logic

levels and AGTL compatible input logic levels.

VID2

Voltage Identification signal from the processor. Supports TTL input logic

levels and AGTL compatible input logic levels.

VID3

Voltage Identification signal from the processor. Supports TTL input logic

levels and AGTL compatible input logic levels.

VID4

Voltage Identification signal from the processor. Supports TTL input logic

levels and AGTL compatible input logic levels.

VID5

Voltage Identification signal from the processor. Supports TTL input logic

levels and AGTL compatible input logic levels.

The over-score indicates the signal is active low (“Not”).

10.0 Server Terminology

A/D

Analog to Digital Converter

FSB

FW

Front side bus

ACPI

Advanced Configuration and Power

Interface

Firmware

Gb

Gigabit

ALERT

SMBus signal to bus master that an event

occurred that has been flagged for attention.

GB

Gigabyte

Gbe

GPI

GPIO

HW

I²C

Gigabit Ethernet

General purpose input

General purpose I/O

Hardware

ASF

BMC

BW

Alert Standard Format

Baseboard Management Controller

Bandwidth

DIMM

DP

Dual in line memory module

Dual-processor

Inter integrated circuit (bus)

Local area network

Least Significant Bit

Least Significant Byte

LAN

LSb

LSB

ECC

FRU

Error checking and correcting

Field replaceable unit

7

www.national.com

LVDS

LUT

Mb

Low-Voltage Differential Signaling

Look-Up Table

P/S

PCI

PDB

POR

PS

Power Supply

PCI Local Bus

Megabit

Power Distribution Board

Power On Reset

Power Supply

MB

Megabyte

MP

Multi-processor

MSb

MSB

MTBF

MTTR

NIC

Most Significant Bit

Most Significant Byte

Mean time between failures

Mean time to repair

Network Interface Card (Ethernet Card)

Operating system

SMBCLK and These signals comprise the SMBus

SMBDAT

VRD

interface (data and clock) See the SMBus

Interface section for more information.

Voltage Regulator Down - regulates Vccp

voltage for a CPU

OS

11.0 Recommended Implementation

20194406

Recommended implementation without thermal diode connections

www.national.com

8

20194407

Note: 100 pF cap across each thermal diode is optional and should be placed close to the LM96194, if used. The maximum capacitance between thermal diode

pins is 300 pF.

Thermal diode recommended implementation

9

www.national.com

All of the analog inputs include internal scaling resistors, ex-

ept for AD_IN1, AD_IN2, AD_IN3 and AD_IN8. External scal-

ing resistors are required for measuring ±12V. The inputs are

converted to 8-bit digital values such that a nominal voltage

appears at ¾ scale for positive voltages and ¼ scale for neg-

ative voltages. The analog inputs are intended to be connect-

ed to both baseboard resident VRDs and to standard voltage

rails supplied by a SSI compliant power supply.

12.0 Functional Description

The LM96194 provides 9 channels of voltage monitoring, 4

remote thermal diode monitors, an internal/local ambient tem-

perature sensor, a PROCHOT monitor, 4 fan tachometers, 8

GPIOs, THERMTRIP monitor for masking error events, 1 sets

of 7 VID inputs, an ALERT output and all the associated limit

registers on a single chip, and communicates to the rest of

the baseboard over the System Management Bus (SMBus).

The LM96194 also provides 2 PWM outputs and associated

fan control logic for controlling the speed of system fans.

There are two sets of fan control logic, a lookup table and a

PI (proportional/integral) loop controller. The lookup table and

PI controller are interactive, such that the fans run at the

fastest required speed. Upon a temperature or fan tach error

event, the PWM outputs may be programmed such that they

automatically boost to 100% duty cycle. A timer is included

that sets the minimum time that the fans are in the boost con-

dition when activated by a fan tach error.

The LM96194 has logic that ties a set of dynamically moving

VID inputs to their associated Vccp analog input for real time

window comparison fault determination. Voltage mapping for

VRD10, VRD10 extended and VRD11are supported by the

LM96194. When VRD10 mode is selected GPI8 and GPI9

can be used to detect external error flags whose state is re-

flected in the status registers.

Error events are captured in two sets of mirrored status reg-

isters (BMC Error Status Registers and Host Status Regis-

ters) allowing two controllers access to the status information

without any interference.

The LM96194 incorporates National Semiconductor's

TruTherm technology for precision “Remote Diode” readings

of processors on 90nm process geometry or smaller. Read-

ings from the external thermal diodes and the internal tem-

perature sensor are made available as an 9-bit two's-

complement digital value with the LSb representing 0.5°C.

Filtered temperature readings are available as a 12-bit two's-

complement digital value with the LSb representing 0.0625°

C.

The LM96194's ALERT output supports interrupt mode or

comparator mode of operation. The comparator mode is only

functional for thermal monitoring.

The LM96194 provides a number of internal registers, which

are detailed in the register section of this document.

12.1 Please contact your local sales office for complete

LM96194 applications information.

13.0 Registers

13.1 REGISTER WARNINGS

In most cases, reserved registers and register bits return zero when read. This should not be relied upon, since reserved registers

can be used for future expansion of the LM96194 functions.

Some registers have “N/D” for their default value. This means that the power-up default of the register is not defined. In the case

of value registers, care should be taken to ensure that software does not read a value register until the associated measurement

function has acquired a measurement. This applies to temperatures, voltages, fan RPM, and PROCHOT monitoring.

13.2 REGISTER SUMMARY TABLE

Register Key

Term

N/D

Description

Not Defined

N/A

R

Not Applicable

Read Only

R/W

RWC

Read or Write

Read or Write to Clear

Loc

k

Register Name

Address

Description

FACTORY REGISTERS

x

XOR Test

SMBus Test

Reserved

00h

Used to set the XOR test tree mode

SMBus read/write test register

01h

02h-04h

“REMOTE DIODE” MODE SELECT

Transistor Mode Select

x

05h

06h

Selects Diode Mode (default) or Transistor Mode for “Remote Diode”

measurements

VALUE REGISTER SECTION 1

Zone 1b (CPU Diode b) Temp

Measured value of remote thermal diode temperature channel 1b

10

www.national.com

Loc

k

Register Name

Address

Description

Zone 2b (MMBT3904 Diode b) Temp

Zone 1b (CPU Diode b) Filtered Temp

07h

08h

09h

Measured value of remote thermal diode temperature channel 2b

Filtered value of remote thermal diode temperature channel 1b

Filtered value of remote thermal diode temperature channel 2b

Zone 2b (MMBT3904 Diode b) Fitlered

Temp

PWM1 8-bit Duty Cycle Value

PWM2 8-bit Duty Cycle Value

0Ah

0Bh

8- bit value of the PWM1 duty cycle.

8-bit value of the PWM2 duty cycle

HIGH RESOLUTION PWM OVERIDE REGISTERS

x

PWM1 Duty Cycle Override (low byte)

PWM1 Duty Cycle Override (high byte)

PWM2 Duty Cycle Override (low byte)

PWM2 Duty Cycle Override (high byte)

0Ch

0Dh

0Eh

0Fh

Lower byte of the high resolution PWM1 duty cycle register

Upper byte of the high resolution PWM1 duty cycle register

Lower byte of the high resolution PWM2 duty cycle register

Upper byte of the high resolution PWM2 duty cycle register

EXTENDED RESOLUTION TEMPERATURE VALUE REGISTERS

Z1a_LSB

10h

11h

12h

13h

14h

15h

16h

17h

18h

19h

1Ah

1Bh

1Ch

1Dh

1Eh

1Fh

20h

21h

22h

23h

Zone 1a (CPU) extended resolution unfiltered temperature value register,

least-significant byte

Z1a_MSB

Z1b_LSB

Zone 1a (CPU) extended resolution unfiltered temperature value register,

most-significant byte

Zone 1b (CPU) extended resolution unfiltered temperature value register,

least-significant-byte

Z1b_MSB

Z2a_LSB

Zone 1b (CPU) extended resolution unfiltered temperature value register,

most-significant byte

Zone 2a (MMBT2904) extended resolution unfiltered temperature value

register, least-significant-byte

Z2a_MSB

Z2b_LSB

Zone 2a (MMBT3904) extended resolution unfiltered temperature value

register, most-significant byte

Zone 2b (MMBT3904) extended resolution unfiltered temperature value

register, least-significant-byte

Z2b_MSB

Z1a_F_LSB

Z1a_F_MSB

Z1b_F_LSB

Z1b_F_MSB

Z2a_F_LSB

Z2a_F_MSB

Z2b_F_LSB

Z2b_F_MSB

Z3_LSB

Zone 2b (MMBT3904) extended resolution unfiltered temperature value

register, most-significant byte

Zone 1a (CPU) extended resolution filtered temperature value register,

least-significant byte

Zone 1a (CPU) extended resolution filtered temperature value register,

most-significant byte

Zone 1b (CPU) extended resolution filtered temperature value register,

least-significant-byte

Zone 1b (CPU) extended resolution filtered temperature value register,

most-significant byte

Zone 2a (MMBT3904) extended resolution filtered temperature value

register, least-significant-byte

Zone 2a (MMBT3904) extended resolution filtered temperature value

register, most-significant byte

Zone 2b (MMBT3904) extended resolution filtered temperature value

register, least-significant-byte

Zone 2b (MMBT3904) extended resolution filtered temperature value

register, most-significant byte

Zone 3 (Internal) extended resolution temperature value register, least-

significant byte

Z3_MSB

Zone 3 (Internal) extended resolution temperature value register, least-

significant byte

Z4_LSB

Zone 4 (External Digital) extended resolution temperature value register,

most-significant byte

Z4_MSB

Zone 4 (External Digital) extended resolution temperature value register,

least-significant byte

11

www.national.com

Loc

k

Register Name

Address

Description

Reserved

24h-30h

PI LOOP AND FAN CONTROL SETUP REGISTERS

x

Temperature Source Select

PWM Filter Settings

31h

32h

Selects the temperature source for some temperature zones.

Sets the IIR filter coefficients for the PWM outputs for low resolution

sources

x

PWM1 Filter Shutoff Threshold

PWM2 Filter Shutoff Threshold

PI/LUT Fan Control Bindings

33h

34h

35h

36h

PWM1 Filter Shutoff Threshold

PWM2 Filter Shutoff Threshold

PI/LUT fan control binding configuration

PI Controller Minimum PWM and Hysteresis settings

PI Controller Minimum PWM and

Hysteresis

x

Zone 1 Tcontrol

Zone 2 Tcontrol

Zone 1 Toff

37h

38h

39h

3Ah

3Bh

3Ch

3Dh

Zone 1 (CPU) PI Controller Target Temperature (Tcontrol)

Zone 2 (MMBT3904) PI Controller Target Temperature (Tcontrol)

Zone 1 (CPU) PI Controller Off Temperature (Toff)

Zone 2 (MMBT3904) PI Controller Off Temperature (Toff)

PI controller proportional coefficient

Zone 2 Toff

P Coefficient

I Coefficient

PI controller integral coefficient

PI Exponents

PI controller coefficient exponents

DEVICE IDENTIFICATION REGISTERS

Manufacturer ID

3Eh

3Fh

Contains manufacturer ID code

Version/Stepping

Contains code for major and minor revisions

BMC ERROR STATUS REGISTERS

B_Error Status 1

40h

41h

42h

43h

44h

45h

46h

47h

BMC error status register 1

BMC error register 2

B_Error Status 2

B_Error Status 3

BMC error register 3

B_Error Status 4

BMC error register 4

B_PROCHOT Error Status

Reserved

BMC error register for PROCHOT

B_GPI Error Status

BMC error register for GPIs

BMC error register for Fans

B_Fan Error Status

HOST ERROR STATUS REGISTERS

H_Error Status 1

48h

49h

4Ah

4Bh

4Ch

4Dh

4Eh

4Fh

HOST error status register 1

HOST error register 2

H_Error Status 2

H_Error Status 3

HOST error register 3

H_Error Status 4

HOST error register 4

H_PROCHOT Error Status

Reserved

HOST error register for PROCHOT

H_GPI Error Status

HOST error register for GPIs

HOST error register for Fans

H_Fan Error Status

VALUE REGISTERS SECTION 2

Zone 1a (CPU) Temp

Zone 2a (MMBT3904) Temp

Zone 3 (Internal) Temp

Zone 4 (External Digital) Temp

Zone 1a (CPU) Filtered Temp

Zone 2a (MMBT3904) Filtered Temp

AD_IN1 Voltage

50h

51h

52h

53h

54h

55h

56h

57h

Measured value of remote thermal diode temperature channel 1a

Measured value of remote thermal diode temperature channel 2a

Measured temperature from on-chip sensor

Measured temperature from external temperature sensor

Filtered value of remote thermal diode temperature channel 1a

Filtered value of remote thermal diode temperature channel 2a

Measured value of AD_IN1

AD_IN2 Voltage

Measured value of AD_IN2

www.national.com

12

Loc

k

Register Name

AD_IN3 Voltage

Address

Description

58h

Measured value of AD_IN3

Measured value of AD_IN4

Measured value of AD_IN5

Reserved

59h-5Bh

5Ch

AD_IN4 Voltage

Reserved

5Dh

AD_IN5 Voltage

Reserved

5Eh

5Fh-61h

62h

AD_IN6 Voltage

AD_IN7 Voltage

AD_IN8 Voltage

AD_IN9 Voltage

Measured value of AD_IN6

Measured value of AD_IN7

Measured value of AD_IN8

63h

64h

65h

Measured value of AD_IN9 (V_DD3.3V S/B)

Reserved

66h

Current PROCHOT

Average PROCHOT

67h

68h

Measured PPROCHOT throttle percentage

Average PPROCHOT throttle percentage

Reserved

GPI State

69h-6Ah

6Bh

Current GPIO state

P1_VID

6Ch

6Dh

Current Processor VID value

Reserved

FAN Tach 1 LSB

FAN Tach 1 MSB

FAN Tach 2 LSB

FAN Tach 2 MSB

FAN Tach 3 LSB

FAN Tach 3 MSB

FAN Tach 4 LSB

FAN Tach 4 MSB

6Eh

6Fh

70h

71h

72h

73h

74h

75h

Measured FAN Tach 1 LSB

Measured FAN Tach 1 MSB

Measured FAN Tach 2 LSB

Measured FAN Tach 2 MSB

Measured FAN Tach 3 LSB

Measured FAN Tach 3 MSB

Measured FAN Tach 4 LSB

Measured FAN Tach 4 MSB

Reserved

76h-77h

TEMPERATURE LIMIT REGISTERS

Zone 1 (CPU) Low Temp

78h

79h

7Ah

7Bh

Low limit for external thermal diode temperature channel 1 (D1)

measurement

Zone 1 (CP1) High Temp

High limit for external thermal diode temperature channel 1 (D1)

measurement

Zone 2 (MMBT3904) Low Temp

Zone 2 (MMBT3904) High Temp

Low limit for external thermal diode temperature channel 2 (D2)

measurement

High limit for external thermal diode temperature channel 2 (D2)

measurement

Zone 3 (Internal) Low Temp

7Ch

7Dh

7Eh

7Fh

Low limit for local temperature measurement

High limit for local temperature measurement

Low limit for external digital temperature sensor

High limit for external digital temperature sensor

Zone 3 (Internal) High Temp

Zone 4 (External Digital) Low Temp

Zone 4 (External Digital) High Temp

x

Fan Boost Temp Zone 1

Fan Boost Temp Zone 2

80h

81h

Zone 1 (CPU) fan boost temperature

Zone 2 (MMBT3904) fan boost temperature

13

www.national.com

Loc

k

Register Name

Fan Boost Temp Zone 3

Address

Description

x

82h

83h

84h

85h

Zone 3 (Internal) fan boost temperature

Fan Boost Temp Zone 4

Zone 4 (External Digital) fan boost temperature

Zone 1 and Zone 2 hysteresis for limit comparisons

Zone 3 and Zone 4 hysteresis for limit comparisons

Zone1 and Zone 2 Hysteresis

Zone 3 and Zone 4 Hysteresis

Reserved

86h-8Dh

ZONE 1b and 2b TEMPERATURE READING ADJUSTMENT REGISTERS

Zone 1b Temp Adjust

8Eh

Allows all Zone 1b temperature measurements to be adjusted by a

programmable offset.

Zone 2b Temp Adjust

8Fh

Allows all Zone 2b temperature measurements to be adjusted by a

programmable offset.

OTHER LIMIT REGISTERS

AD_IN1 Low Limit

AD_IN1 High Limit

AD_IN2 Low Limit

AD_IN2 High Limit

AD_IN3 Low Limit

AD_IN3 High Limit

Reserved

90h

Low limit for analog input 1 measurement

High limit for analog input 1 measurement

Low limit for analog input 2 measurement

High limit for analog input 2 measurement

Low limit for analog input 3 measurement

High limit for analog input 3 measurement

91h

92h

93h

94h

95h

96h-9Dh

9Ch

AD_IN4 Low Limit

AD_IN4 High Limit

Reserved

Low limit for analog input 4 measurement (Processor Vccp)

High limit for analog input 4 measurement (Processor Vccp)

9Dh

9Eh-9Fh

A0h

AD_IN5 Low Limit

AD_IN5 High Limit

Reserved

Low limit for analog input 5 measurement

High limit for analog input 5 measurement

A1h

A2h-A7h

A8h

AD_IN6 Low Limit

AD_IN6 High Limit

AD_IN7 Low Limit

AD_IN7 High Limit

AD_IN8 Low Limit

AD_IN8 High Limit

AD_IN9 Low Limit

AD_IN9 High Limit

Low limit for analog input 6 measurement

High limit for analog input 6 measurement

Low limit for analog input 7 measurement

High limit for analog input 7 measurement

Low limit for analog input 8 measurement

High limit for analog input 8 measurement

Low limit for analog input 9 measurement

High limit for analog input 9 measurement

A9h

AAh

ABh

ACh

ADh

AEh

AFh

PROCHOT User Limit

Reserved

B0h

B1h

User settable limit for PROCHOT

Vccp Limit Offsets

Reserved

B2h

B3h

VID offset values for window comparator for CPU Vccp (AD_IN4)

FAN Tach 1 Limit LSB

FAN Tach 1 Limit MSB

FAN Tach 2 Limit LSB

FAN Tach 2 Limit MSB

FAN Tach 3 Limit LSB

FAN Tach 3 Limit MSB

FAN Tach 4 Limit LSB

FAN Tach 4 Limit MSB

B4h

B5h

B6h

B7h

B8h

B9h

BAh

BBh

FAN Tach 1 Limit LSB

FAN Tach 1 Limit MSB

FAN Tach 2 Limit LSB

FAN Tach 2 Limit MSB

FAN Tach 3 Limit LSB

FAN Tach 3 Limit MSB

FAN Tach 4 Limit LSB

FAN Tach 4 Limit MSB

www.national.com

14

Loc

k

Register Name

Address

BCh

Description

SETUP REGISTERS

Special Function Control 1

Controls the hysteresis for voltage limit comparisons. Also selects filtered

or unfiltered temperature usage for temperature limit comparisons and

fan control.

Special Function Control 2

BDh

Enables smart tach detection. Also selects 0.5°C or 1.0°C resolution for

fan control.

x

GPI / VID Level Control

PWM Ramp Control

BEh

BFh

Control the input threshold levels for the VIDx, and GPIO_x inputs.

Controls the ramp rate of the PWM duty cycle when VRD_HOT is

asserted, as well as the ramp rate when PROCHOT exceeds the user

threshold.

x

Fan Boost Hysteresis (Zones 1/2)

Fan Boost Hysteresis (Zones 3/4)

Zones 1/2 Spike Smoothing Control

LUT 1/2 MinPWM and Hysteresis

LUT 3/4 MinPWM and Hysteresis

C0h

C1h

C2h

C3h

C4h

Fan Boost Hysteresis for zones 1 and 2

Fan Boost Hysteresis for zones 3 and 4

Configures Spike Smoothing for zones 1 and 2

Controls MinPWM and hysteresis setting for LUT 1 and 2 auto-fan control

Controls MinPWM and hysteresis setting for LUT 3 and 4 auto-fan control

GPO

C5h

Controls the output state of the GPIO pins

Controls assertion PROCHOT

PROCHOT Control

C6h

C7h

PROCHOT Time Interval

Configures the time window over which the PROCHOT inputs are

measured

x

PWM1 Control 1

PWM1 Control 2

PWM1 Control 3

PWM1 Control 4

C8h

C9h

CAh

CBh

Controls PWM control source bindings.

Controls PWM override and output polarity

Controls PWM spin-up duration and duty cycle

Frequency control for PWM1.

x

PWM2 Control 1

PWM2 Control 2

PWM2 Control 3

PWM2 Control 4

CCh

CDh

CEh

CFh

Controls PWM control source bindings.

Controls PWM override and output polarity

Controls PWM spin-up duration and duty cycle

Frequency control for PWM2

x

LUT 1 Base Temperature

LUT 2 Base Temperature

LUT 3 Base Temperature

LUT 4 Base Temperature

D0h

D1h

D2h

D3h

Base temperature to which look-up table offset is applied for LUT 1

Base temperature to which look-up table offset is applied for LUT 2

Base temperature to which look-up table offset is applied for LUT 3

Base temperature to which look-up table offset is applied for LUT 4

x

Step 2 Temp Offset

Step 3 Temp Offset

Step 4 Temp Offset

Step 5 Temp Offset

Step 6 Temp Offset

Step 7 Temp Offset

Step 8 Temp Offset

Step 9 Temp Offset

Step 10 Temp Offset

Step 11 Temp Offset

Step 12 Temp Offset

Step 13 Temp Offset

D4h

D5h

D6h

D7h

D8h

D9h

DAh

DBh

DCh

DDh

DEh

DFh

Step 2 LUT 1/2 and LUT 3/4 Offset Temperatures

Step 3 LUT 1/2 and LUT 3/4 Offset Temperatures

Step 4 LUT 1/2 and LUT 3/4 Offset Temperatures

Step 5 LUT 1/2 and LUT 3/4 Offset Temperatures

Step 6 LUT 1/2 and LUT 3/4 Offset Temperatures

Step 7 LUT 1/2 and LUT 3/4 Offset Temperatures

Step 8 LUT 1/2 and LUT 3/4 Offset Temperatures

Step 9 LUT 1/2 and LUT 3/4 Offset Temperatures

Step 10 LUT 1/2 and LUT 3/4 Offset Temperatures

Step 11 LUT 1/2 and LUT 3/4 Offset Temperatures

Step 12 LUT 1/2 and LUT 3/4 Offset Temperatures

Step 13 LUT 1/2 and LUT 3/4 Offset Temperatures

15

www.national.com

Loc

k

Register Name

TACH to PWM Binding

Address

Description

E0h

E1h

Controls the tachometer input to PWM output binding

Controls the fan boost function upon a tach error

x

Tach Boost Control

x

LM96194 Status/Control

LM96194 Configuration

E2h

E3h

Gives Master error status, ASF reset control and Max PWM control

Configures various outputs and provides START bit

SLEEP STATE CONTROL AND MASK REGISTERS

Sleep State Control

S1 GPI Mask

E4h

E5h

E6h

E7h

E8h

E9h

EAh

EBh

Used to communicate the system sleep state to the LM96194

Sleep state S1 GPI error mask register

S1 Fan Mask

Sleep state S1 fan tach error mask register

S3 GPI Mask

Sleep state S3 GPI error mask register

S3 Fan Mask

Sleep state S3 fan tach error mask register

S3 Temperature/Voltage Mask

S4/5 GPI Mask

Sleep state S3 temperature or voltage error mask register

Sleep state S4/5 GPI error mask register

S4/5 Temperature/Voltage Mask

OTHER MASK REGISTERS

GPI Error Mask

Sleep state S4/5 temperature or voltage error mask register

ECh

EDh

Error mask register for GPI faults

Miscellaneous Error Mask

Error mask register for VRD_HOT, GPI, and dynamic Vccp limit checking.

ZONE 1a AND 2a TEMPERATURE READING ADJUSTMENT REGISTERS

Zone 1a Temp Adjust

EEh

Allows all Zone 1a temperature measurements to be adjusted by a

programmable offset

Zone 2a Temp Adjust

EFh

Allows all Zone 2a temperature measurements to be adjusted by a

programmable offset

BLOCK COMMANDS

Block Write Command

Block Read Command

Fixed Block 0

F0h

F1h

F2h

F3h

F4h

F5h

F6h

F7h

F8h

F9h

FAh

FBh

FCh

FDh

SMBus Block Write Command Code

SMBus Block Write/Read Process call

Fixed block code address 40h, size 8 bytes

Fixed block code address 48h, size 8 bytes

Fixed block code address 50h, size 6 bytes

Fixed block code address 56h, size 16 bytes

Fixed block code address 67h, size 4 bytes

Fixed block code address 6Eh, size 8 bytes

Fixed block code address 78h, size 12 bytes

Fixed block code address 90h, size 32 bytes

Fixed block code address B4h, size 8 bytes

Fixed block code address C8h, size 8 bytes

Fixed block code address D0h, size 16 bytes

Fixed block code address E5h, size 9 bytes

Fixed Block 1

Fixed Block 2

Fixed Block 3

Fixed Block 4

Fixed Block 5

Fixed Block 6

Fixed Block 7

Fixed Block 8

Fixed Block 9

Fixed Block 10

Fixed Block 11

Reserved

FEh-FFh Reserved for future commands

Please contact your local sales office for complete LM96194 applications information.

www.national.com

16

ESD Susceptibility (Note 4)

Human Body Model

Machine Model

14.0 Absolute Maximum Ratings

(Notes 1, 2)

3 kV

300V

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales Office/

Distributors for availability and specifications.

Charged Device Model

Storage Temperature

Soldering process must comply with National's reflow

temperature profile specifications. Refer to

www.national.com/packaging/. (Note 5)

750V

−65°C to +150°C

Positive Supply Voltage (V_DD

)

6.0V

Voltage on Any Digital Input or

Output Pin

−0.3V to 6.0V

(Except Analog

Inputs)

15.0 Operating Ratings (Notes 1, 2)

Voltage on +5V Input

−0.3V to +6.667V

T_MIN≤ T_A≤ T_MAX

-40°C ≤ T_A≤ +85°C

Voltage at Positive Remote

Diode Inputs, AD_IN1, AD_IN2,

AD_IN3, and AD_IN15 Inputs

Voltage at Other Analog Voltage

Inputs

Operating Temperature Range

−0.3V to (V_DD+ 0.05V)

−0.3V to +6.0V

Nominal Supply Voltage

Supply Voltage Range (V_DD

VID0-VID5

3.3V

+3.0V to +3.6V

−0.05V to +5.5V

−0.05V to

(V_DD+ 0.05V)

)

Input Current at Thermal Diode

Negative Inputs

Input Current at any pin (Note 3)

Package Input Current (Note 3)

Digital Input Voltage Range

±1 mA

±10mA

±100 mA

Package Thermal Resistance

(Note 6)

79°C/W

Maximum Junction Temperature

(Note 9)

(T_JMAX

)

150 °C

DC Electrical Characteristics

The following limits apply for +3.0 V_DCto +3.6 V_DC, unless otherwise noted. Bold face limits apply for T_A= T_Jover T_MINto

T_MAXof the operating range; all other limits T_A= T_J= 25°C unless otherwise noted. T_Ais the ambient temperature of the LM96194;

T_Jis the junction temperature of the LM96194; T_Dis the junction temperature of the thermal diode.

Symbol

Parameter

Conditions

Typical

Limits

Units

(Limits)

(Note 9) (Note 10)

POWER SUPPLY CHARACTERISTICS

Power Supply Current

Converting, Interface and

Fans Inactive, Peak Current

2

1.6

2

2.75

mA (max)

mA

Converting, Interface and

Fans Inactive, Average

Current

Power-On Reset Threshold Voltage

1.6

2.7

V (min)

V (max)

TEMPERATURE-TO-DIGITAL CONVERTER CHARACTERISTICS

Local Temperature Accuracy Over Full Range

±2

±4

±3

°C (max)

-40°C ≤ T_A< 0°C

±2

±1

1

°C (max)

°C

0°C ≤ T_A≤ 85°C

T_A= +55°C

±2.5

Local Temperature Resolution

Remote Thermal Diode Temperature Accuracy(Note

8)

0°C ≤ T_A≤ 85°C

and 0°C ≤ T_D≤ 100°C

±3

±2.5

±4

°C (max)

0°C ≤ T_A≤ 85°C

and T_D=70°C

Remote Thermal Diode Temperature Accuracy

Extended to Down to -40 for MMBT3904 Only

-40°C ≤ T_A< 0°C

and -40°C ≤ T_D< 0°C

Remote Thermal Diode Temperature Accuracy;

targeted for a typical Pentium processor on 90nm or

65nm process (Note 8)

0°C ≤ T_A≤ 85°C

and 25°C ≤ T_D≤ 70°C

±1

°C

Remote Temperature Resolution

Thermal Diode Source Current

1

°C

µA (max)

µA

High Level

Low Level

172

230

10.75

17

www.national.com

Symbol

Parameter

Conditions

Typical

Limits

Units

(Limits)

(Note 9) (Note 10)

Thermal Diode Current Ratio

Total Monitoring Cycle Time

16

T_C

100

ms (max)

ANALOG-TO-DIGITAL VOLTAGE MEASUREMENT CONVERTER CHARACTERISTICS

TUE

Total Unadjusted Error (Note 12)

% of

FS (max)

±2

DNL

PSS

Differential Non-Linearity

±1

LSB

Power Supply (V_DD) Sensitivity

%/V (of

FS)

±1

T_C

Total Monitoring Cycle Time

100

ms (max)

Input Resistance for Inputs with Dividers

200

140

kΩ (min)

AD_IN1- AD_IN3 and AD_IN8 Analog Input Leakage

Current (No Dividers are present on these inputs.)

(Note 13)

60

nA (max)

DIGITAL OUTPUTS: PWM1, PWM2

I_OL

Maximum Current Sink

Output Low Voltage

8

mA (min)

V (max)

V_OL

I_OUT= 8.0 mA

0.4

DIGITAL OUTPUTS: ALL

V_OL

Output Low Voltage (Note excessive current flow

causes self-heating and degrades the internal

temperature accuracy.)

I_OUT= 4.0 mA

I_OUT= 6 mA

0.4

0.55

10

V (min)

µA (max)

mA (max)

pF

I_OH

High Level Output Leakage Current

V_OUT= V_DD

0.1

20

I_OTMAX

Maximum Total Sink Current for all Digital Outputs

Combined

32

C_O

Digital Output Capacitance

DIGITAL INPUTS: ALL

V_IH

V_IL

V_IH

V_IM

Input High Voltage Except Address Select

2.1

0.8

V (min)

V (max)

V (min)

Input Low Voltage Except Address Select

Input High Voltage for Address Select

Input Mid Voltage for Address Select

90% V_DD

43% V_DD

57% V_DD

V (min)

V (max)

V_IL

Input Low Voltage for Address Select

DC Hysteresis

10% V_DD

V (max)

V

V_HYST

I_IH

0.3

20

Input High Current

V_IN= V_DD

V_IN= 0V

−10

10

µA (min)

µA (max)

pF

I_IL

Input Low Current

C_IN

Digital Input Capacitance

DIGITAL INPUTS: P1_VIDx, P2_VIDx, GPI_9, GPI_8, GPIO_7, GPIO_6, GPIO_5, GPIO_4 (When respective bit set in Register

BEh GPI/VID Level Control)

V_IH

V_IL

Alternate Input High Voltage (AGTL+ Compatible)

Alternate Input Low Voltage (AGTL+ Compatible)

0.8

0.4

V (min)

V (max)

www.national.com

18

AC Electrical Characteristics

The following limits apply for +3.0 V_DCto +3.6 V_DC, unless otherwise noted. Bold face limits apply for T_A= T_J= T_MINto T_MAXof

the operating range; all other limits T_A= T_J= 25°C unless otherwise noted.

Symbol

Parameter

Conditions

Typical

Limits

Units

(Limits)

(Note 9) (Note 10)

FAN RPM-TO-DIGITAL CHARACTERISTICS

Counter Resolution

14

2

bits

Number of fan tach pulses count is based

on

pulses

Counter Frequency

Accuracy

22.5

kHz

±6

% (max)

PWM OUTPUT CHARACTERISTICS

Frequency Tolerances

±6

% (max)

Duty-Cycle Tolerance

±2

±6

RESET INPUT/OUTPUT CHARACTERISTICS

Output Pulse Width

Upon Power Up

250

330

ms (min)

ms (max)

Minimum Input Pulse Width

Reset Output Fall Time

10

1

µs (min)

µs (max)

1.6V to 0.4V Logic Levels

SMBus TIMING CHARACTERISTICS

f_SMBCLK

SMBCLK (Clock) Clock Frequency

10

100

kHz (min)

kHz (max)

t_BUF

SMBus Free Time between Stop and

Start Conditions

4.7

4.0

µs (min)

t_HD;STA

Hold time after (Repeated) Start

Condition. After this period, the first clock

is generated.

µs (min)

t_SU;STA

t_SU;STO

t_SU;DAT

t_HD;DAT

Repeated Start Condition Setup Time

Stop Condition Setup Time

4.7

4.0

µs (min)

ns (min)

Data Input Setup Time to SMBCLK High

250

Data Output Hold Time after SMBCLK

Low

300

1075

ns (min)

ns (max)

t_LOW

t_HIGH

SMBCLK Low Period

4.7

50

µs (min)

µs (max)

SMBCLK High Period

4.0

50

µs (min)

µs (max)

t_R

Rise Time

Fall Time

1

µs (max)

ns (max)

t_F

300

t_TIMEOUT

Timeout

SMBDAT or SMBCLK low

time required to

31

ms

ms (min)

ms (max)

ꢀ

25

35

reset the Serial Bus

Interface to the Idle State

t_POR

C_L

Time in which a device must be

operational after power-on reset

V_DD> +2.8V

500

400

ms (max)

pF (max)

Capacitance Load on SMBCLK and

SMBDAT

19

www.national.com

20194403

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is

functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed

specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test

conditions.

Note 2: All voltages are measured with respect to GND, unless otherwise noted.

Note 3: When the input voltage (V_IN) at any pin exceeds the power supplies (V_IN< (GND or AGND) or V_IN> V_DD, except for analog voltage inputs), the current

at that pin should be limited to 10 mA. The 100 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies

with an input current of 10 mA to ten. Parasitic components and/or ESD protection circuitry are shown below for the LM96194’s pins. Care should be taken not

to forward bias the parasitic diode, D1, present on pins D+ and D− as shown in circuits C and D. Doing so by more than 50 mV may corrupt temperature

measurements. D1 and the ESD Clamp are connected between V+ (V_DD, AD_IN16) and GND as shown in circuit B. SNP stands for snap-back device.

Symbol

Pin #

1

Circuit

All Input Circuits

PROCHOT

GND

A

2

GND

3

GND

4

GND

5

GND

6

GPIO_0/TACH1

GPIO_1/TACH2

GPIO_2/TACH3

GPIO_3/TACH4

7

ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀCircuit A

8

9

10

11

12

13

14

15

16

17

GPIO_4 /THERMTRIP

GPIO_5

GPIO_6

GPIO_7

VRD_HOT

GND

SCSI_TERM1

SMBDAT

SMBCLK

ALERT/XtestOut

RESET

18

19

20

21

22

A

ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀCircuit B

AGND

B (Internally

shorted to GND

pin.)

REMOTE1–

REMOTE1+

REMOTE2–

REMOTE+

AD_IN1

23

24

25

26

27

28

29

C

D

C

D

ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀCircuit C

AD_IN2

AD_IN3

www.national.com

20

Symbol

Pin #

Circuit

All Input Circuits

AD_IN4

30

E

AD_IN5

GND

31

32

33

34

35

36

37

38

39

40

E

D

A

B

GND

AD_IN6

AD_IN7

AD_IN8

ADDR_SEL

AD_IN9/V_DD(V+)

GND

ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀCircuit D

B (Internally

shorted to AGND.)

PWM1

41

42

43

44

45

46

47

48

A

PWM2

P1_VID0

P1_VID1

P1_VID2

P1_VID3

P1_VID4

P1_VID5

ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀCircuit E

Note 4: Human body model, 100 pF discharged through a 1.5 kΩ resistor. Machine model, 200 pF discharged directly into each pin. Charged device model (CDM)

simulates a pin slowly acquiring charge (such as from a device sliding down the feeder in an automated assembler) then rapidly being discharged.

Note 5: Reflow temperature profiles are different for lead-free and non lead-free packages.

Note 6: The maximum power dissipation must be de-rated at elevated temperatures and is dictated by T_JMAX, θ_JAand the ambient temperature, T_A. The maximum

allowable power dissipation at any temperature is P_{D MAX}= (T_JMAX− T_A) / θ_JA. The θ_JAfor the LM96194 when mounted to 1 oz. copper foil PCB the θ_JAwith different

air flow is listed in the following table.

Air Flow

Junction to Ambient Thermal Resistance, θ_JA

0 m/s

28 °C/W

25 °C/W

22 °C/W

1.14 m/s (225 LFPM)

2.54 m/s (500 LFPM)

Note 7: See the URL "http://www.national.com/packaging/" for other recommendations and methods of soldering surface mount devices.

Note 8: At the time of first pubication of this specification (Jan 2006), this specification applies to either Pentium or Xeon Processors on 90nm or 65nm process

when TruTherm is selected. When TruTherm is deselected this specification applies to an MMBT3904. This specification does include the error caused by the

variability of the diode ideality and series resistance parameters.

Note 9: Typical parameters are at T_J= T_A= 25 °C and represent most likely parametric norm.

Note 10: Limits are guaranteed to National's AOQL (Average Outgoing Quality Level).

Note 11: TUE (Total Unadjusted Error) includes Offset, Gain and Linearity errors of the ADC.

Note 12: Total Monitoring Cycle Time includes all temperature and voltage conversions.

Note 13: Leakage current approximately doubles every 20 °C.

Note 14: A total digital I/O current of 40 mA can cause 6 mV of offset in Vref.

Note 15: Timing specifications are tested at the TTL logic levels, V_IL= 0.4V for a falling edge and V_IH= 2.4V for a rising edge. TRI-STATE output voltage is forced

to 1.4V.

21

www.national.com

16.0 Physical Dimensions inches (millimeters) unless otherwise noted

48-Lead Molded LLP Package,

Order Number LM96194CISQ or LM96194CIAQX,

NS Package Number SQA48A

www.national.com

22

Notes

23

www.national.com

Notes

THE CONTENTS OF THIS DOCUMENT ARE PROVIDED IN CONNECTION WITH NATIONAL SEMICONDUCTOR CORPORATION

(“NATIONAL”) PRODUCTS. NATIONAL MAKES NO REPRESENTATIONS OR WARRANTIES WITH RESPECT TO THE ACCURACY

OR COMPLETENESS OF THE CONTENTS OF THIS PUBLICATION AND RESERVES THE RIGHT TO MAKE CHANGES TO

SPECIFICATIONS AND PRODUCT DESCRIPTIONS AT ANY TIME WITHOUT NOTICE. NO LICENSE, WHETHER EXPRESS,

IMPLIED, ARISING BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS

DOCUMENT.

TESTING AND OTHER QUALITY CONTROLS ARE USED TO THE EXTENT NATIONAL DEEMS NECESSARY TO SUPPORT

NATIONAL’S PRODUCT WARRANTY. EXCEPT WHERE MANDATED BY GOVERNMENT REQUIREMENTS, TESTING OF ALL

PARAMETERS OF EACH PRODUCT IS NOT NECESSARILY PERFORMED. NATIONAL ASSUMES NO LIABILITY FOR

APPLICATIONS ASSISTANCE OR BUYER PRODUCT DESIGN. BUYERS ARE RESPONSIBLE FOR THEIR PRODUCTS AND

APPLICATIONS USING NATIONAL COMPONENTS. PRIOR TO USING OR DISTRIBUTING ANY PRODUCTS THAT INCLUDE

NATIONAL COMPONENTS, BUYERS SHOULD PROVIDE ADEQUATE DESIGN, TESTING AND OPERATING SAFEGUARDS.

EXCEPT AS PROVIDED IN NATIONAL’S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, NATIONAL ASSUMES NO

LIABILITY WHATSOEVER, AND NATIONAL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY RELATING TO THE SALE

AND/OR USE OF NATIONAL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR

PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY

RIGHT.

LIFE SUPPORT POLICY

NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR

SYSTEMS WITHOUT THE EXPRESS PRIOR WRITTEN APPROVAL OF THE CHIEF EXECUTIVE OFFICER AND GENERAL

COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:

Life support devices or systems are devices which (a) are intended for surgical implant into the body, or (b) support or sustain life and

whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected

to result in a significant injury to the user. A critical component is any component in a life support device or system whose failure to perform

can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness.

National Semiconductor and the National Semiconductor logo are registered trademarks of National Semiconductor Corporation. All other

brand or product names may be trademarks or registered trademarks of their respective holders.

For the most current product information visit us at www.national.com

National Semiconductor

Americas Customer

Support Center

National Semiconductor Europe

Customer Support Center

Fax: +49 (0) 180-530-85-86

National Semiconductor Asia

Pacific Customer Support Center

Email: ap.support@nsc.com

National Semiconductor Japan

Customer Support Center

Fax: 81-3-5639-7507

Email:

new.feedback@nsc.com

Tel: 1-800-272-9959

Email: europe.support@nsc.com

Deutsch Tel: +49 (0) 69 9508 6208

English Tel: +49 (0) 870 24 0 2171

Français Tel: +33 (0) 1 41 91 8790

Email: jpn.feedback@nsc.com

Tel: 81-3-5639-7560

www.national.com


型号：	LM96194CISQ
厂家：	National Semiconductor
描述：	TruTherm⑩ Hardware Monitor with PI Fan Control for Workstation Management TruTherm⑩硬件监控与PI风扇控制工作站管理风扇监控
文件：	总24页 (文件大小：531K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LM96194CISQ [NSC]

相关型号：

LM96194CISQ/NOPB

LM96194CISQX

LM96194CISQX/NOPB

LM9619IEA

LM9627

LM9627CCEA

LM9627CCEA-2

LM9627CCEA-2

LM9627CEA

LM9628

LM9628EVAL-KIT

LM9628IEA