LM9619IEA [ONSEMI]
LM9619IEA;
ONSEMI 
IMAGE SENSOR SOLUTIONS
DEVICE
PERFORMANCE
SPECIFICATION
KODAK KAC-9619
CMOS IMAGE SENSOR
648 (H) X 488 (V)
High Dynamic Range 30 fps
Monochrome CIS
September 2004
Revision 0.4
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Revision 0.4 Sept 04
Preliminary
IMAGE SENSOR SOLUTIONS
LM9619 Monochrome High Dynamic Range CMOS Image Sensor VGA 30 FPS
General Description
Applications
The LM9619 is a high performance, low power, 1/3” VGA CMOS
Active Pixel Sensor capable of capturing grey-scale digital still or
motion images and converting them to a digital data stream.
• Security Cameras
• Machine Vision
• Automotive
• Biometrics
In addition to the active pixel array, an on-chip 12 bit A/D conver-
tor, fixed pattern noise elimination circuits, a video gain and sep-
arate color gain are provided. Furthermore, an integrated
programmable smart timing and control circuit allows the user
maximum flexibility in adjusting integration time, active window
size, gain and frame rate. Various control, timing and power
modes are also provided.
• IR imaging
• Barcode Scanners
Key Specifications
Array Format
Total: 664H x 504V
Active: 648H x 488V
The excellent linear dynamic range of the sensor can be
Effective Image Area
Total: 4.98mm x 3.78 mm
Active: 4.86 mm x 3.66 mm
1/3“
7.5µm x 7.5µm
8,10 & 12 Bit Digital
30 frames per second
extended to above 100dB by programming
a non linear
response curve that matches the response of the human eye.
Optical Format
Pixel Size
Video Outputs
Frame Rate
The LM9619 embeds special metal shields in order to screen the
sun effect when sun image is projected on the non sensitive area
of the sensor.
Dynamic Range
62dB in linear mode
Features
110dB in non linear mode
• Improved light shielding for non active area
• Video or snapshot operations
Electronic Shutter
Rolling reset
0.1%
1.5%
5 V/lux.s
27%
47%
48 CLCC
3.3 V +/-10%
168 mW
-40 to 85oC
FPN
PRNU
Sensitivity
Quantum Efficiency
Fill Factor
• Progressive scan and interlace read out modes.
• Programmable pixel clock, inter-frame and inter-line delays.
• Programmable partial or full frame integration
• Programmable gain and individual color gain
• Horizontal & vertical sub-sampling (2:1 & 4:2)
• Programmable digital video response curve
• Windowing
Package
• External snapshot trigger & event synchronisation signals
• Auto black level compensation
Single Supply
Power Consumption
Operating Temp
• Light shielding feature
• Flexible digital video read-out supporting programmable:
-
-
polarity for synchronisation and pixel clock signals
leading edge adjustment for horizontal synchronization
• Programmable via 2 wire I2C compatible serial interface
• Power on reset & power down mode
System Block Diagram
Storage
LM9619
lens
12bit digital image
Digital Image
Processor
2
I C compatible
event trigger
snapshot
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IMAGE SENSOR SOLUTIONS
Overall Chip Block Diagram
oe
R
d[11:0]
12 Bit A/D
AMP
G
B
MUX
pclk
Row Address
Decoder
hsync
vsync
APS Array
POR
Horizontal
Timing
Vertical
Timing
Reset
Gen
Row Address
Gain
Gen
Control
sda
sclk
2
I C Compatible
Register Bank
Serial I/F
Power
Controller
Clock Gen
sadr
Master Timer
(sequencer)
Control
reset mclk
extsync
snapshot
pdwn
Figure 1. Chip Block Diagram
Connection Diagram
6
5
4
3
2
1
48 47 46 45 44 43
42
RSVD
sclk
7
pwl_ref
snapshot
resetb
41
40
39
38
37
36
35
34
33
32
31
8
atest_in
atest_out
offset
9
pdwn
vss_dig
vdd_dig
hsync
10
11
12
13
14
15
16
17
18
LM9619
vdd_ana1
vss_ana1
48 PIN LCC
vref_adc
vss_ana2
vsync
pclk
vdd_ana2
vss_od2
vdd_od2
mclk
d0
RSVD
19 20 21 22 23 24 25 26 27 28 29 30
Ordering Information
Description
NS Package
LM9619IEA
LM9619
A small PCB that houses the LM9619 sensor together with all necessary discrete components.
LM9619HEADBOARD
The evaluation kit is a complete software/hardware solution designed to give the system designer a
complete raw data evaluation toolset for the LM9619 sensor.
LM96XXEVAL-KIT
The 1/3” lens kit consists of four 1/3” M12 lenses and an M12 mount that can be attached to any
LM9619 headboard (see above).
LM96-1/2LENSKIT
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IMAGE SENSOR SOLUTIONS
Typical Application Circuit
System Control
Camera Control
Serial Control Bus
16
9
10
8
48
7
6
5
3.3V analog
3.3V analog
37
36
33
34
vdd_ana1
vss_ana1
vdd_ana2
vss_ana2
0.1µF
0.1
µF
3.3V digital
F
3.3V digital
47
46
31
32
vdd_od2
vss_od2
vdd_od1
vss_od1
0.1µF
0.1µ
3.3V digital
3.3V digital
44
45
12
11
vdd_od3
vss_od3
vdd_dig
vss_dig
0.1µF
0.1µF
3.3V analog
F
3
2
LM9619
1
vdd_pix
vrl
vsrvdd
0.1µ
1.0µF
3.3V analog
38
42
40
offset
1K1
RSVD
35
vref_adc
10K
atest_in
0.1µF
3.3V analog
56KΩ
18
43
RSVD
RSVD
41
pwl_ref
39
4
atest_out
RSVD
13 14 15
30 29 28 27 26 25 24 23 22 21 20 17
19
Digital Video Bus
Figure 2. Typical Application Diagram
Scan Read Out Direction
pin 1
(0,0)
(0,0)
digital
out
(0,0)
horizontal scan
CMOS Image Sensor
lens
Figure 3. Scan directions and position of origin in imaging system
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Pin Descriptions
Pin
Name
vsrvdd
vrl
I/O
Typ
P
Description
1
0
I
Charge pump output, connect to ground via a1.0µf capacitor.
Anti blooming pin. This pin is normally tied to ground.
3.3 volt supply for the pixel array.
2
A
3
vdd_pix
RSVD
I
P
4
This pin is reserved for future use, do not connect.
Digital input with pull down resistor. This pin is used to program different slave addresses
for the sensor in an I2C compatible system.
5
6
sadr
sda
I
D
D
I2C compatible serial interface data bus. The output stage of this pin has an open drain
driver.
IO
7
8
sclk
I
I
D
D
I2C compatible serial interface clock.
snapshot
Digital input with pull down resistor used to activate (trigger) a snapshot sequence.
Digital input with pull up resistor. When forced to a logic 0 the sensor is reset to its default
power up state. The resetb signal is internally synchronized to mclk which must be run-
ning for a reset to occur.
9
resetb
pdwn
I
I
D
D
Digital input with pull down resistor. When forced to a logic 1 the sensor is put into power
down mode.
10
11
12
vss_dig
vdd_dig
I
I
P
P
0 volt power supply for the digital circuits.
3.3 volt power supply for the digital circuits.
Digital Bidirectional. This is a dual mode pin. When the sensor’s digital video port is con-
figured to be a master, (the default), this pin is an output and is the horizontal synchroni-
zation pulse. When the sensor’s digital video port is configured to be a slave, this pin is
an input and is the row trigger.
13
14
hsync
vsync
IO
IO
D
D
Digital Bidirectional. This is a dual mode pin. When the sensor’s digital video port is con-
figured to be a master, (the default), this pin is an output and is the vertical synchroniza-
tion pulse. When the sensor’s digital video port is configured to be a slave, this pin is an
input and is the frame trigger.
15
16
pclk
IO
I
D
D
Digital output. The pixel clock.
mclk
Digital input. The sensor’s master clock input.
Digital output. Bit 0 of 11 of the digital video output bus. This output can be put into tri-
state mode.
17
18
19
d0
O
D
RSVD
oe
This pin is reserved for future use, do not connect.
Digital input with pull down resistor. When forced to a logic 1 the sensor’s digital video
port d[11:0], vsync & hsync will be tri-stated.
I
D
D
D
D
D
Digital output. Bit 1 of 11 of the digital video output bus. This output can be put into tri-
state mode.
20
21
22
23
d1
d2
d3
d4
O
O
O
O
Digital output. Bit 2 of 11 of the digital video output bus. This output can be put into tri-
state mode.
Digital output. Bit 3 of 11 of the digital video output bus. This output can be put into tri-
state mode.
Digital output. Bit 4 of 11 of the digital video output bus. This output can be put into tri-
state mode.
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Pin Descriptions (Continued)
Pin
Name
I/O
Typ
Description
Digital output. Bit 5 of 11 of the digital video output bus. This output can be put into tri-
state mode.
24
d5
O
D
Digital output. Bit 6 of 11 of the digital video output bus. This output can be put into tri-
state mode.
25
26
27
28
29
30
d6
O
O
O
O
O
O
D
D
D
D
D
D
Digital output. Bit 7 of 11 of the digital video output bus. This output can be put into tri-
state mode.
d7
Digital output. Bit 8 of 11 of the digital video output bus. This output can be put into tri-
state mode.
d8
Digital output. Bit 9 of 11 of the digital video output bus. This output can be put into tri-
state mode.
d9
Digital output. Bit 10 of 11 of the digital video output bus. This output can be put into tri-
state mode.
d10
d11
Digital output. Bit 11 of 11 of the digital video output bus. This output can be put into tri-
state mode.
31
32
33
34
35
36
37
vdd_od2
vss_od2
I
I
I
I
I
I
I
P
P
P
P
A
P
P
3.3 volt supply for the digital IO buffers.
0 volt supply for the digital IO buffers
vdd_ana2
vss_ana2
vref_adc
vss_ana1
vdd_ana1
3.3 volt supply for analog circuits.
0 volt supply for analog circuits.
A/D reference resistor ladder high voltage. Internal resistor to gnd 530Ω resistor.
0 volt supply for analog circuits.
3.3 volt supply for analog circuits.
Analog input used to manually adjust the offset of the sensor. This pin should be tied to
ground.
38
offset
I
A
39
40
atest_out
atest_in
A
A
O
I
Analog test output for factory use only. This pin should not be connected.
Analog test input for factory use only. This pin should be tied to ground.
Analog input used to control the position of the piecewise linear breakpoints. This pin
should be connected to vdd_ana1 via a 56KΩ resistor.
41
pwl_ref
A
I
42
43
44
45
46
47
RSVD
This pin is reserved for future use, do not connect.
This pin is reserved for future use, do not connect.
3.3 volt supply for the sensor.
RSVD
vdd_od3
vss_od3
vss_od1
vdd_od1
I
I
I
I
P
P
P
P
0 volt supply for the sensor.
0 volt supply for the digital IO buffers
3.3 volt supply for the digital IO buffers.
Digital output. The external event synchronization signal is used to synchronize external
events in snapshot mode.
48
extsync
O
D
Legend: (I=Input), (O=Output), (IO=Bi-directional), (P=Power), (D=Digital), (A=Analog).
adc_vref
800Ω
Figure 4. Equivalent Circuits For adc_ref pin
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Absolute Maximum Ratings (Notes 1 & 2)
Operating Ratings (Notes 1 & 2)
Any Positive Supply Voltage
6.5V
Operating Temperature Range (Note 10) -40°C≤T≤+85°C
Voltage On Any Input or Output Pin
Input Current at any pin (Note 3)
ESD Susceptibility (Note 5)
Human Body Model
-0.5V to 6.5V
±25mA
All VDD Supply Voltages
Voltage on vref_adc pin
+3.0V to +3.6V
+1.1V
2000V
200V
±50mA
2.5W
Machine Model
Package Input Current (Note 3)
Package Power Dissipation @ TA(Note 4)
Soldering Temperature Infrared,
10 seconds (Note 6)
220°C
-40°C to 125°C
Storage Temperature
DC and logic level specifications
The following specifications apply for all VDD pins= +3.3V. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25oC.
Min
Typical
note 8
Max
Units
Symbol
Parameter
Conditions
note 9
note 9
sclk, sda, sadr, Digital Input/Output Characteristics (Note: sadr has a pulldown resistor)
VIH
VIL
Logical “1” Input Voltage
Logical “0” Input Voltage
Logical “0” Output Voltage
Hysteresis (SCLK pin only)
0.7*vdd_od
-0.5
vdd_od+0.5
0.3*vdd_od
0.5
V
V
V
V
VOL
Vhys
vdd_od = +3.15V, Iout=3.0mA
vdd_od = +3.15V
0.05*vdd_od
Input Leakage Current (without
pulldown resistor)
Ileak
Vin=vss_od
-1
µA
mclk, snapshot, pdwn, reset, hsync, vsync, oe Digital Input Characteristics (Note: snapshot, pdwn, oe have pulldown re-
sistors and reset has a pullup resistor)
VIH
VIL
Logical “1” Input Voltage
Logical “0” Input Voltage
vdd_dig = +3.6V
vdd_dig = +3.15V
2.0
V
V
0.8
Logical “1” Input Current (without
pulldown resistor)
IIH
IIL
VIH = vdd_dig
VIL = vss_dig
0.1
-1
µA
µA
Logical “0” Input Current (without
pullup resistor)
d0 - d11, pclk, hsync, vsync, extsync, Digital Output Characteristics
VOH
VOL
Logical “1” Output Voltage
Logical “0” Output Voltage
vdd_od=3.15V, Iout=-1.6mA
vdd_od=3.15V, Iout =-1.6mA
2.2
V
V
0.5
VOUT = vss_od
VOUT = vdd_od
-0.1
0.1
µA
µA
IOZ
IOS
TRI-STATE Output Current
Output Short Circuit Current
+/-17
mA
Power Supply Characteristics
Power down mode, no clock.
Operational mode in dark
0.45
35.0
0.71
43.7
mA
mA
IA
ID
Analog Supply Current
Digital Supply Current
Power down mode, no clock.
Operational mode in dark
0.15
16.0
0.3
mA
mA
19.1
Power Dissipation Specifications
The following specifications apply for All VDD pins = +3.3V, mclk = 48MHz, Hclk = 12MHz, frame rate = 30Hz, vref = 1.1 volt. Bold-
face limits apply for TA = TMIN to TMAX: all other limits TA = 25oC.
Min
Typical
note 8
Max
Units
Symbol
Parameter
Conditions
note 9
note 9
Pdwn
PWR
Power Down
Average Power Dissipation
no clock running
in dark
1.98
168
mW
mW
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Video Amplifier Specifications
The following specifications apply for all VDD pins= +3.3V. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25oC
Min
Typical
note 8
Max
Units
Symbol
Parameter
Conditions
note 9
note 9
Vgain
Cgain
Video Amplifier Nominal Gain
Color Amplifiers Nominal Gain
64 linear steps
128 linear steps
0-15
0-14
dB
dB
0
AC Electrical Characteristics
The following specifications apply for All VDD pins = +3.3V. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25oC
Min
Typical
note 8
Max
Units
Symbol
Parameter
Conditions
note 9
note 9
Fmclk
Tch
Input Clock Frequency
Clock High Time
12
10
48
45
MHz
ns
@ CLKmax
Tcl
Clock Low Time
@ CLKmax
@ CLKmax
10
45
ns
Clock Duty Cycle
45/55
55/45
min/max
ns
Trc, Tfc
Fhclk
Clock Input Rise and Fall Time
Internal System Clock Fre-
quency
1.0
14.0
30
MHz
Treset
Reset pulse width
Frame Rate
1.0
1
µs
FRMrate
fps
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate con-
ditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications
and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions
listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions.
Note 2: All voltages are measured with respect to VSS = vss_ana = vss_od = vss_dig = 0V, unless otherwise specified.
Note 3: When the voltage at any pin exceeds the power supplies (VIN < VSS or VIN > VDD), the current at that pin should be lim-
ited to 25mA. The 50mA maximum package input current rating limits the number of pins that can safely exceed the power
supplies with an input current of 25mA.
Note 4: The absolute maximum junction temperature (TJmax) for this device is 125oC. The maximum allowable power dissipation
is dictated by TJmax, the junction-to-ambient thermal resistance (ΘJA), and the ambient temperature (TA), and can be cal-
culated using the formula PDMAX = (TJmax - TA)/ΘJA. In the 48-pin LCC, ΘJA is 38.5oC/W, so PDMAX = 2.5W at 25oC
and 1.94W at the maximum operating ambient temperature of 50oC. Note that the power dissipation of this device under
normal operation will be well under the PDMAX of the package.
Note 5: Human body model is 100pF capacitor discharged through a 1.5kΩ resistor. Machine model is 220pF discharged through
ZERO Ohms.
Note 6: See AN450, “Surface Mounting Methods and Their Effect on Product Reliability”, or the section entitled “Surface Mount”
found in any post 1986 National Semiconductor Linear Data Book, for other methods of soldering surface mount devices.
Note 7: The analog inputs are protected as shown below. Input voltage magnitude up to 500mV beyond the supply rails will not
damage this device. However, input errors will be generated If the input goes above AV+ and below AGND.
VDD
IOP
Internal Circuits
Pad
VSS
Note 8: Typical figures are at TJ = 25oC, and represent most likely parametric norms.
Note 9: Test limits are guaranteed to AOQL (Average Outgoing Quality Level).
Note 10: The dew point temperature (the temperature below which there is a possibility of moisture condensation forming inside the
package) of the package is rated at -20oC. Suitable precautions should be taken to avoid dew formation when operating the
sensor between -40oC and -200C.
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CMOS Active Pixel Array Specifications
Parameter
Value
Units
Number of pixels (row, column)
664 x 504
648 x 488
Total
pixels
pixels
Active
Array size (x,y Dimensions)
4.98 x 3.78
4.86 x 3.66
Total
mm
mm
Active
Pixel Pitch
7.5
47
µm
Fill Factor without micro-lens
%
Image Sensor Specifications
The following specifications apply for All VDD pins = +3.3V, TA = 25oC, Illumination Color Temperature = 2500oK, IR cutoff filter at
700nm, mclk = 48MHz, Hclk = 12MHz, frame rate = 30Hz, vref = 1.1 volt, video gain 0dB.
Min
Typical
note 8
Max
Units
Parameter
Description
note 9
note 9
Optical Sensitivity1 ,2 Measured at the input of the A/D
The pixel output signal due to dark cur-
4.6
Volt/lux.s
LSBs/s
Dark Signal
130
rent.
The RMS temporal noise of the pixel out-
put signal in the dark averaged over all
pixels in the array.
Read Noise2
Dynamic Range2,3
FPN
4
LSBs
dB
The ratio of the saturation pixel output
signal and the read noise expressed in
dB.
62
0.1
0.7
Fixed Pattern Noise: the RMS spatial
noise in the dark excluding the effect of
read noise.
5.4
%
Photo Response Non Uniformity: the
RMS variation of pixel sensitivities as a
percentage of the average optical sensi-
tivity.
PRNU
%
4096
------------
1
The optical sensitivity at the A/D output, in units of LSBs/lux.s, can be calculated using:
⋅ Optical Sensitivity
vref
2.
3.
For effect of clock frequency on Sensitivity, Read Noise and Dynamic range see LM9628 Application note 1.
For effect of sensor operation in piecewise linear mode on Dynamic range see LM9628 Application note 2.
Blemish Specifications
Due to random process deviations, not all pixels in an image sensor array will react in the same way to a given light condition. These
variations are known as blemishes.
Eastman Koak tests the LM9619 CMOS image sensor under both dark and illuminated conditions. These two tests are referred to as
“Dark Tests” and “Standard Light Tests” respectively.
For full documentation of the LM9619 blemish specification and test conditions please refer to the “LM9619 Blemish Specification”
document.
Light Shielding Specifications
The light shielding spec is with respect to Eastman Kodak’s KAC-9618 sensor. Due to limitations in the KAC-9618 design an addi-
tional metal layer has been deployed in order to avoid, as much as possible, any light to hit the non sensitive area of the sensor; this
lead to a dramatic reduction of the artifacts generated when strong light (typically sun) hits these parts. Since the effective light inten-
sity on the silicon, depends strongly form the optic used in the application, is not possible to quantify a limit for this irradiation, but
some real application test has been made to evaluate the improvements; to get these information please refer to appnote
AN01_LM9619_sun_effect1.0.pdf.
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Sensor Response Curves
700
600
500
400
300
200
100
0
400
500
600
700
800
900
1000
WaveLength [nm]
Figure 5. Spectral Response Curve
dark signal
✧
100
10
1
✧
✧
✧
✧
✧
DSNU
✧
✧
✧
✧
✧
✧
✧
20
30
40
50
60
70
80
Temperature [oC]
notes:
1) The dark signal and DSNU both increase linearly with integration time. The results in the graph were
measured at 33 ms integration time.
2) At any temperature, the total spatial noise in the dark can be found by quadratically adding the offset
FPN from the 'Image Sensor Specifications' table and the DSNU from this graph.
Figure 6. Dark signal and Dark Signal Non-Uniformity @ 30 FPS versus Temperature
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Functional Description
0-14dB
R
1.0 OVERVIEW
0-15dB
0-14dB
G
0-14dB
B
Video
12 Bit A/D
1.1
Light Capture and Conversion
MUX
AMP
The LM9619 contains a CMOS active pixel array consisting of
488 rows by 648 columns. This active region is surrounded by 8
columns and 8 rows of optically shielded (black) pixels as shown
in Figure.
Analog pixel values
Digital pixel data
Figure 9: Analog Signals In, Digital Data Out.
8 columns, 8 rows
640 columns, 480 rows
mono-chrome active pixels
black pixels
The digital pixel data is further processed to:
• remove defects due to bad pixels,
• compensate black level, before being framed and presented
on the digital output port. (see Figure 10).
do[11:0]
pclk
hsync
vsync
8 columns, 8 rows
black pixels
Figure 10. Digital Pixel Processing.
1.2
Program and Control Interfaces
Figure 7: CMOS APS region of the LM9619
The programming, control and status monitoring of the LM9619
is achieved through a two wire I2C compatible serial bus. In
addition, a slave address pin is provided (see Figure 11).
At the beginning of a given integration time the on-board timing
and control circuit will reset every pixel in the array one row at a
time as shown in Figure 7
sda
Note that all pixels in the same row are simultaneously reset, but
not all pixels in the array
2
I C Compatible
Register Bank
Serial I/F
sclk
a
b
c
d
e
f
g
h
i
j
k l m n o p q r
0
1
sadr
2
3
4
5
6
7
8
Figure 11. Control Interface to the LM9619.
9
10
11
Additional control and status pins: snapshot and external event
synchronization are provided allowing the latency of the serial
control port to be bypassed during single frame capture. An
interrupt request pin is also available allowing complex snapshot
operations to be controlled via an external micro-processor (see
Figure 12).
12
13
14
15
Analog Data Out
CDS/Shift Register
Figure 8. Sensor Addressing Scheme
extsyn
Timing
snapshot
Generator
At the end of the integration time, the timing and control circuit
will address each row and simultaneously transfer the integrated
value of the pixel to a correlated double sampling circuit and
then to a shift register as shown in Figure 8.
Figure 12. Snapshot & External Event Trigger Signals
Once the correlated double sampled data has been loaded into
the shift register, the timing and control circuit will shift them out
one pixel at a time starting with column “a”.
The pixel data is then fed into an analog video amplifier, where a
user programmed gain is applied .
After gain adjustment the analog value of each pixel is con-
verted to 12 bit digital data as shown in Figure 9.
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Functional Description (continued)
2.2
Programming the scan window (mode b)
2.0 WINDOWING
To programme the scan window in mode b, bit 0 of the Scan
Window LSB Register (SROWLSB). In this mode the binary
value of scan window start and end row addresses are given by
The integrated timing and control circuit allows any size window
in any position within the active region of the array to be read out
with a 1x1 pixel resolution. The window read out is called the
“Display Window”.
scan row start address (bin) = [SwStartRow, SwStartRowLsb]
scan row end address (bin) = [SwEndRow, SwEndRowLsb]
A “Scan Window” must be defined first, by programing the start
and end row addresses as shown in Figure 13. Four coordinates
(start row address, start column address, end row address &
end column address) are programmed to define the size and
location of the “Display Window” to be read out (see Figure 13).
Where:
SwStartRow
is the contents of the Scan Window start row
register (SROWS)
SwEndRow
display col
display col
scan row
end address
start address
start address
is the contents of the Scan Window end row reg-
ister (SROWE)
SwStartRowLsb
display row
start address
is the contents of bit 7 of the Scan Window Row
LSB register (SROWLSB)
SwEndRowLsb
Display Window
is the contents of bit 6 of the Scan Window Row
display row
end address
Scan Window
LSB register (SROWLSB)
2.3
Updating the Scan Window
Active Pixel Array
scan row
After the “Scan Window” coordinates have been programmed,
the UpdateSettings bit in the UPDATE register should be set.
The timing and control circuit will set the new “Scan Window” at
beginning of the next frame and reset the UpdateSettings bit in
the UPDATE register.
end address
Figure 13. Windowing
Notes:
Note a: The “Display Window” must always be defined within
the “Scan Window”.
2.4
Programming the Display Window
Note b: By default the “Display Window” is the complete array.
Note c: The end column address of the “Display Window”
cannot be smaller than 3F hex (63 Decimal).
Five register (DROWS, DROWE, DCOLS, DCOLE and DWLSB)
are provided to program the display window as described in the
register section of this datasheet.
Note d: New “Scan Window” coordinates only take effect at
the beginning of the first frame after the UpdateSet-
tings bit is set in the UPDATE register.
2.1
Programming the scan window (mode a, default)
Two registers (SROWS & SROWE) are provided to program the
size of the scan window. The start and end row address of the
scan window is given by:
scan row start address = (2* SwStartRow) + SwLsb
scan row end address = (2* SwEndRow) + 1 + SwLsb
Where:
SwStartRow
is the contents of the Scan Window start row
register (SROWS)
SwEndROW
is the contents of the Scan Window end row reg-
ister (SROWE)
SwLsb
is bit 6 of the Display Window LSB register
(DWLSB)
This mode is provided for backward compatibility with the
LM9627 and LM9617 CMOS image sensors.
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Functional Description (continued)
3.2
Interlaced Readout Mode
3.0 READ OUT MODES
In interlaced readout mode, pixels are read out in two fields, an
Odd Field followed by an Even Field.
3.1
Progressive Scan Readout Mode
The Odd Field, consisting of all odd rows contained within the
display window, is read out first. Each pixel in the “Odd Field” is
consecutively read out, one pixel at a time, starting with the top
left most pixel.
In progressive scan readout mode, every pixel in every row in
the display window is consecutively read out, one pixel at a time,
starting with the left most pixel in the top most row. Hence, for
the example shown in Figure 14, the read out order will be
a0,b0,...,r0 then a1,b1,...,r1 and so on until pixel r20 is read out.
The Even Field, consisting of all even rows contained within the
display window, is then read out. Each pixel in the “Even Field”
is consecutively read out, one pixel at a time, starting with the
top left most pixel.
Column/Horizontal
a b c d e f g h i j k l m n o p q r
0
1
Notes:
2
3
Note a: When using a monochrome sensor in interlace mode,
the InterlaceMode bit in the MCFG1 register should
be set to a logic one.
Note b: A Scan Window with an odd number of rows,must be
defined when using interlace readout mode.
4
5
6
7
8
9
Figure 15 shows a “Scan Window” of 21 rows and a “Display
Window” of 21 rows and 18 columns. This is broken up into two
fields:
10
11
12
13
• The odd field is read out first. The odd field will consist of pix-
els a0,b0,...,r0; a1,b1,...,r1; ... ; a17,b17,...r17 as shown in fig-
ure 15.
• The even field is then read out. The even field will consist of
pixels a2,b2,...,r2 ; a3,b3,...,r3 ; ... ; a19,b19,...,r19 as shown
in figure 15.
14
15
16
17
18
19
20
Column/Horizontal
Figure 14: Progressive Scan Read Out Mode
a b c d e f g h i j k l m n o p q r
0
2
4
6
8
10
12
14
16
18
20
Odd Field
Column/Horizontal
a b c d e f g h i j k l m n o p q r
1
3
5
7
9
11
13
15
17
19
Even Field
Figure 15. Interlace Read Out
Hence, for the example shown in Figure 15, the display window
is broken up into two fields, as shown in Figure . Pixels
a0,b0,...,r0 followed by a2,b2,...,r2 and so on until pixels
a20,b20,...r20 in the even field are read out first. The even field
read out is followed by pixels in the odd field, a1,b1,...,r1 then
a3,b3,...,r3 until pixels a19,b19,...,r19.
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4.2
4:2 Sub-Sampling
Functional Description (continued)
The timing and control circuit can be programmed to sub-
sample pixels in the display window vertically, horizontally or
both, with an aspect ratio of 4:2 as illustrated in figure 17.
Column/Horizontal
4.0 SUB-SAMPLING MODES
4.1
2:1 Sub-Sampling
a b c d e f g h
i j k l m n o p q r
The timing and control circuit can be programmed to sub-sam-
ple pixels in the display window vertically, horizontally or both,
with an aspect ratio of 2:1 as illustrated in figure 16.
0
1
2
3
4
5
6
7
8
9
Column/Horizontal
q
r
a b c d e f g h
i
j
k l m n o p
0
1
2
3
4
5
6
7
8
9
a) Horizontal Sub-sampling
Column/Horizontal
a b c d e f g h
i j k l m n o p q r
0
1
2
3
4
5
6
7
8
9
a) Horizontal Sub-Sampling
Column/Horizontal
a b c d e f g h
i j k l m n o p q r
0
1
2
3
4
5
6
7
8
b) Vertical Sub-sampling
Column/Horizontal
a b c d e f g h
i j k l m n o p q r
0
1
2
3
4
5
6
7
8
9
9
b) Vertical Sub-Sampling
Column/Horizontal
a b c d e f g h
i j k l l n o p q r
0
1
2
3
c) Horizontal & Vertical Sub-sampling
4
5
6
7
8
9
Not Read Out
Read Out
Figure 17. 4:2 Horizontal and Vertical Sub-Sampling
Notes:
c) Horizontal & Vertical Sub-Sampling
Not Read Out
Note a: To program the sensor in 4:2 Sub-sampling the HSub-
SamEn bit in the MCFG1 register should to be set to a
logic zero.
Note b: Setting the HSubSamEn bit in the MCFG1 to a logic
one will switch on the horizontal sub-sampling, while
setting the VSubSamEn bit in the MCFG1 register will
switch on the vertical sub-sampling.
Note c: Sub-sampling cannot be used with interlace readout
mode.
Note d: When using horizontal sub-sampling Pclk is divided
by 2. The active time of Hsync is the same in sub-
sampled and non sub-sampled mode. Horizontal
sub-sampling does not increase frame rate.
Read Out
Figure 16. 2:1 Horizontal and Vertical Sub-Sampling
Notes:
Note a: To program the sensor in 2:1 Sub-sampling the HSub-
SamEn bit in the MCFG1 register should to be set to a
logic one.
Note b: Setting the HSubSamEn bit in the MCFG1 to a logic
one will switch on the horizontal sub-sampling, while
setting the VSubSamEn bit in the MCFG1 register will
switch on the vertical sub-sampling.
Note c: Sub-sampling cannot be used with interlace readout
mode.
Note d: When using horizontal sub-sampling Pclk is divided
by 2. The active time of Hsync is the same in sub-
sampled and non sub-sampled mode. Horizontal
sub-sampling does not increase frame rate.
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Functional Description (continued)
5.2
Analog Gain and Color Gain
5.0 FRAME RATE & EXPOSURE CONTROL
There are two analog gain stages built into the sensor before the
A/D allowing the video and separate color gains to be pro-
grammed.
5.1
Introduction
A frame is defined as the time it takes to reset every pixel in the
array, integrate the incident light, convert it to digital data and
present it on the digital video port. This is not a concurrent pro-
cess and is characterized in a series of events each needing a
certain amount of time as shown in Figure 18.
The video gain is given by:
Vgain = 1+ 0.07032 * VidGain
Where:
Start
VidGain is the six bit video gain step programmed in the
VGAIN register
Row address = 0
The second stage of programable gain consists of three parallel
channels that allows indvidual RGB gains to be set. For mono-
chrome applications all pixels should be routed to the green
channel (Ggain) by setting the GainMode bit of the MCFG0 regis-
Row delay time
ter to a logic 1.
The red gain is given by:
Transfer all pixels to CDS
Reset all pixels in row
R
gain = 1 + 0.03125 * RGain
Where:
RGain
is the six bit video gain step programmed in the
RGAIN register
Shift all pixels out of row
Row address + 1
The green gain is given by:
G
gain = 1 + 0.03125 * GGain
Yes
No
Last row?
Where:
GGain
is the six bit video gain step programmed in the
GGAIN register
Figure 18. Frame Readout Flow Diagram
The following factors effect frame rate, the:
The blue gain is given by:
Bgain = 1 + 0.03125 * BGain
• frequency of Hclk
• size of the “Scan Window”
• sub sampling mode
• programmed row delay
• programmed frame delay.
Where:
BGain
is the six bit video gain step programmed in the
BGAIN register
The following factors effect exposure but not frame rate
• analog gain
• integration time
• modification of the sensor’s linear response.
This section describes how to program the frame rate and expo-
sure time.
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Functional Description (continued)
5.3
Clock Generation
5.4
Full Frame Integration
The LM9619 contains a clock generation module (figure 19) that
will create three clocks as follows:
Full frame integration is when each pixel in the array integrates
light incident on it for the duration of a frame (see Figure 20).
Hclk,
the horizontal clock. This is an internal system
clock and can be programmed to be the input
clock (mclk) or mclk divided by any number
between 1 and 31. All exposure times are in
multiples of this clock.
The number of Hclk clock cycles required to process & shift out
one row of pixels is given by:
RNHclk = Ropcycle + Rdelay
Where:
To set the frequency of this clock the HclkGen
bits in the VCLKGEN register should be pro-
gramed.For the new frequency to take effect the
UpdateSettings bit in the UPDATE register
should be set. The timing and control circuit will
set the new Hclk frequency at beginning of the
next frame and reset the UpdateSettings bit in
the UPDATE register.
Ropcycle is a fixed integer value of 780 representing the
Row Operation Cycle Time in multiples of Hclk
clock cycles. It is the time required to carry out
all fixed row operations outlined in Figure 18.
Rdelay
a programmable value between 0 & 2047 repre-
senting the Row Delay Time in multiples of Hclk.
This parameter allows the Row Operation Cycle
time to be extended. (See the Row Delay High
and Row Delay Low registers).
pclk
the pixel clock. This is the external pixel clock
that appears at the digital video port. pclk is
always equal to Hclk except when the sensor is
programmed to work sub-sampling mode in
which case pclk will be equal to Hclk divided by
2. This clock cannot be programed.
New Rdelay values only take effect at the begin-
ning of the first frame after the UpdateSettings
bit is set in the UPDATE register.
The number of rows in a scan window is given by:
Aclk
the array clock. This is an internal clock used by
the pixel array.Its frequency does not effect the
exposure time.
SWNrows = (RADend - RADstart) + 1
Where:
To set the frequency of this clock the AclkGen
bits in the VCLKGEN register should be pro-
gramed. For the new frequency to take effect the
UpdateSettings bit in the UPDATE register
should be set. The timing and control circuit will
set the new Hclk frequency at beginning of the
next frame and reset the UpdateSettings bit in
the UPDATE register.
RADend is the end row address of the defined scan win-
dow. (See section 2.0)
RADstart is the start row address of the defined scan win-
dow. (Scan section 2.0).
The number of Hclk clocks required to process a full frame is
given by:
FNHclk = [(Mfactor * SWNrows) + Fdelay] * RNHclk
HclkGen
Hclk
÷
Where:
Mfactor
is a Mode Factor which must be applied. It is
dependent on the selected mode of operation as
shown in the table below:
mclk
ArrayMode
AclkGen
pclk
÷
÷
Progressive Scan
1
Aclk
Vertical Sub-sampling or
Interlace
0.5
Figure 19. Clock Generation Module
SWNrows is the Number of Rows in Selected Scan Win-
dow.
Fdelay
a programmable value between 0 & 4096 repre-
senting the Inter Frame Delay in multiples of
RNHclk. This parameter allows the frame time to
be extended. (See the Frame Delay High and
Frame Delay Low registers).
New Fdelay values only take effect at the begin-
ning of the first frame after the UpdateSettings
bit is set in the UPDATE register.
The frame rate is given by:
Hclk
Frame Rate =
FNHclk
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Functional Description (continued)
Full Integration Time
Partial Integration
Time
Frame
Delay
Frame
Row 2
Row n
Row n
Row 0
Row 0
Row 1
Row x
Row x+
∆
Delay
Programmable Row Delay Row CDS, Reset Row x & Shift
Full Frame integration
Programmable Row Delay
Partial Frame Integration
Row CDS, Reset Row x+ & Shift
∆
Frame N
Figure 20. Partial and Full Frame Integration
5.6 Modification of Linear Response Curve
5.5
Partial Frame Integration
In some cases it is desirable to reduce the time during which the
pixels in the array are allowed to integrate incident light without
changing the frame rate.
The electro-optic transfer curve of the pixel array is linear. While
a linear response is satisfactory for capturing images containing
similar brightness levels, it is not always satisfactory for captur-
ing images with a large variation of brightness levels.
This is known as Partial Fame Integration and can be achieved
by resetting pixels in a given row ahead of the row being
selected for readout as shown in Figure 20. The number of Hclk
clocks required to process a partial frame is given by:
For a fixed integration time, pixels capturing bright areas of a
scene will saturate much faster than pixels capturing darker
regions. When there is a large variation in the light intensities
between the dark and light regions it is not possible to simulta-
neously capture the detail in both regions. One would have to be
sacrificed.
FPHclk = RNHclk * Itime
Where:
Since the response of the human eye to light is non-linear, a
non- linear response such as that shown with the dashed curve
in figure 21 would allow the detail in both the light and dark
regions of the image to be captured and seen.
RNHclk
is the number of Hclk clock cycles required to
process & shift out one row of pixels.
is the number of rows ahead of the current row
Itime
The timing and control circuit built into the LM9619 allows the
linear response of the electro-optic response to be modified into
a piece-wise linear response (approximate gamma)
to be reset. (See the Integration Time High and
Low registers).
New Itime values only take effect at the beginning
of the first frame after the UpdateSettings bit is
set in the UPDATE register.
Saturation level
BP2
The Integration time is subject to the following limits:
Mode
Progressive Scan
Interlace
Limit
BP1
Itime <= SWNrows + Fdelay
Itime <= 2* (SWNrows + Fdelay
)
Sub-Sampled
Itime <= 0.5 * (SWNrows + Fdelay)
Illumination (Lux)
Figure 21. Linear & Non Linear Transfer Responses
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Functional Description (continued)
The LM9619 integrated timing and control circuit allows up to
two break points to be programmed such that a piecewise linear
response can be achieved as shown with the green lines in fig-
ure 21.
Saturation level
Level 2
Level 1
Slope 2
To operate the sensor in piecewise linear mode a 56k ohm resis-
tor must be connected to pin 41 and the following sequence
must be written after system reset:
Slope 1
Address (Hex)
Value
03Hex
set bit 3 to a logic 1
Maximum
illumination level
Slope 0
32Hex
30Hex
03Hex
40Hex
40Hex
Illumination (Lux)
Figure 22. Break Points Programming
The maximum illumination level (see figure 22) that can be
detected by the sensor is determined by the settings of the level
and slope registers.
set bit 3 to a logic 0
For a full explanation of how to use the LM9619 in piecewise lin-
ear mode refer to LM9618/28 Application note 2.
Two registers are provided to define each break point. The Level
register and the Sensitivity register.
The sensitivity of the first branch, (slope 0 in figure 22), is deter-
mined by the time settings and the image sensor characteristics.
The sensitivity (slope), of the other branches is determined by
the value programmed in the Sensitivity registers. The levels at
which the piecewise linear curve switches from one slope to
another are determined by the values programmed in the Level
registers.
5.7
Frame Rate Programming Guide
The table bellow can be used as a guide for programming the sensor. Note that it is assumed that the sensor is being driven with a
48MHz clock. All programmed values are given in decimal.
register
address
fps
vclkgen
rdelayh
rdelayl
16hex
[7:0]
0
fdelayh
fdelayl
18hex
[7:0]
9
srows
srowe
0Chex
[8:1]
251
dwlsb
05hex
15hex
17hex
0Bhex
12hex
[10:8]
[11:8]
0
[8:1]
0
30
4
4
4
4
4
5
5
4
4
5
5
6
6
0
0
0
3
0
0
0
0
2
0
0
0
3
50
50
50
50
50
50
50
50
50
50
50
50
50
15
0
2
40
0
251
7.5
3.75
25
0
6
12
0
251
12
6
12
0
251
172
0
0
0
0
251
12.5
6.25
3.125
5
1
226
188
14
0
251
0
5
0
251
156
255
0
14
4
0
251
23
0
251
4
10
14
13
15
12
0
251
3
0
14
0
251
2
200
241
248
126
0
251
1
0
251
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Functional Description (continued)
Capture
image
Data
Array reset,
programmable
read-out
snapshot
extsync
a) External Shutter Mode
Capture
image
Data
Array reset,
programmable
read-out
snapshot
extsync
b) Normal Mode
Data Read Out
Last Array Reset
Capture Image
SnapIT if extshutter
or
safer & reseRdelay
xfer & reset Rdelay
row 1
row 1
xfer & reset Rdelay
row n
xfer & reset Rdelay
xfer & reset Rdelay
row n
xfer & reset Rdelay
FrameDelay if normal
row 2
row 2
Row 1 Integration Time
Row 2 Integration Time
Row n Integration Time
Figure 23. Timing Diagram in the SNAP State
c) Snapshot Integration
When a TRIGGER is generated, the sensor will enter the SNAP
6.0 SNAPSHOT MODE
state as shown in figure 24.
6.1
Introduction
snapshot
SnapShotPol
Two dedicated pins are provided on the LM9619, snapshot, and
extsync allowing the sensor to be externally controlled to cap-
ture a single image.
Trigger
Gen
TRIGGER
Circuit
SnapShotMode
The snapshot input pin is used to trigger a snapshot, while the
extsync output pin is used to synchronize a light source, strobe
or mechanical shutter.
Figure 25. TRIGGER Generation Logic
The SNAP State in External Shutter Mode
6.3
6.2
Taking a Snapshot
To take a snapshot in external shutter mode, the ShutterMode
By default the sensor will operate in the VIDEO state (see figure
24). To take a snapshot, the snapshot mode must be enabled by
setting the SnapEnable bit in the SNAPSHOTMODE register to
a logic 1. This will cause the sensor to enter the FREEZE state
at the end of the current frame. In the FREEZE state the sensor
is idle.
bit of the SNAPSHOTMODE register must be set.
In this mode three consecutive operations will be carried out in
the SNAP state as follows (see figure 23a):
• Array Reset, during which the extsync pin is kept in-active
and the array is reset one row at a time. The number of times
the array is reset is programmable from 1-3 frames, (see the
SsFrames bits in the SNAPSHOTMODE register).
• Image Capture, the extsync pin will activate. The width of the
extsync signal can be programed from 1 to 2047 lines by pro-
gramming the integration time registers, ITMEH and ITIMEL.
• Array Read Out, the third and final operation reads the image
data out one row at a time.
The sensor will leave the FREEZE state and return to VIDEO
state when the snapshot mode is disabled (SnapEnable bit in
the SNAPSHOTMODE register set to a logic 0)
VIDEO
c:SnapEnable
c: SnapEnable
6.4
The SNAP State in Normal Mode (default)
To take a snapshot in normal mode, the ShutterMode bit of the
SNAPSHOTMODE register must be cleared. In this case the fol-
lowing consecutive operations will be carried out in the SNAP
state (see figure 24b):
FREEZE
c:TRIGGER
• Array Reset, during which the extsync pin is kept in-active
and the array is reset one row at a time. The number of times
the array is reset is programmable from 1-3 frames, (see the
SsFrames bits in the SNAPSHOTMODE register).
• Image Capture, the extsync pin will activate and remain
active for the duration of the capture time. The width of the
image capture can be extended by programming FDELAYH
and FDELAYL, which will increase integration time.
SNAP
Figure 24. Snapshot Mode
• Array Read Out, the image data is read out one row at a
time. During this operation the extsync pin remains active.
Alternatively, when an active snapshot signal is applied to the
snapshot input pin an internal trigger signal, TRIGGER, is gen-
erated as shown in figure 25. The trigger generation circuit will
create two types of TRIGGER as follows:
6.5
Return to the FREEZE State
When read out is complete the sensor will return to the FREEZE
state.
•
Pulse Trigger (SnapshotMode bit of the SNAPSHOTMODE
register is cleared). In this mode (the default) a single TRIG-
GER pulse will be generated.
Level Trigger (SnapshotMode bit of the SNAPSHOTMODE
register is set). In this mode the TRIGGER will remain high as
long as an active level is held on the snapshot pin.
6.6
Return to the VIDEO state
If the snapshot mode is disabled before readout is complete
(SnapEnable bit in the SNAPSHOTMODE register is set to a
logic 0), then at the end of readout the sensor will return to the
VIDEO state.
•
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8.0 POWER MANAGMENT
Functional Description (continued)
8.1
Power Up and Down
7.0 SIGNAL PROCESSING
The LM9619 is equipped with an on-board power management
system allowing the analog and digital circuitry to be switched
off (power down) and on (power up) at any time.
7.1
Bad Pixel Detection & Correction
The LM9619 has a built-in bad pixel detection and correction
block that operates on the fly. This block can be switched off by
the user.
The sensor can be put into power down mode by asserting a
logic one on the “pdwn” pin or by writing to the power down bit in
the main configuration register via the I2C compatible serial
interface.
7.2
Black Level Compensation
In addition to the programmable gain the LM9619 has a built in
black level compensation block as illustrated in Figure 26. This
block can be switched off.
To power up the sensor a logic zero can be asserted on the
“pdwn” pin or write to the power down bit in the main configura-
tion register via the I2C compatible serial interface.
Limit to 0-127
Black Level Estimation
Blank negative values
It will take a few milliseconds for all the circuits to power up. The
power management register contains a bit indicating when the
sensor is ready for use. During this time the sensor cannot be
used for capturing images. A status bit in the power manage-
ment register will indicate when the sensor is ready for use.
-
+
Bypass Mux
Figure 26. Digital Black Level Compensation.
9.0 OFFSET ADJUSTMENT
The level of the offset voltage determines the black level of the
image and has a direct impact on the image quality. Too high an
offset results in a white washed or hazy looking image, while too
low of an offset results in a dark image with low contrast even
though the light conditions are good.
The black level compensation block subtracts the estimated
average black level from the digital video output to compensate
for the temperature and integration time dependent dark signal
level of the pixels. Figure illustrates the black level estimation
circuit built into the LM9618
Integrator
For maximum image quality over a wide range of light conditions
it is necessary to set an appropriate offset voltage before using
the sensor to capture images.
+
-1
Y(z)
G
z
+
-
X(z)
The offset of each part can be adjusted by programming the off-
G
set control register (OCR) via the I2C compatible serial interface.
To calibrate the offset of a given part the following procedure
should be followed:
Figure 27. Black Level Estimation Circuit
After optional clipping (the Clip parameter in the BLCOEFF reg-
ister) of the MSB (used to remove the signal level of hot pixel
noise, the block estimates the average of the black signal level
by means of a low-pass filter that is applied to the series of black
pixel signals of the black pixels that are included in the scan win-
dow. This low-pass filter features a programmable time-con-
stant. The estimated average black level value is then
subtracted from the pixel data. During readout of active pixels,
the running average is frozen and not updated.
• Disable the black level compensation block by writing a logic
1 to bit 4 of the Main Configuration Register 0 (MCFG0:
address 02Hex).
• Set the sensor’s gain to 1 by writing 00Hex to registers
VGAIN, GGAIN, BGAIN, RGAIN.
• Calculate the average black level by reading a full frame and
calculating the average black level (BLaverage) of the first and
last 5 black pixels in the every row of the array.
• If the calculated average black level is greater than the target
black level then set the OffSign bit of the OCR register to a
logic 1, else set it to a logic 0.
The transfer function (in Z-domain) of the low-pass filter in the
black level estimation block is given by:
G
Y(z) = X(z)---------------------------
• The offset can be adjusted by running the following binary
search algorithm on the OffMag parameter in the OCR regis-
ter:
z – (1 – G)
where the gain G is programmable through α:
• For n=6 to 1 step -1
–(7 + α)
G = 2
• {
Set OffMag bit n in the OCR register to a logic one by
An increased value of α (the Alpha parameter in the BLCOEFF
register) increases the loop gain and therefore increases its
time-constant, resulting in a slower update of the integrator.
writing over the I2C compatible interface.
Read a full frame and calculate the average black level
(BLaverage) of the first and last 5 black pixels in the every
The actual black pixels used for the black level estimation is
dependent on the user defined scan window as illustrated in fig-
ure 30. In all cases only the inner 4 rows and columns are used.
row of the array
If (BLaverage < 100) then
Reset OffMag bit n in the OCR register to 0
Scan Window
else
Keep OffMag bit n set to one.
}
Display Window
• Enable the black level compensation block (if desired) by writ-
ing a logic 0 to bit 4 of the Main Configuration Register 0
(MCFG0: address 02Hex)
Black Pixels
Pixel Array
Black Pixels
used for black
level estimation
Figure 28. Black Pixels Used For Black Level Estimation
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Functional Description (continued)
10.4 Data Valid
10.0 SERIAL BUS
The master must ensure that data is stable during the logic 1
state of the sclk pin. All transitions on the sda pin can only occur
when the logic level on the sclk pin is “0” as shown in Figure 31.
The serial bus interface consists of the sda (serial data), sclk
(serial clock) and sadr (device address select) pins. The
LM9619 can operate only as a slave.
The sclk pin is an input, it only and controls the serial interface,
all other clock functions within LM9619 use the master clock pin,
mclk.
sda
sclk
data line
stable;
10.1 Start/Stop Conditions
data line
stable;
change
of data
allowed
The serial bus will recognize a logic 1 to logic 0 transition on the
sda pin while the sclk pin is at logic 1 as the start condition. A
logic 0 to logic 1 transition on the sda pin while the sclk pin is at
logic 1 is interrupted as the stop condition as shown in Figure
29.
data valid
data valid
Figure 31. Data Validity
10.5 Byte Format
Every byte consists of 8 bits. Each byte transferred on the bus
must be followed by an Acknowledge. The most significant bit of
the byte is should always be transmitted first. See Figure 32.
sda
sclk
10.6 Write Operation
S
P
A write operation is initiated by the master with a Start Condition
followed by the sensor’s Device Address and Write bit. When
the master receives an Acknowledge from the sensor it can
transmit 8 bit internal register address. The sensor will respond
with a second Acknowledge signaling the master to transmit 8
write data bits. A third Acknowledge is issued by the sensor
when the data has been successfully received.
start condition
stop condition
Figure 29. Start/Stop Conditions
10.2 Device Address
The serial bus Device Address of the LM9619 is set to 1010101
when sadr is tied low and 0110011 when sadr is tied high. The
value for sadr is set at power up.
The write operation is completed when the master asserts a
Stop Condition or a second Start Condition. See Figure 33.
10.3 Acknowledgment
10.7 Read Operation
The LM9619 will hold the value of the sda pin to a logic 0 during
the logic 1 state of the Acknowledge clock pulse on sclk as
shown in Figure 30.
A read operation is initiated by the master with a Start Condition
followed by the sensor’s Device Address and Write bit. When
the master receives an Acknowledge from the sensor it can
transmit the internal Register Address byte. The sensor will
respond with a second Acknowledge. The master must then
issue a new Start Condition followed by the sensor’s Device
Address and read bit. The sensor will respond with an Acknowl-
edged followed by the Read Data byte.
sda
MSB
from master
ACK
ACK
sda
from sensor
sclk
S
7
8
1
2
9
The read operation is completed when the master asserts a Not
Acknowledge followed by Stop Condition or a second Start Con-
dition. See Figure 34.
Clock pulse
for ACK
START
Figure 30. Acknowledge
MSB
sda
sclk
ack signal
from receiver
ack signal
from receiver
byte complete
7
9
1
8
2
8
9
1
2
ACK
ACK
clock line
held low
S
P
Figure 32. Serial Bus Byte Format
Register
Address
Data
Byte
Device
S
W
A
A
A
R
P
Address
bold sensor action
Figure 33. Serial Bus Write Operation
Device
Register
Address
Device
Data
Byte
_
S
W
A
A
S
A
P
A
Address
Address
bold sensor action
Figure 34. Serial Bus Read Operation
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Functional Description (continued)
This feature allows a programmable digital gain to be imple-
mented when connecting the sensor to 8 or 10 bit digital video
processing systems as illustrated in Figure 36. The unused bits
on the digital video bus can be optionally tri-stated.
11.0 DIGITAL VIDEO PORT
The captured image is placed onto a flexible 12-bit digital port as
shown in Figure 10. The digital video port consists of a program-
mable 12-bit digital Data Out Bus (d[11:0]) and three program-
mable synchronisation signals (hsync, vsync, pclk).
d11
d10
d9
d8
d7
d6
d5
d4
d3
d2
d1
d0
d9
d8
d7
d6
d5
d4
d3
d2
d1
d0
By default the synchronisation signals are configured to operate
in “master” mode. They can be programed to operate in “slave”
mode.
10 bit
Digital
Image
LM9619
Processor
The following sections are a detailed description of the timing
and programming modes of digital video port.
Pixel data is output on a 12-bit digital video bus. This bus can be
tri-stated by asserting the TriState bit in the VIDEOMODE1 reg-
ister.
a) LM9619 Connected to a 10 bit Digital Image Processors
11.1 Digital Video Data Out Bus (d[11:0])
A programmable matrix switch is provided to map the output of
the internal pixel framer to the pins of the digital video bus as
illustrated in Figure 35.
d11
d10
d9
d8
d7
d6
d5
d4
d3
d2
d1
d0
d7
d6
d5
d4
d3
d2
d1
d0
8 bit
Digital
Internal Pixel Framer Output Register
9
8
7
6
5
4
3
2
1
0
11 10
Image
LM9619
Processor
d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0
b) LM9619 Connected to a 8 bit Digital Image Processors
a) MSB Bit 11, Switch Mode (default)
Figure 36. Example of connection to 10/8 bit systems
Internal Pixel Framer Output Register
9
8
7
6
5
4
3
2
1
0
11 10
Synchronisation Signals in Master Mode
By default the sensor’s digital video port’s synchronisation sig-
nals are configured to operate in master mode. In master mode
the integrated timing and control block controls the flow of data
onto the 12-bit digital port, three synchronisation outputs are
provided:
pclk
hsync
vsync
is the pixel clock output pin.
is the horizontal synchronisation output signal.
is the vertical synchronisation output signal.
d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0
b) MSB Bit 10, Switch Mode
11.2 Pixel Clock Output Pin (pclk) (Master Mode)
The pixel clock output pin, pclk, is provided to act as a synchro-
nisation reference for the pixel data appearing at the digital
video out bus pins d[11:0]. This pin can be programmed to oper-
ate in two modes:
Internal Pixel Framer Output Register
9
8
7
6
5
4
3
2
1
0
11 10
• In free running mode the pixel clock output pin, pclk, is always
running with a fixed period. Pixel data appearing on the digital
video bus d[11:0] are synchronized to a specified active edge
of the clock as shown in Figure 37.
d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1
d0
pclk
d[11:0]
c) MSB bit 9, Switch Mode
Internal Pixel Framer Output Register
9
8
7
6
5
4
3
2
1
0
11 10
a) pclk active edge negative
pclk
d[11:0]
b) pclk active edge positive (default)
invalid pixel data
Figure 37. pclk in Free Running Mode
• In data ready mode, the pixel clock output pin (pclk) will pro-
duce a pulse with a specified level every time valid pixel data
appears on the digital video bus d[11:0] as shown in Figure
38.
d0
d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1
d) MSB bit 8, Switch Mode
Figure 35. Digital Video Bus Switching Modes
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Functional Description (continued)
,
11.4 Vertical/Horizontal Synchronisation Pin (vsync)
The vertical synchronisation output pin, vsync, is used as an
indicator for pixel data within a frame. The vsync output pin can
be programmed to operate in two modes as follows:
pclk
d[11:0]
a) pclk active edge negative
• Level mode should be used when the pixel clock, pclk, is pro-
grammed to operate in free running mode. In level mode the
vsync output pin will go to the specified level (high or low) at
the start of each frame and remain at that level until the last
pixel of that row in the frame is placed on d[11:0] as shown in
Figure 41. The hsync level is always synchronized to the
active edge of pclk.
pclk
d[11:0]
b) pclk active edge positive
invalid pixel data
Figure 38. pclk in Data Ready Mode
By default the pixel clock is a free running active low (pixel data
changes on the positive edge of the clock) with a period equal to
the internal hclk. The active edge of the clock can be pro-
grammed such that pixel data changes on the positive or nega-
tive edge of the clock.
pclk
d[11:0]
vsync
a) vsync programmed to be active high
pclk
Frame n+1
Frame n
11.3 Horizontal Synchronisation Output Pin (hsync)
The horizontal synchronisation output pin, hsync, is used as an
indicator for row data. The hsync output pin can be programmed
to operate in two modes as follows:
d[11:0]
vsync
Frame n+1
Frame n
• Level mode should be used when the pixel clock, pclk, is pro-
grammed to operate in free running mode. In level mode the
hsync output pin will go to the specified level (high or low) at
the start of each row and remain at that level until the last
pixel of that row is read out on d[11:0] as shown in Figure 39.
The hsync level is always synchronized to the active edge of
pclk.
b) vsync programmed to be active low
invalid pixel data
Figure 41. vsync in Level Mode
• Pulse mode should be used when the pixel clock, pclk, is pro-
grammed to operate in data ready mode. In pulse mode the
vsync output pin will produce a pulse at the end of each
frame. The width of the pulse will be a minimum of four hclk
cycles and its polarity can be programmed as shown in Figure
42. The vsync level is always synchronized to the active edge
of pclk.
pclk
d[11:0]
hsync
Row n+1
Row n
pclk
d[11:0]
a) hsync programmed to be active high (default)
pclk
d[11:0]
vsync
Frame n+1
a) vsync programmed to be active high
Frame n
hsync
Row n+1
Row n
pclk
d[11:0]
b) hsync programmed to be active low
Figure 39. hsync in Level Mode
Frame n
Frame n+
vsync
• Pulse mode should be used when the pixel clock, pclk, is pro-
grammed to operate in data ready mode. In pulse mode the
hsync output pin will produce a pulse at the end of each row.
The width of the pulse will be a minimum of four pclk cycles
and its polarity can be programmed as shown in Figure 40.
The hsync level is always synchronized to the active edge of
pclk
b) vsync programmed to be active low (default)
invalid pixel data
Figure 42. vsync in pulse mode
11.5 Odd/Even Mode
In odd/even mode the vsync signal is used to indicate when
pixel data from an odd and even field is being placed on the dig-
ital video bus d[11:0]. The polarity of vsync can still be pro-
grammed in this mode as shown in Figure 43
pclk
d[11:0]
hsync
Row n+1
Row n
pclk
d[11:0]
a) hsync programmed to be active high
pclk
d[11:0]
vsync
Even Field
Odd Field
a) vsync programmed to be active high (default)
Row n
Row n+1
hsync
pclk
d[11:0]
b) hsync programmed to be active low
Figure 40. hsync in Pulse Mode
vsync
Even Field
Odd Field
By default the first pixel data at the beginning of each row is
placed on the digital video bus as soon as hsync is activated. It
is possible to program up to 15 dummy pixels to be readout at
the beginning of each row before the real pixel data is readout.
This feature is supported for both level and pulse mode.
b) vsync programmed to be active low
invalid pixel data
Figure 43. vsync in odd/even Mode
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Functional Description (continued)
pclk
vsync
hsync
d[11:0]
c0 c1 c2 c3 c4 c5 c6 c7 c8 c9
c0 c1 c2 c3 c4 c5 c6 c7 c8 c9
c0 c1 c2
c3 c4 c5 c6 c7 c8 c9
c0 c1 c2
c3 c4 c5 c6 c7 c8 c9
row 2
row1
row 1
row 2
frame 1
frame 2
Programmable hsync to 1st valid pixel delay
Programmable inter-frame delay
Programmable row delay
Figure 44. Example of Digital Video Port Timing in Progressive Scan Mode
pclk
vsync
hsync
d[11:0]
c0 c1 c2 c3 c4 c5 c6 c7 c8 c9
c0 c1 c2 c3 c4 c5 c6 c7 c8 c9
c0 c1 c2 c3 c4 c5 c6 c7 c8
c9
c0 c1 c2 c3 c4 c5 c6 c7 c8
c9
row1
row 3
row 2
row 4
Odd Field
Even Field
Programmable hsync to 1st valid pixel delay
Programmable inter-frame delay
Programmable row delay
Figure 45. Example of Digital Video Port Timing in Interlaced Mode
pclk
vsync
hysync
d[11:0]
c0
c2
c4
c6
c8
c0
c2
c4
c6
c8
c0
c2
c
4
c6
c8
c0
c2
c4
c6
c8
row 1
row 3
row 1
row 3
frame 1
frame 2
Programmable hsync to 1st valid pixel delay
Programmable inter-frame delay
Programmable inter-row delay
Figure 46. Example of Digital Video Port Timing in 2:1 Sub-sampling Mode
pclk
vsync
hsync
d[11:0]
c0
c2
c4
c6
c8
c0
c2
c4
c6
c8
c0
c2
c4
c6
c8
c0
c2
c4
c5
c8
row 1
row 2
row 1
row 2
frame 1
frame 2
Programmable hsync to 1st valid pixel delay
Programmable inter-frame delay
Programmable inter-row delay
Figure 47. Example of Digital Video Port Timing in 4:2 Sub-sampling Mode
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Functional Description (continued)
11.6 Synchronisation Signals in Slave Mode
11.7 Row Trigger Input Pin (hsync)
The sensor’s digital video port’s synchronisation signals can be
programmed to operate in slave mode. In slave mode the inte-
grated timing and control block will only start frame and row pro-
cessing upon the receipt of triggers from an external source.
The row trigger input pin, hsync, is used to trigger the process-
ing of a given row. It must be activated for at least two “mclk”
cycle. The first pixel data will appear at d[11:0] “Xmclk“periods
after the assertion of the row trigger, were Xmclk is given by:
Only two synchronization signals are used in slave mode as fol-
lows:
X
mclk = 124 + DWStAd
hsync
vsync
is the row trigger input signal.
is the frame trigger input signal.
Where:
DWStAd is the value of the display window column start
address.
Figure 48 shows the LM9619’s digital video port in slave mode
connected to a digital video processor master DVP.
The polarity of the active level of the row trigger is programma-
ble. By default it is active high.
d[11:0]
hsync
din[11:0]
RowTrig
FrameTrig
11.8 Frame Trigger Input Pin (vsync)
The frame trigger input pin, vsync, is used to reset the row
address counter and prepare the array for row processing. It
must be activated for at least one “mclk” cycle and no more than
96 mclk cycles after the activation of hsync as illustrated in Fig-
ure 50.
vsync
pclk
mclk
MasterClock
DVP
The polarity of the active level of the row trigger is programma-
ble. By default it is active high.
LM9619
Figure 48. LM9619 in slave mode
780 clock cycles per line
hsync
pixel 12
pixel 11
pixel 652
d[11:0]
642 valid pixels
776 777 778 779
0
1
2
3
...
134 135 136 136 137
...
774 775 776 777 778 779
0
1
mclk
count
mclk
Figure 49. hsync slave mode timing diagram for centred display window of 642 pixels
780 clock cycles per line
hsync
vsync
No more than
96 clock cycles
line 0
line 502
line502
line503
internal row
counter
776 777 778 779
0
1
2
3
...
774 775 776 777 778 779
0
1
774 775 776 777 778 779
0
1
mclk
...
count
mclk
Figure 50. vsync slave mode timing diagram for scan window of 504 rows.
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MEMORY MAP
ADDR
Register
UPDATE
Reset Value
00h
Notes
Description
Update Settings Register.
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
21h
22h
REV
Latest Silicon
00h
00h
00h
04h
00h
00h
00h
00h
00h
00h
FBh
00h
00h
FBh
00h
A5h
32h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
Revision Register
MCFG0
MCFG1
PCR
Main Configuration Register 0
Main Configuration Register 1
Power Control Register.
VCLKGEN
VMODE0
VMODE1
VMODE2
SNAPMODE
Video Clock Generator
Video Mode 0 Register
Video Mode 1 Register
Video Mode 2 Register
Snapshot Mode 0 Register
Reserved
SROWS
SROWE
SWLSB
note a
Scan Window Row Start Register
Scan Window Row End Register
Scan Window Mode B LSB Register
Display Window Row Start Register
Display Window Row End Register
Display Window Column Start Register
Display Window Column End Register
Display Window LSB Register.
Integration Time High Register
Integration Time Low Register
Row Delay High Register
note a
note a
DROWS
DROWE
DCOLS
DCOLE
DWLSB
ITIMEH
note a
note a
note a
note a
note a
note a
ITIMEL
RDELAYH
RDELAYL
FDELAYH
FDELAYL
VGAIN
Row Delay Low Register
Frame Delay High Register
Frame Delay Low Register
Video Gain Register
BGAIN
Blue Pixels Gain Register
GGAIN
Green Pixels Gain Register
Red Pixels Gain Register
RGAIN
BP1SLOPEH
BP1SLOPEL
BP1LEVA
BP2SLOPEH
BP2SLOPEL
BP1LEVB
note a
note a
Break Point 1 Slope High Register
Break Point 1 Slope Low Register
Break Point 1 Level Register A
Break Point 2 Slope High Register
Break Point 2 Slope Low Register
Break Point 1 Level Register B
note a
note a
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MEMORY MAP (continued)
ADDR
Register
Reset Value
00h
Notes
Description
23h
24h
Reserved for factory use, must be set to 00 Hex.
25h
26h
27h
28h
29h
2Ah
2Bh
BP2LEV
00h
00h
00h
00h
00h
00h
00h
Break Point 2 Level Register
BLCOEFF
BPTH0H
BPTH0L
BPTH1H
BPTH1L
OCR
Black Level Compensation Coefficient Register
Bad pixel Threshold 0 High Register
Bad pixel Threshold 0 Low Register
Bad pixel Threshold 1 High Register
Bad pixel Threshold 1 Low Register
Offset Compensation Register.
3Bh
7Fh
Reserved for future use.
Note a: Programmed setting will only take effect after the UpdateSettings bit in the UPDATE register is set
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Register Set (continued)
The following section describes all available registers in the
LM9619 register bank and their function.
Register Name Main Configuration 0
Address
Mnemonic
Type:
02 Hex
MCFG0
Read/Write
00 Hex
Register Name Settings Update Register
Mnemonic
Address
Type
UPDATE
00 Hex
Reset Value
Read/Write
00 Hex.
Bit
Bit Symbol
Description
(Read Only Bit)
Reset Value
7
PwrUpBusy
Bit
Bit Symbol
Description
Reserved
Indicates that power on initializa-
tion is in progress. The sensor is
ready for use when this bit is at
logic 0.
7:1
0
UpdateSettings
Set to inform the integrated
timing and control circuit to
update the sensor with the
new settings. This bit is self
resetting. If this bit is set
anytime between the start of
vertical blanking until 4 rows
before the end of the frame
the values will take effect in
the next frame. If the update
bit is set from 3 rows before
end of frame until the start of
vertical blanking the registers
will either take effect in the
next frame or the frame after.
6
PwrDown
Set to power down the sensor.
Writing a logic 1 to this register bit
has the same effect as taking the
pdwn pin high. Clear (the default)
this bit to power up the sensor.
5
4
BPCorrection
BlkLComp
Set to enable the bad pixel detec-
tion and correction circuit. Clear
(the default) to switch it off.
Set to disable the black level com-
pensation circuit. Clear (the
default) to switch it on.
3
2
Reserved
Register Name Device Rev Register
BPmode
Set to configure the bad pixel cor-
rection circuit to operating in
Mnemonic
Address
Type
REV
01 Hex
Read Only.
monochrome mode (this should
be used with monochorme sen-
sors) Clear the (the default) to set
the bad pixel correction circuit to
operate in color mode (this should
be used with color sensors).
Bit
Bit Symbol
SiRev
Description
7:0
The silicon revision register.
1
0
Reserved
GainMode
Set to route all pixels to the green
gain amplifier. Clear (the default)
to route the green, green and blue
pixels to the green,green and blue
amplifiers.
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IMAGE SENSOR SOLUTIONS
Register Set (continued)
Register Name Main Configuration 1
Register Name Power Control Register 1
Address
Mnemonic
Type
03 Hex
Address
Mnemonic
Type
04 Hex
PCR
MCFG1
Read/Write
00 Hex
Read/Write
Reset Value
Reset Value
00 Hex
Bit
Bit Symbol
Description
Bit
Bit Symbol
Description
7
ColorMode
Set when using a monochrome
sensor. When this bit is at a
logic 1, Sub-Sampling is set to
2:1 and every other row is read
out during interlace readout-
mode. Clear (the default) when
using a color sensor. When this
bit is at logic 0, sub-sampling is
set to 4:2 and every other row
pair is read out during interlace
mode.
7:4
3
Reserved
PwdnPGA
Assert to power down the pro-
grammable video gain amplifier.
Clear (the default) to power up the
video gain amplifiers.
2:1
0
PwdnCGA
[1:0]
Assert (11) to power down the pro-
grammable color gain amplifiers.
Clear (00, the default) to power up
the analog gain amplifiers.
6
5
ScanMode
Set to configure the sensor to
operate in interlace readout
mode. Clear (the default) to set
the sensor to operate in pro-
gressive scan read out mode.
PwDnADC
Assert to power down the 12 bit
analog to digital convertor. Clear
(the default) to power up the 12 bit
analog to digital convertor.
Register Name Hclk Generator Register
Address
Mnemonic
Type
05 Hex
HSubSamEn
Set to enable horizontal sub-
sampling. Clear (the default) to
disable horizontal sub-sampling.
VCLKGEN
Read/Write
04 Hex.
Reset Value
NOTE: When horizontal sub-
sampling is enabled Pclk is
divided by 2. The Hsync active
time is the same in both sub-
sampled and non sub-sampled
mode. Therefore frame rate
does not increase with horizon-
tal sub-sampling.
Bit
Bit Symbol
PumpClkGen
Description
7:6
Use to divide the frequency of
the sensors master clock input,
mclk to generate the internal
charge pump clock, PumpClk as
shown in the table below.
00 PumpClk = mclk
01 PumpClk = mclk/2
10 PumpClk = mclk/4
11 PumpClk = mclk/8
4
VSubSamEn
SlaveMode
Assert to enable vertical sub-
sampling. Clear (the default) to
disable vertical sub-sampling.
3
2
Reserved
Use to configure the digital
video port’s synchronisation sig-
nal to operate in slave mode. By
default the digital video’s port’s
synchronization signals are con-
figured to operate in master
mode.
5
Reserved
4:0
HclkGen
Use to divide the frequency of
the sensors master clock input,
mclk to generate the internal
sensor clock, Hclk.
Program 00 Hex (the default) for
Hclk to equal mclk or divide
mclk by any number between 1
and 31.
1:0
Reserved
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IMAGE SENSOR SOLUTIONS
Register Set (continued)
Register Name Digital Video Mode 0
Register Name Digital Video Mode 1
Address
Mnemonic
Type
06 Hex
Address
Mnemonic
Type
07 Hex
VMODE0
Read/Write
00 Hex
VMODE1
Read/Write
00 Hext
Reset Value
Reset Value
Bit
Bit Symbol
Description
Bit
Bit Symbol
Description
7:6
PixDataSel
Use to program the number of
active bits on the digital video bus
d[11:0], starting from the MSB
(d[11]). Inactive bits are tri-stated.:
7
6
PixClkMode
VsyncMode
Assert to set the pclk to “data
ready mode”. Clear, the default, to
set pclk to “free running mode”.
Assert to set the vsync pin to
“pulse mode”. Clear (the default)
to set the vsync signal to “level
mode”.
00 12 bit mode, bits
d[11:0] of the digital
video bus are active.
This is the default.
01 10 bit mode, bits
d[11:2] of the digital
video bus are active.
10 8 bit mode, bits
d[11:4] of the digital
video bus are active.
5
HsyncMode
Assert to force the hsync signal to
pulse for a minimum of four pixel
clocks at the end of each row.
Clear (the default) to force the
hsync signal to a level indicating
valid data within a row.
4
3
PixClkPol
VsynPol
Assert to set the active edge of
the pixel clock to negative. Clear
(the default) to set the active edge
of the clock to positive.
11 Reserved.
5:4
PixDataMsb
Use to program the routing of the
MSB output of the internal video
A/D to a bit on the digital video
bus.
Assert to force the vsync signal to
generate a logic 0 during a frame
readout (Level Mode), or a nega-
tive pulse at the end of a frame
readout (Pulse Mode). Clear (the
default) to force the vsync signal
to generate a logic 1 during a
frame readout (Level Mode), or a
negative pulse at the end of a
frame readout (Pulse Mode).
00 A/D [11:0] -> d[11:0].
01 A/D [10:0] -> d[11:1]
10 A/D [9:0] -> d[11:2]
11 A/D [8:0] -> d[11:3]
3:0
Reserved
2
HsynPol
Assert to force the hsync signal to
generate a logic 0 during a row
readout (Level Mode), or a nega-
tive pulse at the end of a row
readout (Pulse Mode). Clear (the
default) to force the hsync signal
to generate a logic 1 during a row
readout (Level Mode), or a nega-
tive pulse at the end of a readout
(Pulse Mode).
1
0
OddEvenEn
TriState
Assert to force the vsync pin to act
as an odd/even field indicator.
Clear (the default) to force the
vsync pin to act as a vertical syn-
chronization signal.
Assert to tri-state all output signals
(data and control) on the digital
video port. Clear (default) to
enable all signals (data and con-
trol) on the digital video port.
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IMAGE SENSOR SOLUTIONS
Register Set (continued)
Register Name Digital Video Mode 2
Register Name Scan Window Row Start Register
Address
Mnemonic
Type
08 Hex
Address
Mnemonic
Type
0B Hex
VMODE2
Read/Write
00 Hex
SROWS
Read/Write
00 Hex
Reset Value
Reset Value
Bit
7:4
Bit Symbol
HsyncAdjust
Description
Bit
Bit Symbol
Description
Use to program the leading edge
of hsync to the first valid pixel at
the beginning of each row. This
can be 0-hex to F-hex corre-
sponding to 0 - 15 pixel clocks.
Default 0.
7:0
SwStartRow
[8:1]
Use to program the scan window’s
start row address MSBs. If bit 6 of
register DWLSB is set to 1 the
start row address is incremented
by 1 else the raw value is used.
3:0
Reserved
Register Name Scan Window Row End Register
Address
Mnemonic
Type
0C Hex
Register Name Snapshot Mode Configuration Register
SROWE
Read/Write
FB Hex
Address
Mnemonic
Type
09 Hex
SNAPMODE
Read/Write
00 Hex
Reset Value
Reset Value
Bit
Bit Symbol
Description
Bit
Bit Symbol
Description
7:0
SwEndRow
[8:1]
Use to program the scan window’s
end row address MSBs. If bit 6 of
register DWLSB is set to 1 the end
row address is incremented by 1.
else the raw value is used.
7:6
SsFrames
Program to set the number of
frames required before readout
during a snapshot with no external
shutter, (see Figure 24). By
default these two bits are set to
00. Set to any value but 00 for
snapshot to function properly..:
Register Name Scan Window Mode B LSB Register
Address
Mnemonic
Type
0DHex
SWLSB
Read/Write
00 Hexx
00 Reserved
01 one frame
10 two frames
11 three frames
Reset Value
Bit
Bit Symbol
Description
7
SwMode
Use to program the scan window’s
addressing mode. Set to a logic
one for mode b and a logic 0 for
mode a.
5
4
ShutterMode
Assert to indicate that an external
shutter will be used during snap-
shot mode. Clear (the default) to
indicate that snapshot mode will
be carried out without the aid of an
external shutter.
6:2
1
Reserved
SwEndRow
[0]
Use to program bit 0 of the scan
window’s end row address.
0
SwStartRow
[0]
Use to program bit 0 of the scan
window’s start row address.
ExtSynPol
Assert to set the active level of the
extsync signal to 0. Clear (the
default) to set the active level of
the extsync signal to 1.
Register Name Display Window Row Start Register
Address
Mnemonic
Type
0E Hex
DROWS
Read/Write
3
2
Reserved
SnapshotMod
Assert to set the snapshot pin to
level mode. In level mode the sen-
sor will continually run snapshot
sequences as long as the snap-
shot pin is held to the active level.
Clear (the default) to set the snap-
shot signal to pulse mode. In
pulse mode the sensor will only
carry out one snapshot sequence
per pulse applied to the snapshot
pin.
Reset Value
00 Hex
Bit
Bit Symbol
DwStartRow
Description
7:0
Use to program the display win-
dow’s start row address MSBs.
The LSB can be programmed
using the DWLSB register.
Register Name Display Row End Register
Address
Mnemonic
Type
0F Hex
DROWE
Read/Write
FB Hex
1
0
SnapShotPol
SnapEnable
Assert to set the snapshot pin to
be active on the positive edge.
Clear (the default) to set the snap-
shot pin to be active on the nega-
tive edge.
Reset Value
Bit
Bit Symbol
DwEndRow
Description
7:0
Use to program the display win-
dow’s end row address. The LSB
can be programmed using the
DWLSB register.
Set to enable the external snap-
shot pin. Clear (the default) to dis-
able the external snapshot pin.
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IMAGE SENSOR SOLUTIONS
Register Set (continued)
Register Name Display Window Column Start Register
Register Name Integration Time High Register
Address
Mnemonic
Type
10 Hex
Address
Mnemonic
Type
13 Hex
DCOLS
Read/Write
00 Hex
ITIMEH
Read/Write
00 Hex.
Reset Value
Reset Value
Bit
Bit Symbol
DwStartCol
Description
Bit
Bit Symbol
Description
7:0
Use to program the display win-
dow’s start column address
MSBs. The two LSBs can be pro-
grammed using the DWLSB regis-
ter.
7:4
Reserved
3:0
Itime[11:8]
Program to set the integration
time of the array. The value pro-
grammed in the register is the
number of rows ahead of the
selected row to be reset.
Register Name Display Window Column End Register
Address
Mnemonic
Type
11 Hex
Register Name Integration Time Low Register
DCOLE
Read/Write
A5 Hex
Address
Mnemonic
Type
14 Hex
ITIMEL
Reset Value
Read/Write
00 Hex.
Bit
Bit Symbol
DwEndCol
Description
Reset Value
Bit
Bit Symbol
Itime[7:0]
Description
7:0
Use to program the display win-
dow’s end column address MSBs.
The two LSBs can be pro-
grammed using the DWLSB regis-
ter.
7:0
Program to set the integration
time of the array. The value pro-
grammed in the register is the
number of rows ahead of the
selected row to be reset.
Register Name Display Window LSB register
Address
Mnemonic
Type
12 Hex
Register Name Row Delay High Register
DWLSB
Read/Write
32 Hex
Address
Mnemonic
Type
15 Hex
RDELAYH
Read/Write
00 Hex.
Reset Value
Bit
Bit Symbol
Description
Reset Value
Bit
Bit Symbol
Description
7
Reserved
6
SwLsb
Assert to increment the value of
the scan window start and end
row addresses by 1. Clear (the
default) to use the raw values.
7:3
Reserved
2:0
Rdelay[10:8]
Use to program the MSBs of the
row delay.
Register Name Row Delay Low Register
5
4
3
2
1
0
DwCel[1]
DwCel[0]
DwCSL[1]
DwCSL [0]
DwERLsb
DwSRLsb
Use to program bit 1 of the display
window’s end column address.
Default is 1.
Address
Mnemonic
Type
16 Hex
RDELAYL
Read/Write
00 Hex
Reset Value
Use to program bit 0 of the display
window’s end column address.
Default is 1.
Bit
Bit Symbol
Rdelay[7:0]
Description
7:0
Use to program the LSBs of the
row delay.
Use to program bit 1 of the display
window’s start column address.
Default is 0.
Register Name Frame Delay High Register
Address
Mnemonic
Type
17
Use to program bit 0 of the display
window’s start column address.
Default is 0.
FDELAYH
Read/Write
00 Hex
Reset Value
Use to program bit 0 of the display
window’s end row address.
Default is 1.
Bit
Bit Symbol
Description
7:4
Reserved
Use to program bit 0 of the display
window’s start row address.
Default is 0.
3:0
FDelay[11:8]
Use to program the MSBs of the
frame delay.
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IMAGE SENSOR SOLUTIONS
Register Set (continued)
Register Name Frame Delay Low Register
Register Name Break Point 1 Slope High Register
Address
Mnemonic
Type
18 Hex
Address
Mnemonic
Type
1D Hex
FDELAYL
Read/Write
00 Hex
BP1SLOPEH
Read/Write
00 Hex.
Reset Value
Reset Value
Bit
Bit Symbol
FDelay [7:0]
Description
Bit
Bit Symbol
Description
Reserved
7:0
Use to program the LSBs of
the frame delay.
7:6
5:0
Bp1Slope[13:8]
This register allows the slope
of the curve up to the first
breakpoint (slope 0 in figure
22) to be programed. When
the high and low registers are
cleared no breakpoint will
result.
Register Name Video Gain Register
Address
Mnemonic
Type
19 Hex
VGAIN
Read/Write
00 Hex
Reset Value
Bit
Bit Symbol
VidGain
Description
Register Name Break Point 1 Slope Low Register
7:0
Use to program the overall video
gain. 00hex corresponds to a gain
of 0dB while 3Fhex corresponds
to a gain of 15dB. Steps are in log-
arithmic increments.
Address
Mnemonic
Type
1E Hex
BP1SLOPEL
Read/Write
00 Hex
Reset Value
Bit
Bit Symbol
Bp1Slope[7:0]
Description
Register Name Blue Pixels Gain Register
Address
Mnemonic
Type
1A Hex
7:0
This register allows the slope
of the curve up to the first
breakpoint (slope 0 in figure
22) to be programed. When
the high and low registers are
cleared no breakpoint will
result.
BGAIN
Read/Write
00 Hex
Reset Value
Bit
Bit Symbol
BlueGain
Description
7:0
Use to program the gain of green
pixels. 00hex corresponds to a
gain of 0dB while 7Fhex corre-
sponds to a gain of 14dB. Steps
are in linear increments.
Register Name Break Point 3 Level Register
Address
Mnemonic
Type
1F Hex
BP1LEVA
Read/Write
00 Hex
Reset Value
Register Name Green Pixels Gain Register
Address
Mnemonic
Type
1B Hex
Bit
Bit Symbol
Bp1LevelA
Description
GGAIN
Read/Write
00 Hex
7:0
This register defines the level
at which the first breakpoint is
applied (break point 1 in figure
22). Note Bp1LevelB (register
BP1LEVB) must be pro-
grammed to be equal to
Bp1LevelA
Reset Value
Bit
Bit Symbol
GreenGain
Description
7:0
Use to program the gain of green
pixels. 00hex corresponds to a
gain of 0dB while 7Fhex corre-
sponds to a gain of 14dB. Steps
are in linear increments.
Register Name Break Point 2 Slope High Register
Address
Mnemonic
Type
20 Hex
BP2SLOPEH
Read/Write
00 Hex
Register Name Red Pixels Gain Register
Address
1C Hex
RGAIN
00 Hex
Reset Value
Mnemonic
Reset Value
Bit
Bit Symbol
Description
Reserved
Bit
Bit Symbol
Description
7:6
7:0
RedGain
Use to program the gain of red
pixels. 00hex corresponds to a
gain of 0dB while 7Fhex corre-
sponds to a gain of 14dB. Steps
are in linear increments.
5:0
Bp2Slope[13:8]
This register allows the slope
of the curve to the second
breakpoint (slope 1 in figure
22) to be programed. When
the high and low registers are
cleared no breakpoint will
result.
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IMAGE SENSOR SOLUTIONS
Register Set (continued)
Register Name Break Point 2 Slope Low Register
Register Name Black Level Compensation Coefficient
Register
Address
Mnemonic
Type
21 Hex
BP2SLOPEL
Read/Write
00 Hex
Address
Mnemonic
Type
26 Hex
BLCOEFF
Reset Value
Read/Write
Reset Value
00 Hex
Bit
Bit Symbol
Bp2Slope[7:0]
Description
Bit
7:6
5:3
Bit Symbol
Description
7:0
This register allows the slope
of the curve to the second
break point (slope 1 in figure
22) to be programed. When
the high and low registers are
cleared no breakpoint will
result.
Reserved
Clip[2:0]
Use to define the number of MSBs
of the incoming black pixels. If set
to zero no clipping will occur
000 No Clipping
Register Name Break Point 1 Level Register
001 drop d[11], use d[10:0]
010 drop d[11:10], use d[9:0]
011 drop d[11:9], use d[8:0]
100 drop d[11:8], use d[7:0]
101 drop d[11:7], use d[6:0]
110 drop d[11:6], use d[5:0]
111 drop d[11:5], use d[4:0]
Address
Mnemonic
Type
22 Hex
BP1LEVB
Read/Write
00 Hex
Reset Value
Bit
Bit Symbol
Bp1LevelB
Description
7:0
This register defines the level
at which the first breakpoint is
applied (break point 1 in figure
22). Note Bp1LevelA (register
BP1LEVA) must be pro-
grammed to be equal to
Bp1LevelB
2:0
Alpha[2:0]
Exponential averaging coefficient
for black pixels. Increasing the
value of alpha decreases the rate
of convergence of the black level
compensation block.
Register Name Break Point 2 Level Register
Register Name Bad Pixel Threshold 0 High Register
Address
Mnemonic
Type
25 Hex
Address
Mnemonic
Type
27 Hex
BP2LEV
Read/Write
00 Hex
BPTH0H
Read/Write
00 Hex.
Reset Value
Reset Value
Bit
Bit Symbol
BpT0 [11:4]
Description
Bit
Bit Symbol
Bp2Level
Description
7:0
Use to program the MSBs of
the bad pixel correction
threshold 0.
7:0
This register defines the level
at which the first breakpoint is
applied (break point 2 in figure
22).
Register Name Bad Pixel Threshold 0 Low Register
Address
Mnemonic
Type
28 Hex
BPTH0L
Read/Write
00 Hex
Reset Value
Bit
Bit Symbol
BpT0 [3.0]
Description
7:4
Use to program the LSBs of
the bad pixel correction
threshold 0.
3:0
Reserved
Register Name Bad Pixel Threshold 1 High Register
Address
Mnemonic
Type
29 Hex
BPTH1H
Read/Write
00 Hex
Reset Value
Bit
Bit Symbol
THR1[11.4]
Description
7:0
Use to program the MSBs of
the bad pixel correction
threshold 1.
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IMAGE SENSOR SOLUTIONS
Register Set (continued)
Register Name Bad Pixel Threshold 1 Low Register
Address
Mnemonic
Type
2A Hex
BPTH1L
Read/Write
00 Hex
Reset Value
Bit
Bit Symbol
Description
7:4
THR1 [3.0]
Use to program the MSBs of
the bad pixel correction
threshold 1.
3:0
Reserved
Register Name Offset Compensation Register
Address
Mnemonic
Type
2BH Hex
OCR
Read/Write
00 Hex
Reset Value
Bit
Bit Symbol
Description
7
OffSign
Sign of the Offset value. A
logic 0 indicates a positive
offset will be added while a
logic 1 indicates a negative
offset will be added.
6:1
0
OffMag
Magnitude of the offset to be
added or subtracted.
Reserved. This bit must be
set to a logic 0.
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IMAGE SENSOR SOLUTIONS
Timing Information
1.0 DIGITAL VIDEO PORT MASTER MODE TIMING
pclk
hsync
t2
t1
d[11:0]
P0
P1
Pn
t3
Figure 51. Row Timing Diagram
pclk
vsync
t6
t5
hsync
R2
R3
Rn
t1
t2
Figure 52. Frame Timing
pclk
vsync
t6
t5
hsync
R0
R1
R2
t2
Rn
t1
Inter Frame Delay
Frame (n)
Figure 53. Frame Delay Timing (With Inter Frame Delay).
Label
Descriptions
Min
Typ
Max
t0
pclk period
74.4ns
83.3ns
1.0µs
hsync low
hsync high
level mode
pulse mode
(116-HsyncAdjust + Rdelay) *pclk
16 * pclk
(see note a)
(see note a)
t1
level mode
pulse mode
(664 -HsyncAdjust) *pclk
764 * pclk
t2
t3
t5
first valid pixel data after hsync active
HsyncAdjust * pclk
(see note a)
(see note a)
vsync low
level mode
pulse mode
(Fdelay + 116) *pclk
16 * pclk
vsync high
level mode
pulse mode
(FNHclk - 116 - Fdelay
16 * pclk
)
* pclk
(see note a)
t6
Note a: See Frame Rate Programming section for more details
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Timing Information (continued)
2.0 DIGITAL VIDEO PORT SLAVE MODE TIMING
t1
t3
trigger row n
hsync
trigger row n+1
t2
d[11:0]
P654
P655
P640
P652
P653
P652
P653
P654
P1
mclk
Row n-1
Row n
Figure 54. Slave Mode Row Trigger and Readout Timing
trigger last row
in frame n
hsync
t5
trigger Frame n+1
vsync
mclk
t4
Figure 55. Slave Mode d[11:0], hsync & vsync to pclk Timing
d[11:0]
mclk
t6
Figure 56. Rising Edge of mclk to Valid Pixel Data
The following specifications apply for all supply pins = +3.0V & CL = 10pF unless otherwise noted. Boldface limits apply for TA =
TMIN to TMAX: all other limits TA = 25oC (Note 7)
Label
t1
Descriptions
Min
Typ
Max
Pulse width of row trigger
2 * mclk
124 * mclk
780 * mclk
t2
First pixel out after rising edge of row trigger
Minimum time between row triggers.
124 * mclk
t3
Max time to assert next frame trigger after last row
trigger.
t4
96 * mclk
t5
t6
Pulse width of Frame trigger
2 * mclk
Time to valid pixel data after rising edge of mclk
44ns
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IMAGE SENSOR SOLUTIONS
Timing Information (continued)
3.0 DIGITAL VIDEO PORT SINGLE FRAME CAPTURE (SNAPSHOT MODE) TIMING
t1
snapshot
extsync
t4
t3
t2
Figure 57. Snapshot Mode Timing With External Shutter
t1
snapshot
extsync
t3
t2
t4
Figure 58. Snapshot Timing Without External Shutter
Label
t1
Descriptions
Equation
Minimum Snapshot Trigger Pulse Width
Minimum time from Snapshot Pulse to extsync
Array Integration Time
2
* mclk
(see notes a & b)
(see notes a & b)
(see notes a & b)
(see notes a & b)
t2
FNHclk
FNHclk
FNHclk
t3
t4
Pixel Read Out
Note a: See 5.0Frame Rate Programming section for more details
Note b: See Snapshot Mode for more details
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IMAGE SENSOR SOLUTIONS
Timing Information (continued)
4.0 SERIAL BUS TIMING
Sr
P
Sr
tfDA
tfDA
SDA
t
HD;DAT
HD;STA
t
t
t
SU;STA
SU;STO
t
SU;DAT
SCLK
trCL
trCL1
trCL
trCL1
(1)
= Rp resistor pull-up
tLOW
tHIGH
tHIGH
tLOW
= MCS current source pull-up
(1) Rising edge of the first SCLK pulse after an acknowledge bit.
Figure 59. I2C Compatible Serial Bus Timing.
The following specifications apply for all supply pins = +3.3V, CL = 10pF, and sclk = 400KHz unless otherwise noted. Boldface limits
apply for TA = TMIN to TMAX: all other limits TA = 25oC (Note 7)
PARAMETER
SYMBOL
fSCLH
MIN
0
MAX
UNIT
KHz
µS
sclk clock frequency
400
Set-up time (repeated) START condition
Hold time (repeated) START condition
LOW period of the sclk clock
HIGH period of the sclk clock
Data set-up time
tSU;STA
tHD;STA
tLOW
0.6
0.6
1.3
0.6
180
0
-
-
µS
-
µS
tHIGH
-
µS
tSU;DAT
tHD;DAT
tSU;STO
Cb
-
nS
Data hold time
0.9
µS
Set-up time for STOP condition
Capacitive load for sda and sclk lines
0.6
µS
400
pF
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IMAGE SENSOR SOLUTIONS
Mechanical Information
H
Optical Center
K
F
Glass Lid
Chip
E
D
B
C
A
min
typ
max
Dimension
Description
*
(mm)
(mm)
(mm)
A
Distance from top of die to bottom of cavity
Top of die to top of glass lid
Top of die to bottom of glass lid
Max total thickness of die
0.692
0.724
0.756
B
C
D
E
F
0.774
0.255
1.054
0.420
1.334
0.585
2.580
0.750
7.231
8.425
14.520
14.520
+2o
Thickness of lid
0.530
7.031
8.225
14.090
14.090
-2o
0.640
7.131
8.325
14.220
14.220
0o
X-Coordinate of optical center (nom)
Y-Coordinate of optical center (nom)
X-Dimension of Package
G
H
K
Y-Dimension of Package
Die Rotational Accuracy
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Email:imagers@kodak.com
IMAGE SENSOR SOLUTIONS
Package Information
*
*
* For optical center information see Mechanical Information Section on Page 39
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41
Email:imagers@kodak.com
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