JM3851012501SGA [TI]

LF198JAN Monolithic Sample-and-Hold Circuits; LF198JAN单片采样保持电路


型号：	JM3851012501SGA
厂家：	TEXAS INSTRUMENTS
描述：	LF198JAN Monolithic Sample-and-Hold Circuits LF198JAN单片采样保持电路采样保持电路
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中文：	中文翻译
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LF198JAN

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SNOSAJ2A –FEBRUARY 2005–REVISED MARCH 2013

LF198JAN Monolithic Sample-and-Hold Circuits

Check for Samples: LF198JAN

FEATURES

DESCRIPTION

The LF198 is a monolithic sample-and-hold circuit

which utilizes BI-FET technology to obtain ultra-high

dc accuracy with fast acquisition of signal and low

droop rate. Operating as a unity gain follower, dc gain

accuracy is 0.002% typical and acquisition time is as

low as 6 μs to 0.01%. A bipolar input stage is used to

achieve low offset voltage and wide bandwidth. Input

offset adjust is accomplished with a single pin, and

does not degrade input offset drift. The wide

bandwidth allows the LF198 to be included inside the

feedback loop of 1 MHz op amps without having

stability problems. Input impedance of 10¹⁰Ω allows

high source impedances to be used without

degrading accuracy.

•

Operates from ±5V to ±18V Supplies

Less Than 10 μs Acquisition Time

TTL, PMOS, CMOS Compatible Logic Input

0.5 mV Typical Hold Step at C_h= 0.01 μF

Low Input Offset

0.002% Gain Accuracy

Low Output Noise in Hold Mode

Input Characteristics Do Not Change During

Hold Mode

•

High Supply Rejection Ratio in Sample or Hold

Wide Bandwidth

Space Qualified

P-channel junction FET's are combined with bipolar

devices in the output amplifier to give droop rates as

low as 5 mV/min with a 1 μF hold capacitor. The

JFET's have much lower noise than MOS devices

used in previous designs and do not exhibit high

temperature instabilities. The overall design ensures

no feed-through from input to output in the hold

mode, even for input signals equal to the supply

voltages.

Logic Inputs on the LF198 are Fully Differential

with Low Input Current, Allowing Direct

Connection to TTL, PMOS, and CMOS.

Differential Threshold is 1.4V. The LF198 will

Operate from ±5V to ±18V Supplies.

Connection Diagrams

Figure 1. TO-99 Package

See Package Number LMC

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

LF198JAN

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Typical Connection and Performance Curve

Acquisition Time

Functional Diagram

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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

Absolute Maximum Ratings⁽¹⁾

Supply Voltage

±18V

500 mW

Power Dissipation (Package Limitation)⁽²⁾

Operating Ambient Temperature Range

Storage Temperature Range

−55°C ≤T_A≤ +125°C

−65°C to +150°C

+150°C

Maximum Junction Temperature (T_Jmax

)

Input Voltage

Equal to Supply Voltage

+7V, −30V

Indefinite

Logic To Logic Reference Differential Voltage⁽³⁾

Output Short Circuit Duration

Hold Capacitor Short Circuit Duration

Lead Temperature (Soldering, 10 sec.)

10 sec

300°C

TO-99 (Still Air @ 0.5W)

TO-99 (500 LF/Min Air Flow @ 0.5W)

TO-99

160°C/W

θ_JA

Thermal Resistance

84°C/W

θ_JC

48°C/W

ESD Tolerance⁽⁴⁾

500V

(1) “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for

which the device is functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see the

Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance characteristics may

degrade when the device is not operated under the listed test conditions

(2) The maximum power dissipation must be derated at elevated temperatures and is dictated by T_JMAX, θ_JA, and the ambient temperature,

T_A. The maximum allowable power dissipation at any temperature is P_D= (T_JMAX− T_A)/θ_JA, or the number given in the Absolute

Maximum Ratings, whichever is lower. .

(3) Although the differential voltage may not exceed the limits given, the common-mode voltage on the logic pins may be equal to the

supply voltages without causing damage to the circuit. For proper logic operation, however, one of the logic pins must always be at least

2V below the positive supply and 3V above the negative supply.

(4) Human body model, 100pF discharged through 1.5KΩ

Quality Conformance Inspection

Mil-Std-883, Method 5005 — Group A

Subgroup

Description

Temperature (°C)

+25°C

Static tests at

+125°C

−55°C

Static tests at

Dynamic tests at

+25°C

+125°C

−55°C

Functional tests at

Switching tests at

+25°C

+125°C

−55°C

+25°C

+125°C

−55°C

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Electrical Characteristics DC Parameters

Symbol

Parameter

Sub-

groups

Conditions

Notes

Min

Max

Unit

V_IO

Input Offset Voltage

-3.0

-5.0

-3.0

-5.0

-3.0

-5.0

-3.0

-5.0

-3.0

-5.0

-1.0

-25

-1.0

-25

-1

3.0

5.0

3.0

5.0

3.0

5.0

3.0

5.0

3.0

5.0

2, 3

+V_CC= 3.5V, -V_CC= -26.5V,

V_CM= 11.5V

+V_CC= 26.5V, -V_CC= -3.5V,

V_CM= -11.5V

2, 3

+V_CC= 15V, -V_CC= -15V,

V_CM= 0V

2, 3

+V_CC= 7V, -V_CC= -3V,

V_CM= 2V

2, 3

+V_CC= 3V, -V_CC= -7V,

V_CM= -2V

2, 3

I_IB

Input Bias Current

+V_CC= 3.5V, -V_CC= -26.5V,

V_CM= 11.5V

2, 3

+V_CC= 26.5V, -V_CC= -3.5V,V_CM

-11.5V

2, 3

+V_CC= 15V, -V_CC= -15V,

V_CM= 0V

-25

-1

2, 3

+V_CC= 7V, -V_CC= -3V,

V_CM= 2V

-25

-1.0

-25

2.0

2, 3

+V_CC= 3V, -V_CC= -7V,

V_CM= -2V

2, 3

Z_I

Input Impedance

+V_CC= 3.5V to 26.6V,

-V_CC= -26.5V to -3.5V,

V_CM= 11.5V to -11.5V

GΩ

1.0

6.0

GΩ

2, 3

V_{IO Adj}

Input Offset Voltage Adjustment

Power Supply Rejection Ratio

Supply Current

+V_CC= 15V, -V_CC= -15V,

V_CM= 0V

1, 2, 3

V_{IO Adj}

+V_CC= 15V, -V_CC= -15V,

V_CM= 0V

-6.0

1, 2, 3

PSRR+

PSRR-

I_CC

-V_CC= -18V,

+V_CC= 18V to 12V

+V_CC= 18V,

-V_CC= -12V to -18V

1.0

5.5

6.5

1,2

+V_CC= 15V, -V_CC= -15V,

V_CM= 0V

A_E

Gain Error

+V_CC= 3.5V to 26.5V,

-V_CC= -26.5V to -3.5V,

V_CM= -11.5V to 11.5V

-0.005 0.005

-0.02

-0.04

0.02

0.04

2, 3

+V_CC= 3V to 7V,

-V_CC= -7V to -3V,

V_CM= -2V to 2V

2, 3

R_SC

Series Charge Resistance

+V_CC= 15V, -V_CC= -15V,

V_CM= 0V

400

Ω

1, 2, 3

I_IH(a)

I_IH(b)

I_IL(a)

I_IL(b)

Logical 1 Input Current

Logical 0 Input Current

Output Short Circuit Current

+V_CC= 8.5V, -V_CC= -21.5V

+V_CC= 21.5V, -V_CC= -8.5V

µA

1, 2, 3

-1.0

1.0

I_OS

+V_CC= 15V, -V_CC= -15V,

V_CM= 0V

-25

1, 2, 3

I_OS

Output Short Circuit Current

+V_CC= 15V, -V_CC= -15V,

V_CM= 0V

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Electrical Characteristics DC Parameters (continued)

Symbol

Parameter

Sub-

groups

Conditions

Notes

Min

Max

Unit

I_CH

Hold Capacitor Charge Current

-3.0

-2.0

+V_CC= 15V, -V_CC= -15V,

V_CM= 0V

2, 3

I_CH

Hold Capacitor Charge Current

Differential Logic Threshold

3.0

2.0

+V_CC= 15V, -V_CC= -15V,

V_CM= 0V

2, 3

V_Th(H)

V_Th(L)

+V_CC= 15V, -V_CC= -15V,

V_CM= 0V

Logic = 2.0V, Logic Ref = 2.0V

1.0

-10

µA

1, 2, 3

Differential Logic Threshold

+V_CC= 15V, -V_CC= -15V,

V_CM= 0V

Logic = 0.8V, Logic Ref = 2.0V

I_HL

Z_O

Hold Mode Leakage Current

See⁽¹⁾

-0.100 0.100

-50 50

-0.100 0.100

+V_CC= 3.5V, -V_CC= -26.5V,

V_CM= -11.5V

+V_CC= 26.5V, -V_CC= -3.5V, V_CM

= 11.5V

-50

Output Impedance

+V_CC= 15V, -V_CC= -15V,

V_CM= 0V

2.0

Ω

1, 2, 3

V_HS

(HOLD) Step Voltage

See⁽²⁾

-2.0

-5.0

-2.0

-5.0

2.0

5.0

2.0

5.0

2, 3

+V_CC= 3.5V, -V_CC= -26.5V, V_CM

= 11.5V

+V_CC= 26.5V, -V_CC= -3.5V, V_CM

= -11.5V

2, 3

F_RR

Feedthrough Rejection Ratio

+V_CC= 15V, -V_CC= -15V,

V_CM= 0V, V_I= 0V to 11.5V

2, 3

+V_CC= 15V, -V_CC= -15V,

V_CM= 0V, V_I= 11.5V to 0V

2, 3

+V_CC= 15V, -V_CC= -15V,

V_CM= 0V, V_I= 0V to -11.5V

2, 3

+V_CC= 15V, -V_CC= -15V,

V_CM= 0V, V_I= -11.5V to 0V

2, 3

(1) Leakage current is measured at a junction temperature of 25°C. The effects of junction temperature rise due to power dissipation or

elevated ambient can be calculated by doubling the 25°C value for each 11°C increase in chip temperature. Leakage is ensured over full

input signal range.

(2) Hold step is sensitive to stray capacitive coupling between input logic signals and the hold capacitor. 1 pF, for instance, will create an

additional 0.5 mV step with a 5V logic swing and a 0.01μF hold capacitor. Magnitude of the hold step is inversely proportional to hold

capacitor value.

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AC/DC Parameters

Symbol

Parameter

Sub-

groups

Conditions

Notes

Min Max

Unit

Delta V_IO

Delta T

Input Offset Voltage Temp

Sensitivity

-20

µV/°C

8A, 8B

T_AQ

Aquisition Time

+V_CC= 15V, -V_CC= -15V

300

1.5

µS

T_AP

Aperture Time

T_S

Settling Time

F_RRAC

Feedthrough Rejection Ratio

+V_CC= 15V, -V_CC= -15V,

V_I= 20Vpp

µS

TR_TS

Transient Response (settling time) +V_CC= 3.5V, -V_CC= -26.5V,

V_I= 100mV pulse

2.5

+V_CC= 26.5V, -V_CC= -3.5V,

V_I= 100mV pulse

TR_OS

Transient Response (overshoot)

+V_CC= 3.5V, -V_CC= -26.5V,

V_I= 100mV pulse

+V_CC= 26.5V, -V_CC= -3.5V,

V_I= 100mV pulse

en_H

en_S

Noise

+V_CC= 15V, -V_CC= -15V

mV_RMS

DC Parameters: Drift Values

Delta calculations performed on S-Level devices at group B, subgroup 5 ONLY.

Symbol

V_IO

I_IB

Parameters

Input Offset Voltage

Conditions

Sub-

groups

Notes

Min Max

Unit

+V_CC= 15V, -V_CC= -15V,

V_CM= 0V

-0.5

-2.5

0.5

2.5

Input Bias Current

+V_CC= 15V, -V_CC= -15V,

V_CM= 0V

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Typical Performance Characteristics

Dielectric Absorption

Error in Hold Capacitor

Aperture Time⁽¹⁾

Figure 2.

Figure 3.

Dynamic Sampling Error⁽¹⁾

Output Droop Rate

Figure 4.

Figure 5.

Hold Step⁽¹⁾

“Hold” Settling Time⁽¹⁾

Figure 6.

Figure 7.

(1) See Definition of Terms

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Typical Performance Characteristics (continued)

Leakage Current into Hold

Capacitor

Phase and Gain (Input to

Output, Small Signal)

Figure 8.

Figure 9.

Gain Error

Power Supply Rejection

Figure 10.

Figure 11.

Output Short Circuit Current

Output Noise

See Definition of Terms

Figure 12.

Figure 13.

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Typical Performance Characteristics (continued)

Feedthrough Rejection Ratio

(Hold Mode)

Input Bias Current

Figure 14.

Figure 15.

Output Transient at Start

of Sample Mode

Hold Step vs Input Voltage

Figure 16.

Figure 17.

Output Transient at Start

of Hold Mode

Figure 18.

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LOGIC INPUT CONFIGURATIONS

TTL & CMOS

3V ≤ V_LOGIC(Hi State) ≤ 7V

Threshold = 1.4V

Threshold = 1.4V*Select for 2.8V at pin 8

CMOS

7V ≤ V_LOGIC(Hi State) ≤ 15V

Threshold = 0.6 (V⁺) + 1.4V

Threshold = 0.6 (V⁺) − 1.4V

Op Amp Drive

Threshold ≈ +4V

Threshold = −4V

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Application Hints

HOLD CAPACITOR

Hold step, acquisition time, and droop rate are the major trade-offs in the selection of a hold capacitor value. Size

and cost may also become important for larger values. Use of the curves included with this data sheet should be

helpful in selecting a reasonable value of capacitance. Keep in mind that for fast repetition rates or tracking fast

signals, the capacitor drive currents may cause a significant temperature rise in the LF198.

A significant source of error in an accurate sample and hold circuit is dielectric absorption in the hold capacitor. A

mylar cap, for instance, may “sag back” up to 0.2% after a quick change in voltage. A long sample time is

required before the circuit can be put back into the hold mode with this type of capacitor. Dielectrics with very low

hysteresis are polystyrene, polypropylene, and Teflon. Other types such as mica and polycarbonate are not

nearly as good. The advantage of polypropylene over polystyrene is that it extends the maximum ambient

temperature from 85°C to 100°C. Most ceramic capacitors are unusable with > 1% hysteresis. Ceramic “NPO” or

“COG” capacitors are now available for 125°C operation and also have low dielectric absorption. For more exact

data, see the curve Dielectric Absorption Error. The hysteresis numbers on the curve are final values, taken after

full relaxation. The hysteresis error can be significantly reduced if the output of the LF198 is digitized quickly after

the hold mode is initiated. The hysteresis relaxation time constant in polypropylene, for instance, is 10—50 ms. If

A-to-D conversion can be made within 1 ms, hysteresis error will be reduced by a factor of ten.

DC AND AC ZEROING

DC zeroing is accomplished by connecting the offset adjust pin to the wiper of a 1 kΩ potentiometer which has

one end tied to V⁺and the other end tied through a resistor to ground. The resistor should be selected to give

≈0.6 mA through the 1k potentiometer.

AC zeroing (hold step zeroing) can be obtained by adding an inverter with the adjustment pot tied input to output.

A 10 pF capacitor from the wiper to the hold capacitor will give ±4 mV hold step adjustment with a 0.01 μF hold

capacitor and 5V logic supply. For larger logic swings, a smaller capacitor (< 10 pF) may be used.

LOGIC RISE TIME

For proper operation, logic signals into the LF198 must have a minimum dV/dt of 1.0 V/μs. Slower signals will

cause excessive hold step. If a R/C network is used in front of the logic input for signal delay, calculate the slope

of the waveform at the threshold point to ensure that it is at least 1.0 V/μs.

SAMPLING DYNAMIC SIGNALS

Sample error to moving input signals probably causes more confusion among sample-and-hold users than any

other parameter. The primary reason for this is that many users make the assumption that the sample and hold

amplifier is truly locked on to the input signal while in the sample mode. In actuality, there are finite phase delays

through the circuit creating an input-output differential for fast moving signals. In addition, although the output

may have settled, the hold capacitor has an additional lag due to the 300Ω series resistor on the chip. This

means that at the moment the “hold” command arrives, the hold capacitor voltage may be somewhat different

than the actual analog input. The effect of these delays is opposite to the effect created by delays in the logic

which switches the circuit from sample to hold. For example, consider an analog input of 20 Vp-p at 10 kHz.

Maximum dV/dt is 0.6 V/μs. With no analog phase delay and 100 ns logic delay, one could expect up to (0.1

μs)(0.6V/μs)= 60 mVerror if the “hold” signal arrived near maximum dV/dt of the input. A positive-going input

would give a +60 mV error. Now assume a 1 MHz (3 dB) bandwidth for the overall analog loop. This generates a

phase delay of 160 ns. If the hold capacitor sees this exact delay, then error due to analog delay will be (0.16 μs)

(0.6 V/μs) = −96 mV. Total output error is +60 mV (digital) −96 mV (analog) for a total of −36 mV. To add to the

confusion, analog delay is proportioned to hold capacitor value while digital delay remains constant. A family of

curves (dynamic sampling error) is included to help estimate errors.

A curve labeled Aperture Time has been included for sampling conditions where the input is steady during the

sampling period, but may experience a sudden change nearly coincident with the “hold” command. This curve is

based on a 1 mV error fed into the output.

A second curve, Hold Settling Time indicates the time required for the output to settle to 1 mV after the “hold”

command.

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DIGITAL FEEDTHROUGH

Fast rise time logic signals can cause hold errors by feeding externally into the analog input at the same time the

amplifier is put into the hold mode. To minimize this problem, board layout should keep logic lines as far as

possible from the analog input and the C_hpin. Grounded guarding traces may also be used around the input line,

especially if it is driven from a high impedance source. Reducing high amplitude logic signals to 2.5V will also

help.

Guarding Technique

Figure 19. Use 10-pin layout. Guard around C_his tied to output.

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Typical Applications

Sample and Difference Circuit

(Output Follows Input in Hold Mode)

X1000 Sample & Hold

V_OUT= V_B+ ΔV_IN(HOLD MODE)

*For lower gains, the LM108 must be frequency compensated

Ramp Generator with Variable Reset Level

Integrator with Programmable Reset Level

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Output Holds at Average of Sampled Input

Increased Slew Current

Reset Stabilized Amplifier (Gain of 1000)

Fast Acquisition, Low Droop Sample & Hold

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2–Channel Switch

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Synchronous Correlator for Recovering

Signals Below Noise Level

Gain

Z_IN

1 ± 0.02%

10¹⁰

≃ 1 MHz

1 ± 0.2%

47 kΩ

≃ 400 kHz

−90 dB

Crosstalk @ 1 kHz −90 dB

Offset

≤ 6 mV

≤ 75 mV

DC & AC Zeroing

Staircase Generator

*Select for step height

50k → ≅ 1V Step

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Differential Hold

Capacitor Hysteresis Compensation

**Adjust for amplitude

Definition of Terms

Hold Step: The voltage step at the output of the sample and hold when switching from sample mode to hold

mode with a steady (dc) analog input voltage. Logic swing is 5V.

Acquisition Time: The time required to acquire a new analog input voltage with an output step of 10V. Note that

acquisition time is not just the time required for the output to settle, but also includes the time required for all

internal nodes to settle so that the output assumes the proper value when switched to the hold mode.

Gain Error: The ratio of output voltage swing to input voltage swing in the sample mode expressed as a per cent

difference.

Hold Settling Time: The time required for the output to settle within 1 mV of final value after the “hold” logic

command.

Dynamic Sampling Error: The error introduced into the held output due to a changing analog input at the time

the hold command is given. Error is expressed in mV with a given hold capacitor value and input slew rate. Note

that this error term occurs even for long sample times.

Aperture Time: The delay required between “Hold” command and an input analog transition, so that the

transition does not affect the held output.

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REVISION HISTORY SECTION

Date

Revision

Section

Originator

Changes

Released

02/25/05

New release, Corporate format

All

L. Lytle

1 MDS converted to corp. datasheet format.

MJLF198–X Rev 2B0 MDS to be archived.

03/20/13

Changed layout of National Data Sheet to TI

format

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PACKAGE OPTION ADDENDUM

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20-Mar-2013

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package Qty

Eco Plan Lead/Ball Finish

MSL Peak Temp

Op Temp (°C)

Top-Side Markings

Samples

Drawing

(1)

(2)

(3)

(4)

JL198BGA

ACTIVE

TO-99

LMC

TBD

Call TI

-55 to 125

JM38510/12501BGA Q ACO

JM38510/12501BGA Q >T

JL198SGA

ACTIVE

LMC

-55 to 125

JM38510/12501SGA Q ACO

JM38510/12501SGA Q >T

JL198BGA

JM38510/12501BGA

JM38510/12501SGA

M38510/12501BGA

M38510/12501SGA

JM38510/12501BGA Q ACO

JM38510/12501BGA Q >T

JL198SGA

JM38510/12501SGA Q ACO

JM38510/12501SGA Q >T

JL198BGA

JM38510/12501BGA Q ACO

JM38510/12501BGA Q >T

JL198SGA

JM38510/12501SGA Q ACO

JM38510/12501SGA Q >T

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

⁽³⁾MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

20-Mar-2013

⁽⁴⁾Only one of markings shown within the brackets will appear on the physical device.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF LF198JAN, LF198JAN-SP :

Military: LF198JAN

•

Space: LF198JAN-SP

•

NOTE: Qualified Version Definitions:

Military - QML certified for Military and Defense Applications

•

Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application

•

Addendum-Page 2

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