JM3851012909BPA [TI]

DUAL PERIPHERAL DRIVERS; DUAL外设驱动程序


型号：	JM3851012909BPA
厂家：	TEXAS INSTRUMENTS
描述：	DUAL PERIPHERAL DRIVERS DUAL外设驱动程序驱动
文件：	总16页 (文件大小：517K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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SLRS022A − DECEMBER 1976 − REVISED OCTOBER 1995

SN55461, SN55462, SN55463 . . . JG PACKAGE

SN75461, SN75462, SN75463 . . . D OR P PACKAGE

(TOP VIEW)

PERIPHERAL DRIVERS FOR

HIGH-VOLTAGE, HIGH-CURRENT DRIVER

APPLICATIONS

• Characterized for Use to 300 mA

• High-Voltage Outputs

• No Output Latch-Up at 30 V (After

Conducting 300 mA)

GND

• Medium-Speed Switching

SN55461, SN55462, SN55463 . . . FK PACKAGE

(TOP VIEW)

• Circuit Flexibility for Varied Applications

and Choice of Logic Function

• TTL-Compatible Diode-Clamped Inputs

• Standard Supply Voltages

20 19

• Plastic DIP (P) With Copper Lead Frame for

Cooler Operation and Improved Reliability

• Package Options Include Plastic Small

Outline Packages, Ceramic Chip Carriers,

and Standard Plastic and Ceramic 300-mil

DIPs

9 10 11 12 13

SUMMARY OF SERIES 55461/75461

DEVICE

SN55461

SN55462

SN55463

SN75461

SN75462

SN75463

LOGIC

AND

NAND

PACKAGES

FK, JG

D, P

NC − No internal connection

AND

NAND

D, P

description

These dual peripheral drivers are functionally interchangeable with SN55451B through SN55453B and

SN75451B through SN75453B peripheral drivers, but are designed for use in systems that require higher

breakdown voltages than those devices can provide at the expense of slightly slower switching speeds. Typical

applications include logic buffers, power drivers, relay drivers, lamp drivers, MOS drivers, line drivers, and

memory drivers.

The SN55461/SN75461, SN55462/SN75462, and SN55463/SN75463 are dual peripheral AND, NAND, and

OR drivers respectively (assuming positive logic), with the output of the gates internally connected to the bases

of the npn output transistors.

Series SN55461 drivers are characterized for operation over the full military temperature range of −55°C

to 125°C. Series SN75461 drivers are characterized for operation from 0°C to 70°C.

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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

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SLRS022A − DECEMBER 1976 − REVISED OCTOBER 1995

†

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

SN55’

SN75’

UNIT

Supply voltage, V

(see Note 1)

Input voltage, V

5.5

Intermitter voltage (see Note 2)

Off-state output voltage, V

Continuous collector or output current (see Note 3)

400

500

400

500

Peak collector or output current (t ≤ 10 ms, duty cycle ≤ 50%, see Note 4)

Continuous total power dissipation

See Dissipation Rating Table

Operating free-air temperature range, T

−55 to 125

0 to 70

°C

Storage temperature range, T

stg

−65 to 150

260

−65 to 150

Case temperature for 60 seconds, T

FK package

JG package

D or P package

Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds

300

260

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. Voltage values are with respect to network GND unless otherwise specified.

2. This is the voltage between two emitters A and B.

3. This value applies when the base-emitter resistance (R ) is equal to or less than 500 Ω.

4. Both halves of these dual circuits may conduct rated current simultaneously; however, power dissipation averaged over a short time

interval must fall within the continuous dissipation rating.

DISSIPATION RATING TABLE

≤ 25°C

DERATING FACTOR

= 70°C

T = 125°C

PACKAGE

POWER RATING

ABOVE T = 25°C

POWER RATING POWER RATING

725 mW

5.8 mW/°C

11.0 mW/°C

8.4 mW/°C

8.0 mW/°C

464 mW

880 mW

672 mW

640 mW

−

1375 mW

275 mW

210 mW

−

1050 mW

1000 mW

recommended operating conditions

SN55’

SN75’

MIN NOM

UNIT

MIN NOM

MAX

Supply voltage, V

4.5

5.5

4.75

5.25

High-level input voltage, V

Low-level input voltage, V

0.8

Operating free-air temperature, T

−55

125

°C

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

^{POST OFFICE BOX 1443}• HOUSTON, TEXAS 77251−1443

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SLRS022A − DECEMBER 1976 − REVISED OCTOBER 1995

†

logic symbol

logic diagram (positive logic)

†

This symbol is in accordance with ANSI/IEEE Std 91-1984

and IEC Publication 617-12.

GND

Pin numbers shown are for D, JG, and P packages.

schematic (each driver)

FUNCTION TABLE

(each driver)

4 kΩ

1.6 kΩ

130 Ω

L (on state)

H (off state)

positive logic:

Y = AB or A + B

500 Ω

1 kΩ

GND

Resistor values shown are nominal.

electrical characteristics over recommended operating free-air temperature range

SN55461

SN75461

†

PARAMETER

Input clamp voltage

TEST CONDITIONS

UNIT

‡

MIN TYP

MAX

MIN TYP

MAX

= MIN,

I = −12 mA

−1.2

−1.5

−1.2

−1.5

= MIN,

= 35 V

= MIN,

High-level output current

300

0.5

0.8

100

µA

= MIN,

= 100 mA

= 0.8 V,

0.25

0.5

0.25

0.5

0.4

0.7

Low-level output voltage

= MIN,

= 300 mA

Input current at maximum input voltage

High-level input current

= MAX, V = 5.5 V

µA

= MAX, V = 2.4 V

Low-level input current

= MAX, V = 0.4 V

−1

−1.6

−1

−1.6

Supply current, outputs high

Supply current, outputs low

= MAX, V = 5 V

CCH

CCL

= MAX, V = 0

†

‡

For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.

All typical values are at V

= 5 V, T = 25°C.

switching characteristics, V

= 5 V, T = 25°C

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Propagation delay time, low-to-high-level output

Propagation delay time, high-to-low-level output

Transition time, low-to-high-level output

PLH

PHL

TLH

THL

≈ 200 mA,

= 50 Ω,

C = 15 pF,

See Figure 1

Transition time, high-to-low-level output

SN55461

SN75461

−10

= 30 V,

≈ 300 mA,

High-level output voltage after switching

See Figure 2

−10

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

^{POST OFFICE BOX 1443}• HOUSTON, TEXAS 77251−1443

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SLRS022A − DECEMBER 1976 − REVISED OCTOBER 1995

†

logic symbol

logic diagram (positive logic)

†

This symbol is in accordance with ANSI/IEEE Std 91-1984

and IEC Publication 617-12.

GND

Pin numbers shown are for D, JG, and P packages.

schematic (each driver)

FUNCTION TABLE

(each driver)

1.6 kΩ

4 kΩ

130 Ω

1.6 kΩ

H (off state)

L (on state)

positive logic:

Y = AB or A + B

500 Ω

1 kΩ

GND

Resistor values shown are nominal.

electrical characteristics over recommended operating free-air temperature range

SN55462

SN75462

†

PARAMETER

Input clamp voltage

TEST CONDITIONS

UNIT

‡

TYP

‡

TYP

MIN

MAX MIN

MAX

= MIN,

I = −12 mA

−1.2

−1.5

−1.2

−1.5

= MIN,

= 35 V

= 0.8 V,

= MIN,

High-level output current

300

0.5

0.8

100

µA

= MIN,

= 100 mA

0.25

0.5

0.25

0.5

0.4

0.7

Low-level output voltage

= MIN,

= 300 mA

Input current at maximum input voltage

High-level input current

= MAX, V = 5.5 V

µA

= MAX, V = 2.4 V

Low-level input current

= MAX, V = 0.4 V

−1.1

−1.6

−1.1

−1.6

Supply current, outputs high

Supply current, outputs low

= MAX, V = 0

CCH

CCL

= MAX, V = 5 V

†

‡

For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.

All typical values are at V

= 5 V, T = 25°C.

switching characteristics, V

= 5 V, T = 25°C

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Propagation delay time, low-to-high-level output

Propagation delay time, high-to-low-level output

Transition time, low-to-high-level output

PLH

PHL

TLH

THL

≈ 200 mA,

= 50 Ω,

C = 15 pF,

See Figure 1

Transition time, high-to-low-level output

SN55462

SN75462

−10

= 30 V,

≈ 300 mA,

High-level output voltage after switching

See Figure 2

−10

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

^{POST OFFICE BOX 1443}• HOUSTON, TEXAS 77251−1443

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SLRS022A − DECEMBER 1976 − REVISED OCTOBER 1995

†

logic symbol

logic diagram (positive logic)

≥1

†

This symbol is in accordance with ANSI/IEEE Std 91-1984

and IEC Publication 617-12.

GND

Pin numbers shown are for D, JG, and P packages.

schematic (each driver)

FUNCTION TABLE

(each driver)

4 kΩ

1.6 kΩ

4 kΩ

130 Ω

L (on state)

H (off state)

positive logic:

Y = A + B or A B

500 Ω

1 kΩ

Resistor values shown are nominal.

GND

electrical characteristics over recommended operating free-air temperature range

SN55463

SN75463

†

PARAMETER

Input clamp voltage

TEST CONDITIONS

UNIT

‡

TYP

‡

TYP

MIN

MAX MIN

MAX

= MIN, I = −12 mA

−1.2

−1.5

−1.2

−1.5

= MIN,

= 35 V

= MIN,

= 0.8 V,

High-level output current

300

0.5

0.8

100

µA

= MIN,

= 100 mA

0.25

0.5

0.25

0.5

0.4

0.7

Low-level output voltage

= MIN,

= 300 mA

Input current at maximum input voltage

High-level input current

= MAX, V = 5.5 V

µA

= MAX, V = 2.4 V

Low-level input current

= MAX, V = 0.4 V

−1

−1.6

−1

−1.6

Supply current, outputs high

Supply current, outputs low

= MAX, V = 5 V

CCH

CCL

= MAX, V = 0

†

‡

For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.

All typical values are at V

= 5 V, T = 25°C.

switching characteristics, V

= 5 V, T = 25°C

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Propagation delay time, low-to-high-level output

Propagation delay time, high-to-low-level output

Transition time, low-to-high-level output

PLH

PHL

TLH

THL

≈ 200 mA,

= 50 Ω,

C = 15 pF,

See Figure 1

Transition time, high-to-low-level output

SN55463

SN75463

−10

= 30 V,

≈ 300 mA,

High-level output voltage after switching

See Figure 2

−10

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

^{POST OFFICE BOX 1443}• HOUSTON, TEXAS 77251−1443

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SLRS022A − DECEMBER 1976 − REVISED OCTOBER 1995

PARAMETER MEASUREMENT INFORMATION

≤ 5 ns

90%

1.5 V

≤ 10 ns

90%

1.5 V

3 V

Input

2.4 V

10 V

= 50 Ω

Input

’461

’463

10%

0.5 µs

’461

’462

0 V

3 V

Output

≤ 5 ns

≤ 10 ns

Pulse

Generator

(see Note A)

Input

’462

Circuit

Under

90%

= 15 pF

1.5 V

Test

(see Note B)

10%

(see Note B)

0 V

PHL

90%

PLH

90%

GND SUB

’463

50%

10%

50%

10%

Output

0.4 V

TLH

THL

VOLTAGE WAVEFORMS

TEST CIRCUIT

NOTES: A. The pulse generator has the following characteristics: PRR ≤ 1 MHz, Z ≈ 50 Ω.

C includes probe and jig capacitance.

Figure 1. Test Circuit and Voltage Waveforms for Switching Times

= 30 V

≤ 5 ns

90%

≤ 10 ns

3 V

90%

1.5 V

Input

2 mH

1.5 V

Input

2.4 V

5 V

’461

’463

10%

90%

10%

40 µs

0 V

3 V

65 Ω

1N3064

’461

’462

≤ 5 ns

≤ 10 ns

Output

Pulse

Generator

(see Note A)

90%

1.5 V

Circuit

Under

Input

’462

1.5 V

Test

(see Note B)

10%

= 15 pF

0 V

(see Note B)

GND SUB

’463

Output

0.4 V

VOLTAGE WAVEFORMS

NOTES: A. The pulse generator has the following characteristics: PRR ≤ 12.5 kHz, Z = 50 Ω.

TEST CIRCUIT

C includes probe and jig capacitance.

Figure 2. Test Circuit and Voltage Waveforms for Latch-Up Test

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

^{POST OFFICE BOX 1443}• HOUSTON, TEXAS 77251−1443

PACKAGE OPTION ADDENDUM

www.ti.com

25-Jan-2012

PACKAGING INFORMATION

Status ⁽¹⁾

Eco Plan ⁽²⁾

MSL Peak Temp ⁽³⁾

Samples

Orderable Device

Package Type Package

Drawing

Pins

Package Qty

Lead/

Ball Finish

(Requires Login)

JM38510/12908BPA

JM38510/12909BPA

M38510/12908BPA

SN55461JG

ACTIVE

OBSOLETE

ACTIVE

CDIP

SOIC

PDIP

SOIC

TBD

A42

N / A for Pkg Type

Call TI

A42

N / A for Pkg Type

Call TI

OBSOLETE

ACTIVE

Call TI

SN55462JG

Call TI

SN55463JG

Call TI

SN75461D

Call TI

SN75461P

Call TI

SN75462D

Green (RoHS

& no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

SN75462DE4

SN75462DG4

SN75462DR

ACTIVE

SOIC

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

2500

Green (RoHS

& no Sb/Br)

SN75462DRE4

SN75462DRG4

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

SN75462P

SN75462PE4

SN75463D

ACTIVE

PDIP

SOIC

PDIP

LCCC

CDIP

LCCC

CDIP

Pb-Free (RoHS)

TBD

CU NIPDAU N / A for Pkg Type

OBSOLETE

ACTIVE

Call TI

SN75463DR

SN75463P

TBD

Pb-Free (RoHS)

TBD

CU NIPDAU N / A for Pkg Type

SN75463PE4

SNJ55461FK

SNJ55461JG

SNJ55462FK

SNJ55462JG

SNJ55463JG

ACTIVE

OBSOLETE

ACTIVE

Call TI

TBD

POST-PLATE N / A for Pkg Type

ACTIVE

TBD

A42

N / A for Pkg Type

Call TI

OBSOLETE

TBD

Call TI

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

25-Jan-2012

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

⁽³⁾MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF SN55461, SN55462, SN55463, SN75461, SN75462, SN75463 :

Catalog: SN75461, SN75462, SN75463

•

Military: SN55461, SN55462, SN55463

•

NOTE: Qualified Version Definitions:

Catalog - TI's standard catalog product

•

Military - QML certified for Military and Defense Applications

•

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

19-Mar-2008

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0 (mm)

B0 (mm)

K0 (mm)

Pin1

Diameter Width

(mm) W1 (mm)

(mm) (mm) Quadrant

SN75462DR

SOIC

2500

330.0

12.4

6.4

5.2

2.1

8.0

12.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

19-Mar-2008

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SOIC

SPQ

Length (mm) Width (mm) Height (mm)

340.5 338.1 20.6

SN75462DR

2500

Pack Materials-Page 2

MECHANICAL DATA

MCER001A – JANUARY 1995 – REVISED JANUARY 1997

JG (R-GDIP-T8)

CERAMIC DUAL-IN-LINE

0.400 (10,16)

0.355 (9,00)

0.280 (7,11)

0.245 (6,22)

0.065 (1,65)

0.045 (1,14)

0.310 (7,87)

0.290 (7,37)

0.063 (1,60)

0.015 (0,38)

0.020 (0,51) MIN

0.200 (5,08) MAX

0.130 (3,30) MIN

Seating Plane

0.023 (0,58)

0.015 (0,38)

0°–15°

0.100 (2,54)

0.014 (0,36)

0.008 (0,20)

4040107/C 08/96

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. This package can be hermetically sealed with a ceramic lid using glass frit.

D. Index point is provided on cap for terminal identification.

E. Falls within MIL STD 1835 GDIP1-T8

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