CY74FCT16500TTSSOP [TI]
18-Bit Registered Transceivers; 18位寄存收发器
| 型号： | CY74FCT16500TTSSOP |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 18-Bit Registered Transceivers |
| 文件： | 总6页 (文件大小：66K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Data sheet acquired from Cypress Semiconductor Corporation.
Data sheet modified to remove devices not offered.
CY74FCT16500T
CY74FCT162500T
SCCS056 - August 1994 - Revised March 2000
18-Bit Registered Transceivers
Features
Functional Description
• FCT-C speed at 4.6 ns
• Power-off disable outputs permits live insertion
• Edge-rate control circuitry for significantly improved
noise characteristics
• Typical output skew < 250 ps
• ESD > 2000V
• TSSOP (19.6-mil pitch) and SSOP (25-mil pitch)
packages
• Industrial temperature range of −40˚C to +85˚C
• VCC = 5V ± 10%
These 18-bit universal bus transceivers can be operated in
transparent, latched, or clock modes by combining D-type
latches and D-type flip-flops. Data flow in each direction is
controlled by output-enable (OEAB and OEBA), latch enable
(LEAB and LEBA), and clock inputs (CLKAB and CLKBA)
inputs. For A-to-B data flow, the device operates in transparent
mode when LEAB is HIGH. When LEAB is LOW, the A data is
latched if CLKAB is held at a HIGH or LOW logic level. If LEAB
is LOW, the A bus data is stored in the latch/flip-flop on the
HIGH-to-LOW transition of CLKAB. OEAB performs the output
enable function on the B port. Data flow from B-to-A is similar
to that of A-to-B and is controlled by OEBA, LEBA, and
CLKBA. The output buffers are designed with power-off
disable feature that allows live insertion of boards.
CY74FCT16500T Features:
• 64 mA sink current, 32 mA source current
• Typical VOLP (ground bounce) <1.0V at VCC = 5V,
TA = 25˚C
The CY74FCT16500T is ideally suited for driving
high-capacitance loads and low-impedance backplanes.
The CY74FCT162500T has 24-mA balanced output drivers
with current limiting resistors in the outputs. This reduces the
need for external terminating resistors and provides for
minimal undershoot and reduced ground bounce. The
CY74FCT162500T is ideal for driving transmission lines.
CY74FCT162500T Features:
• Balanced 24 mA output drivers
• Reduced system switching noise
• Typical VOLP (ground bounce) <0.6V at VCC = 5V,
TA= 25˚C
Logic Block Diagram
Pin Configuration
SSOP/TSSOP
Top View
GND
1
2
3
4
56
55
54
OEAB
LEAB
CLKAB
B
1
A
1
OEAB
GND
GND
53
52
51
50
B
2
A
2
5
6
CLKBA
B
V
A
3
3
V
CC
CC
LEBA
OEBA
7
B
A
4
4
5
6
49
48
47
46
8
A
A
B
B
5
6
9
CLKAB
LEAB
10
11
GND
GND
A
7
B
7
45
44
43
12
13
A
A
B
B
B
8
9
8
C
D
C
D
14
15
16
17
18
9
B
1
A
10
42
41
A
1
10
A
A
B
11
B
12
11
12
40
39
38
GND
GND
C
D
C
D
A
A
A
B
13
14
15
19
20
21
22
23
13
14
15
B
37
36
35
34
B
V
V
CC
CC
B
16
A
16
17
A
33
32
31
30
29
B
17
24
25
TO 17 OTHER CHANNELS
GND
GND
FCT16500-1
A
B
18
26
27
28
18
OEBA
LEBA
CLKBA
GND
FCT16500-2
Copyright © 2000, Texas Instruments Incorporated
CY74FCT16500T
CY74FCT162500T
Maximum Ratings[5, 6]
Pin Summary
(Above which the useful life may be impaired. For user
guidelines, not tested.)
Name
Description
OEAB
OEBA
LEAB
LEBA
CLKAB
CLKBA
A
A-to-B Output Enable Input
Storage Temperature .......................Com’l −55°C to +125°C
B-to-A Output Enable Input (Active LOW)
A-to-B Latch Enable Input
Ambient Temperature with
Power Applied................................... Com’l −55°C to +125°C
B-to-A Latch Enable Input
DC Input Voltage .................................................−0.5V to +7.0V
DC Output Voltage ..............................................−0.5V to +7.0V
A-to-B Clock Input (Active LOW)
DC Output Current
(Maximum Sink Current/Pin) ...........................−60 to +120 mA
B-to-A Clock Input (Active LOW)
A-to-B Data Inputs or B-to-A Three-State Outputs
B-to-A Data Inputs or A-to-B Three-State Outputs
Power Dissipation..........................................................1.0W
B
Static Discharge Voltage............................................>2001V
(per MIL-STD-883, Method 3015)
Function Table[1, 2]
Operating Range
Inputs
Outputs
OEAB
LEAB
CLKAB
A
X
L
B
Z
Ambient
Range
Industrial
Temperature
VCC
L
X
H
H
L
X
X
X
−40°C to +85°C
5V ± 10%
H
H
H
H
H
H
L
H
L
H
L
L
H
X
X
H
L
H
L
B[3]
B[4]
L
Electrical Characteristics Over the Operating Range
Parameter
Description
Input HIGH Voltage
Test Conditions
Min.
Typ.[7]
Max.
Unit
VIH
VIL
VH
VIK
IIH
2.0
V
V
Input LOW Voltage
Input Hysteresis[8]
0.8
100
mV
V
Input Clamp Diode Voltage
Input HIGH Current
Input LOW Current
VCC=Min., IIN=−18 mA
VCC=Max., VI=VCC
−0.7
−1.2
±1
µA
µA
µA
IIL
VCC=Max., VI=GND.
VCC=Max., VOUT=2.7V
±1
IOZH
High Impedance Output Current
(Three-State Output pins)
±1
IOZL
High Impedance Output Current
(Three-State Output pins)
VCC=Max., VOUT=0.5V
±1
µA
IOS
IO
Short Circuit Current[9]
Output Drive Current[9]
Power-Off Disable
VCC=Max., VOUT=GND
VCC=Max., VOUT=2.5V
VCC=0V, VOUT≤4.5V[10]
−80
−50
−140
−200
−180
±1
mA
mA
µA
IOFF
Notes:
1. H = HIGH Voltage Level. L = LOW Voltage Level. X = Don’t Care. Z = HIGH Impedance.
2. A-to-B data flow is shown, B-to-A data flow is similar but uses OEBA, LEBA, and CLKBA.
3. Output level before the indicated steady-state input conditions were established.
= HIGH-to-LOW Transition.
4. Output level before the indicated steady-state input conditions were established, provided that CLKAB was LOW before LEAB went LOW.
5. Operation beyond the limits set forth may impair the useful life of the device. Unless otherwise noted, these limits are over the operating free-air temperature
range.
6. Unused inputs must always be connected to an appropriate logic voltage level, preferably either VCC or ground.
7. Typical values are at VCC= 5.0V, TA= +25˚C ambient.
8. This parameter is specified but not tested.
9. Not more than one output should be shorted at a time. Duration of short should not exceed one second. The use of high-speed test apparatus and/or sample
and hold techniques are preferable in order to minimize internal chip heating and more accurately reflect operational values. Otherwise prolonged shorting of
a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parametric tests. In any sequence of parameter
tests, IOS tests should be performed last.
10. Tested at +25˚C.
2
CY74FCT16500T
CY74FCT162500T
Output Drive Characteristics for CY74FCT16500T
Parameter
Description
Test Conditions
Min.
2.5
Typ.[7]
3.5
Max.
Unit
VOH
Output HIGH Voltage
VCC=Min., IOH=−3 mA
V
VCC=Min., IOH=−15 mA
VCC=Min., IOH=−32 mA
VCC=Min., IOL=64 mA
2.4
3.5
2.0
3.0
VOL
Output LOW Voltage
0.2
0.55
V
Output Drive Characteristics for CY74FCT162500T
Parameter
Description
Output LOW Current[9]
Output HIGH Current[9]
Output HIGH Voltage
Output LOW Voltage
Test Conditions
VCC=5V, VIN=VIH or VIL, VOUT=1.5V
VCC=5V, VIN=VIH or VIL, VOUT=1.5V
VCC=Min., IOH=−24 mA
Min.
60
Typ.[7]
115
Max.
150
Unit
mA
mA
V
IODL
IODH
−60
2.4
−115
3.3
−150
VOH
VOL
VCC=Min., IOL=24 mA
0.3
0.55
V
Capacitance[8] (TA = +25˚C, f = 1.0 MHz)
Parameter
Description
Input Capacitance
Output Capacitance
Test Conditions
Typ.[7] Max.
Unit
pF
CIN
VIN = 0V
4.5
5.5
6.0
8.0
COUT
VOUT = 0V
pF
Power Supply Characteristics
Parameter
Description
Test Conditions
Typ.[7]
Max.
Unit
ICC
Quiescent Power Supply Current VCC=Max.
VIN≤0.2V,
VIN≥VCC−0.2V
5
500
µA
∆ICC
QuiescentPowerSupplyCurrent VCC=Max.
(TTL inputs HIGH)
VIN=3.4V[11]
0.5
75
1.5
mA
ICCD
Dynamic Power Supply
Current[12]
VCC=Max., One Input Toggling, VIN=VCC or
50%DutyCycle,OutputsOpen, VIN=GND
OEAB=OEBA=VCC or GND
120
µA/MHz
IC
Total Power Supply Current[13]
VCC=Max., f0=10 MHz
(CLKAB), f1=5 MHz, 50% Duty VIN=GND
Cycle, Outputs Open,
VIN=VCC or
0.8
1.3
1.7
3.2
mA
mA
VIN=3.4V or
One Bit Toggling,
VIN=GND
OEAB=OEBA=VCC
LEAB=GND
VCC=Max., f0=10 MHz,
f1=2.5 MHz, 50% Duty
Cycle, Outputs Open,
Eighteen Bits Toggling,
OEAB=OEBA=VCC
LEAB=GND
VIN=VCC or
VIN=GND
3.8
8.5
6.5[14]
mA
mA
VIN=3.4V or
VIN=GND
20.8[14]
Notes:
11. Per TTL driven input (VIN=3.4V); all other inputs at VCC or GND.
12. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
13. IC
=
=
=
=
=
=
=
=
=
=
IQUIESCENT + IINPUTS + IDYNAMIC
IC
ICC+∆ICCDHNT+ICCD(f0/2 + f1N1)
ICC
Quiescent Current with CMOS input levels
Power Supply Current for a TTL HIGH input (VIN=3.4V)
Duty Cycle for TTL inputs HIGH
∆ICC
DH
NT
ICCD
f0
f1
N1
Number of TTL inputs at DH
Dynamic Current caused by an input transition pair (HLH or LHL)
Clock frequency for registered devices, otherwise zero
Input signal frequency
Number of inputs changing at f1
All currents are in milliamps and all frequencies are in megahertz.
14. Values for these conditions are examples of the ICC formula. These limits are specified but not tested.
3
CY74FCT16500T
CY74FCT162500T
Switching Characteristics Over the Operating Range[15]
CY74FCT16500CT/
CY74FCT162500AT CY74FCT162500CT
Fig.
Parameter
Description
Min.
Max.
150
5.1
Min.
Max.
150
4.6
Unit
MHz
ns
No.[16]
fMAX
CLKAB or CLKBA frequency
tPLH
tPHL
Propagation Delay
A to B or B to A
1.5
1.5
1.5
1.5
1.5
3.0
0
1.5
1.5
1.5
1.5
1.5
3.0
0
1, 3
1, 5
1, 5
1, 7, 8
1, 7, 8
9
tPLH
tPHL
Propagation Delay
LEBA to A, LEAB to B
5.6
5.6
6.0
5.6
5.3
5.3
5.4
5.2
ns
ns
ns
ns
ns
ns
tPLH
tPHL
Propagation Delay
CLKBA to A, CLKAB to B
tPZH
tPZL
Output Enable Time
OEBA to A, OEAB to B
tPHZ
tPLZ
Output Disable Time
OEBA to A, OEAB to B
tSU
Set-Up Time, HIGH or LOW
A to CLKAB, B to CLKBA
tH
Hold Time, HIGH or LOW
A to CLKAB, B to CLKBA
9
tSU
Set-Up Time, HIGH or LOW
A to LEAB, B to LEBA
Clock HIGH
Clock LOW
3.0
1.5
1.5
3.0
1.5
1.5
ns
ns
ns
4
4
4
tH
Hold Time, HIGH or LOW
A to LEAB, B to LEBA
tW
LEAB or LEBA Pulse Width HIGH
3.0
3.0
2.5
3.0
ns
ns
ns
5
5
tW
CLKAB or CLKBA Pulse Width HIGH or LOW
Output Skew[17]
tSK(O)
0.5
0.5
Ordering Information CY74FCT16500T
Speed
Package
Name
Operating
Range
(ns)
Ordering Code
CY74FCT16500CTPACT
CY74FCT16500CTPVC/PVCT
Package Type
4.6
Z56
O56
56-Lead (240-Mil) TSSOP
56-Lead (300-Mil) SSOP
Industrial
Ordering Information CY74FCT162500T
Speed
(ns)
Package
Operating
Range
Ordering Code
CY74FCT162500CTPVC
74FCT162500CTPVCT
CT74FCT162500ATPVC
74FCT162500ATPVCT
Name
O56
O56
O56
O56
Package Type
4.6
56-Lead (300-Mil) SSOP
56-Lead (300-Mil) SSOP
56-Lead (300-Mil) SSOP
56-Lead (300-Mil) SSOP
Industrial
5.1
Industrial
Notes:
15. Minimum limits are specified but not tested on Propagation Delays.
16. See “Parameter Measurement Information” in the General Information section.
17. Skew between any two outputs of the same package switching in the same direction. This parameter is ensured by design.
4
CY74FCT16500T
CY74FCT162500T
Package Diagrams
56-Lead Shrunk Small Outline Package O56
56-Lead Thin Shrunk Small Outline Package Z56
5
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pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
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BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
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Copyright 2000, Texas Instruments Incorporated
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