CY74FCT16501ETPAC [CYPRESS]
Registered Bus Transceiver, FCT Series, 1-Func, 18-Bit, True Output, CMOS, PDSO56, 0.240 INCH, 0.0196 INCH PITCH, TSSOP-56;
| 型号： | CY74FCT16501ETPAC |
| 厂家： | 
CYPRESS |
| 描述： | Registered Bus Transceiver, FCT Series, 1-Func, 18-Bit, True Output, CMOS, PDSO56, 0.240 INCH, 0.0196 INCH PITCH, TSSOP-56 光电二极管 输出元件 逻辑集成电路 触发器 |
| 文件： | 总7页 (文件大小：106K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
2H501
fax id: 7047
CY74FCT16501T
CY74FCT162501T
CY74FCT162H501T
18-Bit Registered Transceiver
Features
Functional Description
• Low power, pin-compatible replacement for ABT
functions
• FCT-E speed at 3.8 ns
• Power-off disable outputs permits live insertion
• Edge-rate control circuitry for significantly improved
noise characteristics
• Typical output skew < 250 ps
• ESD > 2000V
• TSSOP (19.6 mil pitch) and SSOP (25-mil pitch)
packages
These 18-bit universal bus transceivers can be operated in
transparent, latched or clock modes by combining D-type
latches and D-type flip-flops. Data flow in each direction is
controlled by output enable (OEAB and OEBA), latch enable
(LEAB and LEBA), and clock inputs (CLKAB and CLKBA). For
A-to-B data flow, the device operates in transparent mode when
LEAB is HIGH. When LEAB is LOW, the A data is latched if
CLKAB is held at a HIGH or LOW logic level. If LEAB is LOW,
the A bus data is stored in the latch/flip-flop on the
LOW-to-HIGH transition of CLKAB. OEAB performs the output
enable function on the B port. Data flow from B-to-A is similar
to that of A-to-B and is controlled by OEBA, LEBA, and CLKBA.
The output buffers are designed with a power-off disable fea-
ture to allow live insertion of boards.
• Industrial temperature range of 40°C to +85°C
−
• V = 5V 10%
±
CC
CY74FCT16501T Features:
The CY74FCT16501T is ideally suited for driving
high-capacitance loads and low-impedance backplanes.
• 64 mA sink current, 32 mA source current
• Typical V
(ground bounce) <1.0V at V = 5V,
CC
OLP
THE CY74FCT162501T has 24-mA balanced output drivers
with current limiting resistors in the outputs. This reduces the
need for external terminating resistors and provides for minimal
T = 25°C
A
CY74FCT162501T Features:
undershoot
and
reduced
ground
bounce.
The
• Balanced 24 mA output drivers
• Reduced system switching noise
CY74FCT162501T is ideal for driving transmission lines.
The CY74FCT162H501T is a 24-mA balanced output part, that
has “bus hold” on the data inputs. The device retains the input’s
last state whenever the input goes to high impedance. This
eliminates the need for pull-up/down resistors and prevents
floating inputs.
• Typical V
(ground bounce) <0.6V at V = 5V,
CC
OLP
T = 25°C
A
CY74FCT162H501T Features:
• Bus hold retains last active state
• Eliminates the need for external pull-up or pull-down
resistors
Pin Configuration
SSOP/TSSOP
Functional Block Diagram
Top View
OEAB
LEAB
1
2
56
55
GND
CLKAB
A
1
B
1
GND
3
4
54
53
GND
A
2
B
2
5
6
7
52
51
50
OEAB
A
B
3
3
CLKBA
LEBA
V
CC
V
CC
A
4
B
4
8
9
49
48
A
A
B
5
5
6
B
6
10
11
12
13
14
15
16
17
18
19
20
21
22
23
47
46
45
44
43
42
41
40
39
38
37
36
35
34
OEBA
GND
GND
CLKAB
A
A
A
B
7
7
8
9
B
8
LEAB
B
9
A
A
A
B
10
10
C
D
C
D
B
11
B
1
11
12
A
1
B
12
GND
GND
B
13
A
13
C
D
C
D
A
B
14
14
A
B
15
15
V
CC
V
CC
A
A
B
16
16
17
24
25
26
27
28
33
32
31
30
29
B
17
GND
GND
FCT16501-1
TO 17 OTHER CHANNELS
B
18
A
18
CLKBA
GND
OEBA
LEBA
FCT16501-2
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
August 19994 – Revised October 30, 1997
CY74FCT16501T
CY74FCT162501T
CY74FCT162H501T
Maximum Ratings[6, 7]
Pin Description
(Above which the useful life may be impaired. For user
guidelines, not tested.)
Name
Description
OEAB
OEBA
LEAB
LEBA
A-to-B Output Enable Input
Storage Temperature .....................................−55°C to +125°C
B-to-A Output Enable Input (Active LOW)
A-to-B Latch Enable Input
Ambient Temperature with
Power Applied ..................................................−55°C to +125°C
B-to-A Latch Enable Input
DC Input Voltage................................................. −0.5V to +7.0V
DC Output Voltage.............................................. −0.5V to +7.0V
CLKAB A-to-B Clock Input
CLKBA B-to-A Clock Input
DC Output Current
(Maximum Sink Current/Pin)............................−60 to +120 mA
A
A-to-B Data Inputs or B-to-A Three-State
[1]
Power Dissipation...........................................................1.0W
Outputs
Static Discharge Voltage........................................... >2001V
(per MIL-STD-883, Method 3015)
B
B-to-A Data Inputs or A-to-B Three-State
Outputs
[1]
Operating Range
Function Table[2, 3]
Ambient
Range
Industrial
Temperature
V
CC
Inputs
Outputs
B
−40°C to +85°C
5V ± 10%
OEAB
LEAB
CLKAB
A
L
H
H
H
X
H
H
L
X
X
X
X
L
Z
L
H
L
H
L
H
L
H
H
[4]
H
H
L
L
L
X
X
B
[5]
H
B
Notes:
1. On the 74FCT162H501T these pins have bus hold.
2. A-to-B data flow is shown. B-to-A data flow is similar but uses OEBA, LEBA, and CLKBA.
3. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
Z = High-impedance
= LOW-to-HIGH Transition
4. Output level before the indicated steady-state input conditions were established.
5. Output level before the indicated steady-state input conditions were established, provided that CLKAB was HIGH before LEAB went LOW.
6. Operation beyond the limits set forth may impair the useful life of the device. Unless otherwise noted, these limits are over the operating free-air temperature range.
7. Unused inputs must always be connected to an appropriate logic voltage level, preferably either VCC or ground.
2
CY74FCT16501T
CY74FCT162501T
CY74FCT162H501T
Electrical Characteristics Over the Operating Range
[8]
Parameter
Description
Input HIGH Voltage
Test Conditions
Min.
Typ.
Max.
Unit
V
V
V
V
V
2.0
IH
IL
H
Input LOW Voltage
0.8
V
[9]
Input Hysteresis
100
mV
V
Input Clamp Diode Voltage
Input HIGH Current
V
V
=Min., I =−18 mA
−0.7
−1.2
±1
IK
CC
IN
I
Standard
Bus Hold
Standard
=Max., V =V
CC
µA
IH
CC
I
±100
±1
I
Input LOW Current
V
V
=Max., V =GND
µA
µA
µA
µA
mA
IL
CC
CC
I
Bus Hold
±100
[10]
I
I
Bus Hold Sustain Current on Bus Hold Input
=Min.,
V =2.0V
−50
BBH
BBL
I
V =0.8V
+50
I
[10]
I
I
Bus Hold Overdrive Current on Bus Hold Input
V
V
V
=Max., V =1.5V
TBD
±1
BHHO
BHLO
CC
CC
CC
I
I
High Impedance Output Current
(Three-State Output pins)
=Max., V
=2.7V
=0.5V
=GND
µA
µA
OZH
OUT
OUT
I
High Impedance Output Current
(Three-State Output pins)
=Max., V
±1
OZL
[11]
I
I
I
Short Circuit Current
V
V
V
=Max., V
=Max., V
−80
−50
−140
−200
−180
±1
mA
mA
µA
OS
O
CC
CC
CC
OUT
[11]
Output Drive Current
=2.5V
OUT
[12]
Power-Off Disable
=0V, V
≤4.5V
OFF
OUT
Output Drive Characteristics for CY74FCT16501T
[8]
Parameter
Description
Test Conditions
=Min., I =−3 mA
Min.
2.5
Typ.
Max.
Unit
V
Output HIGH Voltage
V
V
V
V
3.5
3.5
3.0
0.2
V
OH
CC
CC
CC
CC
OH
=Min., I =−15 mA
2.4
OH
=Min., I =−32 mA
2.0
OH
V
Output LOW Voltage
=Min., I =64 mA
0.55
V
OL
OL
Output Drive Characteristics for CY74FCT162501T, CY74FCT162H501T
[8]
Parameter
Description
Test Conditions
=5V, V =V or V , V
IL OUT
Min.
60
Typ.
Max.
150
Unit
mA
mA
V
[11]
I
I
Output LOW Current
Output HIGH Current
Output HIGH Voltage
Output LOW Voltage
V
V
V
V
=1.5V
=1.5V
115
−115
3.3
ODL
ODH
CC
CC
CC
CC
IN
IH
[11]
=5V, V =V or V , V
IL OUT
−60
2.4
−150
IN
IH
V
V
=Min., I =−24 mA
OH
OH
OL
=Min., I =24 mA
0.3
0.55
V
OL
Notes:
8. Typical values are at VCC= 5.0V, TA= +25°C ambient.
9. This parameter is guaranteed but not tested.
10. Pins with bus hold are described in Pin Description.
11. Not more than one output should be shorted at a time. Duration of short should not exceed one second. The use of high-speed test apparatus and/or sample
and hold techniques are preferable in order to minimize internal chip heating and more accurately reflect operational values. Otherwise prolonged shorting of
a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parametric tests. In any sequence of parameter
tests, IOS tests should be performed last.
12. Tested at +25°C.
3
CY74FCT16501T
CY74FCT162501T
CY74FCT162H501T
Capacitance[9] (T = +25°C, f = 1.0 MHz)
A
[8]
Parameter
Description
Input Capacitance
Output Capacitance
Test Conditions
Typ.
4.5
Max.
6.0
Unit
pF
C
C
V
V
= 0V
IN
IN
= 0V
5.5
8.0
pF
OUT
OUT
Power Supply Characteristics
[13]
[8]
Sym.
Parameter
Test Conditions
Min. Typ.
Max.
Unit
I
Quiescent Power Supply
Current
V
V
V
=Max.
V <0.2V
—
—
—
5
500
µA
CC
CC
CC
CC
IN
V >V −0.2V
IN
CC
[14]
∆I
Quiescent Power Supply
Current TTL inputs HIGH
= Max., V
3.4V
IN =
0.5
75
1.5
mA
CC
I
Dynamic Power Supply
=Max., Outputs Open
V =V or
120
µA/
MHz
CCD
IN
CC
[15]
Current
OEAB=OEBA=V or GND
V =GND
CC
IN
One Input Toggling,
50% Duty Cycle
I
Total Power Supply
Current
V
=Max., Outputs Open
V =V or
—
—
0.8
1.3
1.7
3.2
mA
C
CC
IN
CC
[16]
f =10MHz (CLKAB)
V =GND
0
IN
50% Duty Cycle
OEAB=OEBA=V
V =3.4V or
IN
CC
V =GND
IN
LEAB = GND, One Bit Toggling
f = 5MHz, 50% Duty Cycle
1
[17]
V
=Max., Outputs Open
V =V or
—
—
3.8
8.5
6.5
CC
IN
CC
f = 10MHz (CLKAB)
V =GND
0
IN
50% Duty Cycle
OEAB=OEBA=V
LEAB=GND
[17]
V =3.4V or
20.8
IN
CC
V =GND
IN
Eighteen Bits Toggling
f =2.5MHz, 50% Duty Cycle
1
Notes:
13. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
14. Per TTL driven input (VIN=3.4V); all other inputs at VCC or GND.
15. This parameter is not directly testable, but is derived for use in Total Power Supply.
16. IC= IQUIESCENT + IINPUTS + IDYNAMIC
IC
=
=
=
=
=
=
=
=
=
ICC+∆ICCDHNT+ICCD(f0/2 + f1N1)
ICC
∆ICC
DH
NT
ICCD
f0
Quiescent Current with CMOS input levels
Power Supply Current for a TTL HIGH input (VIN=3.4V)
Duty Cycle for TTL inputs HIGH
Number of TTL inputs at DH
Dynamic Current caused by an input transition pair (HLH or LHL)
Clock frequency for registered devices, otherwise zero
Input signal frequency
f1
N1
Number of inputs changing at f1
All currents are in milliamps and all frequencies are in megahertz.
17. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested.
4
CY74FCT16501T
CY74FCT162501T
CY74FCT162H501T
[18]
Switching Characteristics Over the Operating Range
CY74FCT16501AT
CY74FCT162501AT
CY74FCT16501CT
CY74FCT162501CT
CY74FCT16501ET
CY74FCT162501ET
CY74FCT162H501AT CY74FCT162H501CT CY74FCT162H501ET
Fig.
[19]
Min.
Max.
Min.
Max.
Min.
Max.
Parameter
Description
Unit No.
f
CLKAB or CLKBA
frequency
—
150
—
150
—
150
MHz
—
MAX
[20]
t
t
Propagation Delay
A to B or B to A
1.5
1.5
1.5
5.1
5.6
5.6
1.5
1.5
1.5
4.6
5.3
5.3
1.5
1.5
1.5
3.8
4.2
4.2
ns
1,3
1,5
1,5
PLH
PHL
t
t
Propagation Delay
LEBA to A, LEAB to B
ns
PLH
PHL
t
t
Propagation Delay
CLKBA to A,
ns
PLH
PHL
CLKAB to B
t
t
Output Enable Time
OEBA to A, OEAB to B
1.5
1.5
3.0
6.0
5.6
—
1.5
1.5
3.0
5.6
5.2
—
1.5
1.5
2.4
4.8
5.2
—
ns
ns
ns
1,7,8
1,7,8
4
PZH
PZL
t
t
Output Disable Time
OEBA to A, OEAB to B
PHZ
PLZ
t
t
t
Set-Up Time,
HIGH or LOW
A to CLKAB,
B to CLKBA
SU
H
Hold Time
0
—
0
—
0
—
ns
4
HIGH or LOW
A to CLKAB,
B to CLKBA
Set-Up Time, Clock
HIGH or LOW LOW
3.0
1.5
1.5
—
—
—
3.0
1.5
1.5
—
—
—
2.0
1.5
0.5
—
—
—
ns
ns
ns
4
4
4
SU
A to LEAB,
B to LEBA
HIGH
Clock
t
Hold Time, HIGH or
LOW, A to LEAB,
B to LEBA
H
t
t
LEAB or LEBA Pulse
Width HIGH
3.0
3.0
—
—
3.0
3.0
—
—
3.0
3.0
—
—
ns
ns
5
5
W
W
[20]
CLKAB or CLKBA
Pulse Width HIGH or
[20]
LOW
[21]
t
Output Skew
—
0.5
—
0.5
—
0.5
ns
—
SK(O)
Notes:
18. Minimum limits are guaranteed, but not tested, on propagation delays.
19. See “Parameter Measurement Information” in the General Information section.
20. This parameter is guaranteed but not tested.
21. Skew between any two outputs of the same package switching in the same direction. This parameter guaranteed by design.
5
CY74FCT16501T
CY74FCT162501T
CY74FCT162H501T
Ordering Information CY74FCT16501T
Speed
Package
Name
Operating
Range
(ns)
Ordering Code
CY74FCT16501ETPAC
CY74FCT16501ETPVC
CY74FCT16501CTPAC
CY74FCT16501CTPVC
CY74FCT16501ATPAC
CY74FCT16501ATPVC
Package Type
56-Lead (240-Mil) TSSOP
3.8
Z56
O56
Z56
O56
Z56
O56
Industrial
Industrial
Industrial
56-Lead (300-Mil) SSOP
56-Lead (240-Mil) TSSOP
56-Lead (300-Mil) SSOP
56-Lead (240-Mil) TSSOP
56-Lead (300-Mil) SSOP
4.6
5.1
Ordering Information CY74FCT162501T
Speed
(ns)
Package
Operating
Range
Ordering Code
CY74FCT162501ETPAC
CY74FCT162501ETPVC
CY74FCT162501CTPAC
CY74FCT162501CTPVC
CY74FCT162501ATPAC
CY74FCT162501ATPVC
Name
Package Type
3.8
4.6
5.1
Z56
56-Lead (240-Mil) TSSOP
56-Lead (300-Mil) SSOP
56-Lead (240-Mil) TSSOP
56-Lead (300-Mil) SSOP
56-Lead (240-Mil) TSSOP
56-Lead (300-Mil) SSOP
Industrial
Industrial
Industrial
O56
Z56
O56
Z56
O56
Ordering Information CY74FCT162H501T
Speed
(ns)
Package
Operating
Range
Ordering Code
CY74FCT162H501ETPAC
CY74FCT162H501ETPVC
CY74FCT162H501CTPAC
CY74FCT162H501CTPVC
CY74FCT162H501ATPAC
CY74FCT162H501ATPVC
Name
Package Type
3.8
4.6
5.1
Z56
56-Lead (240-Mil) TSSOP
56-Lead (300-Mil) SSOP
56-Lead (240-Mil) TSSOP
56-Lead (300-Mil) SSOP
56-Lead (240-Mil) TSSOP
56-Lead (300-Mil) SSOP
Industrial
Industrial
Industrial
O56
Z56
O56
Z56
O56
Document #: 38-00382-C
6
CY74FCT16501T
CY74FCT162501T
CY74FCT162H501T
Package Diagrams
56-Lead Shrunk Small Outline Package O56
56-Lead Thin Shrunk Small Outline Package Z56
© Cypress Semiconductor Corporation, 1997. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
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