CDC2586PAHRG4 [TI]
3.3V PLL CLock Driver with 1/2x, 1x and 2x Frequency Options 52-TQFP;
| 型号： | CDC2586PAHRG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 3.3V PLL CLock Driver with 1/2x, 1x and 2x Frequency Options 52-TQFP 驱动 信息通信管理 逻辑集成电路 |
| 文件： | 总14页 (文件大小：306K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CDC2586
www.ti.com
SCAS337D–FEBRUARY 1993–REVISED APRIL 2004
3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS
FEATURES
•
Application for Synchronous DRAM,
High-Speed Microprocessor
•
Low Output Skew for Clock-Distribution
and Clock-Generation Applications
•
•
TTL-Compatible Inputs and Outputs
•
•
Operates at 3.3-V VCC
Outputs Have Internal 26-Ω Series
Resistors to Dampen Transmission-Line
Effects
Distributes One Clock Input to 12
Outputs
•
•
•
State-of-the-Art EPIC-IIB™ BiCMOS Design
Significantly Reduces Power Dissipation
•
Two Select Inputs Configure Up to Nine
Outputs to Operate at One-Half or Double
the Input Frequency
Distributed VCC and Ground Pins Reduce
Switching Noise
•
•
No External RC Network Required
Packaged in 52-Pin Thin Quad Flat Package
External Feedback (FBIN) Synchronizes the
Outputs to the Clock Input
PAH PACKAGE
(TOP VIEW)
52 51 50 49 48 47 46 45 44 43 42 41 40
39
GND
1Y1
V
4Y3
1
CC
38
37
36
35
34
33
32
31
30
29
28
27
2
V
CC
GND
3
GND
1Y2
V
CC
4
4Y2
GND
5
V
CC
6
GND
1Y3
V
CC
7
4Y1
GND
GND
8
V
CC
9
GND
GND
2Y1
10
11
12
13
V
CC
3Y3
GND
V
CC
14 15 16 17 18 19 20 21 22 23 24 25 26
NC – No internal connection
DESCRIPTION
The CDC2586 is a high-performance, low-skew, low-jitter clock driver. It uses a phase-lock loop (PLL) to
precisely align, in both frequency and phase, the clock output signals to the clock input (CLKIN) signal. It is
specifically designed for use with popular microprocessors operating at speeds from 50 MHz to 100 MHz or
down to 25 MHz on outputs configured for half-frequency operation. Each output has an internal 26-Ω series
resistor that improves the signal integrity at the load. The CDC2586 operates at nominal 3.3-V VCC
.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC-IIB is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 1993–2004, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
CDC2586
www.ti.com
SCAS337D–FEBRUARY 1993–REVISED APRIL 2004
The feedback input (FBIN) synchronizes the output clocks in frequency and phase to CLKIN. One of the twelve
output clocks must be fed back to FBIN for the PLL to maintain synchronization between CLKIN and the outputs.
The output used as feedback is synchronized to the same frequency as CLKIN.
The Y outputs can be configured to switch in phase and at the same frequency as CLKIN. Select inputs (SEL1,
SEL0) configure up to nine Y outputs, in banks of three, to operate at one-half or double the CLKIN frequency
depending on which output is fed back to FBIN (see Table 1 and Table 2). All output signal duty cycles are
adjusted to 50% independent of the duty cycle at CLKIN.
Output-enable (OE) provides output control. When OE is high, the outputs are in the high-impedance state.
When OE is low, the outputs are active. TEST is used for factory testing of the device and can be used to bypass
the PLL. TEST should be strapped to GND for normal operation.
Unlike many products containing PLLs, the CDC2586 does not require external RC networks. The loop filter for
the PLL is included on-chip, minimizing component count, board space, and cost.
Because it is based on PLL circuitry, the CDC2586 requires a stabilization time to achieve phase lock of the
feedback signal to the reference signal. This stabilization time is required following power up and application of a
fixed-frequency, fixed-phase signal at CLKIN, as well as following any changes to the PLL reference or feedback
signals. Such changes occur upon change of the select inputs, enabling of the PLL via TEST, and upon enable
of all outputs via OE.
The CDC2586 is characterized for operation from 0°C to 70°C.
DETAILED DESCRITPION OF OUTPUT CONFIGURATIONS
The voltage-controlled oscillator (VCO) used in the CDC2586 PLL has a frequency range of 100 MHz to 200
MHz, twice the operating frequency range of the CDC2586 outputs. The output of the VCO is divided by two and
four to provide reference frequencies with a 50% duty cycle of one-half and one-fourth the VCO frequency. The
SEL0 and SEL1 inputs select which of the two signals are buffered to each bank of device outputs.
One device output must be externally wired to FBIN to complete the PLL. The VCO operates such that the
frequency and phase of this output matches that of the CLKIN signal. In the case that a VCO/2 output is wired to
FBIN, the VCO must operate at twice the CLKIN frequency resulting in device outputs that operate at either the
same or one-half the CLKIN frequency. If a VCO/4 output is wired to FBIN, the device outputs operate at twice or
the same as the CLKIN frequency.
2
CDC2586
www.ti.com
SCAS337D–FEBRUARY 1993–REVISED APRIL 2004
Output Configuration A
Output configuration A is valid when any output configured as a 1x frequency output in Table 1 is fed back to
FBIN. The input frequency range for CLKIN is 50 MHz to 100 MHz when using output configuration A. Outputs
configured as 1/2 outputs operate at half the CLKIN frequency, while outputs configured as 1x outputs operate at
the same frequency as CLKIN.
Table 1. Output Configuration A(1)
INPUTS
OUTPUTS
1/2×
FREQUENCY
1×
SEL1
SEL0
FREQUENCY
L
L
L
H
L
None
1Yn
All
2Yn, 3Yn, 4Yn
3Yn, 4Yn
4Yn
H
H
1Yn, 2Yn
1Yn, 2Yn, 3Yn
H
(1) n = 1, 2, 3
Output Configuration B
Output configuration B is valid when any output configured as a 1x frequency output in Table 2 is fed back to
FBIN. The input frequency range for CLKIN is 25 MHz to 50 MHz when using output configuration B. Outputs
configured as 1x outputs operate at the CLKIN frequency, while outputs configured as 2x outputs operate at
double the frequency of CLKIN.
Table 2. Output Configuration B(1)
INPUTS
OUTPUTS
1×
2×
SEL1
SEL0
FREQUENCY
FREQUENCY
L
L
L
H
L
All
1Yn
None
2Yn, 3Yn, 4Yn
3Yn, 4Yn
4Yn
H
H
1Yn, 2Yn
1Yn, 2Yn, 3Yn
H
(1) n = 1, 2, 3
3
CDC2586
www.ti.com
SCAS337D–FEBRUARY 1993–REVISED APRIL 2004
FUNCTIONAL BLOCK DIAGRAM
OE
CLR
FBIN
Phase-Lock Loop
÷2
CLR
÷2
CLK
TEST
One of Four Identical
Outputs – 1Yn
SEL0
SEL1
Select
Logic
1Y1–1Y3
One of Four Identical
Outputs – 2Yn
2Y1–2Y3
One of Four Identical
Outputs – 3Yn
3Y1–3Y3
One of Four Identical
Outputs – 4Yn
4Y1–4Y3
4
CDC2586
www.ti.com
SCAS337D–FEBRUARY 1993–REVISED APRIL 2004
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME
NO.
Clock input. CLKIN is the clock signal to be distributed by the CDC2586 clock-driver circuit. CLKIN
provides the reference signal to the integrated PLL that generates the clock output signals. CLKIN must
have a fixed frequency and fixed phase for the PLL to obtain phase lock. Once the circuit is powered
up and a valid CLKIN signal is applied, a stabilization time is required for the PLL to phase lock the
feedback signal to its reference signal.
CLKIN
45
I
CLR
40
48
I
I
CLR is used for testing purposes only.
Feedback input. FBIN provides the feedback signal to the internal PLL. FBIN must be hardwired to one
of the 12 clock outputs to provide frequency and phase lock. The internal PLL adjusts the output clocks
to obtain zero phase delay between FBIN and CLKIN.
FBIN
Output enable. OE is the output enable for all outputs. When OE is low, all outputs are enabled. When
OE is high, all outputs are in the high-impedance state. Since the feedback signal for the PLL is taken
directly from an output, placing the outputs in the high-impedance state interrupts the feedback loop;
therefore, when a high-to-low transition occurs at OE, enabling the output buffers, a stabilization time is
required before the PLL obtains phase lock.
OE
42
I
Output configuration select. SEL0 and SEL1 select the output configuration for each output bank (e.g.,
1/2×, 1×, or 2×) (see Table 1 and Table 2).
SEL1, SEL0
TEST
51, 50
41
I
I
TEST is used to bypass the PLL circuitry for factory testing of the device. When TEST is low, all
outputs operate using the PLL circuitry. When TEST is high, the outputs are placed in a test mode that
bypasses the PLL circuitry. TEST should be strapped to GND for normal operation.
Output ports. These outputs are configured by the select inputs (SEL1, SEL0) to transmit one-half or
one-fourth the frequency of the VCO. The relationship between the CLKIN frequency and the output
frequency is dependent on the select inputs and the frequency of the output being fed back to FBIN
(see Table 1 and Table 2). The duty cycle of the Y output signals is nominally 50%, independent of the
duty cycle of CLKIN. Each output has an internal series resistor to dampen transmission-line effects
and improve the signal integrity at the load.
1Y1-1Y3
2Y1-2Y3
3Y1-3Y3
2, 5, 8 12,
15, 18 22,
25, 28
O
O
Output ports. 4Y1-4Y3 transmit one-half the frequency of the VCO regardless of the state of the select
inputs. The relationship between the CLKIN frequency and the output frequency is dependent on the
frequency of the output being fed back to FBIN (see Table 1 and Table 2). The duty cycle of the Y
output signals is nominally 50%, independent of the duty cycle of CLKIN. Each output has an internal
series resistor to dampen transmission-line effects and improve the signal integrity at the load.
4Y1-4Y3
32, 35, 38
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
(1)
(2)
UNIT
-0.5 V to 4.6 V
-0.5 V to 7 V
-0.5 V to 5.5 V
24 mA
Supply voltage range, VCC
Input voltage range, VI(2)
Voltage range applied to any output in the high state or power-off state, VO
Current into any output in the low state, IO
Input clamp current, IIK(VI< 0)
-20 mA
Output clamp current, IOK(VO< 0)
-50 mA
(3)
Maximum power dissipation at TA = 55°C (in still air)
1.2 W
Storage temperature range, Tstg
-65°C to 150°C
(1) Stresses beyond those listed under "absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
(3) The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 75 mils. For
more information, see the Package Thermal Considerations application note in the ABT Advanced BiCMOS Technology Data Book,
literature number SCBD002.
5
CDC2586
www.ti.com
SCAS337D–FEBRUARY 1993–REVISED APRIL 2004
(1)
RECOMMENDED OPERATING CONDITIONS
MIN
3
MAX
3.6
UNIT
VCC
VIH
VIL
VI
Supply voltage
V
High-level input voltage
Low-level input voltage
Input voltage
2
V
V
0.8
5.5
-12
12
0
0
V
IOH
IOL
TA
High-level output current
Low-level output current
Operating free-air temperature
mA
mA
°C
70
(1) Unused inputs must be held high or low to prevent them from floating.
ELECTRICAL CHARACTERISTICS
over recommended operating free-air temperature range (unless otherwise noted)
TA = 25°C
PARAMETER
TEST CONDITIONS
UNIT
V
MIN
MAX
VIK
VCC = 3 V,
II = -18 mA
-1.2
VCC = MIN to MAX(1)
VCC = 3 V,
,
IOH = -100 µA
IOH = -12 mA
IOL = 100 µA
IOL = 12 mA
VI = 3.6 V
VCC-0.2
2
VOH
V
0.2
0.8
±10
±1
10
-10
1
VOL
VCC = 3 V
V
VCC = 0,
II
µA
VCC = 3.6 V,
VCC = 3.6 V,
VCC = 3.6 V,
VI = VCC or GND
VO = 3 V
IOZH
IOZL
µA
µA
VO = 0
Outputs high
Outputs low
Outputs disabled
VCC = 3.6 V, IO= 0,
VI = VCC or GND
ICC
1
mA
1
Ci
VI = VCC or GND
VO = VCC or GND
4
pF
pF
Co
8
(1) For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
TIMING REQUIREMENTS
over recommended ranges of supply voltage and operating free-air temperature
MIN
MAX UNIT
VCO operating at four times the CLKIN frequency
VCO operating at double the CLKIN frequency
25
50
50
MHz
100
fclock
Clock frequency
Input clock duty cycle
40%
60%
50
After SEL1, SEL0
After OE↓
50
µs
50
Stabilization time(1)
After power up
After CLKIN
50
(1) Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. In order for phase lock to
be obtained, a fixed-frequency, fixed-phase reference signal must be present at CLKIN. Until phase lock is obtained, the specifications
for propagation delay and skew parameters given in the switching characteristicstable are not applicable.
6
CDC2586
www.ti.com
SCAS337D–FEBRUARY 1993–REVISED APRIL 2004
SWITICHING CHARACTERISTICS
over recommended ranges of supply voltage and operating free-air temperature, CL = 15 pF (see (1) and Figure 1 through
Figure 3)
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
MIN
MAX UNIT
fmax
100
MHz
Duty cycle
Y
45%
55%
(2)
tphase error
CLKIN↑
CLKIN↑
Y↑
Y↑
-500 +500
ps
ps
ns
ns
ns
ns
jitter
200
0.5
1
(2)
tsk(o)
(2)
tsk(pr)
tr
tf
1.4
1.4
(1) The specifications for parameters in this table are applicable only after any appropriate stabilization time has elapsed.
(2) The propagation delay, tphase error, is dependent on the feedback path from any output to FBIN. The tphase error, tsk(o),and tsk(pr)
specifications are valid only for equal loading of all outputs.
PARAMETER MEASUREMENT INFORMATION
3 V
0 V
Input
1.5 V
1.5 V
t
phase error
From Output
Under Test
V
V
OH
2 V
0.8 V
2 V
Output
C = 15 pF
1.5 V
L
500 Ω
0.8 V
(see Note A)
OL
t
r
t
f
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
LOAD CIRCUIT
A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 100 MHz, ZO = 50 Ω,
tr≤ 2.5 ns, tf ≤ 2.5 ns.
C. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
7
CDC2586
www.ti.com
SCAS337D–FEBRUARY 1993–REVISED APRIL 2004
PARAMETER MEASUREMENT INFORMATION (continued)
CLKIN
t
t
phase error 1
Outputs
Operating
at 1/2 CLKIN
Frequency
phase error 2
t
t
phase error 3
t
phase error 4
phase error 7
Outputs
Operating
at CLKIN
t
t
t
t
phase error 5
phase error 8
Frequency
phase error 9
phase error 6
A. Output skew, tsk(o), is calculated as the greater of:
•
•
The difference between the fastest and slowest of tphase error n (n = 1, 2, . . . 6)
The difference between the fastest and slowest of tphase error n (n = 7, 8, 9)
B. Process skew, tsk(pr), is calculated as the greater of:
•
The difference between the maximum and minimum tphase error n (n = 1, 2, . . . 6) across multiple devices under
identical operating conditions
•
The difference between the maximum and minimum tphase
identical operating conditions
(n = 7, 8, 9) across multiple devices under
n
error
C. For configuration A, see Table 1
Figure 2. Waveforms for Calculation of tsk(o)for Configuration A
8
CDC2586
www.ti.com
SCAS337D–FEBRUARY 1993–REVISED APRIL 2004
PARAMETER MEASUREMENT INFORMATION (continued)
CLKIN
t
phase error 10
Outputs
Operating
at CLKIN
t
phase error 11
phase error 12
Frequency
t
t
phase error 13
Outputs
Operating
at 2 CLKIN
t
phase error 14
Frequency
t
phase error 15
A. Output skew, tsk(o), is calculated as the greater of:
The difference between the fastest and slowest of tphase error n (n = 10, 11, . . . 15)
B. Process skew, tsk(pr), is calculated as the greater of:
•
•
The difference between the maximum and minimum tphase
under identical operating conditions
(n = 10, 11, . . . 15) across multiple devices
n
error
C. For configuration B, see Table 2
Figure 3. Waveforms for Calculation of tsk(o)for Configuration B
9
PACKAGE OPTION ADDENDUM
www.ti.com
12-Jan-2006
PACKAGING INFORMATION
Orderable Device
CDC2586PAH
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
TQFP
PAH
52
52
52
52
160 Green (RoHS & CU NIPDAU Level-4-260C-72 HR
no Sb/Br)
CDC2586PAHG4
CDC2586PAHR
CDC2586PAHRG4
TQFP
TQFP
TQFP
PAH
PAH
PAH
160 Green (RoHS & CU NIPDAU Level-4-260C-72 HR
no Sb/Br)
1500 Green (RoHS & CU NIPDAU Level-4-260C-72 HR
no Sb/Br)
1500 Green (RoHS & CU NIPDAU Level-4-260C-72 HR
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Mar-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) W1 (mm)
(mm) (mm) Quadrant
CDC2586PAHR
TQFP
PAH
52
1500
330.0
24.4
13.0
13.0
1.5
16.0
24.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Mar-2008
*All dimensions are nominal
Device
Package Type Package Drawing Pins
TQFP PAH 52
SPQ
Length (mm) Width (mm) Height (mm)
346.0 346.0 41.0
CDC2586PAHR
1500
Pack Materials-Page 2
MECHANICAL DATA
MTQF005A – OCTOBER 1994 – REVISED DECEMBER 1996
PAH (S-PQFP-G52)
PLASTIC QUAD FLATPACK
0,38
0,22
M
0,65
0,13
39
27
40
26
52
14
0,13 NOM
1
13
7,80 TYP
Gage Plane
10,20
SQ
9,80
12,20
SQ
0,25
11,80
0,05 MIN
0°–7°
1,05
0,95
0,75
0,45
Seating Plane
0,10
1,20 MAX
4040281/C 11/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
1
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相关型号：
CDC303N
LOW SKEW CLOCK DRIVER, 6 TRUE OUTPUT(S), 2 INVERTED OUTPUT(S), PDIP16, 0.300 INCH, PLASTIC, DIP-16
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