CDC2582PAH [TI]
3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH DIFFERENTIAL LVPECL CLOCK INPUTS; 3.3 -V锁相环时钟差分LVPECL时钟输入驱动器
| 型号： | CDC2582PAH |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH DIFFERENTIAL LVPECL CLOCK INPUTS |
| 文件： | 总10页 (文件大小：145K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CDC2582
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
WITH DIFFERENTIAL LVPECL CLOCK INPUTS
SCAS379B – FEBRUARY 1993 – REVISED FEBRUARY 1996
Low Output Skew for Clock-Distribution
and Clock-Generation Applications
Application for Synchronous DRAMs
Outputs Have Internal 26-Ω Series
Resistors to Dampen Transmission-Line
Effects
Operates at 3.3-V V
CC
Distributes Differential LVPECL Clock
Inputs to 12 TTL-Compatible Outputs
State-of-the-Art EPIC-ΙΙB BiCMOS Design
Significantly Reduces Power Dissipation
Two Select Inputs Configure Up to Nine
Outputs to Operate at One-Half or Double
the Input Frequency
Distributed V
and Ground Pins Reduce
CC
Switching Noise
No External RC Network Required
Packaged in 52-Pin Quad Flatpack
External Feedback Input (FBIN) Is Used to
Synchronize the Outputs With the Clock
Inputs
PAH PACKAGE
(TOP VIEW)
52 51 50 49 48 47 46 45 44 43 42 41 40
39
GND
1Y1
V
4Y3
GND
V
4Y2
GND
V
4Y1
GND
GND
V
3Y3
GND
1
CC
38
37
36
35
34
33
32
31
30
29
28
27
2
V
3
CC
GND
1Y2
4
CC
5
V
6
CC
GND
1Y3
7
CC
8
V
9
CC
GND
GND
2Y1
10
11
12
13
CC
V
CC
14 15 16 17 18 19 20 21 22 23 24 25 26
description
The CDC2582 is a high-performance, low-skew, low-jitter clock driver. It uses a phase-lock loop (PLL) to
precisely align the frequency and phase of the clock output signals to the differential LVPECL clock (CLKIN,
CLKIN)inputsignals. Itisspecifically designed to operate at speeds from 50 MHz to 100 MHz or down to 25 MHz
on outputs configured as half-frequency outputs. Each output has an internal 26-Ω series resistor that improves
the signal integrity at the load. The CDC2582 operates at 3.3-V V
.
CC
The feedback input (FBIN) synchronizes the frequency of the output clocks with the input clock (CLKIN, CLKIN)
signals. One of the twelve output clocks must be fed back to FBIN for the PLL to maintain synchronization
between the differential CLKIN and CLKIN inputs and the outputs. The output used as feedback is synchronized
to the same frequency as the clock (CLKIN and CLKIN) inputs.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC-ΙΙB is a trademark of Texas Instruments Incorporated.
Copyright 1996, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDC2582
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
WITH DIFFERENTIAL LVPECL CLOCK INPUTS
SCAS379B – FEBRUARY 1993 – REVISED FEBRUARY 1996
description (continued)
TheYoutputscanbeconfiguredtoswitchinphaseandatthesamefrequencyasdifferentialclockinputs(CLKIN
and CLKIN). Select (SEL1, SEL0) inputs configure up to nine Y outputs, in banks of three, to operate at one-half
or double the differential clock input frequency, depending upon the feedback configuration (see Tables 1
and 2). All output signal duty cycles are adjusted to 50% independent of the duty cycle at the input clocks.
Output-enable (OE) is provided for output control. When OE is high, the outputs are in the low state. When OE
is low, the outputs are active. CLR is negative-edge triggered and can be used to reset the outputs operating
at half frequency. TEST is used for factory testing of the device and can be used to bypass the PLL. TEST should
be strapped to GND for normal operation.
Unlike many products containing a PLL, the CDC2582 does not require external RC networks. The loop filter
for the PLL is included on chip, minimizing component count, board space, and cost.
Because it is based on PLL circuitry, the CDC2582 requires a stabilization time to achieve phase lock of the
feedback signal to the reference signal. This stabilization time is required following power up and application
of a fixed-frequency, fixed-phase signal at CLKIN and CLKIN, as well as following any changes to the PLL
reference or feedback signal. Such changes occur upon change of SEL1 and SEL0, enabling the PLL via TEST,
and upon enable of all outputs via OE.
The CDC2582 is characterized for operation from 0°C to 70°C.
detailed description of output configurations
The voltage-controlled oscillator (VCO) used in the CDC2582 has a frequency range of 100 MHz to 200 MHz,
twice the operating frequency range of the CDC2582 outputs. The output of the VCO is divided by 2 and by 4
to provide reference frequencies with a 50% duty cycle of one-half and one-fourth the VCO frequency. SEL0
and SEL1 determine which of the two signals are buffered to each bank of device outputs.
One device output must be externally wired to FBIN to complete the PLL. The VCO operates such that the
frequency of this output matches that of the CLKIN/CLKIN signals. In the case that a VCO/2 output is wired to
FBIN, the VCO must operate at twice the CLKIN/CLKIN frequency, resulting in device outputs that operate at
thesameorone-halftheCLKIN/CLKINfrequency. IfaVCO/4outputiswiredtoFBIN, thedeviceoutputsoperate
at the same or twice the CLKIN/CLKIN frequency.
output configuration A
Output configuration A is valid when any output configured as a 1× frequency output in Table 1 is fed back to
FBIN. The frequency range for the differential clock input is 50 MHz to 100 MHz when using output configuration
A. Outputs configured as 1/2× outputs operate at half the input clock frequency, while outputs configured as 1×
outputs operate at the same frequency as the differential clock input.
Table 1. Output Configuration A
INPUTS
OUTPUTS
1/2×
1×
SEL1 SEL0
FREQUENCY FREQUENCY
L
L
L
H
L
None
1Yn
All
2Yn, 3Yn, 4Yn
3Yn, 4Yn
4Yn
H
H
1Yn, 2Yn
1Yn, 2Yn, 3Yn
H
NOTE: n = 1, 2, 3
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDC2582
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
WITH DIFFERENTIAL LVPECL CLOCK INPUTS
SCAS379B – FEBRUARY 1993 – REVISED FEBRUARY 1996
output configuration B
Output configuration B is valid when any output configured as a 1× frequency output in Table 2 is fed back to
FBIN. The frequency range for the differential clock inputs is 25 MHz to 50 MHz when using output configuration
B. Outputs configured as 1× outputs operate at the input clock frequency, while outputs configured as 2× outputs
operate at double the frequency of the differential clock inputs.
Table 2. Output Configuration B
INPUTS
OUTPUTS
1×
2×
SEL1 SEL0
FREQUENCY FREQUENCY
L
L
L
H
L
All
1Yn
None
2Yn, 3Yn, 4Yn
3Yn, 4Yn
4Yn
H
H
1Yn, 2Yn
1Yn, 2Yn, 3Yn
H
NOTE: n = 1, 2, 3
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDC2582
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
WITH DIFFERENTIAL LVPECL CLOCK INPUTS
SCAS379B – FEBRUARY 1993 – REVISED FEBRUARY 1996
functional block diagram
OE
CLR
FBIN
CLR
2
Phase-Lock Loop
2
CLKIN
CLKIN
TEST
One of Three Identical
Outputs – 1Yn
SEL0
SEL1
Select
Logic
1Y1–1Y3
One of Three Identical
Outputs – 2Yn
2Y1–2Y3
One of Three Identical
Outputs – 3Yn
3Y1–3Y3
One of Three Identical
Outputs – 4Yn
4Y1–4Y3
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDC2582
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
WITH DIFFERENTIAL LVPECL CLOCK INPUTS
SCAS379B – FEBRUARY 1993 – REVISED FEBRUARY 1996
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME
NO.
Clock input. CLKIN and CLKIN are the differential clock signals to be distributed by the CDC2582
clock-driver circuit. These inputs are used to provide the reference signal to the integrated PLL that
generates the clock-output signals. CLKIN and CLKIN must have a fixed frequency and fixed phase for the
PLL to obtain phase lock. Once the circuit is powered up and valid CLKIN and CLKIN signals are applied,
a stabilization time is required for the PLL to phase lock the feedback signal to its reference signal.
CLKIN
CLKIN
44, 45
I
Clear. CLR is used to reset the VCO/4 reference frequency. CLR is negative-edge triggered and should be
CLR
40
48
I
I
strapped to V
or GND for normal operation.
CC
Feedback input. FBIN provides the feedback signal to the internal PLL. FBIN must be hardwired to one of
the twelve clock outputs to provide frequency and phase lock. The internal PLL adjusts the output clocks
to obtain zero-phase delay between the FBIN and the differential clock input (CLKIN and CLKIN).
FBIN
Output enable. OE is the output enable for all outputs. When OE is low, all outputs are enabled. When OE
is high, all outputs are in the high-impedance state. Since the feedback signal for the PLL is taken directly
from an output terminal, placing the outputs in the high-impedance state interrupts the feedback loop;
therefore, when a high-to-low transition occurs at OE, enabling the output buffers, a stabilization time is
required before the PLL obtains phase lock.
OE
42
I
Output configuration select. SEL0 and SEL1 select the output configuration for each output bank
(e.g., 1×, 1/2×, or 2×) (see Tables 1 and 2).
SEL1, SEL0
TEST
51, 50
41
I
I
TEST is used to bypass the PLL circuitry for factory testing of the device. When TEST is low, all outputs
operate using the PLL circuitry. When TEST is high, the outputs are placed in a test mode that bypasses
the PLL circuitry. TEST should be strapped to GND for normal operation.
These outputs are configured by SEL1 and SEL0 to transmit one-half or one-fourth the frequency of the
VCO. The relationship between the input clock frequency and the output frequency is dependent on SEL1
and SEL0 and the frequency of the output being fed back to FBIN. The duty cycle of the Y outputs is
nominally 50% independent of the duty cycle of the input clock signals. Each output has an internal series
resistor to dampen transmission-line effects and improve the signal integrity at the load.
1Y1–1Y3
2Y1–2Y3
3Y1–3Y3
2, 5, 8
12, 15, 18
22, 25, 28
O
O
These outputs transmit one-half the frequency of the VCO. The relationship between the input clock
frequency and the output frequency is dependent on the frequency of the output being fed back to FBIN.
The duty cycle of the Y outputs is nominally 50% independent of the duty cycle of CLKIN. Each output has
an internal series resistor to dampen transmission-line effects and improve the signal integrity at the load.
4Y1–4Y3
32, 35, 38
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
I
Voltage range applied to any output in the high state or power-off state, V (see Note 1) . . . –0.5 V to 5.5 V
O
Current into any output in the low state, I
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 mA
O
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –20 mA
IK
I
Output clamp current, I
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
OK
O
Maximum power dissipation at T = 55°C (in still air) (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 W
Storage temperature range, T
A
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils.
Formoreinformation, refertothePackageThermalConsiderationsapplicationnoteintheABTAdvancedBiCMOSTechnologyData
Book, literature number SCBD002.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDC2582
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
WITH DIFFERENTIAL LVPECL CLOCK INPUTS
SCAS379B – FEBRUARY 1993 – REVISED FEBRUARY 1996
recommended operating conditions (see Note 3)
MIN
MAX
UNIT
V
V
Supply voltage
3
3.6
V
CC
CLKIN, CLKIN
Other inputs
CLKIN, CLKIN
Other inputs
V
CC
–1.025
High-level input voltage
V
V
IH
2
0
0
V
CC
–1.62
V
V
Low-level input voltage
IL
0.8
5.5
–12
12
Input voltage
V
I
I
I
High-level output current
Low-level output current
Operating free-air temperature
mA
mA
°C
OH
OL
T
A
70
NOTE 3: Unused inputs must be held high or low to prevent them from floating.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
T
= 25°C
A
PARAMETER
TEST CONDITIONS
UNIT
V
MIN
MAX
V
V
V
V
V
= 3 V,
I = –18 mA
–1.2
IK
CC
CC
CC
I
†
= MIN to MAX ,
I
I
I
I
= –100 µA
= – 12 mA
= 100 µA
= 12 mA
V
–0.2
OH
OH
OL
OL
CC
V
OH
= 3 V,
2
0.2
0.8
±10
±1
5
V
OL
V
CC
= 3 V
V
†
V
V
= 0 or MAX ,
V = 3.6 V
I
CC
I
I
µA
mA
I
= 3.6 V,
V = V
or GND
CC
I
CC
Outputs high
Outputs low
V
CC
= 3.6 V,
I
O
= 0,
CC
V = V
or GND
5
I
CC
C
C
V = 3 V or 0
4
pF
pF
i
I
V
O
= 3 V or 0
8
o
†
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDC2582
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
WITH DIFFERENTIAL LVPECL CLOCK INPUTS
SCAS379B – FEBRUARY 1993 – REVISED FEBRUARY 1996
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
MIN
25
MAX
50
UNIT
VCO is operating at four times the CLKIN/CLKIN frequency
VCO is operating at double the CLKIN/CLKIN frequency
f
Clock frequency
MHz
clock
50
100
60%
50
Input clock duty cycle
40%
After SEL1, SEL0
After OE↓
†
Stabilization time
50
µs
After power up
50
†
Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be obtained, a
fixed-frequency, fixed-phase reference signal must be present at CLKIN. Until phase lock is obtained, the specifications for propagation delay
and skew parameters given in the switching characteristics table are not applicable.
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C = 15 pF (see Note 4 and Figures 1, 2, and 3)
L
FROM
TO
(OUTPUT)
PARAMETER
(INPUT)
MIN
MAX
UNIT
Duty cycle
Y
45%
100
55%
f
MHz
ps
max
Jitter
CLKIN↑
CLKIN↑
Y↑
Y
200
500
0.5
1
(pk-pk)
‡
t
t
t
t
t
–500
ps
phase error
‡
Y
ns
sk(o)
‡
Y
ns
sk(pr)
1.4
1.4
ns
r
f
ns
‡
Thepropagationdelay,t
are only valid for equal loading of all outputs.
,isdependentonthefeedbackpathfromanyoutputtoFBIN.Thet
,t
,andt
specifications
sk(pr)
phaseerror
phaseerror sk(o)
NOTE 4: The specifications for parameters in this table are applicable only after any appropriate stabilization time has elapsed.
PARAMETER MEASUREMENT INFORMATION
2.4 V
1.6 V
CLKIN
2 V
2 V
CLKIN
t
phase error
V
V
OH
2 V
0.8 V
2 V
0.8 V
1.5 V
Output
From Output
Under Test
OL
500 Ω
C
= 15 pf
L
t
t
f
r
(see Note A)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
LOAD CIRCUIT FOR OUTPUTS
NOTES: A.
B. The outputs are measured one at a time with one transition per measurement.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
C includes probe and jig capacitance.
L
O
r
f
Figure 1. Load Circuit and Voltage Waveforms
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDC2582
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
WITH DIFFERENTIAL LVPECL CLOCK INPUTS
SCAS379B – FEBRUARY 1993 – REVISED FEBRUARY 1996
PARAMETER MEASUREMENT INFORMATION
CLKIN
CLKIN
t
t
phase error 1
Outputs
Operating
at 1/2 CLKIN
Frequency
phase error 2
t
t
phase error 3
t
t
t
phase error 4
phase error 7
phase error 8
phase error 9
Outputs
Operating
at CLKIN
t
t
phase error 5
Frequency
phase error 6
NOTES: A. Output skew, t
, is calculated as the greater of:
sk(o)
– The difference between the fastest and slowest of t
– The difference between the fastest and slowest of t
(n = 1, 2, . . . 6)
(n = 7, 8, 9)
phase error n
phase error n
B. Process skew, t , is calculated as the greater of:
sk(pr)
– The difference between the maximum and minimum t
operating conditions
(n = 1, 2, . . . 6) across multiple devices under identical
phase error n
– The difference between the maximum and minimum t
operating conditions
(n = 7, 8, 9) across multiple devices under identical
phase error n
Figure 2. Skew Waveforms and Calculations
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDC2582
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
WITH DIFFERENTIAL LVPECL CLOCK INPUTS
SCAS379B – FEBRUARY 1993 – REVISED FEBRUARY 1996
PARAMETER MEASUREMENT INFORMATION
CLKIN
CLKIN
t
phase error 10
Outputs
Operating
at CLKIN
Frequency
t
phase error 11
phase error 12
t
t
phase error 13
Outputs
Operating
at 2X CLKIN
Frequency
t
phase error 14
t
phase error 15
NOTES: A. Output skew, t
, is calculated as the greater of:
sk(o)
– The difference between the fastest and slowest of t
(n = 10, 11, . . . 15)
phase error n
B. Process skew, t
, is calculated as the greater of:
sk(pr)
– Thedifferencebetweenthemaximumandminimumt
operating conditions
(n=10, 11, . . . 15)acrossmultipledevicesunderidentical
phaseerrorn
Figure 3. Waveforms for Calculation of t
and t
sk(pr)
sk(o)
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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