CD4034BMN [TI]
4000/14000/40000 SERIES, 8-BIT BIDIRECTIONAL PARALLEL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PDIP24, PLASTIC, DIP-24;
| 型号： | CD4034BMN |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 4000/14000/40000 SERIES, 8-BIT BIDIRECTIONAL PARALLEL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PDIP24, PLASTIC, DIP-24 光电二极管 输出元件 逻辑集成电路 触发器 |
| 文件： | 总12页 (文件大小：198K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
February 1988
CD4034BM/CD4034BC 8-Stage TRI-STATE Bidirectional
É
Parallel/Serial Input/Output Bus Register
General Description
The CD4034BM/CD4034BC is an 8-bit CMOS static shift
register with two parallel bidirectional data ports (A and B)
which, when combined with serial shifting operations, can
be used to (1) bidirectionally transfer parallel data between
two buses, (2) convert serial data to parallel form and direct
them to either of two buses, (3) store (recirculate) parallel
data, or (4) accept parallel data from either of two buses
and convert them to serial form. These operations are con-
trolled by five control inputs:
All register stages are D-type master-slave flip-flops with
separate master and slave clock inputs generated internally
to allow synchronous or asynchronous data transfer from
master to slave.
All inputs are protected against damage due to static dis-
.
SS
charge by diode clamps to V
and V
DD
Features
Y
Wide supply voltage range
High noise immunity
Low power TTL
3.0V to 18V
0.45 V (typ.)
A ENABLE (AE): ‘‘A’’ data port is enabled only when AE
is at logical ‘‘1’’. This allows the use of a common bus
for multiple packages.
Y
Y
DD
Fan out of 2 driving 74L
or 1 driving 74LS
compatibility
A-BUS-TO-B-BUS/B-BUS-TO-A-BUS (A/B): This input
controls the direction of data flow. When at logical ‘’1’’,
data flows from port A to B (A is input, B is output).
When at logical ‘‘0’’, the data flow direction is reversed.
Y
RCA CD4034B second source
Applications
Y
Parallel Input/Parallel Output
Parallel Input/Serial Output
Serial Input/Parallel Output
Serial Input/Serial Output register
Shift right/shift left register
ASYNCHRONOUS/SYNCHRONOUS (A/S): When A/S
is at logical ‘‘0’’, data transfer occurs at positive tran-
sition of the CLOCK. When A/S is at logical ‘‘1’’, data
transfer is independent of the CLOCK for parallel opera-
tion. In serial mode, A/S input is internally disabled such
that operation is always synchronous. (Asynchronous
serial operation is not possible.)
Y
Y
Y
Y
Y
Shift right/shift left with parallel loading
Address register
Buffer register
PARALLEL/SERIAL (P/S): A logical ‘‘1’’ P/S input al-
lows data transfer into the registers via A or B port (syn-
Bus system register with enable parallel lines at bus
side
e
e
logical ‘‘0’’, asynchronous if A/S
chronous if A/S
Y
Y
Y
Y
Y
Double bus register system
logical ‘‘1’’). A logical ‘‘0’’ P/S allows serial data to
transfer into the register synchronously with the positive
transition of the CLOCK, independent of the A/S input.
Up-down Johnson or ring counter
Pseudo-random code generators
Sample and hold register (storage, counting, display)
Frequency and phase comparator
CLOCK: Single phase, enabled only in synchronous
e
logical ‘‘0’’
e
logical ‘‘0’’.
mode. (Either P/S
e
logical ‘‘1’’ and A/S
or P/S
Connection Diagram
Dual-In-Line Package
Order Number CD4034B
TL/F/5963–1
Top View
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.
C
1995 National Semiconductor Corporation
TL/F/5963
RRD-B30M105/Printed in U. S. A.
Absolute Maximum Ratings (Notes 1 & 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Recommended Operating
Conditions (Note 2)
a
a
3 V to 15 V
DC Supply Voltage (V
)
DD
DC DC
Input Voltage (V
)
IN
0 V to V
V
DC DD DC
b
a
DC Supply Voltage (V
)
DD
0.5 V to 18 V
DC
DC
Operating Temperature Range (T )
A
b
a
0.5 V
Input Voltage (V
IN
)
0.5 V to V
DC DD
DC
b
b
a
55 C to 125 C
CD4034BM
CD4034BC
§
40 C to 85 C
§
§
b
a
65 C to 150 C
Storage Temp. Range (T )
S
§
§
a
§
Power Dissipation (P )
D
Dual-In-Line
Small Outline
700 mW
500 mW
Lead Temperature (T )
L
(Soldering, 10 seconds)
260 C
§
DC Electrical Characteristics CD4034BM (Note 2)
b
a
a
55 C
§
25 C
§
125 C
§
Symbol
Parameter
Conditions
Units
Min Max Min
Typ Max Min Max
e
e
e
e
V
I
Quiescent Device Current
V
DD
V
DD
V
DD
5V, V
IN
or V
DD SS
5
5
150
300
600
mA
mA
mA
DD
e
10V, V
15V, V
V
V
or V
10
20
10
20
IN
IN
DD
DD
SS
SS
e
or V
e
e
e
V
V
V
V
Low Level Output Voltage
High Level Output Voltage
Low Level Input Voltage
High Level Input Voltage
V
V
V
5V
0.05
0.05
0.05
0.05
0.05
0.05
0.05
0.05
0.05
V
V
V
OL
OH
IL
DD
DD
DD
10V
15V
e
e
e
V
DD
V
DD
V
DD
5V
4.95
9.95
4.95
9.95
4.95
9.95
V
V
V
10V
15V
14.95
14.95
14.95
e
e
e
e
0.5V or 4.5V
V
DD
V
DD
V
DD
5V, V
1.5
3.0
4.0
1.5
3.0
4.0
1.5
3.0
4.0
V
V
V
O
e
e
10V, V
15V, V
1.0V or 9.0V
O
O
1.5V or 13.5V
e
e
e
e
0.5V or 4.5V
V
DD
V
DD
V
DD
5V, V
O
3.5
7.0
3.5
7.0
3.5
7.0
V
V
V
IH
e
e
10V, V
15V, V
1.0V or 9.0V
O
O
1.5V or 13.5V 11.0
11.0
11.0
e
e
e
e
0.4V
I
I
Low Level Output Current
(Note 3)
V
V
V
5V, V
O
0.64
1.6
0.51
1.3
0.36
0.9
mA
mA
mA
OL
DD
DD
DD
e
e
10V, V
15V, V
0.5V
1.5V
O
O
4.2
3.4
2.4
e
e
e
e
5V, V
O
b
b
b
0.36
High Level Output Current
(Note 3)
V
DD
V
DD
V
DD
4.6V
0.64
0.51
mA
mA
mA
OH
e
e
b
b
b
b
b
b
10V, V
15V, V
9.5V
1.6
4.2
1.3
3.4
0.9
2.4
O
O
13.5V
-5
e
e
e
e
b
b
b
b
I
I
Input Curent
V
V
15V, V
15V, V
0V
0.1
0.1
10
10
1.0
mA
mA
IN
DD
IN
-5
15V
0.1
0.1
10
0.1
0.1
1.0
1.0
DD
IN
-5
e
e
e
e
b
b
b
b
TRI-STATE Leakage
Current
V
V
15V, V
15V, V
0V
0.1
0.1
1.0
mA
mA
OZ
DD
O
-5
10
15V
DD
O
Note 1: ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. Except for ‘‘Operating Temperature Range’’
they are not meant to imply that the devices should be operated at these limits. The table of ‘‘Electrical Characteristics’’ provides conditions for actual device
operation.
e
Note 2: V
0V unless otherwise specified.
and I are tested one output at a time.
SS
Note 3: I
OH
OL
2
DC Electrical Characteristics CD4034BC (Note 2)
b
a
a
85 C
40 C
§
25 C
§
§
Symbol
Parameter
Conditions
Units
Min Max Min
Typ Max Min Max
e
e
e
e
V
I
Quiescent Device Current
V
DD
V
DD
V
DD
5V, V
IN
or V
DD SS
20
40
80
20
40
80
150
300
600
mA
mA
mA
DD
e
10V, V
15V, V
V
V
or V
IN
IN
DD
DD
SS
SS
e
or V
e
e
e
V
V
V
V
Low Level Output Voltage
High Level Output Voltage
Low Level Input Voltage
High Level Input Voltage
V
V
V
5V
0.05
0.05
0.05
0.05
0.05
0.05
0.05
0.05
0.05
V
V
V
OL
OH
IL
DD
DD
DD
10V
15V
e
e
e
V
DD
V
DD
V
DD
5V
4.95
9.95
4.95
9.95
4.95
9.95
V
V
V
10V
15V
14.95
14.95
14.95
e
e
e
e
0.5V or 4.5V
V
DD
V
DD
V
DD
5V, V
1.5
3.0
4.0
1.5
3.0
4.0
1.5
3.0
4.0
V
V
V
O
e
e
10V, V
15V, V
1.0V or 9.0V
O
O
1.5V or 13.5V
e
e
e
e
0.5V or 4.5V
V
DD
V
DD
V
DD
5V, V
O
3.5
7.0
3.5
7.0
3.5
7.0
V
V
V
IH
e
e
10V, V
15V, V
1.0V or 9.0V
O
O
1.5V or 13.5V 11.0
11.0
11.0
e
e
e
e
0.4V
I
I
Low Level Output Current
(Note 3)
V
V
V
5V, V
O
0.52
1.3
0.44
1.1
0.36
0.9
mA
mA
mA
OL
DD
DD
DD
e
e
10V, V
15V, V
0.5V
1.5V
O
O
3.6
3.0
2.4
e
e
e
e
5V, V
O
b
b
b
0.36
High Level Output Current
(Note 3)
V
DD
V
DD
V
DD
4.6V
0.52
0.44
mA
mA
mA
OH
e
b
b
b
b
b
b
10V, V
9.5V
1.3
3.6
1.1
3.0
0.9
2.4
O
e
15V, V
13.5V
O
-5
e
e
e
e
b
b
b
b
b
b
I
I
Input Current
V
V
15V, V
15V, V
0V
0.3
0.3
10
10
1.0
mA
mA
IN
DD
IN
-5
15V
0.3
0.3
10
0.3
0.3
1.0
1.0
DD
IN
-5
e
e
e
e
b
b
TRI-STATE Leakage
Current
V
V
15V, V
15V, V
0V
0.3
0.3
1.0
mA
mA
OZ
DD
O
-5
10
15V
DD
O
AC Electrical Characteristics*
e
t 20 ns, unless otherwise specified
f
e
e
e
e
T
A
25 C, C
§
50 pF, R
200k, input t
L
L
r
Symbol
, t
Parameter
Propagation Delay Time, A (B)
Conditions
Min
Typ
Max
Units
e
e
e
t
V
DD
V
DD
V
DD
5V
280
120
85
700
270
190
ns
ns
ns
PHL PLH
Synchronous Parallel Data or Serial
Data Input, B (A) Parallel Data
Output
10V
15V
e
e
e
t , t
PHL PLH
Propagation Delay Time, A (B)
A (B) Asynchronous Parallel Data
Input, B (A) Parallel Data Output
V
DD
V
DD
V
DD
5V
280
120
85
700
270
190
ns
ns
ns
10V
15V
e
e
e
e
e
e
t , t
PHZ PLZ
Propagation Delay Time from A/B
or AE to High Impedance State at A
Outputs or from A/B to High
V
DD
V
DD
V
DD
5V,
R
1.0 kX
1.0 kX
1.0 kX
95
60
45
220
130
100
ns
ns
ns
L
L
L
10V, R
15V, R
Impedance State at B Outputs
e
e
e
e
e
e
t , t
PZH PZL
Propagation Delay Time from A/B
or AE to Logical ‘‘1’’ or Logical ‘‘0’’
State at A Outputs or from A/B to
Logical ‘‘1’’ or Logical ‘‘0’’ State at
B Outputs
V
DD
V
DD
V
DD
5V,
R
1.0 kX
1.0 kX
1.0 kX
180
75
480
190
140
ns
ns
ns
L
L
L
10V, R
15V, R
55
3
AC Electrical Characteristics*
e
t 20 ns, unless otherwise specified (Continued)
f
e
e
e
e
T
A
25 C, C
§
50 pF, R
200k, input t
L
L
r
Symbol
Parameter
Output Transition Time
Conditions
Min
Typ
Max
Units
e
e
e
t
f
t
t
t
t
t
, t
THL TLH
V
DD
V
DD
V
DD
5V
100
50
200
100
80
ns
ns
ns
10V
15V
40
e
e
e
Maximum Clock Input Frequency
Minimum Clock Pulse Width
V
V
V
5V
2
5
7
4
MHz
MHz
MHz
CL
DD
DD
DD
10V
15V
10
14
e
e
e
, t
WL WH
V
DD
V
DD
V
DD
5V
125
50
250
100
70
ns
ns
ns
10V
15V
35
e
e
e
, t
RCL FCL
Maximum Clock Rise & Fall Time
V
DD
V
DD
V
DD
5V
15
15
15
ms
ms
ms
10V
15V
e
e
e
Parallel (A or B) and Serial Data
Setup Time
V
DD
V
DD
V
DD
5V
25
10
7
70
30
20
ns
ns
ns
SU
SU
WH
10V
15V
e
e
e
Control Inputs AE, A/B, P/S,
A/S Setup Time
V
DD
V
DD
V
DD
5V
110
35
280
100
60
ns
ns
ns
10V
15V
60
e
e
e
Minimum High Level AE, A/B, P/S,
A/S Pulse Width
V
DD
V
DD
V
DD
5V
160
70
400
160
90
ns
ns
ns
10V
15V
40
C
C
Average Input Capacitance
A and B Data I/O and A/B Control
7
15
pF
IN
Input
Any Other Input
5
7.5
pF
pF
Power Dissipation Capacitance
(Note 4)
155
PD
*AC Parameters are guaranteed by DC correlated testing.
Note 4: C
determines the no-load power consumption of any CMOS device. For complete explanation see 54C/74C Family Characteristics application note,
PD
AN-90.
Logic Diagram
TL/F/5963–2
4
Schematic Diagram
TL/F/5963–3
5
Switching Time Waveforms and Test Circuits
Synchronous Operation
TL/F/5963–5
e
e
20 ns
t , CL
r
t , CL
f
Asynchronous Operation
TL/F/5963–6
TL/F/5963–4
TL/F/5963–7
TL/F/5963–8
TL/F/5963–10
TL/F/5963–9
6
Applications
16-Bit Parallel In/Parallel Out, Parallel In/Serial Out,
Serial In/Parallel Out, Serial In/Serial Out Register
TL/F/5963–11
7
Applications (Continued)
16-Bit Serial In/Gated Parallel Out Register
TL/F/5963–12
Frequency and Phase Comparator
TL/F/5963–13
TL/F/5963–14
e
*When f
f , t is proportional to the phase of f with respect to f .
2 W 1 2
1
8
Applications (Continued)
Shift Right/Shift Left with Parallel Inputs
TL/F/5963–15
Shift left input must be disabled during parallel entry.
A ‘‘High’’ (‘‘Low’’) on the Shift Left/Shift Right input allows
serial data on the Shift Left Input (Shift Right Input) to enter
the register on the positive transition of the clock signal. A
‘‘high’’ on the ‘‘A’’ Enable Input disables the ‘‘A’’ parallel
data lines on Registers 1 and 2 and enables the ‘‘A’’ data
lines on Registers 3 and 4 and allows parallel data into Reg-
isters 1 and 2. Other logic schemes may be used in place of
registers 3 and 4 for parallel loading.
When parallel inputs are not used Registers 3 and 4 and
associated logic are not required.
9
Truth Table
‘‘A’’ Enable P/S A/B A/S Mode
Operation*
0
0
0
0
0
0
1
1
1
1
1
1
0
0
1
1
1
1
0
0
1
1
1
1
0
1
0
0
1
1
0
1
0
0
1
1
X
X
0
1
0
1
X
X
0
1
0
1
Serial
Serial
Synchronous Serial data input, A- and B-Parallel data outputs disabled.
Synchronous Serial data input, B-Parallel data output.
Parallel B Synchronous Parallel data inputs, A-Parallel data outputs disabled.
Parallel B Asynchronous Parallel data inputs, A-Parallel data outputs disabled.
Parallel A-Parallel data inputs disabled, B-Parallel data outputs, synchronous data recirculation.
Parallel A-Parallel data inputs disabled, B-Parallel data outputs, asynchronous data recirculation.
Serial
Serial
Synchronous Serial data input, A-Parallel data output.
Synchronous Serial data input, B-Parallel data output.
Parallel B Synchronous Parallel data input, A-Parallel data output.
Parallel B Asynchronous Parallel data input, A-Parallel data output.
Parallel A Synchronous Parallel data input, B-Parallel data output.
Parallel A Asynchronous Parallel data input, B-Parallel data output.
e
X
Don’t Care
e
*For synchronous operation (serial mode or when A/S
0 in parallel mode), outputs change state at positive transition of the clock.
10
Physical Dimensions inches (millimeters)
Ceramic Dual-In-Line Package (J)
Order Number CD4034BMJ or CD4034BCJ
NS Package Number J24A
11
Physical Dimensions inches (millimeters) (Continued)
Molded Dual-In-Line Package (N)
Order Number CD4034BMN or CD4034BCN
NS Package Number N24A
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and whose
failure to perform, when properly used in accordance
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
National Semiconductor
Corporation
National Semiconductor
Europe
National Semiconductor
Hong Kong Ltd.
National Semiconductor
Japan Ltd.
a
1111 West Bardin Road
Arlington, TX 76017
Tel: 1(800) 272-9959
Fax: 1(800) 737-7018
Fax:
(
49) 0-180-530 85 86
@
13th Floor, Straight Block,
Ocean Centre, 5 Canton Rd.
Tsimshatsui, Kowloon
Hong Kong
Tel: (852) 2737-1600
Fax: (852) 2736-9960
Tel: 81-043-299-2309
Fax: 81-043-299-2408
Email: cnjwge tevm2.nsc.com
a
a
a
a
Deutsch Tel:
English Tel:
Fran3ais Tel:
Italiano Tel:
(
(
(
(
49) 0-180-530 85 85
49) 0-180-532 78 32
49) 0-180-532 93 58
49) 0-180-534 16 80
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
相关型号：
CD4034BNSR
4000/14000/40000 SERIES, 8-BIT BIDIRECTIONAL PARALLEL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PDSO24, GREEN, PLASTIC, SOP-24
TI
CD4034BNSRE4
4000/14000/40000 SERIES, 8-BIT BIDIRECTIONAL PARALLEL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PDSO24, GREEN, PLASTIC, SOP-24
TI
CD4034BPW
4000/14000/40000 SERIES, 8-BIT BIDIRECTIONAL PARALLEL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PDSO24, GREEN, PLASTIC, TSSOP-24
TI
CD4034BPWG4
4000/14000/40000 SERIES, 8-BIT BIDIRECTIONAL PARALLEL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PDSO24, GREEN, PLASTIC, TSSOP-24
TI
CD4034BPWR
4000/14000/40000 SERIES, 8-BIT BIDIRECTIONAL PARALLEL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PDSO24, GREEN, PLASTIC, TSSOP-24
TI
CD4034BPWRE4
4000/14000/40000 SERIES, 8-BIT BIDIRECTIONAL PARALLEL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PDSO24, GREEN, PLASTIC, TSSOP-24
TI
©2020 ICPDF网 联系我们和版权申明