CD4034BMS [INTERSIL]
CMOS 8-Stage Static Bidirectional Parallel/Serial Input/Output Bus Register; CMOS 8级静态双向并行/串行输入/输出总线寄存器
| 型号： | CD4034BMS |
| 厂家： | 
Intersil |
| 描述： | CMOS 8-Stage Static Bidirectional Parallel/Serial Input/Output Bus Register |
| 文件： | 总14页 (文件大小：150K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CD4034BMS
CMOS 8-Stage Static Bidirectional Parallel/Serial
Input/Output Bus Register
December 1992
Features
Description
• High Voltage Types (20V Rating)
• Bidirectional Parallel Data Input
• Parallel or Serial Inputs/Parallel Outputs
CD4034BMS is a static eight-stage parallel-or serial-input
parallel-output register. It can be used to:
1) bidirectionally transfer parallel information between two
buses, 2) convert serial data to parallel form and direct the
• Asynchronous or Synchronous Parallel Data Loading
parallel data to either of two buses, 3) store (recirculate) par-
allel data, or 4) accept parallel data from either of two buses
and convert that data to serial form. Inputs that control the
operations include a single-phase CLOCK (CL), A DATA
ENABLE (AE), ASYNCHRONOUS/SYNCHRONOUS (A/S),
A-BUS-TO-B-BUS/B-BUS-TO-A-BUS (A/B), and PARAL-
LEL/SERIAL (P/S).
• Parallel Data-Input Enable on “A” Data Lines (3-State
Output)
• Data Recirculation for Register Expansion
• Multipackage Register Expansion
• Fully Static Operation DC-to-10MHz (typ.) at
VDD = 10V
Data inputs include 16 bidirectional parallel data lines of
which the eight A data lines are inputs (3-state outputs) and
the B data lines are outputs (inputs) depending on the signal
level on the A/B input. In addition, an input for SERIAL DATA
is also provided.
• Standardized Symmetrical Output Characteristics
• 100% Tested for Quiescent Current at 20V
• 5V, 10V and 15V Parametric Ratings
All register stages are D-type master-slave flip-flops with
separate master and slave clock inputs generated internally
to allow synchronous or asynchronous data transfer from
master to slave. Isolation from external noise and the effects
of loading is provided by output buffering.
• Maximum Input Current of 1µA at 18V Over Full
Package-Temperature Range;
- 100nA at 18V and +25oC
• Noise Margin (Over Full Package Temperature Range):
- 1V at VDD = 5V
- 2V at VDD = 10V
Pinout
- 2.5V at VDD = 15V
CD4034BMS
TOP VIEW
• Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of
‘B’ Series CMOS Devices”
1
2
3
4
5
6
7
8
9
24
VDD
8
7
6
5
4
3
2
23 8
Applications
22 7
• Parallel Input/Parallel Output, Serial Input/Parallel Out-
put, Serial Input/Serial Output Register
21 6
20 5
• Shift Right/Shift Left Register
• Shift Right/Shift Left With Parallel Loading
• Address Register
19 4
18 3
17 2
1
“A” ENABLE
16 1
• Buffer Register
SERIAL INPUT 10
A/B 11
15 CLOCK
14 A/S
13 P/S
• Bus System Register with Enable Parallel Lines at Bus
Side
VSS 12
• Double Bus Register System
• Up-Down Johnson or Ring Counter
• Pseudo-Random Code Generators
• Sample and Hold Register (Storage, Counting,
Display)
• Frequency and Phase Comparator
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
File Number 3307
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
7-837
CD4034BMS
Parallel Operation
Functional Diagram
A high P/S input signal allows data transfer into the register
via the parallel data lines synchronously with the positive
transition of the clock provided the A/S input is low. If the A/S
input is high the transfer is independent of the clock. The
direction of data flow is controlled by the A/B input. When
this signal is high the A data lines are inputs (and B data
lines are outputs); a low A/B signal reverses the direction of
data flow.
SI
AE
STEERING
LOGIC
A/B
A/S
P/S
CL
The AE input is an additional feature which allows many reg-
isters to feed data to a common bus. The A DATA lines are
enabled only when this signal is high.
SI
Q
A1
B1
SI
Data storage through recirculation of data in each register
stage is accomplished by making the A/B signal high and the
AE signal low.
6
STAGES
Serial Operation
A low P/S signal allows serial data to transfer into the regis-
ter synchronously with the positive transition of the clock.
The A/S input is internally disabled when the register is in
the serial mode (asynchronous serial operation is not
allowed).
Q
SI
A8
B8
The serial data appears as output data on either the B lines
(when A/B is high) or the A lines (when A/B is low and the
AE signal is high).
Register expansion can be accomplished by simply cascad-
ing CD4034BMS packages.
The CD4034BMS is supplied in these 24 lead outline pack-
ages:
Braze Seal DIP
H4V
Ceramic Flatpack H4P
7-838
Specifications CD4034BMS
Absolute Maximum Ratings
Reliability Information
DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V
(Voltage Referenced to VSS Terminals)
Thermal Resistance . . . . . . . . . . . . . . . .
Ceramic DIP and FRIT Package . . . . . 80 C/W
Flatpack Package . . . . . . . . . . . . . . . . 70 C/W
θ
θ
jc
ja
o
o
20 C/W
o
o
Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V
DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA
20 C/W
o
Maximum Package Power Dissipation (PD) at +125 C
o
o
o
o
Operating Temperature Range. . . . . . . . . . . . . . . . -55 C to +125 C
Package Types D, F, K, H
For TA = -55 C to +100 C (Package Type D, F, K) . . . . . . 500mW
o
o
For TA = +100 C to +125 C (Package Type D, F, K) . . . . .Derate
o
o
o
Storage Temperature Range (TSTG) . . . . . . . . . . . -65 C to +150 C
Linearity at 12mW/ C to 200mW
Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW
For TA = Full Package Temperature Range (All Package Types)
o
Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265 C
At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for
10s Maximum
o
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175 C
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
MIN MAX UNITS
GROUP A
SUBGROUPS
PARAMETER
Supply Current
SYMBOL
CONDITIONS (NOTE 1)
TEMPERATURE
o
IDD
VDD = 20V, VIN = VDD or GND
1
+25 C
-
10
1000
10
µA
µA
µA
nA
nA
nA
nA
nA
nA
mV
V
o
2
+125 C
-
o
VDD = 18V, VIN = VDD or GND
3
-55 C
-
o
Input Leakage Current
Except A and B Lines
IIL
VIN = VDD or GND
VIN = VDD or GND
VDD = 20
1
+25 C
-100
-
o
2
+125 C
-1000
-
o
VDD = 18V
VDD = 20
3
-55 C
-100
-
o
Input Leakage Current
Except A and B Lines
IIH
1
+25 C
-
-
-
-
100
1000
100
50
o
2
+125 C
o
VDD = 18V
3
-55 C
o
o
o
Output Voltage
VOL15 VDD = 15V, No Load
VOH15 VDD = 15V, No Load (Note 3)
1, 2, 3
+25 C, +125 C, -55 C
o
o
o
Output Voltage
1, 2, 3
+25 C, +125 C, -55 C 14.95
-
o
Output Current (Sink)
Output Current (Sink)
Output Current (Sink)
IOL5
IOL10
IOL15
VDD = 5V, VOUT = 0.4V
VDD = 10V, VOUT = 0.5V
VDD = 15V, VOUT = 1.5V
1
+25 C
0.53
1.4
3.5
-
-
mA
mA
mA
mA
mA
mA
mA
V
o
1
+25 C
-
o
1
+25 C
-
o
Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V
Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V
Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V
Output Current (Source) IOH15 VDD = 15V, VOUT = 13.5V
1
+25 C
-0.53
-1.8
-1.4
-3.5
-0.7
2.8
o
1
+25 C
-
o
1
+25 C
-
o
1
1
+25 C
-
o
N Threshold Voltage
P Threshold Voltage
Functional
VNTH
VPTH
F
VDD = 10V, ISS = -10µA
+25 C
-2.8
0.7
o
VSS = 0V, IDD = 10µA
1
+25 C
V
o
VDD = 2.8V, VIN = VDD or GND
VDD = 20V, VIN = VDD or GND
VDD = 18V, VIN = VDD or GND
VDD = 3V, VIN = VDD or GND
VDD = 5V, VOH > 4.5V, VOL < 0.5V
7
+25 C
VOH > VOL <
VDD/2 VDD/2
V
o
7
+25 C
o
8A
8B
1, 2, 3
+125 C
o
-55 C
o
o
o
Input Voltage Low
(Note 2)
VIL
VIH
VIL
+25 C, +125 C, -55 C
-
1.5
V
V
V
V
o
o
o
Input Voltage High
(Note 2)
VDD = 5V, VOH > 4.5V, VOL < 0.5V
1, 2, 3
1, 2, 3
1, 2, 3
+25 C, +125 C, -55 C 3.5
-
4
-
o
o
o
Input Voltage Low
(Note 2)
VDD = 15V, VOH > 13.5V,
VOL < 1.5V
+25 C, +125 C, -55 C
-
o
o
o
Input Voltage High
(Note 2)
VIH
IOZL
VDD = 15V, VOH > 13.5V,
VOL < 1.5V
+25 C, +125 C, -55 C
11
o
Tri-State Output
Leakage
VIN = VDD or GND
VOUT = 0V
VDD = 20V
1
2
3
1
2
3
+25 C
-0.4
-
-
µA
µA
µA
µA
µA
µA
o
+125 C
-12
o
VDD = 18V
VDD = 20V
-55 C
-0.4
-
o
Tri-State Output
Leakage
IOZH
VIN = VDD or GND
VOUT = VDD
+25 C
-
-
-
0.4
12
0.4
o
+125 C
o
VDD = 18V
-55 C
NOTES: 1. All voltages referenced to device GND, 100% testing being 3. Foraccuracy, voltageismeasureddifferentiallytoVDD. Limit
implemented.
is 0.050V max.
2. Go/No Go test with limits applied to inputs.
7-839
Specifications CD4034BMS
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
MIN
GROUP A
SUBGROUPS TEMPERATURE
PARAMETER
SYMBOL
CONDITIONS
MAX
700
945
400
540
UNITS
ns
o
Propagation Delay
Parallel In to Parallel Out
TPHL
TPLH
VDD = 5V, VIN = VDD or GND
(Notes 1, 2)
9
+25 C
-
-
-
-
o
o
10, 11
9
+125 C, -55 C
ns
o
Propagation Delay
3 State
AE to Out ‘A’
TPLZ
TPHZ
VDD = 5V, VIN = VDD or GND
(Notes 2, 3)
+25 C
ns
o
o
10, 11
+125 C, -55 C
ns
o
Propagation Delay
3-State AE to Out ‘A’
TPZL
TPZH
VDD = 5V, VIN = VDD or GND
(Notes 2, 3)
9
+25 C
-
400
540
200
270
-
ns
ns
o
o
10, 11
9
+125 C, -55 C
-
o
Transition Time
TTHL
TTLH
VDD = 5V, VIN = VDD or GND
(Notes 1, 2)
+25 C
-
-
ns
o
o
10, 11
9
+125 C, -55 C
ns
o
Maximum Clock Input
Frequency
FCL
VDD = 5V, VIN = VDD or GND
(Note 2)
+25 C
2
MHz
MHz
o
o
10, 11
+125 C, -55 C
1.48
-
NOTES:
1. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
o
o
2. -55 C and +125 C limits guaranteed, 100% testing being implemented.
3. CL = 50pF, RL = 1K, Input TR, TF < 20ns.
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER
Supply Current
SYMBOL
CONDITIONS
NOTES
TEMPERATURE
MIN
MAX
5
UNITS
µA
o
o
IDD
VDD = 5V, VIN = VDD or GND
1, 2
-55 C, +25 C
-
-
-
-
-
-
-
o
+125 C
150
10
µA
o
o
VDD = 10V, VIN = VDD or GND
VDD = 15V, VIN = VDD or GND
1, 2
1, 2
-55 C, +25 C
µA
o
+125 C
300
10
µA
o
o
-55 C, +25 C
µA
o
+125 C
600
50
µA
o
o
Output Voltage
Output Voltage
Output Voltage
Output Voltage
Output Current (Sink)
VOL
VOL
VOH
VOH
IOL5
VDD = 5V, No Load
VDD = 10V, No Load
VDD = 5V, No Load
VDD = 10V, No Load
VDD = 5V, VOUT = 0.4V
1, 2
1, 2
1, 2
1, 2
1, 2
+25 C, +125 C,
mV
o
-55 C
o
o
+25 C, +125 C,
-
50
-
mV
V
o
-55 C
o
o
+25 C, +125 C,
4.95
9.95
o
-55 C
o
o
+25 C, +125 C,
-
V
o
-55 C
o
+125 C
0.36
-
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
o
-55 C
0.64
-
-
o
Output Current (Sink)
Output Current (Sink)
Output Current (Source)
Output Current (Source)
Output Current (Source)
IOL10
IOL15
VDD = 10V, VOUT = 0.5V
VDD = 15V, VOUT = 1.5V
1, 2
1, 2
1, 2
1, 2
1, 2
+125 C
0.9
o
-55 C
1.6
-
o
+125 C
2.4
-
o
-55 C
4.2
-
o
IOH5A VDD = 5V, VOUT = 4.6V
IOH5B VDD = 5V, VOUT = 2.5V
+125 C
-
-
-
-
-
-
-0.36
-0.64
-1.15
-2.0
-0.9
-1.6
o
-55 C
o
+125 C
o
-55 C
o
IOH10
VDD = 10V, VOUT = 9.5V
+125 C
o
-55 C
7-840
Specifications CD4034BMS
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)
LIMITS
MIN
PARAMETER
SYMBOL
CONDITIONS
NOTES
TEMPERATURE
MAX
-2.4
-4.2
3
UNITS
mA
o
Output Current (Source)
IOH15
VDD =15V, VOUT = 13.5V
1, 2
+125 C
-
-
-
o
-55 C
mA
o
o
Input Voltage Low
Input Voltage High
VIL
VDD = 10V, VOH > 9V,
VOL < 1V
1, 2
1, 2
+25 C, +125 C,
V
o
-55 C
o
o
VIH
VDD = 10V, VOH > 9V,
VOL < 1V
+25 C, +125 C,
+7
-
V
o
-55 C
o
Propagation Delay
Parallel In to Parallel Out
TPHL
TPLH
VDD = 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V
VDD = 10V
VDD = 15V
VDD = 10V
VDD = 15V
VDD = 10V
VDD = 15V
VDD = 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V
VDD = 5V
VDD = 10V
VDD = 15V
Any Input
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3, 4
1, 2, 3, 4
1, 2, 3, 4
1, 2, 3, 4
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2
+25 C
-
-
240
170
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
µs
ns
ns
ns
pF
o
+25 C
o
Propagation Delay
Serial to Parallel Out
TPHL
TPLH
+25 C
700
-
o
+25 C
240
170
160
120
160
120
100
80
o
+25 C
-
o
Propagation Delay 3-State
AE to Out ‘A’
TPLZ
TPHZ
+25 C
-
o
+25 C
-
o
Propagation Delay 3-State
AE to Out ‘A’
TPZL
TPZH
+25 C
-
o
+25 C
-
o
Transition Time
TTLH
TTHL
+25 C
-
o
+25 C
-
o
Maximum Clock Input
Frequency
FCL
TS
+25 C
5
7
-
-
o
+25 C
-
o
Minimum Data Setup
Time
Serial Data to Clock
+25 C
160
60
o
+25 C
-
o
+25 C
-
40
o
Minimum Data Setup
Time Parallel Data to
Clock
TS
+25 C
-
50
o
+25 C
-
30
o
+25 C
-
20
o
Minimum Clock Pulse
Width
TW
+25 C
-
250
100
70
o
+25 C
-
o
+25 C
-
o
Maximum Clock Rise and
Fall Time (Note 5)
TRCL
TFCL
+25 C
-
15
o
+25 C
-
15
o
+25 C
-
15
o
Minimum High Level
Pulse Width AE, P/S, A/S
TW
+25 C
-
350
140
80
o
+25 C
-
o
+25 C
-
o
Input Capacitance
NOTES:
CIN
+25 C
-
7.5
1. All voltages referenced to device GND.
2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized
on initial design release and upon design changes which would affect these characteristics.
3. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
4. CL = 50pF, RL = 1K, Input TR, TF < 20ns.
5. If more than one unit is cascaded, tRCL should be made less than or equal to the sum of the transition time and the fixed propagation
delay of the output of the driving stage for the estimated capacitive load.
7-841
Specifications CD4034BMS
TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER
Supply Current
SYMBOL
IDD
CONDITIONS
NOTES
1, 4
TEMPERATURE
MIN
MAX
25
UNITS
o
VDD = 20V, VIN = VDD or GND
VDD = 10V, ISS = -10µA
VDD = 10V, ISS = -10µA
+25 C
-
-2.8
-
µA
V
o
N Threshold Voltage
VNTH
∆VTN
1, 4
+25 C
-0.2
±1
o
N Threshold Voltage
Delta
1, 4
+25 C
V
o
P Threshold Voltage
VTP
VSS = 0V, IDD = 10µA
VSS = 0V, IDD = 10µA
1, 4
1, 4
+25 C
0.2
-
2.8
V
V
o
P Threshold Voltage
Delta
∆VTP
+25 C
±1
o
Functional
F
VDD = 18V, VIN = VDD or GND
VDD = 3V, VIN = VDD or GND
VDD = 5V
1
+25 C
VOH >
VDD/2
VOL <
VDD/2
V
o
Propagation Delay Time
TPHL
TPLH
1, 2, 3, 4
+25 C
-
1.35 x
ns
o
+25 C
Limit
o
NOTES: 1. All voltages referenced to device GND.
2. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
3. See Table 2 for +25 C limit.
4. Read and Record
O
TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25 C
PARAMETER
Supply Current - MSI-2
Output Current (Sink)
Output Current (Source)
SYMBOL
IDD
DELTA LIMIT
± 1.0µA
IOL5
± 20% x Pre-Test Reading
± 20% x Pre-Test Reading
IOH5A
TABLE 6. APPLICABLE SUBGROUPS
MIL-STD-883
CONFORMANCE GROUP
Initial Test (Pre Burn-In)
Interim Test 1 (Post Burn-In)
Interim Test 2 (Post Burn-In)
PDA (Note 1)
METHOD
100% 5004
100% 5004
100% 5004
100% 5004
100% 5004
100% 5004
100% 5004
Sample 5005
Sample 5005
Sample 5005
Sample 5005
GROUP A SUBGROUPS
READ AND RECORD
IDD, IOL5, IOH5A
1, 7, 9
1, 7, 9
IDD, IOL5, IOH5A
IDD, IOL5, IOH5A
1, 7, 9
1, 7, 9, Deltas
Interim Test 3 (Post Burn-In)
PDA (Note 1)
1, 7, 9
IDD, IOL5, IOH5A
1, 7, 9, Deltas
Final Test
2, 3, 8A, 8B, 10, 11
1, 2, 3, 7, 8A, 8B, 9, 10, 11
1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas
1, 7, 9
Group A
Group B
Subgroup B-5
Subgroup B-6
Subgroups 1, 2, 3, 9, 10, 11
Subgroups 1, 2, 3
Group D
1, 2, 3, 8A, 8B, 9
NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2.
TABLE 7. TOTAL DOSE IRRADIATION
TEST
READ AND RECORD
MIL-STD-883
METHOD
CONFORMANCE GROUPS
PRE-IRRAD
POST-IRRAD
PRE-IRRAD
POST-IRRAD
Table 4
Group E Subgroup 2
5005
1, 7, 9
Table 4
1, 9
7-842
Specifications CD4034BMS
TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS
OSCILLATOR
FUNCTION
OPEN
GROUND
VDD
9V ± -0.5V
50kHz
25kHz
Static Burn-In 1
Note 1
1 - 8
12, 15 - 23
9 - 11, 13, 14, 24
Static Burn-In 2
Note 1
1 - 8
-
12
1 - 8, 11 - 14
12
9 - 11, 13 - 24
9, 24
Dynamic Burn-In
Note 1
16 - 23
15
10
Irradiation
Note 2
1 - 8
9 - 11, 13 - 24
NOTE:
1. Each pin except VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V
2. Each pin except VDD and GND will have a series resistor of 47K ± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures,
VDD = 10V ± 0.5V
Logic Diagram
*
N
N
AB
M
M
M
L
L
*
K
K
AE
VDD
P/S
*
*
P/S
P/S
A/S
CLS
CLS
CLM
VSS
*INPUTS PROTECTED BY
CMOS PROTECTION
NETWORK
*
CLM
CLOCK
FLIP-FLOP TRUTH TABLE
INPUTS
OUTPUT
CLM
CLS
D
0
0
0
X
1
1
1
Q
0
0
Invalid Condition
0
1
1
Invalid Condition
X = Don’t Care
1 = High Level
0 = Low Level
7-843
CD4034BMS
trCL
tfCL
VDD
90%
50%
10%
CLOCK
INPUT
0
0
“A” OR “B”
DATA
INPUTS
50%
INPUT
**
**
tSHL
tTLH
tTHL
tSLH
“B” OR “A”
DATA
OUTPUTS
VDD
0
tTLH
tTHL
90%
50%
10%
VDD
90%
50%
10%
OUTPUT
0
tPLH
tPHL
tPLH
tPHL
*Input refers to any of the “A” or “B” data inputs, “A” ENABLE,
SERIAL INPUT, A/B, P/S, or A/S inputs
**tSLH and tSHL are Set-Up times
FIGURE 2. SYNCHRONOUS OPERATION PROPAGATION DE-
LAY TIMES, TRANSITION TIMES, AND SET-UP
TIMES
FIGURE 1. ASYNCHRONOUS OPERATION PROPAGATION
DELAY TIME AND TRANSITION TIME
CLOCK
A ENABLE
P/S
A/B
A/S
SERIAL DATA
A1
A2
A3
A4
A5
A6
A7
A8
B1
B2
B3
B4
B5
B6
B7
B8
B DATA LINES ARE OUTPUTS
A DATA
LINES ARE
OUTPUTS
FIGURE 3. TIMING DIAGRAM
7-844
CD4034BMS
Typical Performance Characteristics
AMBIENT TEMPERATURE (TA) = +25oC
AMBIENT TEMPERATURE (TA) = +25oC
15.0
30
25
GATE-TO-SOURCE VOLTAGE (VGS) = 15V
GATE-TO-SOURCE VOLTAGE (VGS) = 15V
12.5
10.0
7.5
20
15
10V
10V
5.0
10
5
2.5
5V
5V
0
5
10
15
0
5
10
15
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
FIGURE 4. TYPICAL OUTPUT LOW (SINK) CURRENT
CHARACTERISTICS
FIGURE 5. MINIMUM OUTPUT LOW (SINK) CURRENT
CHARACTERISTICS
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
-15
-10
-5
0
-15
-10
-5
0
0
0
AMBIENT TEMPERATURE (TA) = +25oC
AMBIENT TEMPERATURE (TA) = +25oC
GATE-TO-SOURCE VOLTAGE (VGS) = -5V
-5
GATE-TO-SOURCE VOLTAGE (VGS) = -5V
-10
-15
-20
-25
-30
-5
-10V
-10V
-10
-15
-15V
-15V
FIGURE 6. TYPICAL OUTPUT HIGH (SOURCE) CURRENT
CHARACTERISTICS
FIGURE 7. MINIMUM OUTPUT HIGH (SOURCE) CURRENT
CHARACTERISTICS
106
AMBIENT TEMPERATURE (TA) = +25oC
8
AMBIENT TEMPERATURE (TA) = +25oC
6
4
2
SUPPLY VOLTAGE (VDD) = 15V
105
8
6
200
4
10V
10V
2
SUPPLY VOLTAGE (VDD) = 5V
150
104
8
6
4
5V
2
100
103
102
10V
15V
8
6
4
50
CL = 50pF
CL = 15pF
2
0
2
4
6 8
2
4
6 8
102
2
4
6 8
103
2
4
6 8
104
2
4
6 8
105
0
20
40
60
80
100
1
10
INPUT FREQUENCY (fI) (kHz)
LOAD CAPACITANCE (CL) (pF)
FIGURE 8. TYPICAL TRANSITION TIME AS A FUNCTION OF
LOAD CAPACITANCE
FIGURE 9. TYPICAL DYNAMIC POWER DISSIPATION AS A
FUNCTION OF CLOCK FREQUENCY
7-845
CD4034BMS
Typical Performance Characteristics (Continued)
AMBIENT TEMPERATURE (TA) = +25oC
700
600
500
SUPPLY VOLTAGE (VDD) = 5V
400
300
200
100
10V
15V
0
20
30
40
50
60
70
80
90
100
LOAD CAPACITANCE (CL) (pF)
FIGURE 10. TYPICAL PROPAGATION DELAY TIME AS A FUNC-
TION OF LOAD CAPACITANCE [A(B) PARALLEL
DATA INPUT TO B(A) PARALLEL DATA OUTPUT,
SYNCHRONOUS OR ASYNCHRONOUS])
7-846
CD4034BMS
1 OF 8 STAGES
K
An
p
n
VDD
M
Q’
Q’
VSS
K
PROTECTION NETWORK
ON ALL “A” AND “B”
DATA INPUTS
P/S
CLM
CLS
D
p
n
p
n
p
n
M
N
SERIAL
DATA
VSS
VDD
CLM
CLS
P/S
CLM
CLS
VDD
p
n
p
n
Q’
N
CLM
CLS
L
VSS
p
n
VSS
Q (TO NEXT STAGE D)
PROTECTION NETWORK
ON SERIAL DATA INPUT
Bn
L
FIGURE 11. REGISTER STAGE LOGIC DIAGRAM (1 OF 8 STAGES)
TRUTH TABLE REGISTER INPUT-LEVELS AND
RESULTING REGISTER OPERATION
“A”
ENABLE
P/S
0
A/B
0
A/S
X
OPERATION*
0
0
0
0
0
Serial Mode; Synch. Serial Data Input, “A” Parallel Data Outputs Disabled
Serial Mode; Synch. Serial Data Input, “B” Parallel Data Output
0
1
X
1
0
0
Parallel Mode; “B” Synch. Parallel Data Inputs, “A” Parallel Data Outputs Disabled
Parallel Mode; “B” Asynch. Parallel Data Inputs, “A” Parallel Data Outputs Disabled
1
0
1
1
1
0
Parallel Mode; “A” Parallel Data Inputs Disabled, “B” Parallel Data Outputs, Synch. Data
Recirculation
0
1
1
1
Parallel Mode; “A” Parallel Data Inputs Disabled, “B” Parallel Data Outputs, Asynch. Data
Recirculation
1
1
1
1
1
1
0
0
1
1
1
1
0
1
0
0
1
1
X
X
0
1
0
1
Serial Mode; Synch. Serial Data Input, “A” Parallel Data Output
Serial Mode; Synch. Serial Data Input, “B” Parallel Data Output
Parallel Mode; “B” Synch. Parallel Data Input, “A” Parallel Data Output
Parallel Mode; “B” Asynch. Parallel Data Input, “A” Parallel Data Output
Parallel Mode; “A” Synch, Parallel Data Input, “B” Parallel Data Output
Parallel Mode; “A” Asynch. Parallel Data Input, “B” Parallel Data Output
*Outputs change at positive transition of clock in the serial mode and when the A/S control input is “low” in the parallel mode. During
transfer from parallel to serial operation A/S should remain low in order to prevent DS transfer into Flip Flops.
1 = High Level
0 = Low Level
X = Don’t Care
7-847
CD4034BMS
Applications
VDD
VDD
AE
SI
A/B
A/S
CL
P/S
AE
SI
A/B
A/S
CL
P/S
A PARALLEL
DATA
CD4034
A PARALLEL
DATA
CD4034
SERIAL
DATA
VDD
VDD
B PARALLEL
DATA
B PARALLEL
DATA
SERIAL
DATA
SERIAL
DATA
P/S
A/S
CL
FIGURE 12. 16-BIT PARALLEL IN/PARALLEL OUT, PARALLEL IN/SERIAL OUT,
SERIAL IN/PARALLEL OUT SERIAL IN/SERIAL OUT REGISTER
“A” ENABLE
AE
SI
A/B
A/S
CL
P/S
AE
SI
A/B
A/S
CL
P/S
A PARALLEL
DATA
CD4034
A PARALLEL
DATA
CD4034
SERIAL
DATA
B PARALLEL
DATA
B PARALLEL
DATA
SERIAL
DATA
SERIAL
DATA
A/B
CL
FIGURE 13. 16-BIT SERIAL IN/GATED PARALLEL OUT REGISTER
BUS LINES
DOUBLE - BUS SYSTEM
(ENABLE INPUTS ON BOTH SIDES)
(SINGLE)
P/S
1
AE
1
AE
1
P/S
1
P/S
1
AE
1
CD4034
W REG
2
3
4
5
6
7
8
2
3
4
5
6
7
8
2
3
2
3
4
5
6
7
8
2
3
4
5
6
7
8
2
3
X(1)
REG
X(2)
REG
TO 2ND
BUS
SYSTEM
MEMORY
UNIT
4
5
6
7
4
B
5
6
7
8
A
B
B
A
A
CD4034
CD4034
8
SI A/B A/S CL
SI A/B A/S CL
SI A/B A/S CL
SI A/B A/S CL
SI A/B A/S CL
P/S
P/S
AE
AE
1
1
2
3
1
2
3
4
5
6
7
8
1
2
3
2
3
4
5
6
7
8
Z REG
Y REG
ARITHMETIC
UNIT
PERIPHERAL
UNIT
4
5
6
7
4
5
6
7
B
B
A
A
CD4034
CD4034
8
8
THE “A” ENABLE (AE) AND A/B SIGNALS CONTROL ALL
COMBINATIONS OF TRANSFER BETWEEN THE REGISTERS
AND BUS SYSTEMS
FIGURE 14. SINGLE AND DOUBLE-BUS SYSTEMS
7-848
CD4034BMS
Applications (Continued)
SHIFT LEFT OUTPUT
“A” ENABLE
AE
SHIFT LEFT/
SHIFT RIGHT
P/S
“A” PARALLEL DATA
“A” PARALLEL DATA
SHIFT RIGHT
OUTPUT
SHIFT RIGHT
INPUT
AE 1
8
AE 1
8
REG. 2
SI
SI
CD4034
P/S
P/S
REG. 1
CD4034
CLOCK
A/S
CL
A/S
CL
1
1
A/B
A/B
SHIFT
LEFT INPUT*
A/S
PARALLEL
ENTRY
A/S
CL
AE
AE 1
A PARALLEL DATA
8
8
AE 1
A PARALLEL DATA
8
8
SI
SI
P/S
P/S
REG. 3
CD4034
REG. 4
CD4034
A/S
CL
A/S
CL
VDD
VDD
B PARALLEL DATA
B PARALLEL DATA
1
1
A/B
A/B
FIGURE 15. SHIFT RIGHT/SHIFT LEFT WITH PARALLEL INPUTS
A “High” (“Low”) on the shift Left/Shift Right input allows Other logic schemes may be used in place of registers 3 and
serial data on the Shift Left Input (Shift Right Input) to enter 4 for parallel loading.
the register on the positive transition of the clock signal. A
When parallel inputs are not used Reg. 3 and 4 and associ-
“high” on the “A” Enable Input disables the “A” parallel data
ated logic are not required.
lines Reg. 1 and 2 and enables the “A” data lines on regis-
ters 3 and 4 and allows parallel data into registers 1 and 2.
* Shift left input must be disabled during parallel entry.
SAMPLE/HOLD
AE
AE
SI
1
1
8
8
SERIAL
A PARALLEL DATA
SI
“A” PARALLEL DATA
CD4034
DATA
SERIAL DATA
VDD
VDD
A/B
A/S
CL
A/B
A/S
CL
P/S
CD4034
A/S
CLOCK
B PARALLEL DATA
CLOCK
“B” PARALLEL DATA
P/S
CD4016
P/S
TO DISPLAY ETC
N = 1 - 8
SERIAL
OUTPUT
CD4016
N STAGE SELECTION
FIGURE 17. SAMPLE AND HOLD REGISTER - SERIAL/PARAL-
LEL IN - PARALLEL OUT
FIGURE 16. N-STAGE SHIFT REGISTER WITH FIXED SERIAL
OUTPUT LINE
7-849
CD4034BMS
Chip Dimensions and Pad Layout
Dimension in parenthesis are in millimeters and are
derived from the basic inch dimensions as indicated.
Grid graduations are in mils (10-3 inch).
METALLIZATION: Thickness: 11kÅ − 14kÅ, AL.
PASSIVATION: 10.4kÅ - 15.6kÅ, Silane
BOND PADS: 0.004 inches X 0.004 inches MIN
DIE THICKNESS: 0.0198 inches - 0.0218 inches
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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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850
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