CD4035 [NSC]
4-Bit Parallel-In/Parallel-Out Shift Register; 4位并行输入/并行输出移位寄存器
| 型号： | CD4035 |
| 厂家： | 
National Semiconductor |
| 描述： | 4-Bit Parallel-In/Parallel-Out Shift Register |
| 文件： | 总6页 (文件大小：142K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
February 1988
CD4035BM/CD4035BC
4-Bit Parallel-In/Parallel-Out Shift Register
General Description
Features
Y
Wide supply voltage range
3.0V to 15V
0.45 V (typ.)
The CD4035B 4-bit parallel-in/parallel-out shift register is a
monolithic complementary MOS (CMOS) integrated circuit
constructed with P- and N-channel enhancement mode
transistors. This shift register is a 4-stage clocked serial reg-
ister having provisions for synchronous parallel inputs to
each stage and serial inputs to the first stage via JK logic.
Register stages 2, 3, and 4 are coupled in a serial ‘‘D’’ flip-
flop configuration when the register is in the serial mode
(parallel/serial control low).
Y
High noise immunity
DD
Y
Low power TTL
compatibility
Fan out of 2 driving 74L
or 1 driving 74LS
Y
4-stage clocked operation
Y
Synchronous parallel entry on all 4 stages
JK inputs on first stage
Y
Y
Y
Y
Y
Y
Y
Asynchronous true/complement control on all outputs
Reset control
Parallel entry via the ‘‘D’’ line of each register stage is per-
mitted only when the parallel/serial control is ‘‘high’’.
Static flip-flop operation; master/slave configuration
Buffered outputs
In the parallel or serial mode, information is transferred on
positive clock transitions.
Low power dissipation
High speed
5 mW (typ.) (ceramic)
to 5 MHz
When the true/complement control is ‘‘high’’, the true con-
tents of the register are available at the output terminals.
When the true/complement control is ‘‘low’’, the outputs are
the complements of the data in the register. The true/com-
plement control functions asynchronously with respect to
the clock signal.
Applications
Y
Y
Y
Y
Y
Automotive
Alarm systems
Industrial controls
Remote metering
Computers
Y
Data terminals
Y
Instrumentation
Y
Medical electronics
JK input logic is provided on the first stage serial input to
minimize logic requirements particularly in counting and se-
quence-generation applications. With JK inputs connected
together, the first stage becomes a ‘‘D’’ flip-flop. An asyn-
chronous common reset is also provided.
Logic Diagram
TL/F/5964–1
e
e
e
e
e
P/S
T/C
*TG
0
1
serial mode
true outputs
Input to output is:
a) A bidirectional low impedance when control input 1 is low and control input 2 is high.
b) An open circuit when control input 1 is high and control input 2 is low.
transmission gate
TL/F/5964–2
C
1995 National Semiconductor Corporation
TL/F/5964
RRD-B30M105/Printed in U. S. A.
Absolute Maximum Ratings (Notes 1 and 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Lead Temperature (T )
L
(Soldering, 10 seconds)
260 C
§
b
a
0.5V to 18V
Operating Conditions (Note 2)
DC Supply Voltage (V
)
DD
b
a
DC Supply Voltage (V
)
DD
3V to 15V
Input Voltage (V
IN
)
0.5V to V
0.5V
DD
b
a
65 C to 150 C
Input Voltage (V
)
0V to V V
DD
Storage Temperature Range (T )
S
§
§
IN
Operating Temperature Range (T )
A
Power Dissipation (P )
D
b
b
a
55 C to 125 C
CD4035BM
CD4035BC
Dual-In-Line
Small Outline
700 mW
500 mW
§
40 C to 85 C
§
a
§
§
DC Electrical Characteristics CD4035BM (Note 2)
b
a
a
55 C
§
Max Min
25 C
125 C
§
Typ
§
Min Max
Symbol
Parameter
Conditions
Units
Min
Max
e
e
e
e
e
e
I
Quiescent Device Current
V
DD
V
DD
V
DD
5V, V
IN
V or V
DD SS
5
0.3
0.5
1.0
5
150
300
600
mA
mA
mA
DD
10V, V
15V, V
V
DD
V
DD
or V
or V
10
20
10
20
IN
IN
SS
SS
k
1.0 mA
V
V
V
V
Low Level Output Voltage
High Level Output Voltage
Low Level Input Voltage
High Level Input Voltage
I
OL
OH
IL
l
O
l
e
e
e
V
5V
10V
15V
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
V
V
V
DD
DD
DD
V
V
k
I
1.0 mA
l
O
l
e
e
e
V
5V
10V
15V
4.95
9.95
4.95
9.95
5
4.95
9.95
V
V
V
DD
DD
DD
V
V
10
15
14.95
14.95
14.95
k
I
1.0 mA
l
O
l
e
e
e
e
O
V
5V,
10V,
15V,
V
0.5V or 4.5V
1.0V or 9.0V
1.5V or 13.5V
1.5
3.0
4.0
1.5
3.0
4.0
1.5
3.0
4.0
V
V
V
DD
DD
DD
e
e
V
V
V
O
V
O
k
I
1.0 mA
IH
l
O
l
e
e
e
e
e
e
V
5V,
10V,
15V,
V
0.5V or 4.5V
1.0V or 9.0V
3.5
7.0
3.5
7.0
3.5
7.0
V
V
V
DD
DD
DD
O
V
V
V
V
O
O
1.5V or 13.5V 11.0
11.0
11.0
e
e
e
e
e
e
I
I
I
Low Level Output Current
(Note 3)
V
V
V
5V,
10V,
15V,
V
0.4V
0.5V
1.5V
0.64
1.6
0.51
1.3
0.88
2.25
8.8
0.36
0.9
mA
mA
mA
OL
DD
DD
DD
O
V
V
O
O
4.2
3.4
2.4
e
e
e
e
e
e
b
b
b
b
b
b
b
High Level Output Current
(Note 3)
V
DD
V
DD
V
DD
5V,
10V,
15V,
V
4.6V
9.5V
0.25
0.62
0.2 0.36
0.14
0.35
mA
mA
mA
OH
IN
O
V
V
0.5
1.5
0.9
O
O
b
b
b
1.1
13.5V
1.8
3.5
b
5
e
e
e
e
b
0.1
b
b
0.1
b
1.0 mA
Input Current
V
V
15V,
15V,
V
V
0V
0.1
10
0.1
DD
IN
10b
1.0
mA
5
15V
DD
IN
DC Electrical Characteristics CD4035BC (Note 2)
b
a
a
85 C
40 C
§
25 C
§
Typ Max
§
Symbol
Parameter
Conditions
Units
Min
Max
Min
Min
Max
e
e
e
e
e
e
I
Quiescent Device Current
V
DD
V
DD
V
DD
5V, V
IN
V or V
DD SS
20
40
80
0.5
1.0
5.0
20
40
80
150
300
600
mA
mA
mA
DD
10V, V
15V, V
V
DD
V
DD
or V
or V
IN
IN
SS
SS
k
1 mA
V
Low Level Output Voltage
High Level Output Voltage
I
OL
l
O
l
e
e
e
V
5V
10V
15V
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
V
V
V
DD
DD
DD
V
V
k
V
OH
I
1 mA
l
O
l
e
e
e
V
5V
10V
15V
4.95
9.95
4.95
9.95
5
4.95
9.95
V
V
V
DD
DD
DD
V
V
10
14.95
14.95 15
14.95
2
DC Electrical Characteristics CD4035BC (Note 2) (Continued)
b
40 C
25 C
85 C
§
§
Min Max
§
Typ
Symbol
Parameter
Conditions
Units
Min
Max
Min
Max
k
V
IL
Low Level Input Voltage
I
O
1 mA
l
l
e
e
e
e
V
V
V
5V,
10V,
15V,
V
0.5V or 4.5V
1.0V or 9.0V
1.5V or 13.5V
1.5
3.0
4.0
1.5
3.0
4.0
1.5
3.0
4.0
V
V
V
DD
DD
DD
O
e
e
V
V
O
O
k
1 mA
V
IH
High Level Input Voltage
I
l
O
l
e
e
e
e
V
5V,
10V,
15V,
V
0.5V or 4.5V 3.5
1.0V or 9.0V 7.0
1.5V or 13.5V 11.0
3.5
7.0
3.5
7.0
V
V
V
DD
DD
DD
O
e
e
V
V
V
V
O
O
11.0
11.0
e
e
e
e
e
e
I
I
I
Low Level Output Current
(Note 3)
V
V
V
5V,
10V,
15V,
V
0.4V
0.5V
1.5V
0.52
1.3
0.44
1.1
0.88
2.25
8.8
0.36
0.9
mA
mA
mA
OL
OH
IN
DD
DD
DD
O
V
V
O
O
3.6
3.0
2.4
e
e
e
e
e
e
b
b
b
b
b
0.12
High Level Output Current
(Note 3)
V
DD
V
DD
V
DD
5V,
10V,
15V,
V
O
4.6V
9.5V
0.2
0.5
1.4
0.16 0.36
mA
mA
mA
b
b
b
b
V
V
0.4
1.2
0.9
b
3.5
0.3
1.0
O
O
13.5V
b
5
e
e
e
e
b
0.3
b
b
0.3
b
Input Current
V
V
15V,
15V,
V
V
0V
0.3
10
0.3
1.0 mA
DD
IN
10b
1.0 mA
5
15V
DD
IN
Note 1: ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed, they are not meant to imply that the devices
should be operated at these limits. The table of ‘‘Recommended Operating Conditions’’ and ‘‘Electrical Characteristics’’ provides conditions for actual device
operation.
e
Note 2: V
0V unless otherwise specified.
and I are tested one output at a time.
SS
Note 3: I
OH
OL
AC Electrical Characteristics*
e
e
e
e
200k, t and t 20 ns, unless otherwise specified.
f
T
A
25 C, C
§
50 pF, R
L
L
r
Symbol
CLOCKED OPERATION
Parameter
Conditions
Min
Typ
Max
Units
e
e
e
t
t
t
t
t
t
, t
PHL PLH
Propagation Delay Time
V
V
V
5V
10V
15V
250
100
75
500
200
150
ns
ns
ns
DD
DD
DD
e
e
e
Transition Time High
Low to High
V
DD
V
DD
V
DD
5V
10V
15V
90
50
40
175
75
ns
ns
ns
THL
TLH
60
e
e
e
Transition Time
Low to High
V
DD
V
DD
V
DD
5V
10V
15V
135
70
270
140
120
ns
ns
ns
60
e
e
e
, t
WL WH
Minimum Clock Pulse Width
Clock Rise and Fall Time
V
DD
V
DD
V
DD
5V
10V
15V
335
165
100
135
50
ns
ns
ns
40
e
e
e
, t
rCL fCL
V
DD
V
DD
V
DD
5V
10V
15V
15
10
5
ms
ms
ms
Minimum Set-up Time
J/K Lines
S
e
e
e
V
DD
V
DD
V
DD
5V
10V
15V
250
100
80
500
200
160
ns
ns
ns
e
e
e
t
t
f
Parallel-In Lines
V
V
V
5V
10V
15V
250
100
80
500
200
160
ns
ns
ns
S
DD
DD
DD
e
e
e
P/S Control
V
DD
V
DD
V
DD
5V
10V
15V
100
40
200
80
ns
ns
ns
S
35
60
e
e
e
Maximum Clock Frequency
V
DD
V
DD
V
DD
5V
10V
15V
1.5
3
2.5
6
MHz
MHz
MHz
MAX
5
9
3
AC Electrical Characteristics*
e
e
e
e
200k, t and t 20 ns, unless otherwise specified. (Continued)
f
T
A
25 C, C
§
50 pF, R
L
L
r
Symbol
CLOCKED OPERATION (Continued)
Input Capacitance
RESET OPERATION
Parameter
Conditions
Min
Typ
Max
Units
C
IN
Any Input
5
7.5
pF
e
e
e
t , t
PHL PLH
Propagation Delay Time
V
DD
V
DD
V
DD
5V
10V
15V
300
150
85
500
200
150
ns
ns
ns
e
e
e
t
Minimum Reset Pulse Width
V
DD
V
DD
V
DD
5V
10V
15V
75
30
25
250
110
80
ns
ns
ns
WH
*AC Parameters are guaranteed by DC correlated testing.
Truth Table
b
t
1 (Inputs)
R
t (Outputs)
n
n
C
L
J
K
Q
n
Q
n
b
1
L
L
L
L
0
I
X
X
0
0
0
0
0
0
0
0
0
I
I
X
I
0
Q
Q
b
TOGGLE
1
MODE
n
1
1
Q
n
b
L
K
X
X
X
X
I
0
0
I
I
I
X
X
Q
b
n
0
b
n
1
X
Switching Time Waveforms
TL/F/5964–3
T/C Input Low
Reset Input Low
4
Connection Diagram
Dual-In-Line Package
TL/F/5964–4
Top View
Order Number CD4035B
Physical Dimensions inches (millimeters)
Ceramic Dual-In-Line Package (J)
Order Number CD4035BMJ or CD4035BCJ
NS Package Number J16A
5
Physical Dimensions inches (millimeters) (Continued)
Molded Dual-In-Line Package (N)
Order Number CD4035BMN or CD4035BCN
NS Package Number N16E
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SEMICONDUCTOR CORPORATION. As used herein:
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systems which, (a) are intended for surgical implant
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failure to perform, when properly used in accordance
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
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