CC2564YFVT [TI]
Bluetooth Controller 54-DSBGA;型号: | CC2564YFVT |
厂家: | TEXAS INSTRUMENTS |
描述: | Bluetooth Controller 54-DSBGA 电信 电信集成电路 |
文件: | 总43页 (文件大小:496K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
CC256x
www.ti.com
SWRS121B –JULY 2012–REVISED MAY 2013
Bluetooth® and Dual Mode Controller
1 FEATURES
123456
• Single-Chip Bluetooth Smart Ready Solution
Integrating Bluetooth Basic Rate
• Advanced Power Management for Extended
Battery Life and Ease of Design:
(BR)/Enhanced Data Rate (EDR)/Low Energy
(LE) Features Fully Compliant With the
Bluetooth 4.0 Specification Up to the HCI Layer
– On-Chip Power Management, Including
Direct Connection to Battery
– Low Power Consumption for Active,
Standby, and Scan Bluetooth Modes
– Shutdown and Sleep Modes to Minimize
Power Consumption
• BR/EDR Features Include:
– Up to 7 Active Devices
– Scatternet: Up to 3 Piconets Simultaneously,
1 as Master and 2 as Slaves
• Physical Interfaces:
– Up to 2 SCO Links on the Same or Different
Piconets
– Standard HCI Over H4 UART With Maximum
Rate of 4 Mbps
– Support for All Voice Air-Coding –
– Fully Programmable Digital PCM-I2S™
Codec Interface
• CC256x Bluetooth Hardware Evaluation Tool:
PC-Based Application to Evaluate RF
Performance of the Device and Configure
Service Pack
Continuously Variable Slope Delta (CVSD),
A-Law, μ-Law, and Transparent (Uncoded)
• LE Features Include:
– Supports Up to 6 Simultaneous Connections
– Multiple Sniff Instances that are Tightly
Coupled to Achieve Minimum Power
Consumption
– Independent Buffering for LE Allows Large
Numbers of Multiple Connections Without
Affecting BR/EDR Performance.
– Includes Built-In Coexistence and
Prioritization Handling for BR/EDR and LE
• Flexibility for Easy Stack Integration and
Validation into Various Microcontrollers, Such
as MSP430™ and Other MCUs
• Highly Optimized for Low-Cost Designs:
– Single-Ended 50-Ω RF Interface
– Package Footprint: 76 Pins, 0.6-mm Pitch,
8.10- x 7.83-mm mrQFN
• Best-in-class Bluetooth (RF) performance (TX
power, RX sensitivity, blocking)
– Class 1.5" TX Power Up to +12 dBm
– Internal Temperature Detection and
Compensation to Ensure Minimal Variation
in RF Performance Over Temperature, No
External Calibration Required
– Improved Adaptive Frequency Hopping
(AFH) Algorithm With Minimum Adaptation
Time
– Provides Longer Range, Including 2x Range
Over Other BLE-Only Solutions
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
MSP430 is a trademark of Texas Instruments.
ARM7TDMIE is a registered trademark of ARM Limited.
ARM is a registered trademark of ARM Physical IP, Inc.
2
3
4
5
6
Bluetooth is a registered trademark of Bluetooth SIG, Inc.
I2S is a trademark of Philips Electronics.
PRODUCTION DATA information is current as of publication date. Products conform to
specifications per the terms of the Texas Instruments standard warranty. Production
processing does not necessarily include testing of all parameters.
Copyright © 2012–2013, Texas Instruments Incorporated
CC256x
SWRS121B –JULY 2012–REVISED MAY 2013
www.ti.com
1
2
3
FEATURES ............................................... 1
DESCRIPTION ........................................... 3
BLUETOOTH ............................................. 5
3.1 BR/EDR Features .................................... 5
3.2 LE Features .......................................... 5
5.2 Bluetooth BR/EDR RF Performance ............... 26
5.3 Bluetooth LE RF Performance ..................... 29
5.4 Interface Specifications ............................. 31
6
REFERENCE DESIGN AND BOM FOR POWER
AND RADIO CONNECTIONS ........................ 33
7
8
mrQFN MECHANICAL DATA ........................ 34
CHIP PACKAGING AND ORDERING ............... 36
8.1 Package and Ordering Information ................. 36
8.2 Empty Tape Portion ................................ 37
8.3 Device Quantity and Direction ...................... 37
8.4 Insertion of Device ................................. 37
8.5 Tape Specification .................................. 38
8.6 Reel Specification .................................. 38
8.7 Packing Method .................................... 38
8.8 Packing Specification ............................... 39
3.3
Changes from Bluetooth v2.1 + EDR to v3.0 and
v4.0 .................................................. 6
3.4 Transport Layers ..................................... 6
DETAILED DESCRIPTION ............................. 7
4.1 Pin Designation ...................................... 7
4.2 Terminal Functions .................................. 8
4.3 Device Power Supply ............................... 10
4.4 Clock Inputs ........................................ 13
4.5 Functional Blocks ................................... 16
DEVICE SPECIFICATIONS ........................... 22
4
5
5.1
General Device Requirements and Operation ..... 22
2
Contents
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SWRS121B –JULY 2012–REVISED MAY 2013
2 DESCRIPTION
The TI CC256x device is a complete Bluetooth BR/EDR/LE HCI solution that reduces design effort and
enables fast time to market. Based on TI’s seventh-generation Bluetooth core, the device brings a
product-proven solution that supports Bluetooth 4.0 dual mode (BR/EDR/LE) protocols.
TI’s power-management hardware and software algorithms provide significant power savings in all
commonly used Bluetooth BR/EDR/LE modes of operation.
When coupled with an MCU device, this HCI device provides best-in-class RF performance for markets
such as:
•
•
•
•
•
Mobile phone accessories
Sports and fitness applications
Wireless audio solutions
Remote controls
Toys
With transmit power and receive sensitivity, this solution provides a best-in-class range of about 2x,
compared to other BLE-only solutions. A royalty-free software Bluetooth stack available from TI is pre-
integrated with TI's MSP430 and ARM® M4 MCUs. The stack is also available for MFi solutions and on
other MCUs through TI's partner Stonestreet One (www.stonestreetone.com). Some of the profiles
supported today include:
•
•
•
Serial port profile (SPP)
Human interface device (HID)
Several BLE profiles (these profiles vary based on the supported MCU)
In addition to software, this solution consists of a reference design with a low BOM cost. For more
information on TI’s wireless platform solutions for Bluetooth, see TI's Wireless Connectivity Wiki
(www.ti.com/connectivitywiki).
Table 2-1 shows the CC256x family members.
Table 2-1. CC256x Family Members
Device
Technology Supported
Description
BR/EDR
LE
ANT
CC2560A
CC2564
Bluetooth 4.0 (with EDR)
Bluetooth 4.0 + BLE(1)
Bluetooth 4.0 + ANT(1)
√
√
√
√
√
(1) The CC2564 device does not support simultaneous operation of LE and ANT.
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DESCRIPTION
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Figure 2-1 shows the device block diagram.
CC256x
2.4-GHz
band pass filter
LE
coprocessor
PCM/I2S
RF
I/O
interface
Modem
arbitrator
DRP
BR/EDR
main processor
HCI
UART
Power
management
Clock
management
Power Shutdown Slow
clock
Fast
clock
SWRS121-001
Note: The LE coprocessor is not enabled in the CC2560A device.
Figure 2-1. Functional Block Diagram
4
DESCRIPTION
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3 BLUETOOTH
3.1 BR/EDR Features
The CC256x device fully complies with the Bluetooth 4.0 specification up to the HCI level (for the family
members and technology supported, see Table 2-1):
•
•
•
•
Up to seven active devices
Scatternet: Up to 3 piconets simultaneously, 1 as master and 2 as slaves
Up to two synchronous connection oriented (SCO) links on the same or different piconets
Very fast AFH algorithm for asynchronous connection-oriented link (ACL) and extended SCO (eSCO)
link
•
Supports typically 12-dBm TX power without an external power amplifier (PA), thus improving
Bluetooth link robustness
•
•
DRP single-ended 50-Ω I/O for easy RF interfacing
Internal temperature detection and compensation to ensure minimal variation in RF performance over
temperature
•
Flexible pulse-code modulation (PCM) and inter-IC sound (I2S) digital codec interface:
–
–
–
–
–
–
–
Full flexibility of data format (linear, A-Law, μ-Law)
Data width
Data order
Sampling
Slot positioning
Master and slave modes
High clock rates up to 15 MHz for slave mode (or 4.096 MHz for master mode)
•
Support for all voice air-coding
–
–
–
–
Continuously variable slope delta (CVSD)
A-Law
μ-Law
Transparent (uncoded)
3.2 LE Features
The device fully complies with the Bluetooth 4.0 specification up to the HCI level (for the family members
and technology supported, see Table 2-1):
•
•
•
•
Solution optimized for proximity and sports use cases
Support of up to 6 simultaneous connections
Multiple sniff instances that are tightly coupled to achieve minimum power consumption
Independent buffering for LE, allowing large numbers of multiple connections without affecting BR/EDR
performance.
•
Includes built-in coexistence and prioritization handling for BR/EDR and LE
NOTE
ANT is not available when BLE is enabled.
Copyright © 2012–2013, Texas Instruments Incorporated
BLUETOOTH
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3.3 Changes from Bluetooth v2.1 + EDR to v3.0 and v4.0
The Bluetooth core specification v3.0 and v4.0 introduces new features, including these major areas of
improvement applicable to the CC256x family (Bluetooth HCI controller):
•
•
v3.0 features in BR/EDR:
–
–
Enhanced power control (EPC)
HCI Read Encryption Key Size command
v4.0 introduces LE, including:
–
–
–
–
LE physical layer and link layer
Enhancements to HCI for LE
LE direct test mode
Advanced Encryption Standard (AES)
No features are deprecated in v3.0 and v4.0.
For more information, see the Bluetooth SIG website.
3.4 Transport Layers
Figure 3-1 shows the Bluetooth transport layers.
H4 UART transport layer
Host controller interface
General
modules:
Data
Control
Event
HCI vendor-
specific
HCI data handler
HCI command handler
Trace
Timers
Sleep
Data
Link manager
Data
Link controller
RF
SWRS092-002
Figure 3-1. Bluetooth Transport Layers
6
BLUETOOTH
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4 DETAILED DESCRIPTION
4.1 Pin Designation
Figure 4-1 shows the bottom view of the pin designations.
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
NC
NC
DIG_LDO_OUT
HCI_CTS
DIG_LDO_OUT
VSS
A30
A29
A28
A27
A26
A25
A24
A23
A22
A21
B27
B26
B25
B24
B23
B22
B21
B20
B19
B1
B2
B3
B4
B5
B6
B7
B8
SRAM_LDO_OUT
DIG_LDO_OUT
MLDO_OUT
DIG_LDO_OUT
VSS_FREF
VDD_IO
NC
XTALM/FREFM
XTALP/FREFP
MLDO_OUT
TX_DBG
HCI_RX
NC
MLDO_IN
SLOW_CLK
VDD_IO
VSS
nSHUTD
CL1.5_LDO_IN
CL1.5_LDO_OUT
MLDO_OUT
VDD_IO
NC
ADC_PPA_LDO_OUT
BT_RF
NC
NC
MLDO_OUT
VDD_IO
NC
B9
NC
NC
SWRS121-002
NOTE: NC = Not connected
Figure 4-1. Pin Designation (Bottom View)
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DETAILED DESCRIPTION
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4.2 Terminal Functions
Table 4-1 describes the terminal functions.
Table 4-1. Device Pad Descriptions
Pull
at
Reset
Def.
I/O
Name
I/O Signals
No.
Description
Dir.(1)
Type(2)
HCI universal asynchronous receiver/transmitter (UART) data
receive
HCI_RX
HCI_TX
HCI_RTS
A26
A33
A32
PU
PU
PU
I
8 mA
8 mA
8 mA
O
O
HCI UART data transmit
HCI UART request-to-send
The host is allowed to send data when HCI_RTS is low.
HCI UART clear-to-send
HCI_CTS
A29
PU
I
8 mA
4 mA
The CC256x device is allowed to send data when HCI_CTS is
low.
AUD_FSYNC
AUD_CLK
AUD_IN
A35
B32
B34
B33
PD
PD
PD
PD
I/O
I/O
I
pulse-code modulation (PCM) frame-sync signal
Fail-safe
Fail-safe
Fail-safe
Fail-safe
HY, 4 mA PCM clock
4 mA
4 mA
PCM data input
AUD_OUT
O
PCM data output
TI internal debug messages. TI recommends
leaving an internal test point.
TX_DBG
B24
PU
O
2 mA
Clock Signals
SLOW_CLK
A25
B4
I
I
32.768-kHz clock in
Fail-safe
Fail-safe
Fast clock in analog (sine wave)
Output terminal of fast-clock crystal
XTALP/FREFP
XTALM/FREFM
Fast clock in digital (square wave)
Input terminal of fast-clock crystal
A4
I
Fail-safe
Analog Signals
BT_RF
B8
A6
I/O
I
Bluetooth RF I/O
nSHUTD
PD
Shutdown input (active low)
Power and Ground Signals
A17,
A34,
A38,
B18,
B19,
B21,
B22,
B25
VDD_IO
I
I/O power supply (1.8-V nominal)
Main LDO input
Connect directly to battery
MLDO_IN
B5
I
A5, A9,
B2, B7
MLDO_OUT
I/O
Main LDO output (1.8-V nominal)
Power amplifier (PA) LDO input
Connect directly to battery
CL1.5_LDO_IN
B6
A7
I
CL1.5_LDO_OUT
O
PA LDO output
A2, A3,
B15,
B26,
B27,
B35,
B36
Digital LDO output
QFN pin B26 or B27 must be shorted to other
DIG_LDO_OUT pins on the PCB.
DIG_LDO_OUT
O
SRAM_LDO_OUT
DCO_LDO_OUT
B1
O
O
SRAM LDO output
DCO LDO output
A12
(1) I = input; O = output; I/O = bidirectional
(2) I/O Type: Digital I/O cells. HY = input hysteresis, current = typical output current
8
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Table 4-1. Device Pad Descriptions (continued)
Pull
at
Reset
Def.
I/O
Name
No.
Description
Dir.(1)
Type(2)
ADC_PPA_LDO_OUT
VSS
A8
O
I
ADC/PPA LDO output
Ground
A24,
A28
VSS_DCO
VSS_FREF
No Connect
NC
B11
B3
I
I
DCO ground
Fast clock ground
A1
Not connected
Not connected
Not connected
Not connected
Not connected
Not connected
Not connected
Not connected
Not connected
Not connected
Not connected
Not connected
Not connected
Not connected
Not connected
Not connected
Not connected
Not connected
Not connected
Not connected
TI internal use
TI internal use
TI internal use
TI internal use
TI internal use
TI internal use
TI internal use
TI internal use
TI internal use
TI internal use
TI internal use
TI internal use
TI internal use
NC
A10
A11
A14
A18
A19
A20
A21
A22
A23
A27
A30
A31
A40
B9
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
B10
B16
B17
B20
B23
A13
A15
A16
A36
A37
A39
B12
B13
B14
B29
B30
B31
B28
NC
NC
NC
NC
NC
O
O
NC
NC
I/O
I/O
I/O
I/O
I
NC
NC
NC
NC
NC
I
NC
O
NC
O
NC
I/O
I
NC
NC
I
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4.3 Device Power Supply
The CC256x power-management hardware and software algorithms provide significant power savings,
which is a critical parameter in a microcontroller-based system.
The power-management module is optimized for drawing very low currents.
4.3.1 Power Sources
The CC256x device requires two power sources:
•
•
VDD_IN: Main power supply for the Bluetooth core
VDD_IO: Power source for the 1.8-V I/O ring
The device includes several on-chip voltage regulators for increased noise immunity and can be
connected directly to the battery.
4.3.2 Device Power-Up and Power-Down Sequencing
The device includes these power-up requirements (see also Figure 4-2):
•
nSHUTD must be low. VDD_IN and VDD_IO are don't-care when nSHUTD is low. However, signals
are not allowed on the I/O pins if I/O power is not supplied, because the I/Os are not fail-safe.
Exceptions are SLOW_CLK_IN and AUD_xxx, which are fail-safe and can tolerate external voltages
with no VDD_IO and VDD_IN.
•
•
•
VDD_IO and VDD_IN must be stable before releasing nSHUTD.
The fast clock must be stable within 20 ms of nSHUTD going high.
The slow clock must be stable within 2 ms of nSHUTD going high.
The device indicates that the power-up sequence is complete by asserting RTS low, which occurs up to
100 ms after nSHUTD goes high. If RTS does not go low, the device is not powered-up. In this case,
ensure that the sequence and requirements are met.
Shut down
before
VDD_IO
removed
20 µs max
nSHUTD
VDD_IO
VDD_IN
2 ms max
SLOW CLOCK
20 ms max
FAST CLOCK
ꢀ00 ms
HCI_RTS
CC256x ready
SWRS098-008
Figure 4-2. Power-Up and Power-Down Sequence
10
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4.3.3 Power Supplies and Shutdown—Static States
The nSHUTD signal puts the device in ultra-low power mode and also performs an internal reset to the
device. The rise time for nSHUTD must not exceed 20 μs, and nSHUTD must be low for a minimum of
5 ms.
To prevent conflicts with external signals, all I/O pins are set to the high-impedance state during shutdown
and power up of the device. The internal pull resistors are enabled on each I/O pin, as described in
Table 4-1.
Table 4-2 describes the static operation states.
Table 4-2. Power Modes
VDD_IN(1)
VDD_IO(1)
nSHUTD(1)
PM_MODE
Comments
1
2
3
4
5
6
7
8
None
None
Asserted
Shut down
I/O state is undefined. No I/O voltages are allowed on non fail-
safe pins.
None
None
None
Present
Present
None
Deasserted
Asserted
Not allowed
Shut down
Not allowed
Shut down
Not allowed
Shut down
Active
I/O state is undefined. No I/O voltages are allowed on non fail-
safe pins.
I/Os are defined as 3-state with internal pullup or pulldown
enabled.
None
Deasserted
Asserted
I/O state is undefined. No I/O voltages are allowed on nonfail-
safe pins.
Present
Present
Present
Present
I/O state is undefined. No I/O voltages are allowed on nonfail-
safe pins.
None
Deasserted
Asserted
I/O state is undefined. No I/O voltages are allowed on nonfail-
safe pins.
Present
I/OS are defined as 3-state with internal pullup or pulldown
enabled.
Present
Deasserted
See Section 4.3.4, I/O States In Various Power Modes.
(1) The terms None or Asserted can imply any of the following conditions: directly pulled to ground or driven low, pulled to ground through a
pulldown resistor, or left NC or floating (high-impedance output stage).
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4.3.4 I/O States In Various Power Modes
CAUTION
Some device I/Os are not fail-safe (see Table 4-1). Fail-safe means that the pins do not
draw current from an external voltage applied to the pin when I/O power is not supplied
to the device. External voltages are not allowed on these I/O pins when the I/O supply
voltage is not supplied because of possible damage to the device.
I/O Name
Shut Down(1)
I/O State
Default Active(1)
Deep Sleep(1)
Pull
PU
PU
PU
PU
PD
PD
PD
PD
PU
I/O State
Pull
PU
—
I/O State
Pull
PU
—
HCI_RX
Z
Z
Z
Z
Z
Z
Z
Z
Z
I
I
O
O
I
HCI_TX
O-H
HCI_RTS
HCI_CTS
AUD_CLK
AUD_FSYNC
AUD_IN
O-H
—
—
I
I
PU
PD
PD
PD
PD
—
PU
PD
PD
PD
PD
I
I
I
I
I
AUD_OUT
TX_DBG
Z
O
Z
(1) I = input, O = output, Z = Hi-Z, — = no pull, PU = pullup, PD = pulldown, H = high, L = low
12
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4.4 Clock Inputs
4.4.1 Slow Clock
An external source must supply the slow clock and connect to the SLOW_CLK_IN pin. The source must
be a digital signal in the range of 0 to 1.8 V.
The accuracy of the slow clock frequency must be 32.768 kHz ±250 ppm for Bluetooth use (as specified in
the Bluetooth specification).
The external slow clock must be stable within 64 slow-clock cycles (2 ms) following the release of
nSHUTD.
4.4.2 Fast Clock Using External Clock Source
An external clock source is fed to an internal pulse-shaping cell to provide the fast clock signal for the
device. The device incorporates an internal, automatic clock-scheme detection mechanism that
automatically detects the fast-clock scheme used and configures the FREF cell accordingly. This
mechanism ensures that the electrical characteristics (loading) of the fast-clock input remain static
regardless of the scheme used and eliminates any power-consumption penalty-versus-scheme used.
This section describes the requirements for fast clock use. The frequency variation of the fast-clock source
must not exceed ±20 ppm (as defined by the Bluetooth specification).
The external clock can be AC- or DC-coupled, sine or square wave.
4.4.2.1 External FREF DC-Coupled
Figure 4-3 and Figure 4-4 show the clock configuration when using a square wave, DC-coupled external
source for the fast clock input.
NOTE
A shunt capacitor with a range of 10 nF must be added on the oscillator output to reject high
harmonics and shape the signal to be close to a sinusoidal waveform.
TI recommends using only a dedicated LDO to feed the oscillator. Do not use the same VIO
for the oscillator and the CC256x device.
FREFP
CC256x
FREFM
SWRS121-009
Figure 4-3. Clock Configuration (Square Wave, DC-Coupled)
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VFref [V]
2.1
Vhigh_min
1.0
Vlow_max
0.37
–0.2
t
clksqtd_wrs064
Figure 4-4. External Fast Clock (Square Wave, DC-Coupled)
Figure 4-5 and Figure 4-6 show the clock configuration when using a sine wave, DC-coupled external
source for the fast clock input.
FREFP
CC256x
FREFM
VDD_IO
SWRS121-007
Figure 4-5. Clock Configuration (Sine Wave, DC-Coupled)
VIN
1.6 V
VPP = 0.4 – 1.6 Vp-p
Vdc = 0.2 – 1.4 V
0
t
SWRS097-023
Figure 4-6. External Fast Clock (Sine Wave, DC-Coupled)
4.4.2.2 External FREF Sine Wave, AC-Coupled
Figure 4-7 shows the configuration when using a sine wave, AC-coupled external source for the fast-clock
input.
FREFP
68 pF
CC256x
FREFM
VDD_IO
SWRS121-008
Figure 4-7. Clock Configuration (Sine Wave, AC-Coupled)
14
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VIN [V]
1 V
VPP = 0.4 – 1.6 Vp-p
0.8
0.2
0
t
–0.2
–0.8
SWRS097-022
Figure 4-8. External Fast Clock (Sine Wave, AC-Coupled)
In cases where the input amplitude is greater than 1.6 Vp-p, the amplitude can be reduced to within limits.
Using a small series capacitor forms a voltage divider with the internal input capacitance of approximately
2 pF to provide the required amplitude at the device input.
4.4.2.3 Fast Clock Using External Crystal
The CC256x device incorporates an internal crystal oscillator buffer to support a crystal-based fast-clock
scheme. The supported crystal frequency is 26 MHz.
The frequency accuracy of the fast clock source must not exceed ±20 ppm (including the accuracy of the
capacitors, as specified in the Bluetooth specification).
Figure 4-9 shows the recommended fast-clock circuitry.
CC256x
C1
XTALM
Oscillator
buffer
XTAL
XTALP
C2
SWRS098-003
Figure 4-9. Fast-Clock Crystal Circuit
Table 4-3 lists component values for the fast-clock crystal circuit.
Table 4-3. Fast-Clock Crystal Circuit Component
Values
FREQ (MHz)
C1 (pF)(1)
C2 (pF)(1)
26
12
12
(1) To achieve the required accuracy, values for C1 and C2 must be
taken from the crystal manufacturer's data sheet and layout
considerations.
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4.5 Functional Blocks
The CC256x architecture comprises a DRP and a point-to-multipoint baseband core. The architecture is
based on a single-processor ARM7TDMIE® core. The device includes several on-chip peripherals to
enable easy communication with a host system and the Bluetooth BR/EDR/LE core.
4.5.1 DRP
The device is the third generation of TI Bluetooth single-chip devices using DRP architecture.
Modifications and new features added to the DRP further improve radio performance.
Figure 4-10 shows the DRP block diagram.
Transmitter path
Amplitude
TX digital data
Digital
ADPLL
DPA
Phase
Receiver path
IFA
RX digital data
Demodulation
ADC
Filter
LNA
SWRS092-005
Figure 4-10. DRP Block Diagram
4.5.1.1 Receiver
The receiver uses near-zero-IF architecture to convert the RF signal to baseband data. The signal
received from the external antenna is input to a single-ended LNA (low-noise amplifier) and passed to a
mixer that downconverts the signal to IF, followed by a filter and amplifier. The signal is then quantized by
a sigma-delta analog-to-digital converter (ADC) and further processed to reduce the interference level.
The demodulator digitally downconverts the signal to zero-IF and recovers the data stream using an
adaptive-decision mechanism. The demodulator includes EDR processing with:
•
•
State-of-the-art performance
A maximum-likelihood sequence estimator (MLSE) to improve the performance of basic-rate GFSK
sensitivity
•
Adaptive equalization to enhance EDR modulation
New features include:
•
•
LNA input range narrowed to increase blocking performance
Active spur cancellation to increase robustness to spurs
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4.5.1.2 Transmitter
The transmitter is an all-digital, sigma-delta phase-locked loop (ADPLL) based with a digitally controlled
oscillator (DCO) at 2.4 GHz as the RF frequency clock. The transmitter direct modulates the digital PLL.
The power amplifier is also digitally controlled. The transmitter uses the polar-modulation technique. While
the phase-modulated control word is fed to the ADPLL, the amplitude-modulated controlled word is fed to
the class-E amplifier to generate a Bluetooth standard-compliant RF signal.
New features include:
•
•
Improved TX output power
LMS algorithm to improve the differential error vector magnitude (DEVM)
4.5.2 Host Controller Interface
The CC256x device incorporates one UART module dedicated to the HCI transport layer. The HCI
interface transports commands, events, and asynchronous connection-oriented link (ACL) between the
device and the host using HCI data packets.
The UART module supports the H4 (4-wire) protocol with a maximum baud rate of 4 Mbps for all fast-
clock frequencies.
After power up, the baud rate is set for 115.2 kbps, regardless of the fast-clock frequency.
The baud rate can thereafter be changed with a VS command. The device responds with a Command
Complete event (still at 115.2 kbps), after which the baud rate change occurs.
HCI hardware includes the following features:
•
•
•
Receiver detection of break, idle, framing, FIFO overflow, and parity error conditions
Transmitter underflow detection
CTS and RTS hardware flow control
Table 4-4 lists the UART module default settings.
Table 4-4. UART Default Settings
Parameter
Bit rate
Value
115.2 kbps
8 bits
Data length
Stop-bit
1
Parity
None
4.5.2.1 UART 4-Wire Interface—H4
The interface includes four signals: TX, RX, CTS, and RTS. Flow control between the host and the
CC256x device is bytewise by hardware.
Figure 4-11 shows how the device obtains flow control.
HCI_RX
HCI_TX
Host_RX
Host_TX
Host
CC256x
HCI_CTS
HCI_RTS
Host_CTS
Host_RTS
SWRS121-003
Figure 4-11. HCI UART Connection
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When the UART RX buffer of the CC256x device passes the flow control threshold, it sets the UART_RTS
signal high to stop transmission from the host.
When the UART_CTS signal is set high, the CC256x device stops its transmission on the interface. If
HCI_CTS is set high while transmitting a byte, the CC256x device finishes transmitting the byte and stops
the transmission.
4.5.2.2 eHCILL—4-Wire Power-Management Protocol
The CC256x device includes a mechanism that handles the transition between operating mode and deep-
sleep low-power mode. The protocol occurs through the UART and is known as the enhanced HCI low
level (eHCILL) power-management protocol.
4.5.3 Digital Codec Interface
The codec interface is a fully programmable port to support seamless interfacing with different PCM and
Inter-IC Sound (I2S) codec devices. The interface includes the following features:
•
•
•
•
•
•
•
Two voice channels
Master and slave modes
All voice coding schemes defined by the Bluetooth specification: linear, A-Law, and μ-Law
Long and short frames
Different data sizes, order, and positions
High flexibility to support a variety of codecs
Bus sharing: Data_Out is in Hi-Z mode when the interface is not transmitting voice data.
4.5.3.1 Hardware Interface
The interface includes four signals:
•
•
•
•
Clock: configurable direction (input or output)
Frame_Sync and Word_Sync: configurable direction (input or output)
Data_In: input
Data_Out: output or 3-state
The CC256x device can be master of the interface when generating the clock and the frame-sync signals
or the slave when receiving these two signals.
For slave mode, clock input frequencies of up to 15 MHz are supported. At clock rates above 12 MHz, the
maximum data burst size is 32 bits.
For master mode, the CC256x device can generate any clock frequency between 64 kHz and 4.096 MHz.
4.5.3.2 I2S
When the codec interface is configured to support the I2S protocol, these settings are recommended:
•
•
Bidirectional, full-duplex interface
Two time slots per frame: time slot-0 for the left channel audio data; and time slot-1 for the right
channel audio data
•
Each time slot is configurable up to 40 serial clock cycles long, and the frame is configurable up to 80
serial clock cycles long.
4.5.3.3 Data Format
The data format is fully configurable:
•
The data length can be from 8 to 320 bits in 1-bit increments when working with 2 channels, or up to
640 bits when working with 1 channel. The data length can be set independently for each channel.
•
The data position within a frame is also configurable within 1 clock (bit) resolution and can be set
independently (relative to the edge of the Frame_Sync signal) for each channel.
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•
The Data_In and Data_Out bit order can be configured independently. For example; Data_In can start
with the most-significant bit (MSB); Data_Out can start with the least-significant bit (LSB). Each
channel is separately configurable. The inverse bit order (that is, LSB first) is supported only for
sample sizes up to 24 bits.
•
•
It is not necessary for Data_In and Data_Out to be the same length.
The Data_Out line is configured to Hi-Z output between data words. Data_Out can also be set for
permanent Hi-Z, regardless of data out. This allows the CC256x device to be a bus slave in a
multislave PCM environment. At power up, Data_Out is configured as Hi-Z.
4.5.3.4 Frame Idle Period
The codec interface handles frame idle periods, in which the clock pauses and becomes 0 at the end of
the frame, after all data are transferred.
The CC256x device supports frame idle periods both as master and slave of the codec bus.
When the CC256x device is master of the interface, the frame idle period is configurable. There are two
configurable parameters:
•
Clk_Idle_Start: indicates the number of clock cycles from the beginning of the frame to the beginning of
the idle period. After Clk_Idle_Start clock cycles, the clock becomes 0.
•
Clk_Idle_End: indicates the time from the beginning of the frame to the end of the idle period. The time
is given in multiples of clock periods.
The delta between Clk_Idle_Start and Clk_Idle_End is the clock idle period.
For example, for clock rate = 1 MHz, frame sync period = 10 kHz, Clk_Idle_Start = 60, Clk_Idle_End = 90.
Between both frame-sync signals there are 70 clock cycles (instead of 100). The clock idle period starts
60 clock cycles after the beginning of the frame and lasts 90 – 60 = 30 clock cycles. This means that the
idle period ends 100 – 90 = 10 clock cycles before the end of the frame. The data transmission must end
before the beginning of the idle period.
Figure 4-12 shows the frame idle timing.
Frame period
Frame_Sync
Data_In
Data_Out
Frame idle
Clock
Clk_Idle_Start
Clk_Idle_End
frmidle_swrs064
Figure 4-12. Frame Idle Period
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4.5.3.5 Clock-Edge Operation
The codec interface of the CC256x device can work on the rising or the falling edge of the clock and can
sample the frame-sync signal and the data at inversed polarity.
Figure 4-13 shows the operation of a falling-edge-clock type of codec. The codec is the master of the bus.
The frame-sync signal is updated (by the codec) on the falling edge of the clock and is therefore sampled
(by the CC256x device) on the next rising clock. The data from the codec is sampled (by the CC256x
device) on the falling edge of the clock.
PCM FSYNC
PCM CLK
D7
D6
D5
D4
D2
D1
D0
D3
PCM DATA IN
CC256x
SAMPLE TIME
SWRS121-004
Figure 4-13. Negative Clock Edge Operation
4.5.3.6 Two-Channel Bus Example
Figure 4-14 shows a 2-channel bus in which the two channels have different word sizes and arbitrary
positions in the bus frame. (FT stands for frame timer.)
...
Clock
...
FT
2
5
127 0
1
3
4
6
7
8
9
42 43 44
127 0
Fsync
MSB
bit bit bit bit bit bit bit bit
MSB
LSB
LSB
bit bit bit bit bit bit bit bit bit bit bit
10
...
...
Data_Out
Data_In
0
1
2
3
4
5
6
7
8
9
0
1
2
3
4
5
6
7
bit bit bit bit bit bit bit bit bit bit bit
10
bit bit bit bit bit bit bit bit
1
0
1
2
3
4
5
6
7
8
9
0
2
3
4
5
6
7
PCM_data_window
CH2 data
start FT = 43
CH1 data start FT = 0
CH1 data length = 11
CH2 data
length = 8
Fsync period = 128
Fsync length = 1
twochpcm_swrs064
Figure 4-14. Two-Channel Bus Timing
4.5.3.7 Improved Algorithm For Lost Packets
The CC256x device features an improved algorithm to improve voice quality when received voice data
packets are lost. There are two options:
•
Repeat the last sample: possible only for sample sizes up to 24 bits. For sample sizes larger than 24
bits, the last byte is repeated.
•
Repeat a configurable sample of 8 to 24 bits (depending on the real sample size) to simulate silence
(or anything else) in the bus. The configured sample is written in a specific register for each channel.
The choice between those two options is configurable separately for each channel.
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4.5.3.8 Bluetooth and Codec Clock Mismatch Handling
In Bluetooth RX, the CC256x device receives RF voice packets and writes them to the codec interface. If
the CC256x device receives data faster than the codec interface output allows, an overflow occurs. In this
case, the Bluetooth has two possible behavior modes:
•
Allow overflow: if overflow is allowed, the Bluetooth continues receiving data and overwrites any data
not yet sent to the codec.
•
Do not allow overflow: if overflow is not allowed, RF voice packets received when the buffer is full are
discarded.
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5 DEVICE SPECIFICATIONS
Unless otherwise indicated, all measurements are taken at the device pins of the TI test evaluation board
(EVB).
All specifications are over process, voltage and temperature, unless otherwise indicated.
5.1 General Device Requirements and Operation
5.1.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted)
NOTE
Unless otherwise indicated, all parameters are measured as follows:
VDD_IN = 3.6 V, VDD_IO = 1.8 V
(1)
See
Value
Unit
Ratings over operating free-air temperature range
VDD_IN
Supply voltage range
–0.5 to 4.8
–0.5 to 2.145
–0.5 to 2.1
–0.5 to (VDD_IO + 0.5)
–40 to 85
V(2)
V
VDDIO_1.8V
Input voltage to analog pins(3)
Input voltage to all other pins
Operating ambient temperature range(4)
Storage temperature range
Bluetooth RF inputs
V
V
°C
°C
dBm
–55 to 125
10
Human body model (HBM)(6)
Charged device model (CDM)(7)
Device
Device
500
ESD stress
voltage(5)
V
250
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Maximum allowed depends on accumulated time at that voltage: VDD_IN is defined in Section 6, Reference Design for Power and
Radio Connections.
(3) Analog pins: BT_RF, XTALP, and XTALM
(4) The reference design supports a temperature range of –20°C to 70°C because of the operating conditions of the crystal.
(5) ESD measures device sensitivity and immunity to damage caused by electrostatic discharges into the device.
(6) The level listed is the passing level per ANSI/ESDA/JEDEC JS-001. JEDEC document JEP155 states that 500-V HBM allows safe
manufacturing with a standard ESD control process, and manufacturing with less than 500-V HBM is possible, if necessary precautions
are taken. Pins listed as 1000 V can actually have higher performance.
(7) The level listed is the passing level per EIA-JEDEC JESD22-C101E. JEDEC document JEP157 states that 250-V CDM allows safe
manufacturing with a standard ESD control process, and manufacturing with less than 250-V CDM is possible, if necessary precautions
are taken. Pins listed as 250 V can actually have higher performance.
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5.1.2 Recommended Operating Conditions
Rating
Condition
Sym
VDD_IN
VDD_IO
VIH
Min
Max
Unit
V
Power supply voltage
I/O power supply voltage
High-level input voltage
Low-level input voltage
2.2
4.8
1.92
1.62
V
Default
Default
0.65 x VDD_IO
VDD_IO
0.35 x VDD_IO
10
V
VIL
0
1
1
V
I/O input rise and all times,10% to 90% — asynchronous mode
tr and tf
ns
ns
I/O input rise and fall times, 10% to 90% — synchronous mode
(PCM)
2.5
Voltage dips on VDD_IN (VBAT
duration = 577 μs to 2.31 ms, period = 4.6 ms
Maximum ambient operating temperature(1)
)
400
85
mV
°C
(2)
–40
(1) The device can be reliably operated for 7 years at Tambient of 85°C, assuming 25% active mode and 75% sleep mode (15,400
cumulative active power-on hours).
(2) A crystal-based solution is limited by the temperature range required of the crystal to meet 20 ppm.
5.1.3 Current Consumption
5.1.3.1 Static Current Consumption
Operational Mode
Min
Typ
1
Max
7
Unit
Shutdown mode(1)
Deep sleep mode(2)
Idle mode
µA
µA
40
4
105
mA
mA
mA
mA
Total I/O current consumption in active mode
Continuous transmission—GFSK(3)
Continuous transmission—EDR(4)(5)
1
77
82.5
(1) VBAT + VIO + VSHUTDOWN
(2) VBAT + VIO
(3) At maximum output power (12 dBm)
(4) At maximum output power (10 dBm)
(5) Both π/4 DQPSK and 8DPSK
5.1.3.2 Dynamic Current Consumption
5.1.3.2.1 Current Consumption for Different Bluetooth BR/EDR Scenarios
Conditions: VDD_IN = 3.6 V, 25°C, 26-MHz XTAL, nominal unit, 4-dBm output power
Operational Mode
Master and Slave
Average Current
Unit
Synchronous connection oriented (SCO) link HV3
Extended SCO (eSCO) link EV3 64 kbps, no retransmission
eSCO link 2-EV3 64 kbps, no retransmission
Master and slave
Master and slave
Master and slave
13.7
13.2
10
mA
mA
mA
GFSK full throughput: TX = DH1, RX = DH5
EDR full throughput: TX = 2-DH1, RX = 2-DH5
EDR full throughput: TX = 3-DH1, RX = 3-DH5
Master and slave
Master and slave
Master and slave
40.5
41.2
41.2
mA
mA
mA
Sniff, one attempt, 1.28 seconds
Master and slave
Master and slave
Master and slave
250
400
500
μA
μA
μA
Page or inquiry scan 1.28 seconds, 11.25 ms
Page (1.28 seconds) and inquiry (2.56 seconds) scans,
11.25 ms
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Conditions: VDD_IN = 3.6 V, 25°C, 26-MHz fast clock, nominal unit, 4-dBm output power
Operational Mode
Master and Slave
Master and slave
Master and slave
Master and slave
Average Current
Unit
mA
mA
mA
Synchronous connection oriented (SCO) link HV3
Extended SCO (eSCO) link EV3 64 kbps, no retransmission
eSCO link 2-EV3 64 kbps, no retransmission
12
11.5
8.3
GFSK full throughput: TX = DH1, RX = DH5
EDR full throughput: TX = 2-DH1, RX = 2-DH5
EDR full throughput: TX = 3-DH1, RX = 3-DH5
Master and slave
Master and slave
Master and slave
38.5
39.2
39.2
mA
mA
mA
Sniff, one attempt, 1.28 seconds
Master and slave
Master and slave
Master and slave
76 and 100
300
μA
μA
μA
Page or inquiry scan 1.28 seconds, 11.25 ms
Page (1.28 seconds) and inquiry (2.56 seconds) scans,
11.25 ms
430
5.1.3.2.2 Current Consumption for Different LE Scenarios
Conditions: VDD_IN = 3.6 V, 25°C, 26-MHz fast clock, nominal unit, 10 dBm output power
Mode
Description
Average Current
Unit
Advertising in all three channels
1.28-seconds advertising interval
15 bytes advertise data
Advertising, nonconnectable
104
µA
Advertising in all three channels
1.28-seconds advertising interval
15 bytes advertise data
Advertising, discoverable
Scanning
121
302
169
µA
µA
µA
Listening to a single frequency per window
1.28-seconds scan interval
11.25-ms scan window
500-ms connection interval
0-ms slave connection latency
Empty TX and RX LL packets
Connected (master role)
5.1.4 General Electrical Characteristics
Rating
Condition
At 2, 4, 8 mA
At 0.1 mA
At 2, 4, 8 mA
At 0.1 mA
Resistance
Capacitance
CL = 20 pF
typ = 6.5
Min
Max
VDD_IO
VDD_IO
0.2 x VDD_IO
0.2
Unit
V
High-level output voltage, VOH
0.8 x VDD_IO
VDD_IO – 0.2
V
Low-level output voltage, VOL
0
0
1
V
V
I/O input impedance
MΩ
pF
ns
μA
5
Output rise and fall times, 10% to 90% (digital pins)
10
I/O pull currents
PCM-I2S bus, TX_DBG
PU
PD
PU
PD
3.5
9.5
50
9.7
55
typ = 27
All others
typ = 100
300
360
μA
typ = 100
50
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5.1.5 nSHUTD Requirements
Parameter
Sym
VIH
Min
1.42
0
Max
1.98
0.4
Unit
V
(1)
Operation mode level
(1)
Shutdown mode level
VIL
V
Minimum time for nSHUT_DOWN low to reset the device
Rise and fall times
5
ms
μs
tr and tf
20
(1) Internal pulldown retains shut-down mode when no external signal is applied to this pin.
5.1.6 Slow Clock Requirements
Characteristics
Condition
Sym
Min
Typ
Max
Unit
Input slow clock frequency
32768
Hz
Bluetooth
±250
200
Input slow clock accuracy
(Initial + temp + aging)
ppm
Input transition time tr and tf
(10% to 90%)
tr and tf
15%
Frequency input duty cycle
50%
85%
Slow clock input voltage limits
Square wave, DC-coupled
VIH
VIL
0.65 ×
VDD_IO
VDD_IO
V peak
V peak
0
1
0.35 ×
VDD_IO
Input impedance
Input capacitance
MΩ
5
pF
5.1.7 External Fast Clock Crystal Requirements and Operation
Characteristics
Condition
Sym
Min
Typ
Max
Unit
Supported crystal frequencies
fin
26
MHz
Frequency accuracy
(Initial + temperature + aging)
±20
ppm
26 MHz, external capacitance = 8 pF
Iosc = 0.5 mA
650
490
940
710
Crystal oscillator negative resistance
Ω
26 MHz, external capacitance = 20 pF
Iosc = 2.2 mA
5.1.8 Fast Clock Source Requirements (–40°C to +85°C)
Characteristics
Condition
Sym
Min
Typ
Max
Unit
MHz
ppm
V
Supported frequencies
FREF
26
Reference frequency accuracy
Fast clock input voltage limits
Initial + temp + aging
±20
0.37
2.1
Square wave, DC-coupled
VIL
VIH
–0.2
1.0
0.4
0.4
0
V
Sine wave, AC-coupled
1.6
Vp-p
Vp-p
V
Sine wave, DC-coupled
1.6
Sine wave input limits, DC-coupled
Square wave, DC-coupled
1.6
Fast clock input rise time
(as % of clock period)
10%
Duty cycle
35%
50%
65%
Phase noise for 26 MHz
@ offset = 1 kHz
@ offset =10 kHz
@ offset = 100 kHz
–123.4
–133.4
–138.4
dBc/Hz
dBc/Hz
dBc/Hz
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5.2 Bluetooth BR/EDR RF Performance
All parameters in this section that are fast-clock dependent are verified using a 26-MHz XTAL under a
temperature range from –20°C to 70°C and an RF load of 50 Ω at the BT_RF port of the IC.
5.2.1 Bluetooth Receiver—In-Band Signals
Characteristics
Condition
Min
Typ
Max
Bluetooth
Unit
Specification
Operation frequency range
Channel spacing
2402
2480
MHz
MHz
Ω
1
Input impedance
50
Sensitivity, dirty TX on(1)
GFSK, BER = 0.1%
–91.5
–90.5
–81
–95
–70
–70
dBm
Pi/4-DQPSK, BER = 0.01%
8DPSK, BER = 0.01%
Pi/4-DQPSK
–94.5
–87.5
1E–7
–70
BER error floor at sensitivity + 10
dB, dirty TX off
1E–6
1E–6
–5
1E–5
1E–5
–20
8DPSK
Maximum usable input power
GFSK, BER = 0.1%
Pi/4-DQPSK, BER = 0.1%
8DPSK, BER = 0.1%
dBm
–10
–10
Intermodulation characteristics
C/I performance
Level of interferers
For n = 3, 4, and 5
–36
–30
–39
dBm
dB
GFSK, co-channel
EDR, co-channel
8
10
11
20
–5
11
13
21
0
Pi/4-DQPSK
8DPSK
9.5
Note:
16.5
–10
Numbers show desired-signal to
interfering-signal ratio.
GFSK, adjacent ±1 MHz
Smaller numbers indicate better
C/I performance.
EDR, adjacent ±1 MHz, (image)
Pi/4-DQPSK
8DPSK
–10
–5
–5
0
–1
5
Image = –1 MHz
GFSK, adjacent +2 MHz
EDR, adjacent, +2 MHz,
–38
–38
–38
–28
–28
–22
–45
–45
–44
–10
–63
–35
–35
–30
–20
–20
–13
–43
–43
–36
–30
–30
–25
–20
–20
–13
–40
–40
–33
Pi/4-DQPSK
8DPSK
GFSK, adjacent –2 MHz
EDR, adjacent –2 MHz
Pi/4-DQPSK
8DPSK
GFSK, adjacent ≥ |±3| MHz
EDR, adjacent ≥ |±3|MHz
Pi/4-DQPSK
8DPSK
RF return loss
dB
RX mode LO leakage
Frf = (received RF frequency – 0.6 MHz)
–58
dBm
(1) Sensitivity degradation up to 3 dB may occur for minimum and typical values where the Bluetooth frequency is a harmonic of the fast
clock.
5.2.2 Bluetooth Receiver—General Blocking
Characteristics
Condition
30 to 2000 MHz
Min
Typ
–6
Unit
Blocking performance over full range, according to Bluetooth
dBm
(1)
specification
2000 to 2399 MHz
2484 to 3000 MHz
3 to 12.75 GHz
–6
–6
–6
(1) Exceptions are taken out of the total 24 allowed in the Bluetooth specification.
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5.2.3 Bluetooth Transmitter—GFSK
Characteristics
Min
Typ
Max
Bluetooth
Unit
Specification
Maximum RF output power(1)
Power variation over Bluetooth band
Gain control range
10
–1
12
dBm
dB
1
30
5
dB
Power control step
2
8
2 to 8
≤ –20
≤ –40
Adjacent channel power |M–N| = 2
Adjacent channel power |M–N| > 2
–45
–50
–39
–42
dBm
(1) To modify maximum output power, use an HCI VS command.
5.2.4 Bluetooth Transmitter—EDR
Characteristics
Min
Typ
Max
Bluetooth
Unit
Specification
Maximum RF output
power(1)
Pi/4-DQPSK
8DPSK
6
6
8
8
dBm
dB
Relative power
–2
–1
1
1
–4 to +1
Power variation over Bluetooth band
Gain control range
30
5
Power control step
2
8
2 to 8
≤ –26
≤ –20
≤ –40
Adjacent channel power |M–N| = 1
–36
–30
–42
–30
–23
–40
dBc
dBm
dBm
(2)
Adjacent channel power |M–N| = 2
Adjacent channel power |M–N| > 2
(2)
(1) To modify maximum output power, use an HCI VS command.
(2) Assumes 3-dB insertion loss from Bluetooth RF ball to antenna
5.2.5 Bluetooth Modulation—GFSK
Characteristics
Condition
Sym
Min Typ
Max Bluetooth
Specificat
ion
Unit
–20 dB bandwidth
GFSK
925
995
170
≤ 1000
kHz
kHz
Modulation characteristics
Δf1avg
Mod data = 4 1s, 4
0s:
F1 avg 150 165
140 to 175
111100001111...
Δf2max ≥ limit for at
least 99.9% of all
Δf2max
Mod data =
1010101...
F2 max 115 130
> 115
kHz
Δf2avg, Δf1avg
DH1
85
88
> 80
< ±25
< ±40
< 20
%
Absolute carrier frequency drift
–25
–35
25
35
15
kHz
kHz
DH3 and DH5
Drift rate
kHz/
50 μs
Initial carrier frequency tolerance
f0 – fTX
–75
75
< ±75
kHz
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5.2.6 Bluetooth Modulation—EDR
Characteristics
Condition
Min
Typ
Max
Bluetooth
Unit
Specification
Carrier frequency stability
±3
±5
±75
15
13
30
20
30
25
≤ 10
±75
20
kHz
kHz
Initial carrier frequency tolerance
(1)
Rms DEVM
Pi/4-DQPSK
8DPSK
6
6
13
99% DEVM(1)
Pi/4-DQPSK
8DPSK
30
%
20
(1)
Peak DEVM
Pi/4-DQPSK
8DPSK
14
16
35
25
(1) Max performance refers to maximum TX power.
5.2.7 Bluetooth Transmitter—Out-of-Band and Spurious Emissions
Characteristics
Second harmonic(1)
Third harmonic(1)
Condition
Typ
–14
–10
–19
Max
–2
Unit
dBm
dBm
dBm
Measured at maximum output power
–6
Fourth harmonics(1)
–11
(1) Meets FCC and ETSI requirements with external filter shown in Figure 6-1
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5.3 Bluetooth LE RF Performance
All parameters in this section that are fast-clock dependent are verified using a 26-MHz XTAL under a
temperature range from –20°C to 70°C and an RF load of 50 Ω at the BT_RF port of the IC.
5.3.1 BLE Receiver—In Band Signals
Characteristic
Condition
Min
Typ
Max
BLE
Unit
Specification
Operation frequency range
Channel spacing
2402
2480
MHz
MHz
Ω
2
Input impedance
50
Sensitivity dirty TX on(1)
Maximum usable input power
Intermodulation characteristics
PER = 30.8%; dirty TX on
GMSK, PER = 30.8%
–93
–5
–96
≤ –70
≥ –10
≥ –50
dBm
dBm
dBm
Level of interferers.
For n = 3, 4, 5
–36
–30
C/I performance(2)
Image = –1 MHz
GMSK, co-channel
GMSK, adjacent ±1 MHz
GMSK, adjacent +2 MHz
GMSK, adjacent –2 MHz
GMSK, adjacent ≥ |±3| MHz
Frf = (received freq – 0.6 MHz)
8
12
0
≤ 21
≤ 15
dB
–5
–45
–22
–47
–63
–38
–15
–40
–58
≤ –17
≤ –15
≤ –27
RX mode LO leakage
dBm
(1) Sensitivity degradation up to 3 dB may occur where the BLE frequency is a harmonic of the fast clock.
(2) Numbers show wanted signal-to-interfering signal ratio. Smaller numbers indicate better C/I performance.
5.3.2 BLE Receiver—General Blocking
Characteristics
Condition
30–2000 MHz
2000–2399 MHz
2484–3000 MHz
3–12.75 GHz
Min
Typ
–15
–15
–15
–15
BLE Specification
Unit
Blocking performance over full
range, according to BLE
specification(1)
≥ –30
≥ –35
≥ –35
≥ –30
dBm
(1) Exceptions are taken out of the total 10 allowed in the BLE specification.
5.3.3 BLE Transmitter
Characteristics
Min
Typ
Max
BLE
Unit
Specification
Maximum RF output power(1)
Power variation over BLE band
Adjacent channel power |M-N| = 2
Adjacent channel power |M-N| > 2
10
–1
12(2)
≤10
dBm
dB
1
–45
–50
–39
–42
≤ –20
≤ –30
dBm
(1) To modify maximum output power, use an HCI VS command.
(2) To achieve the BLE specification of 10-dBm maximum, an insertion loss of > 2 dB is assumed between the RF ball and the antenna.
Otherwise, use an HCI VS command to modify the output power.
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5.3.4 BLE Modulation
Characteristics
Condition
Mod data = 4 1s, 4
Sym
Min
Typ
Max
BLE
Specification
Unit
Modulation
Δf1avg
Δf1
240
250
260
225 to 275
kHz
characteristics
0s:
avg
1111000011110000...
Δf2max ≥ limit for at
least 99.9% of all
Δf2max
Mod data =
1010101...
Δf2
max
185
210
0.9
≥ 185
kHz
Δf2avg, Δf1avg
0.85
–25
≥ 0.8
Absolute carrier
frequency drift
25
≤ ±50
kHz
Drift rate
15
75
≤ 20
kHz/50 ms
kHz
Initial carrier
–75
≤ ±100
frequency tolerance
5.3.5 BLE Transceiver, Out-Of-Band and Spurious Emissions
See Section 5.2.7, Bluetooth Transmitter, Out-of-Band and Spurious Emissions.
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5.4 Interface Specifications
5.4.1 UART
Figure 5-1 shows the UART timing diagram. Table 5-1 lists the UART timing characteristics.
HCI_RTS
t1
t2
t6
HCI_RX
HCI_CTS
t3
t4
HCI_TX
Start-
bit
Stop-
bit
10bits
td_uart_swrs064
Figure 5-1. UART Timing
Table 5-1. UART Timing Characteristics
Symbol
Characteristics
Condition
Min
37.5
–2.5
–12.5
0
Typ
Max
4000
1.5
Unit
kbps
%
Baud rate
Baud rate accuracy per byte
Baud rate accuracy per bit
CTS low to TX_DATA on
CTS high to TX_DATA off
CTS-high pulse width
Receive and transmit
Receive and transmit
12.5
%
t3
t4
t6
t1
t2
2
2
μs
Hardware flow control
1
byte
bit
1
0
RTS low to RX_DATA on
RTS high to RX_DATA off
μs
Interrupt set to 1/4 FIFO
16
byte
Figure 5-2 shows the UART data frame. Table 5-2 describes the symbols used in Figure 5-2.
tb
TX
STR
D0
D1
Dn
PAR
STP
D2
td_uart_swrs064
Figure 5-2. Data Frame
Table 5-2. Data Frame Key
Symbol
Description
Start-bit
STR
D0...Dn
PAR
Data bits (LSB first)
Parity bit (optional)
Stop-bit
STP
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5.4.2 PCM
Figure 5-3 shows the interface timing for the PCM. Table 5-3 and Table 5-4 list the associated master and
slave parameters.
Tclk
Tw
Tw
AUD_CLK
tis
tih
AUD_IN / FSYNC_IN
top
AUD_OUT / FSYNC_OUT
td_aud_swrs064
Figure 5-3. PCM Interface Timing
Table 5-3. PCM Master
Symbol
Parameter
Condition
Min
Max
Unit
Tclk
Cycle time
244.14
15625
ns
(4.096 MHz)
(64 kHz)
Tw
tis
High or low pulse width
AUD_IN setup time
50% of Tclk min
25
0
tih
AUD_IN hold time
top
top
AUD_OUT propagation time
FSYNC_OUT propagation time
40-pF load
40-pF load
0
10
10
0
Table 5-4. PCM Slave
Symbol
Parameter
Condition
Min
Max
Unit
Tclk
Cycle time
66.67
ns
(15 MHz)
Tw
Tis
Tih
tis
High or low pulse width
AUD_IN setup time
40% of Tclk
8
0
8
0
0
AUD_IN hold time
AUD_FSYNC setup time
AUD_FSYNC hold time
AUD_OUT propagation time
tih
top
40-pF load
21
32
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6 REFERENCE DESIGN AND BOM FOR POWER AND RADIO CONNECTIONS
Figure 6-1 shows the reference schematics for the CC256x device.
Figure 6-1. Reference Schematics
Table 6-1 lists the BOM for the CC256x device.
Table 6-1. Bill of Materials
Reference
Des.
Manufacturer
Part Number
Alternate
Part
Qty
Value
Description
Manufacturer
Note
1
ANT1
NA
ANT_IIFA_CC2420_32mil_MI
R
NA
IIFA_CC2420
Chip antenna Copper
antenna on
PCB
6
2
2
2
1
1
1
1
Capacitor
Capacitor
Capacitor
Capacitor
FL1
0.1 μF
1.0 μF
CAP CER 1.0UF 6.3 V X5R
10% 0402
Kemet
C0402C104K9RACTU
JMK105BJ105KV-F
GRM1555C1H120JZ01D
JMK105BJ474KV-F
LFB212G45SG8C341
ASH7K-32.768KHZ-T
CC256xRVM
CAP CER 10-pF 50 V 5%
NP0 0402
Taiyo Yuden
12 pF (TBD)
0.47 μF
CAP CER 12 pF 6.3 V X5R
10% 0402
Murata Electronics
Taiyo Yuden
CAP CER .47UF 6.3V X5R
±10% 0402
2.45 GHz
FILTER CER BAND PASS
2.45 GHZ SMD
Murata Electronics
Place brown
marking up
OSC1
32,768 kHz 15 pF
OSC 32.768 KHZ 15 pF 1.5 V Abracon Corporation
3.3 V SMD
Optional
U5
CC2560RVM or
CC2564RVM
Bluetooth BR/EDR/LE or ANT
Single-Chip Solution
Texas Instruments
Y1
26 MHz
Crystal, 26 MHz
NDK
NX2016SA
TZ1325D
(Tai-Saw
TST)
1
C31
22 pF
CAP CER 22PF 25V 5% NP0
0201
Murata Electronics
North America
GRM0335C1E220JD01D
Copyright © 2012–2013, Texas Instruments Incorporated
mrQFN MECHANICAL DATA
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7 mrQFN MECHANICAL DATA
RVM (S-PVQFN-N76)
PLASTIC QUAD FLATPACK NO-LEAD
8,10
7,90
SQ
7,83
SQ
7,63
Pin 1 Indentifier
0,90
0,80
0,65
0,55
Seating Plane
0,08
C
0,05
0,00
5,40
4X
4,80
4X
0,30 TYP
0,70
4X
THERMAL PAD
CL –
PKG.
0,17
SIZE AND SHAPE
SHOWN ON SEPARATE SHEET
CL –
PAD
0,60
0,60
4X
0,24
0,50
76X
0,30
0,25
76X
0,10
C A B
0,15
0,60
0,24
4X
0,10
C A B
4211965/B 12/11
Bottom View
NOTES:
A. All linear dimensions are in millimeters. Dimensioning and tolerancing per ASME Y14.5-1994.
B. This drawing is subject to change without notice.
C. QFN (Quad Flatpack No-Lead) Package configuration.
D. The package thermal pad must be soldered to the board for thermal and mechanical performance.
E. See the additional figure in the Product Data Sheet for details regarding the exposed thermal pad features and dimensions.
SWRS115-001
34
mrQFN MECHANICAL DATA
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RVM (S-PVQFN-N76)
PLASTIC QUAD FLATPACK NO-LEAD
THERMAL INFORMATION
This package incorporates an exposed thermal pad that is designed to be attached directly to an external
heatsink. The thermal pad must be soldered directly to the printed circuit board (PCB). After soldering, the
PCB can be used as a heatsink. In addition, through the use of thermal vias, the thermal pad can be attached
directly to the appropriate copper plane shown in the electrical schematic for the device, or alternatively, can be
attached to a special heatsink structure designed into the PCB. This design optimizes the heat transfer from the
integrated circuit (IC).
For information on the Quad Flatpack No-Lead (QFN) package and its advantages, refer to Application Report,
QFN/SON PCB Attachment, Texas Instruments Literature No. SLUA271. This document is available at www.ti.com.
The exposed thermal pad dimensions for this package are shown in the following illustration.
CL-
PKG.
0,17
3,30 0,10
CL-
PAD
3,00 0,10
Bottom View
Exposed Thermal Pad Dimensions
4212066/B 12/11
NOTE: All linear dimensions are in millimeters
SWRS115-018
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mrQFN MECHANICAL DATA
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8 CHIP PACKAGING AND ORDERING
8.1 Package and Ordering Information
The mrQFN packaging is 76 pins and a 0.6-mm pitch.
For detailed information, see Section 7, mrQFN Mechanical Data.
Table 8-1 lists the package and order information for the device family members.
Table 8-1. Package and Order Information
Device
CC2560ARVMT
CC2560ARVMR
CC2564RVMT
CC2564RVMR
Package Suffix
RVM
Pieces/Reel
250
RVM
2500
RVM
250
RVM
2500
Figure 8-1 shows the chip markings for the CC256x family.
O
O
CC2560A
CC2564
\T/ YM7
ZLLL G3
\T/ YM7
ZLLL G3
\T/ = TI logo
Y
M
7
= Last digit of the year
= Month in hex number, 1-C for Jan-Dec
= Primary site code for ANM
= Secondary site code for ANM
Z
LLL = Assembly lot code
= Pin 1 indicator
O
SWRS121-010
Figure 8-1. Chip Markings
8.1.1 Device Support Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers. These
prefixes represent evolutionary stages of product development from engineering prototypes through fully
qualified production devices.
X
Experimental, preproduction, sample or prototype device. Device may not meet all product qualification conditions and
may not fully comply with TI specifications. Experimental/Prototype devices are shipped against the following disclaimer:
“This product is still in development and is intended for internal evaluation purposes.” Notwithstanding any provision to the
contrary, TI makes no warranty expressed, implied, or statutory, including any implied warranty of merchantability of
fitness for a specific purpose, of this device.
null Device is qualified and released to production. TI’s standard warranty applies to production devices.
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8.2 Empty Tape Portion
Figure 8-2 shows the empty portion of the carrier tape.
Empty portion
Empty portion
Device on tape portion
End
Start
The length is to extend
so that no unit is visible
on the outer layer of tape.
swrs064-001
270-mm MIN
User direction of feed
Figure 8-2. Carrier Tape and Pockets
8.3 Device Quantity and Direction
When pulling out the tape, the A1 corner is on the left side (see Figure 8-3).
A1 corner
Carrier tape
Sprocket hole
Embossment
Cover tape
User direction of feed
SWRS064-002
Figure 8-3. Direction of Device
8.4 Insertion of Device
Figure 8-4 shows the insertion of the device.
insert_swrs064
Figure 8-4. Insertion of Device
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8.5 Tape Specification
The dimensions of the tape are:
•
•
Tape width: 16 mm
Cover tape: The cover tape does not cover the index hole and does not shift to outside from the carrier
tape.
•
•
Tape structure: The carrier tape is made of plastic. The device is put in the embossed area of the
carrier tape and covered by the cover tape, which is made of plastic.
ESD countermeasure: The plastic material used in the carrier tape and the cover tape is static
dissipative.
8.6 Reel Specification
Figure 8-5 shows the reel specifications:
•
•
330-mm reel, 16-mm width tape
Reel material: Polystyrene (static dissipative/antistatic)
+2.0
16.4
–0.0
2.0 +–0.5
20.8
Ø 13.0 +0.5/–0.2
SWRS121-006
Figure 8-5. Reel Dimensions (mm)
8.7 Packing Method
The end of the leader tape is secured by drafting tape. The reel is packed in a moisture barrier bag
fastened by heat-sealing (see Figure 8-6).
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Moisture-barrier bag
reelpk_swrs064
Figure 8-6. Reel Packing Method
CAUTION
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all
integrated circuits be handled with appropriate precautions. Failure to observe proper
handling and installation procedures can cause damage. ESD damage can range from
subtle performance degradation to complete device failure. Precision integrated circuits
may be more susceptible to damage because very small parametric changes could
cause devices not to meet their published specifications.
8.8 Packing Specification
8.8.1 Reel Box
Each moisture-barrier bag is packed into a reel box, as shown in Figure 8-7.
rlbx_swrs064
Figure 8-7. Reel Box (Carton)
8.8.2 Reel Box Material
The reel box is made from corrugated fiberboard.
8.8.3 Shipping Box
If the shipping box has excess space, filler (such as cushion) is added.
Figure 8-8 shows a typical shipping box.
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NOTE
The size of the shipping box may vary depending on the number of reel boxes packed.
box_swrs064
Figure 8-8. Shipping Box (Carton)
8.8.4 Shipping Box Material
The shipping box is made from corrugated fiberboard.
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PACKAGE OPTION ADDENDUM
www.ti.com
17-Apr-2013
PACKAGING INFORMATION
Orderable Device
CC2560ARVMR
CC2560ARVMT
CC2564NSYFVR
CC2564NSYFVT
CC2564NYFVR
CC2564NYFVT
CC2564RVMR
CC2564RVMT
CC2564YFVR
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 85
Top-Side Markings
Samples
Drawing
Qty
(1)
(2)
(3)
(4)
ACTIVE
VQFN
VQFN
RVM
76
76
54
54
54
54
76
76
54
54
2500
Green (RoHS
& no Sb/Br)
CU SN
CU SN
Call TI
Call TI
Call TI
Call TI
CU SN
CU SN
Call TI
Call TI
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-1-260C-UNLIM
Level-1-260C-UNLIM
CC256
0A
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
RVM
YFV
YFV
YFV
YFV
RVM
RVM
YFV
YFV
250
5000
250
Green (RoHS
& no Sb/Br)
-40 to 85
CC256
0A
DSBGA
DSBGA
DSBGA
DSBGA
VQFN
Green (RoHS
& no Sb/Br)
CC2564
CC2564
CC2564
CC2564
Green (RoHS
& no Sb/Br)
5000
250
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
2500
250
Green (RoHS
& no Sb/Br)
-40 to 85
-40 to 85
CC256
4
VQFN
Green (RoHS
& no Sb/Br)
CC256
4
DSBGA
DSBGA
5000
250
Green (RoHS
& no Sb/Br)
CC2564
CC2564YFVT
Green (RoHS
& no Sb/Br)
CC2564
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
17-Apr-2013
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
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Addendum-Page 2
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