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Bluetooth^®and Dual-Mode Controller

1 Bluetooth and Dual-Mode Controller

– Package Footprint: 76 Pins, 0.6-mm Pitch,

8.10-mm- x 8.10-mm mrQFN

• Best-in-Class Bluetooth (RF) Performance (TX

1.1 Features

123456

• Single-Chip Bluetooth Solution Integrating

Bluetooth Basic Rate (BR)/Enhanced Data Rate

(EDR)/Low Energy (LE) Features Fully

Compliant With the Bluetooth 4.0 Specification

Up to the HCI Layer

Power, RX Sensitivity, Blocking)

– Class 1.5 TX Power Up to +12 dBm

– Internal Temperature Detection and

Compensation to Ensure Minimal Variation

in RF Performance Over Temperature, No

External Calibration Required

– Improved Adaptive Frequency Hopping

(AFH) Algorithm With Minimum Adaptation

Time

• BR/EDR Features Include:

– Up to 7 Active Devices

– Scatternet: Up to 3 Piconets Simultaneously,

1 as Master and 2 as Slaves

– Up to 2 SCO Links on the Same Piconet

– Support for All Voice Air-Coding –

– Provides Longer Range, Including 2x Range

Over Other BLE-Only Solutions

• Advanced Power Management for Extended

Battery Life and Ease of Design:

Continuously Variable Slope Delta (CVSD),

A-Law, μ-Law, and Transparent (Uncoded)

• CC2560B/CC256B Devices Provide an Assisted

Mode for HFP1.6 Wideband Speech (WBS)

Profile or A2DP Profile to Reduce Host

Processing and Power

– On-Chip Power Management, Including

Direct Connection to Battery

– Low Power Consumption for Active,

Standby, and Scan Bluetooth Modes

– Shutdown and Sleep Modes to Minimize

Power Consumption

• LE Features Include:

– Support of Up to 6 (CC2564) or 10 (CC2564B)

Simultaneous Connections

– Multiple Sniff Instances Tightly Coupled to

Achieve Minimum Power Consumption

– Independent Buffering for LE Allows Large

Numbers of Multiple Connections Without

Affecting BR/EDR Performance.

• Physical Interfaces:

– Standard HCI Over H4 UART With Maximum

Rate of 4 Mbps Supported by All CC256x

Members

– Standard HCI Over H5 UART With Maximum

Rate of 4 Mbps Supported by CC2560B and

CC2564B Devices

– Includes Built-In Coexistence and

Prioritization Handling for BR/EDR and LE

• Flexibility for Easy Stack Integration and

Validation Into Various Microcontrollers, Such

as MSP430™ and ARM^®Cortex™ M3 and M4

MCUs

– Fully Programmable Digital PCM-I2S Codec

Interface

• CC256x Bluetooth Hardware Evaluation Tool:

PC-Based Application to Evaluate RF

Performance of the Device and Configure

Service Pack

• Highly Optimized for Low-Cost Designs:

– Single-Ended 50-Ω RF Interface

1.2 Applications

•

Mobile phone accessories

Sports and fitness applications

Wireless audio solutions

Remote controls

Toys

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2

3

4

5

6

MSP430 is a trademark of Texas Instruments.

Cortex is a trademark of ARM Limited.

ARM7TDMIE is a registered trademark of ARM Limited.

ARM is a registered trademark of ARM Physical IP, Inc.

Bluetooth is a registered trademark of Bluetooth SIG, Inc.

PRODUCTION DATA information is current as of publication date. Products conform to

specifications per the terms of the Texas Instruments standard warranty. Production

processing does not necessarily include testing of all parameters.

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1.3 Description

The TI CC256x device is a complete Bluetooth BR/EDR/LE HCI solution that reduces design effort and

enables fast time to market. Based on TI’s seventh-generation Bluetooth core, the CC256x device brings

a product-proven solution that supports Bluetooth 4.0 dual-mode (BR/EDR/LE) protocols. When coupled

with an MCU device, this HCI device provides best-in-class RF performance.

TI’s power-management hardware and software algorithms provide significant power savings in all

commonly used Bluetooth BR/EDR/LE modes of operation.

With transmit power and receive sensitivity, this solution provides a best-in-class range of about 2x,

compared to other BLE-only solutions. A royalty-free software Bluetooth stack available from TI is pre-

integrated with TI's MSP430 and ARM Cortex M3 and Cortex M4 MCUs. The stack is also available for

MFi solutions and on other MCUs through TI's partner Stonestreet One (www.stonestreetone.com). Some

of the profiles supported today include: serial port profile (SPP), , human interface device (HID), and

several BLE profiles (these profiles vary based on the supported MCU)

In addition to software, this solution consists of a reference design with a low BOM cost. For more

information on TI’s wireless platform solutions for Bluetooth, see TI's Wireless Connectivity Wiki

(processors.wiki.ti.com/index.php/CC256x).

Table 1-1 lists the CC256x family members.

Table 1-1. CC256x Family Members

Device

Description

Technology Supported

Assisted Modes

Supported⁽¹⁾

BR/EDR

LE

ANT

HFP 1.6

A2DP

(WBS)

CC2560A

CC2564⁽²⁾

Bluetooth 4.0 (with EDR)

√

Bluetooth 4.0 + BLE

Bluetooth 4.0 + ANT

Bluetooth 4.0 (with EDR)

Bluetooth 4.0 + BLE

Bluetooth 4.0 + ANT

√

CC2560B

CC2564B⁽²⁾

√

(1) The assisted modes (HFP 1.6 and A2DP) are not supported simultaneously. Furthermore, the assisted modes are not supported

simultaneously with BLE or ANT.

(2) The device does not support simultaneous operation of LE and ANT.

2

Bluetooth and Dual-Mode Controller

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1.4 Functional Block Diagram

CC256x

2.4-GHz

band pass filter

Coprocessor

(See Note)

PCM/I2S

RF

I/O

interface

Modem

arbitrator

DRP

BR/EDR

main processor

HCI

UART

Power

management

Clock

management

Power Shutdown Slow

clock

Fast

clock

SWRS121-001

Note: The following technologies and assisted modes cannot

be used simultaneously with the coprocessor: LE, ANT, assisted

HFP 1.6 (WBS), and assisted A2DP. One and only one

technology or assisted mode can be used at a time.

Figure 1-1. Functional Block Diagram

Bluetooth and Dual-Mode Controller

3

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1

Bluetooth and Dual-Mode Controller ............... 1

1.1 Features ............................................. 1

1.2 Applications .......................................... 1

1.3 Description ........................................... 2

1.4 Functional Block Diagram ........................... 3

4

5

Device Specifications ................................. 28

4.1

General Device Requirements and Operation ..... 28

4.2 Bluetooth BR/EDR RF Performance ............... 32

4.3 Bluetooth LE RF Performance ..................... 34

4.4 Interface Specifications ............................. 36

Reference Design and BOM for Power and Radio

Connections ............................................ 39

mrQFN Mechanical Data ............................. 41

Chip Packaging and Ordering ...................... 43

7.1 Package and Ordering Information ................. 43

7.2 Empty Tape Portion ................................ 44

7.3 Device Quantity and Direction ...................... 44

7.4 Insertion of Device ................................. 44

7.5 Tape Specification .................................. 45

7.6 Reel Specification .................................. 45

7.7 Packing Method .................................... 45

7.8 Packing Specification ............................... 46

Revision History .............................................. 4

2

Bluetooth ................................................. 6

2.1 BR/EDR Features .................................... 6

2.2 LE Features .......................................... 6

6

7

2.3

Changes from CC2560A and CC2564 to CC2560B

and CC2564B Devices .............................. 7

2.4 Transport Layers ..................................... 7

Detailed Description .................................... 8

3.1 Pin Designation ...................................... 8

3.2 Terminal Functions .................................. 9

3.3 Device Power Supply ............................... 11

3.4 Clock Inputs ........................................ 14

3.5 Functional Blocks ................................... 17

3

Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

The following table summarizes the CC256x Data Manual versions.

Version

Literature Number

SWRS121

Date

Notes

(1)

*

July 2012

See

.

(2)

A

B

SWRS121

October 2012

April 2013

See

(3)

SWRS121

See

(1) Initial release.

(2) CC256x QFN Device – SWRS121A: Sections impacted by changes between version * and version A:

•

Title: Revised title from CC256x Bluetooth® BR/EDR/LE Single-Chip Solution.

Features section: Revised and added features, including BR/EDR and LE.

Section 2: Revised section.

Section 3: Moved BR/EDR and LE features to Features section.

Section 5.2: Revised section.

Section 5.3: Revised section.

Section 6: Added BOM.

(3) CC256x QFN Device – SWRS121B: Sections impacted by changes between version A and version B:

•

Title: Revised CC256x Bluetooth® Smart Ready Controller.

Features: Revised.

Section 1-1: Replaced Stellars with ARM M4; replaced A2DP profile with HID.

Table 1-1: Corrected typo: CC2569 > CC2564.

Fig 1-1: Reworded note for clarity.

Table 3-3: Revised values.

Section 3.5.3: Revised list.

Section 4.1.3.2.1: Revised section and table values.

Section 4.2: Revised temperature range and values in tables.

Section 4.3: Revised temperature range and values in tables.

Section 5: Revised reference schematic and BOM.

Fig 7-1: Revised figure.

4

Contents

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Version

Literature Number

Date

Notes

(4)

C

SWRS121

August 2013

See

.

(4) CC256x QFN Device – SWRS121C: Sections impacted by changes between version B and version C:

•

Features: Added assisted modes for HFP1.6 (WBS) and A2DP profiles and H5 protocol support; changed "same or different

piconets" to "same piconet"; Removed CC256xx.

•

Section 2: Added assisted modes for HFP1.6 (WBS) and A2DP profiles and H5 protocol support; changed"same or different

piconets" to "same piconet"; Added "Supports all roles defined by the Bluetooth v4.0 specifications" and "Enable 10 Bluetooth LE

connections".

•

Section 3: Added bullet for assisted modes for HFP1.6 (WBS) and A2DP profiles; Removed CC256xx; Added "One WBS connection

is supported at a time and WBS and NBS connections cannot be used simultaneously in this mode of operation"; Revised Figure 3-

16.

•

Table 3-7: Removed dual-channel support.

Table 3-8: Removed 32-kHz support.

Table 3-9: Removed 4, 8, and 12 block lengths.

Table 3-10: Removed 4 subband.

Table 3-11: Removed SNR allocation method.

Table 3-12: Added assisted A2DP sink and source.

Table 3-13: Changed "sink" to "source".

Section 4: Revised to include assisted modes for HFP1.6 (WBS) and A2DP profiles.

Section 4.1.5: Changed "Internal pulldown" to "An internal 300-kΩ pulldown".

Section 4.5.2: Revised to include information on assisted modes for HFP1.6 (WBS) and A2DP profiles.

Section 4.5.4: Added information on assisted modes for HFP1.6 (WBS) and A2DP profiles.

Section 5: Removed CC256xx.

Section 7: Removed CC256xx.

Contents

5

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2 Bluetooth

2.1 BR/EDR Features

The CC256x device fully complies with the Bluetooth 4.0 specification up to the HCI level (for the family

members and technology supported, see Table 1-1):

•

Up to seven active devices

Scatternet: Up to 3 piconets simultaneously, 1 as master and 2 as slaves

Up to two synchronous connection oriented (SCO) links on the same piconet

Very fast AFH algorithm for asynchronous connection-oriented link (ACL) and extended SCO (eSCO)

link

•

Supports typically 12-dBm TX power without an external power amplifier (PA), thus improving

Bluetooth link robustness

•

Digital radio processor (DRP™) single-ended 50-Ω I/O for easy RF interfacing

Internal temperature detection and compensation to ensure minimal variation in RF performance over

temperature

•

Flexible pulse-code modulation (PCM) and inter-IC sound (I2S) digital codec interface:

–

Full flexibility of data format (linear, A-Law, μ-Law)

Data width

Data order

Sampling

Slot positioning

Master and slave modes

High clock rates up to 15 MHz for slave mode (or 4.096 MHz for master mode)

•

Support for all voice air-coding

–

Continuously variable slope delta (CVSD)

A-Law

μ-Law

Transparent (uncoded)

The CC2560B and CC2564B devices provide an assisted mode for the HFP1.6 (wide-band speech

[WBS]) profile or A2DP profile to reduce host processing and power.

2.2 LE Features

The device fully complies with the Bluetooth 4.0 specification up to the HCI level (for the family members

and technology supported, see Table 1-1):

•

Supports all roles defined by the Bluetooth v4.0 specifications

Solution optimized for proximity and sports use cases

Supports up to 6 (CC2564) or 10 (CC2564B) simultaneous connections

Multiple sniff instances that are tightly coupled to achieve minimum power consumption

Independent buffering for LE, allowing large numbers of multiple connections without affecting BR/EDR

performance.

•

Includes built-in coexistence and prioritization handling for BR/EDR and LE

NOTE

ANT and the assisted modes (HFP1.6 and A2DP) are not available when BLE is enabled.

6

Bluetooth

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2.3 Changes from CC2560A and CC2564 to CC2560B and CC2564B Devices

The CC2560B and CC2564B devices include the following changes from the CC2560A and CC2564

devices:

•

From a hardware perspective, both devices are pin compatible. From a software perspective, each

device requires a different service pack. When operating with the two devices using the supported

Bluetooth stack, the devices are integrated seamlessly and use remains identical for each device.

•

Assisted mode for the HFP1.6 (WBS) profile or the A2DP profile to enable more advanced features

without using host processing or power

•

Support for the H5 protocol in the UART transport layer using 2-wire UART

Enable 10 Bluetooth LE connections

2.4 Transport Layers

Figure 2-1 shows the Bluetooth transport layers.

UART transport layer

Host controller interface

General

modules:

Data

Control

Event

HCI vendor-

specific

HCI data handler

HCI command handler

Trace

Timers

Sleep

Data

Link manager

Data

Link controller

RF

SWRS121-016

Figure 2-1. Bluetooth Transport Layers

Bluetooth

7

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3 Detailed Description

3.1 Pin Designation

Figure 3-1 shows the bottom view of the pin designations.

A1

A2

A3

A4

A5

A6

A7

A8

A9

A10

NC

DIG_LDO_OUT

HCI_CTS

DIG_LDO_OUT

VSS

A30

A29

A28

A27

A26

A25

A24

A23

A22

A21

B27

B26

B25

B24

B23

B22

B21

B20

B19

B1

B2

B3

B4

B5

B6

B7

B8

SRAM_LDO_OUT

DIG_LDO_OUT

MLDO_OUT

DIG_LDO_OUT

VSS_FREF

VDD_IO

NC

XTALM/FREFM

XTALP/FREFP

MLDO_OUT

TX_DBG

HCI_RX

NC

MLDO_IN

SLOW_CLK

VDD_IO

VSS

nSHUTD

CL1.5_LDO_IN

CL1.5_LDO_OUT

MLDO_OUT

VDD_IO

NC

ADC_PPA_LDO_OUT

BT_RF

NC

MLDO_OUT

VDD_IO

NC

B9

NC

SWRS121-002

Figure 3-1. Pin Designation (Bottom View)

8

Detailed Description

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3.2 Terminal Functions

Table 3-1 describes the terminal functions.

Table 3-1. Device Pad Descriptions

Pull

at

Reset

Def.

I/O

Name

I/O Signals

No.

Description

Dir.⁽¹⁾

Type⁽²⁾

HCI universal asynchronous receiver/transmitter (UART) data

receive

HCI_RX

HCI_TX

HCI_RTS

A26

A33

A32

PU

I

8 mA

O

HCI UART data transmit

HCI UART request-to-send

The host is allowed to send data when HCI_RTS is low.

HCI UART clear-to-send

HCI_CTS

A29

PU

I

8 mA

4 mA

The CC256x device is allowed to send data when HCI_CTS is

low.

AUD_FSYNC

AUD_CLK

AUD_IN

A35

B32

B34

B33

PD

I/O

I

pulse-code modulation (PCM) frame-sync signal

Fail-safe

HY, 4 mA PCM clock

4 mA

PCM data input

AUD_OUT

O

PCM data output

TI internal debug messages. TI recommends

leaving an internal test point.

TX_DBG

B24

PU

O

2 mA

Clock Signals

SLOW_CLK

A25

B4

I

32.768-kHz clock in

Fail-safe

Fast clock in analog (sine wave)

Output terminal of fast-clock crystal

XTALP/FREFP

XTALM/FREFM

Fast clock in digital (square wave)

Input terminal of fast-clock crystal

A4

I

Fail-safe

Analog Signals

BT_RF

B8

A6

I/O

I

Bluetooth RF I/O

nSHUTD

PD

Shutdown input (active low)

Power and Ground Signals

A17,

A34,

A38,

B18,

B19,

B21,

B22,

B25

VDD_IO

I

I/O power supply (1.8-V nominal)

Main LDO input

Connect directly to battery

MLDO_IN

B5

I

A5, A9,

B2, B7

MLDO_OUT

I/O

Main LDO output (1.8-V nominal)

Power amplifier (PA) LDO input

Connect directly to battery

CL1.5_LDO_IN

B6

A7

I

CL1.5_LDO_OUT

O

PA LDO output

A2, A3,

B15,

B26,

B27,

B35,

B36

Digital LDO output

QFN pin B26 or B27 must be shorted to other

DIG_LDO_OUT pins on the PCB.

DIG_LDO_OUT

O

SRAM_LDO_OUT

DCO_LDO_OUT

B1

O

SRAM LDO output

DCO LDO output

A12

(1) I = input; O = output; I/O = bidirectional

(2) I/O Type: Digital I/O cells. HY = input hysteresis, current = typical output current

Detailed Description

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Table 3-1. Device Pad Descriptions (continued)

Pull

at

Reset

Def.

I/O

Name

No.

Description

Dir.⁽¹⁾

Type⁽²⁾

ADC_PPA_LDO_OUT

VSS

A8

O

I

ADC/PPA LDO output

Ground

A24,

A28

VSS_DCO

VSS_FREF

No Connect

NC

B11

B3

I

DCO ground

Fast clock ground

A1

Not connected

TI internal use

NC

A10

A11

A14

A18

A19

A20

A21

A22

A23

A27

A30

A31

A40

B9

NC

B10

B16

B17

B20

B23

A13

A15

A16

A36

A37

A39

B12

B13

B14

B29

B30

B31

B28

NC

O

NC

I/O

I

NC

I

NC

O

NC

O

NC

I/O

I

NC

I

10

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3.3 Device Power Supply

The CC256x power-management hardware and software algorithms provide significant power savings,

which is a critical parameter in a microcontroller-based system.

The power-management module is optimized for drawing very low currents.

3.3.1 Power Sources

The CC256x device requires two power sources:

•

VDD_IN: Main power supply for the Bluetooth core

VDD_IO: Power source for the 1.8-V I/O ring

The device includes several on-chip voltage regulators for increased noise immunity and can be

connected directly to the battery.

3.3.2 Device Power-Up and Power-Down Sequencing

The device includes the following power-up requirements (see Figure 3-2):

•

nSHUTD must be low. VDD_IN and VDD_IO are don't-care when nSHUTD is low. However, signals

are not allowed on the I/O pins if I/O power is not supplied, because the I/Os are not fail-safe.

Exceptions are SLOW_CLK_IN and AUD_xxx, which are fail-safe and can tolerate external voltages

with no VDD_IO and VDD_IN.

•

VDD_IO and VDD_IN must be stable before releasing nSHUTD.

The fast clock must be stable within 20 ms of nSHUTD going high.

The slow clock must be stable within 2 ms of nSHUTD going high.

The device indicates that the power-up sequence is complete by asserting RTS low, which occurs up to

100 ms after nSHUTD goes high. If RTS does not go low, the device is not powered up. In this case,

ensure that the sequence and requirements are met.

Shut down

before

VDD_IO

removed

20 µs max

nSHUTD

VDD_IO

VDD_IN

2 ms max

SLOW CLOCK

20 ms max

FAST CLOCK

ꢀ00 ms

HCI_RTS

CC256x ready

SWRS098-008

Figure 3-2. Power-Up and Power-Down Sequence

Detailed Description

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3.3.3 Power Supplies and Shutdown—Static States

The nSHUTD signal puts the device in ultra-low power mode and also performs an internal reset to the

device. The rise time for nSHUTD must not exceed 20 μs, and nSHUTD must be low for a minimum of

5 ms.

To prevent conflicts with external signals, all I/O pins are set to the high-impedance state during shutdown

and power up of the device. The internal pull resistors are enabled on each I/O pin, as described in .

Table 3-2 describes the static operation states.

Table 3-2. Power Modes

VDD_IN⁽¹⁾

VDD_IO⁽¹⁾

nSHUTD⁽¹⁾

PM_MODE

Comments

1

2

3

4

5

6

7

8

None

Asserted

Shut down

I/O state is undefined. No I/O voltages are allowed on nonfail-

safe pins.

None

Present

None

Deasserted

Asserted

Not allowed

Shut down

Not allowed

Shut down

Not allowed

Shut down

Active

I/O state is undefined. No I/O voltages are allowed on nonfail-

safe pins.

I/Os are defined as 3-state with internal pullup or pulldown

enabled.

None

Deasserted

Asserted

I/O state is undefined. No I/O voltages are allowed on nonfail-

safe pins.

Present

I/O state is undefined. No I/O voltages are allowed on nonfail-

safe pins.

None

Deasserted

Asserted

I/O state is undefined. No I/O voltages are allowed on nonfail-

safe pins.

Present

I/OS are defined as 3-state with internal pullup or pulldown

enabled.

Present

Deasserted

See Section 3.3.4, I/O States In Various Power Modes.

(1) The terms None or Asserted can imply any of the following conditions: directly pulled to ground or driven low, pulled to ground through a

pulldown resistor, or left NC or floating (high-impedance output stage).

12

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3.3.4 I/O States In Various Power Modes

CAUTION

Some device I/Os are not fail-safe (see ). Fail-safe means that the pins do not draw

current from an external voltage applied to the pin when I/O power is not supplied to the

device. External voltages are not allowed on these I/O pins when the I/O supply voltage

is not supplied because of possible damage to the device.

I/O Name

Shut Down⁽¹⁾

I/O State

Default Active⁽¹⁾

Deep Sleep⁽¹⁾

Pull

PU

PD

PU

I/O State

Pull

PU

—

I/O State

Pull

PU

—

HCI_RX

Z

I

O

I

HCI_TX

O-H

HCI_RTS

HCI_CTS

AUD_CLK

AUD_FSYNC

AUD_IN

O-H

—

I

PU

PD

—

PU

PD

I

AUD_OUT

TX_DBG

Z

O

Z

(1) I = input, O = output, Z = Hi-Z, — = no pull, PU = pullup, PD = pulldown, H = high, L = low

Detailed Description

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3.4 Clock Inputs

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3.4.1 Slow Clock

An external source must supply the slow clock and connect to the SLOW_CLK_IN pin (for example, the

host or external crystal oscillator). The source must be a digital signal in the range of 0 to 1.8 V.

The accuracy of the slow clock frequency must be 32.768 kHz ±250 ppm for Bluetooth use (as specified in

the Bluetooth specification).

The external slow clock must be stable within 64 slow-clock cycles (2 ms) following the release of

nSHUTD.

3.4.2 Fast Clock Using External Clock Source

An external clock source is fed to an internal pulse-shaping cell to provide the fast-clock signal for the

device. The device incorporates an internal, automatic clock-scheme detection mechanism that

automatically detects the fast-clock scheme used and configures the F_REFcell accordingly. This

mechanism ensures that the electrical characteristics (loading) of the fast-clock input remain static

regardless of the scheme used and eliminates any power-consumption penalty-versus-scheme used.

This section describes the requirements for fast clock use. The frequency variation of the fast-clock source

must not exceed ±20 ppm (as defined by the Bluetooth specification).

The external clock can be AC- or DC-coupled, sine or square wave.

3.4.2.1 External F_REFDC-Coupled

Figure 3-3 and Figure 3-4 show the clock configuration when using a square wave, DC-coupled external

source for the fast clock input.

NOTE

A shunt capacitor with a range of 10 nF must be added on the oscillator output to reject high

harmonics and shape the signal to be close to a sinusoidal waveform.

TI recommends using only a dedicated LDO to feed the oscillator. Do not use the same VIO

for the oscillator and the CC256x device.

FREFP

CC256x

FREFM

SWRS121-009

Figure 3-3. Clock Configuration (Square Wave, DC-Coupled)

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V_Fref[V]

2.1

V_{high_min}

1.0

V_{low_max}

0.37

–0.2

t

clksqtd_wrs064

Figure 3-4. External Fast Clock (Square Wave, DC-Coupled)

Figure 3-5 and Figure 3-6 show the clock configuration when using a sine wave, DC-coupled external

source for the fast clock input.

FREFP

CC256x

FREFM

VDD_IO

SWRS121-007

Figure 3-5. Clock Configuration (Sine Wave, DC-Coupled)

V_IN

1.6 V

VPP = 0.4 – 1.6 Vp-p

V_dc= 0.2 – 1.4 V

0

t

SWRS097-023

Figure 3-6. External Fast Clock (Sine Wave, DC-Coupled)

3.4.2.2 External F_REFSine Wave, AC-Coupled

Figure 3-7 and Figure 3-8 show the configuration when using a sine wave, AC-coupled external source for

the fast-clock input.

FREFP

68 pF

CC256x

FREFM

VDD_IO

SWRS121-008

Figure 3-7. Clock Configuration (Sine Wave, AC-Coupled)

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V_IN[V]

1 V

VPP = 0.4 – 1.6 Vp-p

0.8

0.2

0

t

–0.2

–0.8

SWRS097-022

Figure 3-8. External Fast Clock (Sine Wave, AC-Coupled)

In cases where the input amplitude is greater than 1.6 Vp-p, the amplitude can be reduced to within limits.

Using a small series capacitor forms a voltage divider with the internal input capacitance of approximately

2 pF to provide the required amplitude at the device input.

3.4.2.3 Fast Clock Using External Crystal

The CC256x device incorporates an internal crystal oscillator buffer to support a crystal-based fast-clock

scheme. The supported crystal frequency is 26 MHz.

The frequency accuracy of the fast clock source must not exceed ±20 ppm (including the accuracy of the

capacitors, as specified in the Bluetooth specification).

Figure 3-9 shows the recommended fast-clock circuitry.

CC256x

C1

XTALM

Oscillator

buffer

XTAL

XTALP

C2

SWRS098-003

Figure 3-9. Fast-Clock Crystal Circuit

Table 3-3 lists component values for the fast-clock crystal circuit.

Table 3-3. Fast-Clock Crystal Circuit Component

Values

FREQ (MHz)

C1 (pF)⁽¹⁾

C2 (pF)⁽¹⁾

26

12

(1) To achieve the required accuracy, values for C1 and C2 must be

taken from the crystal manufacturer's data sheet and layout

considerations.

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3.5 Functional Blocks

The CC256x architecture comprises a DRP and a point-to-multipoint baseband core. The architecture is

based on a single-processor ARM7TDMIE^®core. The device includes several on-chip peripherals to

enable easy communication with a host system and the Bluetooth BR/EDR/LE core.

3.5.1 RF

The device is the third generation of TI Bluetooth single-chip devices using DRP architecture.

Modifications and new features added to the DRP further improve radio performance.

Figure 3-10 shows the DRP block diagram.

Transmitter path

Amplitude

TX digital data

Digital

ADPLL

DPA

Phase

Receiver path

IFA

RX digital data

Demodulation

ADC

Filter

LNA

SWRS092-005

Figure 3-10. DRP Block Diagram

3.5.1.1 Receiver

The receiver uses near-zero-IF architecture to convert the RF signal to baseband data. The signal

received from the external antenna is input to a single-ended LNA (low-noise amplifier) and passed to a

mixer that downconverts the signal to IF, followed by a filter and amplifier. The signal is then quantized by

a sigma-delta analog-to-digital converter (ADC) and further processed to reduce the interference level.

The demodulator digitally downconverts the signal to zero-IF and recovers the data stream using an

adaptive-decision mechanism. The demodulator includes EDR processing with:

•

State-of-the-art performance

A maximum-likelihood sequence estimator (MLSE) to improve the performance of basic-rate GFSK

sensitivity

•

Adaptive equalization to enhance EDR modulation

New features include:

•

LNA input range narrowed to increase blocking performance

Active spur cancellation to increase robustness to spurs

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3.5.1.2 Transmitter

The transmitter is an all-digital, sigma-delta phase-locked loop (ADPLL) based with a digitally controlled

oscillator (DCO) at 2.4 GHz as the RF frequency clock. The transmitter direct modulates the digital PLL.

The power amplifier is also digitally controlled. The transmitter uses the polar-modulation technique. While

the phase-modulated control word is fed to the ADPLL, the amplitude-modulated controlled word is fed to

the class-E amplifier to generate a Bluetooth standard-compliant RF signal.

New features include:

•

Improved TX output power

LMS algorithm to improve the differential error vector magnitude (DEVM)

3.5.2 Host Controller Interface

The CC256x device incorporates one UART module dedicated to the HCI transport layer. The HCI

interface transports commands, events, and ACL between the device and the host using HCI data

packets.

All members of the CC256x family support the H4 protocol (4-wire UART) with hardware flow control. The

CC2560B and CC2564B devices also support the H5 protocol (3-wire UART) with software flow control.

The CC256x device automatically detects the protocol when it receives the first command.

The maximum baud rate of the UART module is 4 Mbps; however, the default baud rate after power up is

set to 115.2 kbps. The baud rate can thereafter be changed with a VS command. The device responds

with a Command Complete event (still at 115.2 kbps), after which the baud rate change occurs.

The UART module includes the following features:

•

Receiver detection of break, idle, framing, FIFO overflow, and parity error conditions

Transmitter underflow detection

CTS and RTS hardware flow control (H4 protocol)

XON and XOFF software flow control (H5 protocol)

Table 3-4 lists the UART module default settings.

Table 3-4. UART Default Settings

Parameter

Bit rate

Value

115.2 kbps

8 bits

Data length

Stop-bit

1

Parity

None

3.5.2.1 H4 Protocol—4-Wire UART Interface

The interface includes four signals:

•

TX

RX

CTS

RTS

Flow control between the host and the CC256x device is bytewise by hardware.

Figure 3-11 shows the H4 UART interface.

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HCI_RX

HCI_TX

Host_RX

Host_TX

Host

CC256x

HCI_CTS

HCI_RTS

Host_CTS

Host_RTS

SWRS121-003

Figure 3-11. H4 UART Interface

When the UART RX buffer of the CC256x device passes the flow control threshold, it sets the UART_RTS

signal high to stop transmission from the host.

When the UART_CTS signal is set high, the CC256x device stops its transmission on the interface. If

HCI_CTS is set high while transmitting a byte, the CC256x device finishes transmitting the byte and stops

the transmission.

The H4 protocol device includes a mechanism that handles the transition between active mode and sleep

mode. The protocol occurs through the CTS and RTS UART lines and is known as the enhanced HCI low

level (eHCILL) power-management protocol.

For more information on the H4 UART protocol, see Volume 4 Host Controller Interface, Part A UART

Transport

Layer

of

the

Bluetooth

Core

Specifications

(www.bluetooth.org/en-

us/specification/adoptedspecifications).

3.5.2.2 H5 Protocol—3-Wire UART Interface (CC2560B and CC2564B Devices)

The H5 UART interface consists of three signals (see Figure 3-12):

•

TX

RX

GND

Figure 3-12. H5 UART Interface

The H5 protocol supports the following features:

•

Software flow control (XON/XOFF)

Power management using the software messages:

–

WAKEUP

WOKEN

SLEEP

•

CRC data integrity check

For more information on the H5 UART protocol, see Volume 4 Host Controller Interface, Part D Three-

Wire UART Transport Layer of the Bluetooth Core Specifications (www.bluetooth.org/en-

us/specification/adoptedspecifications).

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3.5.3 Digital Codec Interface

The codec interface is a fully programmable port to support seamless interfacing with different PCM and

I2S codec devices. The interface includes the following features:

•

Two voice channels

Master and slave modes

All voice coding schemes defined by the Bluetooth specification: linear, A-Law, and μ-Law

Long and short frames

Different data sizes, order, and positions

High flexibility to support a variety of codecs

Bus sharing: Data_Out is in Hi-Z mode when the interface is not transmitting voice data.

3.5.3.1 Hardware Interface

The interface includes four signals:

•

Clock: configurable direction (input or output)

Frame_Sync and Word_Sync: configurable direction (input or output)

Data_In: input

Data_Out: output or 3-state

The CC256x device can be the master of the interface when generating the clock and the frame-sync

signals or the slave when receiving these two signals.

For slave mode, clock input frequencies of up to 15 MHz are supported. At clock rates above 12 MHz, the

maximum data burst size is 32 bits.

For master mode, the CC256x device can generate any clock frequency between 64 kHz and 4.096 MHz.

3.5.3.2 I2S

When the codec interface is configured to support the I2S protocol, these settings are recommended:

•

Bidirectional, full-duplex interface

Two time slots per frame: time slot-0 for the left channel audio data; and time slot-1 for the right

channel audio data

•

Each time slot is configurable up to 40 serial clock cycles long, and the frame is configurable up to 80

serial clock cycles long.

3.5.3.3 Data Format

The data format is fully configurable:

•

The data length can be from 8 to 320 bits in 1-bit increments when working with 2 channels, or up to

640 bits when working with 1 channel. The data length can be set independently for each channel.

The data position within a frame is also configurable within 1 clock (bit) resolution and can be set

independently (relative to the edge of the Frame_Sync signal) for each channel.

The Data_In and Data_Out bit order can be configured independently. For example; Data_In can start

with the most significant bit (MSB); Data_Out can start with the least significant bit (LSB). Each

channel is separately configurable. The inverse bit order (that is, LSB first) is supported only for

sample sizes up to 24 bits.

•

It is not necessary for Data_In and Data_Out to be the same length.

The Data_Out line is configured to Hi-Z output between data words. Data_Out can also be set for

permanent Hi-Z, regardless of data out. This allows the CC256x device to be a bus slave in a

multislave PCM environment. At power up, Data_Out is configured as Hi-Z.

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3.5.3.4 Frame Idle Period

The codec interface handles frame idle periods, in which the clock pauses and becomes 0 at the end of

the frame, after all data are transferred.

The CC256x device supports frame idle periods both as master and slave of the codec bus.

When the CC256x device is the master of the interface, the frame idle period is configurable. There are

two configurable parameters:

•

Clk_Idle_Start: indicates the number of clock cycles from the beginning of the frame to the beginning of

the idle period. After Clk_Idle_Start clock cycles, the clock becomes 0.

•

Clk_Idle_End: indicates the time from the beginning of the frame to the end of the idle period. The time

is given in multiples of clock periods.

The delta between Clk_Idle_Start and Clk_Idle_End is the clock idle period.

For example, for clock rate = 1 MHz, frame sync period = 10 kHz, Clk_Idle_Start = 60, Clk_Idle_End = 90.

Between both frame-sync signals there are 70 clock cycles (instead of 100). The clock idle period starts

60 clock cycles after the beginning of the frame and lasts 90 – 60 = 30 clock cycles. This means that the

idle period ends 100 – 90 = 10 clock cycles before the end of the frame. The data transmission must end

before the beginning of the idle period.

Figure 3-13 shows the frame idle timing.

Frame period

Frame_Sync

Data_In

Data_Out

Frame idle

Clock

Clk_Idle_Start

Clk_Idle_End

frmidle_swrs064

Figure 3-13. Frame Idle Period

3.5.3.5 Clock-Edge Operation

The codec interface of the CC256x device can work on the rising or the falling edge of the clock and can

sample the frame-sync signal and the data at inversed polarity.

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Figure 3-14 shows the operation of a falling-edge-clock type of codec. The codec is the master of the bus.

The frame-sync signal is updated (by the codec) on the falling edge of the clock and is therefore sampled

(by the CC256x device) on the next rising clock. The data from the codec is sampled (by the CC256x

device) on the falling edge of the clock.

PCM FSYNC

PCM CLK

D7

D6

D5

D4

D2

D1

D0

D3

PCM DATA IN

CC256x

SAMPLE TIME

SWRS121-004

Figure 3-14. Negative Clock Edge Operation

3.5.3.6 Two-Channel Bus Example

Figure 3-15 shows a 2-channel bus in which the two channels have different word sizes and arbitrary

positions in the bus frame. (FT stands for frame timer.)

...

Clock

...

FT

2

5

127 0

1

3

4

6

7

8

9

42 43 44

127 0

Fsync

MSB

bit bit bit bit bit bit bit bit

MSB

LSB

bit bit bit bit bit bit bit bit bit bit bit

10

...

Data_Out

Data_In

0

1

2

3

4

5

6

7

8

9

0

1

2

3

4

5

6

7

bit bit bit bit bit bit bit bit bit bit bit

10

bit bit bit bit bit bit bit bit

1

0

1

2

3

4

5

6

7

8

9

0

2

3

4

5

6

7

PCM_data_window

CH2 data

start FT = 43

CH1 data start FT = 0

CH1 data length = 11

CH2 data

length = 8

Fsync period = 128

Fsync length = 1

twochpcm_swrs064

Figure 3-15. Two-Channel Bus Timing

3.5.3.7 Improved Algorithm For Lost Packets

The CC256x device features an improved algorithm to improve voice quality when received voice data

packets are lost. There are two options:

•

Repeat the last sample: possible only for sample sizes up to 24 bits. For sample sizes larger than 24

bits, the last byte is repeated.

•

Repeat a configurable sample of 8 to 24 bits (depending on the real sample size) to simulate silence

(or anything else) in the bus. The configured sample is written in a specific register for each channel.

The choice between those two options is configurable separately for each channel.

3.5.3.8 Bluetooth and Codec Clock Mismatch Handling

In Bluetooth RX, the CC256x device receives RF voice packets and writes them to the codec interface. If

the CC256x device receives data faster than the codec interface output allows, an overflow occurs. In this

case, the Bluetooth has two possible behavior modes:

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•

Allow overflow: if overflow is allowed, the Bluetooth continues receiving data and overwrites any data

not yet sent to the codec.

•

Do not allow overflow: if overflow is not allowed, RF voice packets received when the buffer is full are

discarded.

3.5.4 Assisted Modes (CC2560B and CC2564B Devices)

The CC256x devices contain an embedded coprocessor (see Figure 1-1) that can be used for multiple

purposes. The CC2564 and CC2564B devices use this coprocessor to perform the LE or ANT

functionality. The CC2560B and CC2564B devices can use this coprocessor to execute the assisted HFP

1.6 (WBS) or assisted A2DP functions. Only one of these functions can be executed at a time because

they all use the same resources, that is, the coprocessor (see Table 1-1 for the modes of operation

supported by each device).

This section describes the assisted HFP 1.6 (WBS) and assisted A2DP modes of operation in the

CC2560B and CC2564B devices. These modes of operation minimize host processing and power by

taking advantage of the CC256x coprocessor to perform the voice and audio SBC processing required in

HFP1.6 (WBS) and A2DP profiles. This section also compares the architecture of the assisted modes with

the common implementation of the HFP1.6 and A2DP profiles.

The assisted HFP1.6 (WBS) and assisted A2DP modes of operation comply fully with the HFP1.6 and

A2DP Bluetooth specifications. For more information on these profiles, see the corresponding Bluetooth

Profile Specification (www.bluetooth.org/en-us/specification/adopted-specifications).

3.5.4.1 Assisted HFP1.6 (WBS)

The HFP1.6 Profile Specification adds the requirement for WBS support. The WBS feature allows twice

the voice quality versus legacy voice coding schemes at the same air bandwidth (64 kbps). This feature is

achieved using a voice sampling rate of 16 kHz, a modified subband coding (mSBC) scheme, and a

packet loss concealment (PLC) algorithm. The mSBC is a modified version of the mandatory audio coding

scheme used in the A2DP profile with the parameters listed in Table 3-5.

Table 3-5. mSBC Parameters

Parameter

Channel mode

Sampling rate

Allocation method

Subbands

Value

Mono

16 kHz

Loudness

8

Block length

Bitpool

15

26

The assisted HFP1.6 mode of operation implements this WBS feature on the embedded CC256x

coprocessor. That is, the mSBC voice coding scheme and the PLC algorithm are executed in the CC256x

coprocessor rather than in the host, thus minimizing the host processing and power. One WBS connection

is supported at a time and WBS and NBS connections cannot be used simultaneously in this mode of

operation. Figure 3-16 shows the architecture comparison between the common implementation of the

HFP1.6 profile and the assisted HFP1.6 solution.

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Figure 3-16. 3HFP1.6 Architecture Versus Assisted HFP1.6 Architecture

For detailed information on the HFP1.6 profile, see the Hands-Free Profile 1.6 Specification

(www.bluetooth.org/en-us/specification/adopted-specifications).

3.5.4.2 Assisted A2DP

The advanced audio distribution profile (A2DP) enables wireless transmission of high-quality mono or

stereo audio between two devices. A2DP defines two roles:

•

A2DP source is the transmitter of the audio stream.

A2DP sink is the receiver of the audio stream.

A typical use case streams music from a tablet, phone, or PC (the A2DP source) to headphones or

speakers (the A2DP sink). This section describes the architecture of these roles and compares them with

the corresponding assisted-A2DP architecture. To use the air bandwidth efficiently, the audio data must be

compressed in a proper format. The A2DP profile mandates support of SBC coding. Other audio coding

algorithms can be used; however, both Bluetooth devices must support the same coding scheme. SBC

coding is the only coding scheme spread out in all A2DP Bluetooth devices and thus the only coding

scheme supported in the assisted A2DP modes. Table 3-6 lists the recommended parameters for SBC

coding in the assisted A2DP modes.

Table 3-6. Recommended Parameters for SBC Coding in Assisted A2DP Modes

SBC

Mid Quality

High Quality

Encoder

Settings⁽¹⁾

Mono

Joint Stereo

44.1

35

Mono

Joint Stereo

44.1

53

Sampling

frequency

(kHz)

44.1

19

48

18

48

33

44.1

31

48

29

48

51

Bitpool value

(1) Other settings: Block length = 16; allocation method = loudness; subbands = 8.

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Table 3-6. Recommended Parameters for SBC Coding in Assisted A2DP Modes (continued)

Resulting

frame length

(bytes)

46

44

83

79

70

66

119

328

115

345

Resulting bit

rate (Kb/s)

127

132

229

237

193

198

The SBC coding scheme supports a wide variety of configurations to adjust the audio quality. Table 3-7

through Table 3-14 list the supported SBC capabilities in the assisted A2DP modes.

Table 3-7. Channel Modes

Channel Mode

Mono

Status

Supported

Stereo

Joint stereo

Table 3-8. Sampling Frequency

Sampling Frequency (kHz)

Status

16

44.1

48

Supported

Table 3-9. Block Length

Table 3-10. Subbands

Block Length

Status

16

Supported

Subbands

Status

8

Supported

Table 3-11. Allocation Method

Table 3-12. Bitpool Values

Allocation Method

Status

Loudness

Supported

Bitpool Range

Status

Assisted A2DP sink: TBD

Assisted A2DP source: 2–57

Supported

Table 3-13. L2CAP MTU Size

L2CAP MTU Size (Bytes)

Status

Assisted A2DP sink: 260–800

Supported

Assisted A2DP source: 260–1021

Table 3-14. Miscellaneous Parameters

Item

Value

Status

A2DP content protection

AVDTP service

Protected

Basic type

Not supported

Supported

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Table 3-14. Miscellaneous Parameters (continued)

Item

Value

Status

L2CAP mode

L2CAP flush

Basic mode

Nonflushable

Supported

For detailed information on the A2DP profile, see the A2DP Profile Specification (www.bluetooth.org/enus/

specification/adopted-specifications).

3.5.4.2.1 Assisted A2DP Sink

The A2DP sink role is the receiver of the audio stream in an A2DP Bluetooth connection. In this role, the

A2DP layer and its underlying layers are responsible for link management and data decoding. To handle

these tasks, two logic transports are defined:

•

Control and signaling logic transport

Data packet logic transport

The assisted A2DP takes advantage of this modularity to handle the data packet logic transport in the

CC256x device by implementing a light L2CAP layer (L-L2CAP) and light AVDTP layer (L-AVDTP) to

defragment the packets. Then the assisted A2DP performs the SBC decoding on-chip to deliver raw audio

data through the CC256x PCM–I2S interface. Figure 3-17 shows the comparison between a common

A2DP sink architecture and the assisted A2DP sink architecture.

A2DP Sink Architecture

Assisted A2DP Sink Architecture

Host Processor

Bluetooth Stack

44.1 KHz

48 KHz

PCM

/

I2S

Audio

CODEC

16 bits

A2DP

Profile

A2DP

Profile

SBC

AVDTP

Control

Data

Control

L2CAP

HCI

Control Data

HCI

Control

Data

44.1 KHz

48 KHz

HCI

PCM

/

Audio

CODEC

I2S

16 bits

CC256x

Bluetooth Controller

CC256x

Bluetooth Controller

SBC

L-AVDTP

L-L2CAP

Figure 3-17. A2DP Sink Architecture Versus Assisted A2DP Sink Architecture

For more information on the A2DP sink role, see the A2DP Profile Specification (www.bluetooth.org/enus/

specification/adopted-specifications).

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3.5.4.2.2 Assisted A2DP Source

The role of the A2DP source is to transmit the audio stream in an A2DP Bluetooth connection. In this role,

the A2DP layer and its underlying layers are responsible for link management and data encoding. To

handle these tasks, two logic transports are defined:

•

Control and signaling logic transport

Data packet logic transport

The assisted A2DP takes advantage of this modularity to handle the data packet logic transport in the

CC256x device. First, the assisted A2DP encodes the raw data from the CC256x PCM–I2S interface

using an on-chip SBC encoder. The assisted A2DP then implements a light L2CAP layer (L-L2CAP) and

light AVDTP layer (L-AVDTP) to fragment and packetize the encoded audio data. Figure 3-18 shows the

comparison between a common A2DP source architecture and the assisted A2DP source architecture.

A2DP Source Architecture

Assisted A2DP Source Architecture

Host Processor

Bluetooth Stack

44.1 KHz

48 KHz

PCM

/

I2S

Audio

CODEC

16 bits

A2DP

Profile

A2DP

Profile

SBC

AVDTP

Control

Data

Control

L2CAP

HCI

Control Data

HCI

Control

Data

44.1 KHz

48 KHz

HCI

PCM

/

Audio

CODEC

I2S

16 bits

CC256x

Bluetooth Controller

CC256x

Bluetooth Controller

SBC

L-AVDTP

L-L2CAP

Figure 3-18. A2DP Source Architecture Versus Assisted A2DP Source Architecture

For more information on the A2DP source role, see the A2DP Profile Specification

(www.bluetooth.org/enus/ specification/adopted-specifications).

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4 Device Specifications

Unless otherwise indicated, all measurements are taken at the device pins of the TI test evaluation board

(EVB).

All specifications are over process, voltage and temperature, unless otherwise indicated.

4.1 General Device Requirements and Operation

4.1.1 Absolute Maximum Ratings

Over operating free-air temperature range (unless otherwise noted)

NOTE

Unless otherwise indicated, all parameters are measured as follows:

VDD_IN = 3.6 V, VDD_IO = 1.8 V

(1)

See

Value

Unit

Ratings over operating free-air temperature range

VDD_IN

Supply voltage range

–0.5 to 4.8

–0.5 to 2.145

–0.5 to 2.1

–0.5 to (VDD_IO + 0.5)

–40 to 85

V⁽²⁾

V

VDDIO_1.8V

Input voltage to analog pins⁽³⁾

Input voltage to all other pins

Operating ambient temperature range⁽⁴⁾

Storage temperature range

Bluetooth RF inputs

V

°C

dBm

–55 to 125

10

Human body model (HBM)⁽⁶⁾

Charged device model (CDM)⁽⁷⁾

Device

500

ESD stress

voltage⁽⁵⁾

V

250

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating

conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) Maximum allowed depends on accumulated time at that voltage: VDD_IN is defined in Section 5, Reference Design for Power and

Radio Connections.

(3) Analog pins: BT_RF, XTALP, and XTALM

(4) The reference design supports a temperature range of –20°C to 70°C because of the operating conditions of the crystal.

(5) ESD measures device sensitivity and immunity to damage caused by electrostatic discharges into the device.

(6) The level listed is the passing level per ANSI/ESDA/JEDEC JS-001. JEDEC document JEP155 states that 500-V HBM allows safe

manufacturing with a standard ESD control process, and manufacturing with less than 500-V HBM is possible, if necessary precautions

are taken. Pins listed as 1000 V can actually have higher performance.

(7) The level listed is the passing level per EIA-JEDEC JESD22-C101E. JEDEC document JEP157 states that 250-V CDM allows safe

manufacturing with a standard ESD control process, and manufacturing with less than 250-V CDM is possible, if necessary precautions

are taken. Pins listed as 250 V can actually have higher performance.

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4.1.2 Recommended Operating Conditions

Rating

Condition

Sym

VDD_IN

VDD_IO

V_IH

Min

Max

Unit

V

Power supply voltage

I/O power supply voltage

High-level input voltage

Low-level input voltage

2.2

4.8

1.92

1.62

V

Default

0.65 x VDD_IO

VDD_IO

0.35 x VDD_IO

10

V

V_IL

0

1

V

I/O input rise and all times,10% to 90% — asynchronous mode

t_rand t_f

ns

I/O input rise and fall times, 10% to 90% — synchronous mode

(PCM)

2.5

Voltage dips on VDD_IN (V_BAT

duration = 577 μs to 2.31 ms, period = 4.6 ms

Maximum ambient operating temperature⁽¹⁾

)

400

85

mV

°C

(2)

–40

(1) The device can be reliably operated for 7 years at T_ambientof 85°C, assuming 25% active mode and 75% sleep mode (15,400

cumulative active power-on hours).

(2) A crystal-based solution is limited by the temperature range required of the crystal to meet 20 ppm.

4.1.3 Current Consumption

4.1.3.1 Static Current Consumption

Operational Mode

Min

Typ

1

Max

7

Unit

Shutdown mode⁽¹⁾

Deep sleep mode⁽²⁾

Idle mode

µA

40

4

105

mA

Total I/O current consumption in active mode

Continuous transmission—GFSK⁽³⁾

Continuous transmission—EDR⁽⁴⁾⁽⁵⁾

1

77

82.5

(1) V_BAT+ V_IO+ V_SHUTDOWN

(2) V_BAT+ V_IO

(3) At maximum output power (12 dBm)

(4) At maximum output power (10 dBm)

(5) Both π/4 DQPSK and 8DPSK

4.1.3.2 Dynamic Current Consumption

4.1.3.2.1 Current Consumption for Different Bluetooth BR/EDR Scenarios

Conditions: VDD_IN = 3.6 V, 25°C, 26-MHz XTAL, nominal unit, 4-dBm output power

Operational Mode

Master and Slave

Average Current

Unit

Synchronous connection oriented (SCO) link HV3

Extended SCO (eSCO) link EV3 64 kbps, no retransmission

eSCO link 2-EV3 64 kbps, no retransmission

Master and slave

13.7

13.2

10

mA

GFSK full throughput: TX = DH1, RX = DH5

EDR full throughput: TX = 2-DH1, RX = 2-DH5

EDR full throughput: TX = 3-DH1, RX = 3-DH5

Master and slave

40.5

41.2

mA

Sniff, one attempt, 1.28 seconds

Master and slave

250

400

500

μA

Page or inquiry scan 1.28 seconds, 11.25 ms

Page (1.28 seconds) and inquiry (2.56 seconds) scans,

11.25 ms

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Conditions: VDD_IN = 3.6 V, 25°C, 26-MHz fast clock, nominal unit, 4-dBm output power

Operational Mode

Master and Slave

Master and slave

Average Current

Unit

mA

Synchronous connection oriented (SCO) link HV3

Extended SCO (eSCO) link EV3 64 kbps, no retransmission

eSCO link 2-EV3 64 kbps, no retransmission

12

11.5

8.3

GFSK full throughput: TX = DH1, RX = DH5

EDR full throughput: TX = 2-DH1, RX = 2-DH5

EDR full throughput: TX = 3-DH1, RX = 3-DH5

Master and slave

38.5

39.2

mA

Sniff, one attempt, 1.28 seconds

Master and slave

76 and 100

300

μA

Page or inquiry scan 1.28 seconds, 11.25 ms

Page (1.28 seconds) and inquiry (2.56 seconds) scans,

11.25 ms

430

4.1.3.2.2 Current Consumption for Different LE Scenarios

Conditions: VDD_IN = 3.6 V, 25°C, 26-MHz fast clock, nominal unit, 10 dBm output power

Mode

Description

Average Current

Unit

Advertising in all three channels

1.28-seconds advertising interval

15 bytes advertise data

Advertising, nonconnectable

104

µA

Advertising in all three channels

1.28-seconds advertising interval

15 bytes advertise data

Advertising, discoverable

Scanning

121

302

169

µA

Listening to a single frequency per window

1.28-seconds scan interval

11.25-ms scan window

500-ms connection interval

0-ms slave connection latency

Empty TX and RX LL packets

Connected (master role)

4.1.4 General Electrical Characteristics

Rating

Condition

At 2, 4, 8 mA

At 0.1 mA

At 2, 4, 8 mA

At 0.1 mA

Resistance

Capacitance

C_L= 20 pF

typ = 6.5

Min

Max

VDD_IO

0.2 x VDD_IO

0.2

Unit

High-level output voltage, V_OH

0.8 x VDD_IO

V

VDD_IO – 0.2

Low-level output voltage, V_OL

0

1

V

I/O input impedance

MΩ

pF

ns

5

Output rise and fall times, 10% to 90% (digital pins)

10

I/O pull currents

PCM-I2S bus, TX_DBG

PU

PD

PU

PD

3.5

9.5

50

9.7

55

μA

typ = 27

All others

typ = 100

300

360

μA

typ = 100

50

30

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4.1.5 nSHUTD Requirements

Parameter

Sym

V_IH

Min

1.42

0

Max

1.98

0.4

Unit

V

(1)

Operation mode level

(1)

Shutdown mode level

V_IL

V

Minimum time for nSHUT_DOWN low to reset the device

Rise and fall times

5

ms

μs

t_rand t_f

20

(1) An internal 300-kΩ pulldown retains shut-down mode when no external signal is applied to this pin.

4.1.6 Slow Clock Requirements

Characteristics

Condition

Sym

Min

Typ

Max

Unit

Input slow clock frequency

32768

Hz

Bluetooth

±250

±50

Input slow clock accuracy

(Initial + temp + aging)

ppm

ANT

Input transition time t_rand t_f(10% to

90%)

t_rand t_f

200

ns

Frequency input duty cycle

15%

50%

85%

Slow clock input voltage limits

Square wave, DC-coupled

V_IH

V_IL

0.65 ×

VDD_IO

V peak

0

0.35 ×

VDD_IO

Input impedance

Input capacitance

1

MΩ

5

pF

4.1.7 External Fast Clock Crystal Requirements and Operation

Characteristics

Condition

Sym

Min

Typ

Max

Unit

Supported crystal frequencies

f_in

26

MHz

Frequency accuracy

(Initial + temperature + aging)

±20

ppm

26 MHz, external capacitance = 8 pF

I_osc= 0.5 mA

650

490

940

710

Crystal oscillator negative resistance

Ω

26 MHz, external capacitance = 20 pF

I_osc= 2.2 mA

4.1.8 Fast Clock Source Requirements (–40°C to +85°C)

Characteristics

Condition

Sym

Min

Typ

Max

Unit

MHz

ppm

V

Supported frequencies

F_REF

26

Reference frequency accuracy

Fast clock input voltage limits

Initial + temp + aging

±20

0.37

2.1

Square wave, DC-coupled

V_IL

V_IH

–0.2

1.0

0.4

0

V

Sine wave, AC-coupled

1.6

V_p-p

V

Sine wave, DC-coupled

1.6

Sine wave input limits, DC-coupled

Square wave, DC-coupled

1.6

Fast clock input rise time

(as % of clock period)

10%

Duty cycle

35%

50%

65%

Phase noise for 26 MHz

@ offset = 1 kHz

@ offset = 10 kHz

@ offset = 100 kHz

–123.4

–133.4

–138.4

dBc/Hz

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4.2 Bluetooth BR/EDR RF Performance

All parameters in this section that are fast-clock dependent are verified using a 26-MHz XTAL under a

temperature range from –20°C to 70°C and an RF load of 50 Ω at the BT_RF port of the IC.

4.2.1 Bluetooth Receiver—In-Band Signals

Characteristics

Condition

Min

Typ

Max

Bluetooth

Unit

Specification

Operation frequency range

Channel spacing

2402

2480

MHz

Ω

1

Input impedance

50

Sensitivity, dirty TX on⁽¹⁾

GFSK, BER = 0.1%

–91.5

–90.5

–81

–95

–70

Pi/4-DQPSK, BER = 0.01%

8DPSK, BER = 0.01%

Pi/4-DQPSK

–94.5

–87.5

1E–7

dBm

–70

BER error floor at sensitivity +

10 dB, dirty TX off

1E–6

–5

1E–5

–20

8DPSK

Maximum usable input power

GFSK, BER = 0.1%

Pi/4-DQPSK, BER = 0.1%

8DPSK, BER = 0.1%

–10

dBm

–10

Intermodulation characteristics

C/I performance⁽²⁾

Level of interferers

For n = 3, 4, and 5

–36

–30

–39

GFSK, co-channel

EDR, co-channel

8

10

11

13

Pi/4-DQPSK

8DPSK

9.5

Image = –1 MHz

16.5

–10

–5

20

21

GFSK, adjacent ±1 MHz

–5

0

EDR, adjacent ±1 MHz, (image)

Pi/4-DQPSK

8DPSK

–5

0

–1

5

GFSK, adjacent +2 MHz

EDR, adjacent, +2 MHz,

–38

–28

–22

–45

–44

–10

–63

–35

–30

–20

–13

–43

–36

–30

–25

–20

–13

–40

–33

Pi/4-DQPSK

8DPSK

dB

GFSK, adjacent –2 MHz

EDR, adjacent –2 MHz

Pi/4-DQPSK

8DPSK

GFSK, adjacent ≥ |±3| MHz

EDR, adjacent ≥ |±3| MHz

Pi/4-DQPSK

8DPSK

RF return loss

dB

RX mode LO leakage

Frf = (received RF frequency – 0.6 MHz)

–58

dBm

(1) Sensitivity degradation up to 3 dB may occur for minimum and typical values where the Bluetooth frequency is a harmonic of the fast

clock.

(2) Numbers show desired-signal to interfering-signal ratio. Smaller numbers indicate better C/I performance.

4.2.2 Bluetooth Receiver—General Blocking

Characteristics

Condition

30 to 2000 MHz

Min

Typ

–6

Unit

Blocking performance over full range, according to Bluetooth

(1)

specification

2000 to 2399 MHz

2484 to 3000 MHz

3 to 12.75 GHz

–6

dBm

–6

(1) Exceptions are taken out of the total 24 allowed in the Bluetooth specification.

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4.2.3 Bluetooth Transmitter—GFSK

Characteristics

Min

Typ

Max

Bluetooth

Unit

Specification

Maximum RF output power⁽¹⁾

Power variation over Bluetooth band

Gain control range

10

–1

12

dBm

dB

1

30

5

dB

Power control step

2

8

2 to 8

≤ –20

≤ –40

Adjacent channel power |M–N| = 2

Adjacent channel power |M–N| > 2

–45

–50

–39

–42

dBm

(1) To modify maximum output power, use an HCI VS command.

4.2.4 Bluetooth Transmitter—EDR

Characteristics

Min

Typ

Max

Bluetooth

Unit

Specification

Maximum RF output

power⁽¹⁾

Pi/4-DQPSK

8DPSK

6

8

dBm

dB

Relative power

–2

–1

1

–4 to +1

Power variation over Bluetooth band

Gain control range

30

5

Power control step

2

8

2 to 8

≤ –26

≤ –20

≤ –40

Adjacent channel power |M–N| = 1

–36

–30

–42

–30

–23

–40

dBc

dBm

(2)

Adjacent channel power |M–N| = 2

Adjacent channel power |M–N| > 2

(2)

(1) To modify maximum output power, use an HCI VS command.

(2) Assumes 3-dB insertion loss from Bluetooth RF ball to antenna

4.2.5 Bluetooth Modulation—GFSK

Characteristics

Condition

Sym

Min Typ

Max Bluetooth

Specificat

ion

Unit

–20 dB bandwidth

GFSK

925

995

170

≤ 1000

kHz

Modulation characteristics

Δf1avg

Mod data = 4 1s, 4

0s:

F1 avg 150 165

140 to 175

111100001111...

Δf2max ≥ limit for at

least 99.9% of all

Δf2max

Mod data =

1010101...

F2 max 115 130

> 115

kHz

Δf2avg, Δf1avg

DH1

85

88

> 80

< ±25

< ±40

< 20

%

Absolute carrier frequency drift

–25

–35

25

35

15

kHz

DH3 and DH5

Drift rate

kHz/

50 μs

Initial carrier frequency tolerance

f0 – fTX

–75

75

< ±75

kHz

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4.2.6 Bluetooth Modulation—EDR

Characteristics

Condition

Min

Typ

Max

Bluetooth

Unit

Specification

Carrier frequency stability

±3

±5

±75

15

13

30

20

30

25

≤ 10

±75

20

kHz

Initial carrier frequency tolerance

(1)

Rms DEVM

Pi/4-DQPSK

8DPSK

6

13

99% DEVM⁽¹⁾

Pi/4-DQPSK

8DPSK

30

%

20

(1)

Peak DEVM

Pi/4-DQPSK

8DPSK

14

16

35

25

(1) Max performance refers to maximum TX power.

4.2.7 Bluetooth Transmitter—Out-of-Band and Spurious Emissions

Characteristics

Second harmonic⁽¹⁾

Third harmonic⁽¹⁾

Condition

Typ

–14

–10

–19

Max

–2

Unit

dBm

Measured at maximum output power

–6

Fourth harmonics⁽¹⁾

–11

(1) Meets FCC and ETSI requirements with external filter shown in Figure 5-1

4.3 Bluetooth LE RF Performance

All parameters in this section that are fast-clock dependent are verified using a 26-MHz XTAL under a

temperature range from –20°C to 70°C and an RF load of 50 Ω at the BT_RF port of the IC.

4.3.1 BLE Receiver—In-Band Signals

Characteristic

Condition

Min

Typ

Max

BLE

Unit

Specification

Operation frequency range

Channel spacing

2402

2480

MHz

Ω

2

Input impedance

50

Sensitivity dirty TX on⁽¹⁾

Maximum usable input power

Intermodulation characteristics

PER = 30.8%; dirty TX on

GMSK, PER = 30.8%

–93

–5

–96

≤ –70

≥ –10

≥ –50

dBm

Level of interferers.

For n = 3, 4, 5

–36

–30

C/I performance⁽²⁾

Image = –1 MHz

GMSK, co-channel

GMSK, adjacent ±1 MHz

GMSK, adjacent +2 MHz

GMSK, adjacent –2 MHz

GMSK, adjacent ≥ |±3| MHz

Frf = (received freq – 0.6 MHz)

8

12

0

≤ 21

≤ 15

–5

–45

–22

–47

–63

–38

–15

–40

–58

≤ –17

≤ –15

≤ –27

dB

RX mode LO leakage

dBm

(1) Sensitivity degradation up to 3 dB may occur where the BLE frequency is a harmonic of the fast clock.

(2) Numbers show wanted signal-to-interfering signal ratio. Smaller numbers indicate better C/I performance.

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4.3.2 BLE Receiver—General Blocking

Characteristics

Condition

Min

Typ

–15

BLE Specification

≥ –30

Unit

Blocking performance over full

range, according to BLE

specification⁽¹⁾

30 to 2000 MHz

2000 to 2399 MHz

2484 to 3000 MHz

3 to 12.75 GHz

≥ –35

dBm

≥ –35

≥ –30

(1) Exceptions are taken out of the total 10 allowed in the BLE specification.

4.3.3 BLE Transmitter

Characteristics

Min

Typ

Max

BLE

Unit

Specification

Maximum RF output power

10

–1

12⁽¹⁾

≤10

dBm

dB

Power variation over BLE band

Adjacent channel power |M-N| = 2

Adjacent channel power |M-N| > 2

1

–45

–50

–39

–42

≤ –20

≤ –30

dBm

(1) To achieve the BLE specification of 10-dBm maximum, an insertion loss of > 2 dB is assumed between the RF ball and the antenna.

Otherwise, use an HCI VS command to modify the output power.

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4.3.4 BLE Modulation

Characteristics

Condition

Sym

Min

Typ

Max

BLE

Specification

Unit

kHz

Modulation

characteristics

Δf1avg

Mod data = 4 1s, 4

0s:

1111000011110000...

Δf1

avg

240

250

260

225 to 275

Δf2max ≥ limit for at

least 99.9% of all

Δf2max

Mod data =

1010101...

Δf2

max

185

210

0.9

≥ 185

Δf2avg, Δf1avg

0.85

–25

≥ 0.8

Absolute carrier

frequency drift

25

≤ ±50

kHz

Drift rate

15

75

≤ 20

kHz/50 ms

kHz

Initial carrier

–75

≤ ±100

frequency tolerance

4.3.5 BLE Transceiver, Out-Of-Band and Spurious Emissions

See Section 4.2.7, Bluetooth Transmitter, Out-of-Band and Spurious Emissions.

4.4 Interface Specifications

4.4.1 UART

Figure 4-1 shows the UART timing diagram. Table 4-1 lists the UART timing characteristics.

HCI_RTS

t1

t2

t6

HCI_RX

HCI_CTS

t3

t4

HCI_TX

Start-

bit

Stop-

bit

10bits

td_uart_swrs064

Figure 4-1. UART Timing

Table 4-1. UART Timing Characteristics

Symbol

Characteristics

Condition

Min

37.5

–2.5

–12.5

0

Typ

Max

4000

1.5

Unit

kbps

%

Baud rate

Baud rate accuracy per byte

Baud rate accuracy per bit

CTS low to TX_DATA on

CTS high to TX_DATA off

CTS-high pulse width

Receive and transmit

12.5

%

t3

t4

t6

2

μs

Hardware flow control

1

byte

bit

1

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Table 4-1. UART Timing Characteristics (continued)

Characteristics

Condition

Min

Typ

Max

Unit

μs

t1

t2

RTS low to RX_DATA on

RTS high to RX_DATA off

0

2

Interrupt set to 1/4 FIFO

16

byte

Figure 4-2 shows the UART data frame. Table 4-2 describes the symbols used in Figure 4-2.

tb

TX

STR

D0

D1

Dn

PAR

STP

D2

td_uart_swrs064

Figure 4-2. Data Frame

Table 4-2. Data Frame Key

Symbol

Description

Start-bit

STR

D0...Dn

PAR

Data bits (LSB first)

Parity bit (optional)

Stop-bit

STP

4.4.2 PCM

Figure 4-3 shows the interface timing for the PCM. Table 4-3 and Table 4-4 list the associated master and

slave parameters, respectively.

T_clk

T_w

AUD_CLK

t_is

t_ih

AUD_IN / FSYNC_IN

t_op

AUD_OUT / FSYNC_OUT

td_aud_swrs064

Figure 4-3. PCM Interface Timing

Table 4-3. PCM Master

Symbol

Parameter

Condition

Min

Max

Unit

T_clk

Cycle time

244.14

15625

ns

(4.096 MHz)

(64 kHz)

T_w

t_is

High or low pulse width

AUD_IN setup time

50% of T_clkmin

25

0

t_ih

AUD_IN hold time

t_op

AUD_OUT propagation time

FSYNC_OUT propagation time

40-pF load

0

10

0

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Table 4-4. PCM Slave

Symbol

Parameter

Condition

Min

Max

Unit

T_clk

Cycle time

66.67

ns

(15 MHz)

T_w

T_is

T_ih

t_is

High or low pulse width

AUD_IN setup time

AUD_IN hold time

40% of T_clk

8

0

8

0

AUD_FSYNC setup time

AUD_FSYNC hold time

AUD_OUT propagation time

t_ih

t_op

40-pF load

21

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5 Reference Design and BOM for Power and Radio Connections

Figure 5-1 shows the reference schematics for the CC256x device.

FLT1

HCI_TX

F2

H3

G3

H1

RF_IO

BT_ANT_RF

HCI_TX

C9

22 pF

A5

1

3

HCI_RX

HCI_RTS

HCI_CTS

RF_IO

IN

GND

OUT

GND

HCI_RX

HCI_RTS

HCI_CTS

4

2

AUD_FSYNC

AUD_CLK

AUD_IN

E2

E1

C1

D1

AUD_FSYNC

VDD_IO (1.62 to 1.92 V)

AUD_CLK

AUD_IN

AUD_OUT

VDD_IO

AUD_OUT

C2

VDD_IO

NC

G2

D2

NC

CC256X

Bluetooth (BR/EDR)/

Bluetooth Low Energy/ANT

CL1.5_LDO_IN

MLDO_IN

B6

A3

C6

CL1.5_LDO_IN

MLDO_IN

SLOW_CLK

F6

SLOW_CLK_IN

MLDO_OUT

C3

1 mF

C1

8 pF

XTALP

XTALM

A2

B2

XTALP

XTALM

A1

A4

B4

A7

SRAM_LDO_OUT

ADCPPA_LDO_OUT

CL1.5_LDO_OUT

DCO_LDO_OUT

DIG_LDO_OUT

X1

26 MHz

B3

H2

nSHUTD

TX_DBG

nSHUTD

TX_DBG

B1

G1

DIG_LDO_OUT

C4

0.1 mF

C5

0.1 mF

C6

0.1 mF

C7

0.1 mF

C8

0.1 mF

TP1

TP 1.47 mm

C2

8 pF

SWRS098-009

Figure 5-1. Reference Schematics

Figure 5-2. Power Schemes

Table 5-1 lists the BOM for the CC256x device.

Table 5-1. Bill of Materials

Reference

Des.

Manufacturer

Part Number

Alternate

Part

Qty

Value

Description

Manufacturer

Note

1

ANT1

NA

ANT_IIFA_CC2420_32mil_MI

R

NA

IIFA_CC2420

Chip antenna Copper

antenna on

PCB

6

2

Capacitor

0.1 μF

1.0 μF

12 pF

CAP CER 1.0-µF 6.3-V X5R

10% 0402

Kemet

C0402C104K9RACTU

JMK105BJ105KV-F

CAP CER 10-pF 50-V 5%

NP0 0402

Taiyo Yuden

CAP CER 12 pF 6.3-V X5R

10% 0402

Murata Electronics

GRM1555C1H120JZ01D

Reference Design and BOM for Power and Radio Connections

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39

CC256x

SWRS121C –JULY 2012–REVISED OCTOBER 2013

www.ti.com

Table 5-1. Bill of Materials (continued)

Reference

Des.

Manufacturer

Part Number

Alternate

Part

Qty

Value

Description

Manufacturer

Note

2

Capacitor

0.47 μF

CAP CER .47-µF 6.3-V X5R

±10% 0402

Taiyo Yuden

JMK105BJ474KV-F

1

FL1

OSC1

U5

2.45 GHz

FILTER CER BAND PASS

2.45-GHZ SMD

Murata Electronics

LFB212G45SG8C341

ASH7K-32.768KHZ-T

CC256xRVM

Place brown

marking up

32,768 kHz 15 pF

OSC 32.768-kHZ 15-pF 1.5-V Abracon Corporation

3.3-V SMD

Optional

CC2560ARVM,

CC2564RVM,

CC2560BRVM,

CC2564BRVM

Bluetooth BR/EDR/LE or ANT

Texas Instruments

Single-Chip Solution

1

Y1

26 MHz

Crystal, 26 MHz

NDK

NX2016SA

TZ1325D

(Tai-Saw

TST)

C31

22 pF

CAP CER 22-PF 25-V 5%

NP0 0201

Murata Electronics

North America

GRM0335C1E220JD01D

40

mrQFN Mechanical Data

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6 mrQFN Mechanical Data

RVM (S-PVQFN-N76)

PLASTIC QUAD FLATPACK NO-LEAD

8,10

7,90

SQ

7,83

SQ

7,63

Pin 1 Indentifier

0,90

0,80

0,65

0,55

Seating Plane

0,08

C

0,05

0,00

5,40

4X

4,80

4X

0,30 TYP

0,70

4X

THERMAL PAD

CL –

PKG.

0,17

SIZE AND SHAPE

SHOWN ON SEPARATE SHEET

CL –

PAD

0,60

4X

0,24

0,50

76X

0,30

0,25

76X

0,10

C A B

0,15

0,60

0,24

4X

0,10

C A B

4211965/B 12/11

Bottom View

NOTES:

A. All linear dimensions are in millimeters. Dimensioning and tolerancing per ASME Y14.5-1994.

B. This drawing is subject to change without notice.

C. QFN (Quad Flatpack No-Lead) Package configuration.

D. The package thermal pad must be soldered to the board for thermal and mechanical performance.

E. See the additional figure in the Product Data Sheet for details regarding the exposed thermal pad features and dimensions.

SWRS115-001

mrQFN Mechanical Data

41

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RVM (S-PVQFN-N76)

PLASTIC QUAD FLATPACK NO-LEAD

THERMAL INFORMATION

This package incorporates an exposed thermal pad that is designed to be attached directly to an external

heatsink. The thermal pad must be soldered directly to the printed circuit board (PCB). After soldering, the

PCB can be used as a heatsink. In addition, through the use of thermal vias, the thermal pad can be attached

directly to the appropriate copper plane shown in the electrical schematic for the device, or alternatively, can be

attached to a special heatsink structure designed into the PCB. This design optimizes the heat transfer from the

integrated circuit (IC).

For information on the Quad Flatpack No-Lead (QFN) package and its advantages, refer to Application Report,

QFN/SON PCB Attachment, Texas Instruments Literature No. SLUA271. This document is available at www.ti.com.

The exposed thermal pad dimensions for this package are shown in the following illustration.

CL-

PKG.

0,17

3,30 0,10

CL-

PAD

3,00 0,10

Bottom View

Exposed Thermal Pad Dimensions

4212066/B 12/11

NOTE: All linear dimensions are in millimeters

SWRS115-018

42

mrQFN Mechanical Data

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SWRS121C –JULY 2012–REVISED OCTOBER 2013

7 Chip Packaging and Ordering

7.1 Package and Ordering Information

The mrQFN packaging is 76 pins and a 0.6-mm pitch.

For detailed information, see Section 6, mrQFN Mechanical Data.

Table 7-1 lists the package and order information for the device family members.

Table 7-1. Package and Order Information

Device

CC2560ARVMT

CC2560ARVMR

CC2564RVMT

CC2564RVMR

CC2560BRVMT

CC2560BRVMR

CC2564BRVMT

CC2564BRVMR

Package Suffix

RVM

Pieces/Reel

250

RVM

2500

250

RVM

2500

250

RVM

2500

250

RVM

2500

Figure 7-1 shows the chip markings for the CC256x family.

Figure 7-1. Chip Markings

7.1.1 Device Support Nomenclature

To designate the stages in the product development cycle, TI assigns prefixes to the part numbers. These

prefixes represent evolutionary stages of product development from engineering prototypes through fully

qualified production devices.

X

Experimental, preproduction, sample or prototype device. Device may not meet all product qualification conditions and

may not fully comply with TI specifications. Experimental/Prototype devices are shipped against the following disclaimer:

“This product is still in development and is intended for internal evaluation purposes.” Notwithstanding any provision to the

contrary, TI makes no warranty expressed, implied, or statutory, including any implied warranty of merchantability of

fitness for a specific purpose, of this device.

null Device is qualified and released to production. TI’s standard warranty applies to production devices.

Chip Packaging and Ordering

43

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7.2 Empty Tape Portion

Figure 7-2 shows the empty portion of the carrier tape.

Empty portion

Device on tape portion

End

Start

The length is to extend

so that no unit is visible

on the outer layer of tape.

270-mm MIN

User direction of feed

swrs064-001

Figure 7-2. Carrier Tape and Pockets

7.3 Device Quantity and Direction

When pulling out the tape, the A1 corner is on the left side (see Figure 7-3).

A1 corner

Carrier tape

Sprocket hole

Embossment

Cover tape

User direction of feed

SWRS064-002

Figure 7-3. Direction of Device

7.4 Insertion of Device

Figure 7-4 shows the insertion of the device.

insert_swrs064

Figure 7-4. Insertion of Device

44

Chip Packaging and Ordering

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7.5 Tape Specification

The dimensions of the tape are:

•

Tape width: 16 mm

Cover tape: The cover tape does not cover the index hole and does not shift to outside from the carrier

tape.

•

Tape structure: The carrier tape is made of plastic. The device is put in the embossed area of the

carrier tape and covered by the cover tape, which is made of plastic.

ESD countermeasure: The plastic material used in the carrier tape and the cover tape is static

dissipative.

7.6 Reel Specification

Figure 7-5 shows the reel specifications:

•

330-mm reel, 16-mm width tape

Reel material: Polystyrene (static dissipative/antistatic)

+2.0

16.4

–0.0

2.0 +–0.5

20.8

Ø 13.0 +0.5/–0.2

SWRS121-006

Figure 7-5. Reel Dimensions (mm)

7.7 Packing Method

The end of the leader tape is secured by drafting tape. The reel is packed in a moisture barrier bag

fastened by heat-sealing (see Figure 7-6).

Chip Packaging and Ordering

45

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Moisture-barrier bag

reelpk_swrs064

Figure 7-6. Reel Packing Method

CAUTION

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all

integrated circuits be handled with appropriate precautions. Failure to observe proper

handling and installation procedures can cause damage. ESD damage can range from

subtle performance degradation to complete device failure. Precision integrated circuits

may be more susceptible to damage because very small parametric changes could

cause devices not to meet their published specifications.

7.8 Packing Specification

7.8.1 Reel Box

Each moisture-barrier bag is packed into a reel box, as shown in Figure 7-7.

rlbx_swrs064

Figure 7-7. Reel Box (Carton)

7.8.2 Reel Box Material

The reel box is made from corrugated fiberboard.

7.8.3 Shipping Box

If the shipping box has excess space, filler (such as cushion) is added.

Figure 7-8 shows a typical shipping box.

46

Chip Packaging and Ordering

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SWRS121C –JULY 2012–REVISED OCTOBER 2013

NOTE

The size of the shipping box may vary depending on the number of reel boxes packed.

box_swrs064

Figure 7-8. Shipping Box (Carton)

7.8.4 Shipping Box Material

The shipping box is made from corrugated fiberboard.

Chip Packaging and Ordering

47

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IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other

changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest

issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and

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TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms

and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary

to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily

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TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and

applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide

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TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or

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Products

Applications

Audio

www.ti.com/audio

amplifier.ti.com

dataconverter.ti.com

www.dlp.com

Automotive and Transportation www.ti.com/automotive

Communications and Telecom www.ti.com/communications

Amplifiers

Data Converters

DLP® Products

DSP

Computers and Peripherals

Consumer Electronics

Energy and Lighting

Industrial

www.ti.com/computers

www.ti.com/consumer-apps

www.ti.com/energy

dsp.ti.com

Clocks and Timers

Interface

www.ti.com/clocks

interface.ti.com

logic.ti.com

www.ti.com/industrial

www.ti.com/medical

Medical

Logic

Security

www.ti.com/security

Power Mgmt

Microcontrollers

RFID

power.ti.com

Space, Avionics and Defense

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www.ti.com/space-avionics-defense

www.ti.com/video

microcontroller.ti.com

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www.ti.com/omap

OMAP Applications Processors

Wireless Connectivity

TI E2E Community

e2e.ti.com

www.ti.com/wirelessconnectivity

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

Mouser Electronics

Authorized Distributor

Click to View Pricing, Inventory, Delivery & Lifecycle Information:

Texas Instruments:

CC2564RVMT


型号：	CC256X_13
厂家：	TEXAS INSTRUMENTS
描述：	Bluetooth and Dual-Mode Controller 蓝牙和双模式控制器控制器蓝牙
文件：	总51页 (文件大小：1044K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

CC256X_13 [TI]

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