CC2543RHMR [TI]
IC SPECIALTY MICROPROCESSOR CIRCUIT, Microprocessor IC:Other;型号: | CC2543RHMR |
厂家: | TEXAS INSTRUMENTS |
描述: | IC SPECIALTY MICROPROCESSOR CIRCUIT, Microprocessor IC:Other 外围集成电路 |
文件: | 总29页 (文件大小:944K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
CC2543
www.ti.com
SWRS107E –APRIL 2012–REVISED OCTOBER 2013
System-on-Chip for 2.4-GHz RF Applications
1
FEATURES
•
RF section
•
Microcontroller
–
–
–
Single-Chip 2.4-GHz RF Transceiver and
MCU
–
High-Performance and Low-Power 8051
Microcontroller Core With Code Prefetch
Supports 250 kbps, 500 kbps, 1 Mbps and 2
Mbps data rates
–
–
–
–
32-KB Flash Program Memory
1 KB SRAM
Excellent Link Budget, Enabling Long
Range Without External Front-Ends
Hardware Debug Support
Extensive Baseband Automation, Including
Auto-Acknowledgement and Address
Decoding
–
–
Programmable Output Power up to 5 dBm
Excellent Receiver Sensitivity (–90 dBm at
2 Mbps, –98 dBm at 250 kbps)
•
Peripherals
–
Suitable for Systems Targeting Compliance
With Worldwide Radio Frequency
–
Two-Channel DMA with Access to all
Memory Areas and Peripherals
Regulations: ETSI EN 300 328 and EN 300
440 Category 2 (Europe), FCC CFR47 Part
15 (US), and ARIB STD-T66 (Japan)
–
General-Purpose Timers (One 16-Bit, Two
8-Bit)
–
–
–
Radio Timer, 40-Bit
IR Generation Circuitry
Several Oscillators:
–
Accurate RSSI Function
•
•
Layout
–
–
Few External Components
–
–
–
32MHz XOSC
16MHz RCOSC
32kHz RCOSC
Pin Out Suitable for Single Layer PCB
Applications
–
–
Reference Designs Available
–
–
–
–
32-kHz Sleep Timer With Capture
32-pin 5-mm × 5-mm QFN (16 General I/O
Pins) Package
AES Security Coprocessor
UART/SPI/I2C Serial Interface
Low Power
16 General-Purpose I/O pins (3 × 20-mA
Drive Strength, Remaining pins have 4 mA
Drive Strength)
–
–
–
–
–
–
–
Active Mode RX Best Performance: 21.2 mA
Active Mode TX (0 dBm): 26 mA
Power Mode 1 (5 µs Wake-Up): 235 µA
Power mode 2 (sleep timer on): 0.9 µA
Power mode 3 (External interrupts): 0.4µA
Wide Supply Voltage Range (2V to 3.6V)
–
–
–
Watchdog Timer
True Random-Number Generator
ADC and Analog Comparator
Full RAM and Register Retention in All
Power Modes
APPLICATIONS
•
•
•
Proprietary 2.4-GHz Systems
Human Interface Devices (keyboard, mouse)
Consumer Electronics
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2012–2013, Texas Instruments Incorporated
CC2543
SWRS107E –APRIL 2012–REVISED OCTOBER 2013
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
DESCRIPTION
The CC2543 is an optimized system-on-chip (SoC) solution with data rates up to 2Mbps built with low bill-of-
material cost. The CC2543 combines the excellent performance of a leading RF transceiver with a single-cycle
8051 compliant CPU, 32-KB in-system programmable flash memory, up to 1-KB RAM, and many other powerful
features. The CC2543 has efficient power modes with RAM and register retention below 1 μA, making it highly
suited for low-duty-cycle systems where ultra-low power consumption is required. Short transition times between
operating modes further ensure low energy consumption.
The CC2543 is compatible with the CC2541/CC2544/CC2545. It comes in a 5-mm × 5-mm QFN32 package, with
SPI/UART/I2C interface. The CC2543 comes complete with reference designs from Texas Instruments.
The device targets wireless consumer and HID applications. The CC2543 is tailored for peripheral devices such
as wireless mice.
For block diagram, see Figure 7.
ABSOLUTE MAXIMUM RATINGS(1)
over operating free-air temperature range (unless otherwise noted)
MIN
–0.3
–0.3
MAX UNIT
Supply voltage VDD
Voltage on any digital pin
Input RF level
All supply pins must have the same voltage
3.9
V
V
VDD + 0.3 ≤ 3.9
10
dBm
°C
Storage temperature range
–40
125
All pins, excluding 20 and 21, according to human-body model,
JEDEC STD 22, method A114 (HBM)
2.5
1.5
kV
kV
V
All pins, according to human-body model, JEDEC STD 22,
method A114 (HBM)
ESD(2)
According to charged-device model, JEDEC STD 22, method
C101 (CDM)
750
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) CAUTION: ESD sensitive device. Precaution should be used when handing the device in order to prevent permanent damage.
RECOMMENDED OPERATING CONDITIONS
MIN
–40
2
MAX UNIT
Operating ambient temperature range, TA
Operating supply voltage VDD
85
°C
V
All supply pins must have same voltage
3.6
2
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SWRS107E –APRIL 2012–REVISED OCTOBER 2013
ELECTRICAL CHARACTERISTICS
Measured on Texas Instruments CC2543EM reference design with TA = 25°C and VDD = 3 V, unless otherwise noted.
PARAMETER
TEST CONDITIONS
2 Mbps, GFSK, 320-kHz deviation
MIN
TYP
MAX UNIT
RX mode, no peripherals active, low MCU activity
21.2
26
29.4
3
mA
mA
mA
mA
mA
TX mode, 0-dBm output power, no peripherals active, low MCU activity
TX mode, 5-dBm output power, no peripherals active, low MCU activity
Active mode, 16-MHz RCOSC, Low MCU activity
Active mode, 32-MHz clock frequency, low MCU activity
6
Power mode 0, CPU clock halted, all peripherals on, no clock division, 32-MHz
crystal selected
4.5
3.1
mA
mA
I core– Core current
consumption
Power mode 0, CPU clock halted, all peripherals on, clock division at max (Limits
max speed in peripherals except radio), 32-MHz crystal selected
Power mode 1. Digital regulator on; 16-MHz RCOSC and 32-MHz crys tal oscillator
off; 32.753-kHz RCOSC, POR, BOD, and sleep timer active; RAM and register
retention
235
µA
Power mode 2. Digital regulator off, 16 MHz RCOSC and 32 MHz crystal oscillator
off; 32.753 kHz RCOSC, POR and sleep timer active; RAM and register retention
0.9
0.4
µA
µA
Power mode 3. Digital regulator off, no clocks, POR active; RAM and register
retention
Timer 1 (16-bit). Timer running, 32-MHz XOSC used
Radio timer(40 bit). Timer running, 32-MHz XOSC used
Timer 3 (8-bit). Timer running, 32-MHz XOSC used
Timer 4 (8-bit). Timer running, 32-MHz XOSC used
Sleep timer. Including 32.753-kHz RCOSC
90
90
60
70
0.6
µA
µA
µA
µA
µA
I peri– Peripheral
current consumption
(Adds to core
current Icore for each
peripheral unit
activated)
GENERAL CHARACTERISTICS
Measured on Texas Instruments CC2543EM reference design with TA = 25°C and VDD = 3 V, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP MAX UNIT
WAKE-UP AND TIMING
Digital regulator ON, 16-MHz RCOSC and 32-MHz crystal oscillator OFF.
Start-up of 16-MHz RCOSC
Power mode 1 → Active
5
130
500
µs
µs
µs
Power mode 2 or 3 →
Active
Digital regulator OFF, 16 MHz RCOSC and 32 MHz crystal oscillator OFF.
Start-up of regulator and 16 MHz RCOSC
Crystal ESR = 16 Ω. Initially running on 16-MHz RCOSC, with 32-MHz
XOSC OFF
Active → TX or RX
With 32-MHz XOSC initially ON
RCOSC, with 32MHz XOSC OFF
180
130
µs
µs
RX/TX turnaround
RADIO PART
RF frequency range
Programmable in 1-MHz steps
2379
2496
MHz
2 Mbps, GFSK 320-kHz deviation
2-Mbps, GFSK 500 kHz deviation
1-Mbps, GFSK 250 kHz deviation
1-Mbps, GFSK 160 kHz deviation
500 kbps, MSK
Data rates and modulation
formats
250 kbps, GFSK 160 kHz deviation
250 kbps, MSK
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SWRS107E –APRIL 2012–REVISED OCTOBER 2013
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RF RECEIVE SECTION
Measured on Texas Instruments CC2543EM reference design with TA = 25°C, VDD = 3 V, and fC = 2440 MHz, unless
otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
2 Mbps, GFSK, 320-kHz DEVIATION, 0.1% BER
Receiver sensitivity
–86
–8
dBm
dBm
dB
Saturation
Co-channel rejection
Wanted signal at –67 dBm
±2-MHz offset, wanted signal at –67 dBm
–13
–1
In-band blocking rejection
±4-MHz offset, wanted signal at –67 dBm
>±6-MHz offset, wanted signal at –67 dBm
34
dB
38
1-MHz resolution. Wanted signal at –67 dBm, f < 2 GHz
Two exception frequencies with poorer performance
–32
–38
–12
1-MHz resolution. Wanted signal at –67 dBm, 2 GHz > f < 3 GHz
Two exception frequencies with poorer performance
Out-of-band blocking rejection
dBm
1-MHz resolution. Wanted signal at –67 dBm, f > 3GHz
Two exception frequencies with poorer performance
Wanted signal at –64 dBm, 1st interferer is CW, 2nd interferer is GFSK-
modulated signal. Offsets of interferers are:
6 and 12 MHz
Intermodulation
–43
dBm
8 and 16 MHz
10 and 20 MHz
Including both initial tolerance and drift. Sensitivity better than –70 dBm.
250 byte payload.
Frequency error tolerance(1)
Symbol rate error tolerance(2)
–300
–120
300 kHz
120 ppm
Sensitivity better than -70 dBm. 250 byte payload.
2 Mbps, GFSK, 500 kHz DEVIATION, 0.1% BER
Receiver sensitivity
–90
–3
dBm
dBm
dB
Saturation
Co-channel rejection
Wanted signal at –67 dBm
–10
–3
±2 MHz offset, wanted signal at –67 dBm
±4 MHz offset, wanted signal at –67 dBm
>±6 MHz offset, wanted signal at –67 dBm
dB
In-band blocking rejection
36
dB
44
dB
Including both initial tolerance and drift. Sensitivity better than –70 dBm.
250 byte payload.
Frequency error tolerance(1)
Symbol rate error tolerance(2)
–300
–120
300 kHz
120 ppm
Sensitivity better than -70 dBm. 250 byte payload.
1 Mbps, GFSK, 250 kHz DEVIATION, 0.1% BER
Receiver sensitivity
–94
6
dBm
dBm
dB
Saturation
Co-channel rejection
Wanted signal at –67 dBm
–7
0
±1 MHz offset, wanted signal –67 dBm
±2 MHz offset, wanted signal –67 dBm
±3 MHz offset, wanted signal –67 dBm
>±5 MHz offset, wanted signal –67 dBm
30
34
38
In-band blocking rejection
dB
Including both initial tolerance and drift. Sensitivity better than –70 dBm.
250 byte payload.
Frequency error tolerance
Symbol rate error tolerance
–250
-80
250 kHz
80 ppm
Sensitivity better than –70 dBm. 250 byte payload.
(1) Difference between center frequency of the received RF signal and local oscillator frequency
(2) Difference between incoming symbol rate and the internally generated symbol rate
4
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SWRS107E –APRIL 2012–REVISED OCTOBER 2013
RF RECEIVE SECTION (continued)
Measured on Texas Instruments CC2543EM reference design with TA = 25°C, VDD = 3 V, and fC = 2440 MHz, unless
otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
1 Mbps, GFSK, 160 kHz DEVIATION, 0.1% BER
Receiver sensitivity
–91
6
dBm
dBm
dB
Saturation
Co-channel rejection
Wanted signal at –67 dBm
±1 MHz offset, wanted signal at –67 dBm
–8
2
±2 MHz offset, wanted signal at –67 dBm
±3 MHz offset, wanted signal at –67 dBm
>±5 MHz offset, wanted signal at –67 dBm
Including both initial tolerance and drift, Sensitivity better than –67 dBm
Maximum packet length
28
33
36
In band blocking rejection
dB
Frequency error tolerance
Symbol rate error tolerance
500 kbps, MSK, 0.1% BER
Receiver sensitivity
–250
–80
250 kHz
80 ppm
–98
6
dBm
dBm
dB
Saturation
Co-channel rejection
Wanted signal at –67 dBm
–5
21
32
33
±1 MHz offset, wanted signal at –67 dBm
±2 MHz offset, wanted signal at –67 dBm
>±2 MHz offset, wanted signal at –67 dBm
Including both initial tolerance and drift, Sensitivity better than –67dBm
Maximum packet length
In band blocking rejection
dB
Frequency error tolerance
Symbol rate error tolerance
–150
–60
150 kHz
60 ppm
250 kbps, GFSK, 160 kHz DEVIATION , 0.1% BER
Receiver sensitivity
Saturation
–98
6
dBm
dBm
dB
Co-channel rejection
Wanted signal at –67 dBm
–2
22
32
32
±1 MHz offset, wanted signal at –67 dBm
±2 MHz offset, wanted signal at –67 dBm
>±2 MHz offset, wanted signal at –67 dBm
Including both initial tolerance and drift, Sensitivity better than –67 dBm
Maximum packet length
In-band blocking rejection
dB
Frequency error tolerance
Symbol rate error tolerance
250 kbps, MSK, 0.1% BER
Receiver sensitivity
–150
–60
150 kHz
60 ppm
–98
6
dBm
dBm
dB
Saturation
Co-channel rejection
Wanted signal at –67 dBm
–5
21
32
33
±1 MHz offset, wanted signal at –67 dBm
±2 MHz offset, wanted signal at –67 dBm
>2 MHz offset, wanted signal at –67 dBm
Including both initial tolerance and drift, Sensitivity better than –67 dBm
Maximum packet length
In-band blocking rejection
dB
Frequency error tolerance
Symbol rate error tolerance
ALL RATES/FORMATS
–150
–60
150 kHz
60 ppm
Spurious emission in RX.
Conducted measurement
f < 1 GHz
f > 1 GHz
–67
–60
dBm
dBm
Spurious emission in RX.
Conducted measurement
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SWRS107E –APRIL 2012–REVISED OCTOBER 2013
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RF TRANSMIT SECTION
Measured on Texas Instruments CC2543EM reference design with TA = 25°C, VDD = 3 V, and fC = 2440 MHz, unless
otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Delivered to a single-ended 50-Ω load through a balun using
maximum recommended output power setting.
Output power, maximum setting
5
dBm
Delivered to a single-ended 50-Ω load through a balun using
minimum recommended output power setting.
Output power, minimum setting
–20
dBm
Programmable output power range Delivered to a single-ended 50-Ω load through a balun.
25
–46
–46
dB
f < 1 GHz
dBm
dBm
Spurious emission in TX.
Conducted measurement
f > 1 GHz
Suitable for Systems Targeting Compliance With Worldwide Radio Frequency Regulations: ETSI EN
300 328 and EN 300 440 Class 2 (Europe), FCC CFR47 Part 15 (US), and ARIB STD-T66 (Japan)
Use a simple LC filter (1.6nH and 1.8pF in parallel to ground) to pass ETSI conducted requirements below 1GHz
in restricted bands. For radiated measurements low antenna gain for these frequencies (depending on antenna
design) can achieve the same attenuation of these low frequency components (see EM reference design).
32-MHz CRYSTAL OSCILLATOR
Measured on Texas Instruments CC2543EM reference design with TA = 25°C, VDD = 3 V, unless otherwise noted.
PARAMETER
Crystal frequency
TEST CONDITIONS
MIN
TYP
MAX
UNIT
32
MHz
250 kbps and 500 kbps data rates
1 Mbps data rate
2 Mbps data rate
–30
–40
–60
30
40
60
Crystal frequency accuracy
requirement
ppm
Equivalent series resistance
Crystal shunt capacitance
Crystal load capacitance
Start-up time
6
1
60
7
Ω
pF
pF
ms
10
16
0.25
The crystal oscillator must be in power down for a guard time
before it is used again. This requirement is valid for all modes of
operation. The need for power-down guard time can vary with
crystal type and load.
Power-down guard time
3
ms
32-kHz RC OSCILLATOR
Measured on Texas Instruments CC2543EM reference design with TA = 25°C, VDD = 3 V, unless otherwise noted.
PARAMETER
Calibrated frequency
TEST CONDITIONS
MIN
TYP
32.753
±0.2%
0.4
MAX
UNIT
kHz
Frequency accuracy after calibration
Temperature coefficient
Supply-voltage coefficient
Calibration time
%/ºC
%/V
ms
3
2
16-MHz RC OSCILLATOR
Measured on Texas Instruments CC2543EM reference design with TA = 25°C, VDD = 3 V, unless otherwise noted.
PARAMETER
Calibrated frequency
TEST CONDITIONS
MIN
TYP
16
MAX UNIT
MHz
Uncalibrated frequency accuracy
Frequency accuracy after calibration
Start-up time
±18%
±0.6%
10
µs
µs
Initial calibration time
50
6
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SWRS107E –APRIL 2012–REVISED OCTOBER 2013
RSSI CHARACTERISTICS
Measured on Texas Instruments CC2543EM reference design with TA = 25°C, VDD = 3 V, unless otherwise noted.
2Mbps, GFSK, 320-kHz Deviation, 0.1% BER and 2 Mbps, GFSK, 500-kHz Deviation, 0.1% BER
Reduced gain by AC algorithm
High gain by AGC algorithm
Reduced gain by AGC algorithm
High gain by AGC algorithm
64
64
79
99
±3
1
RSSI range(1)
RSSI offset(1)
dB
dBm
Absolute uncalibrated accuracy(1)
Step size (LSB value)
All Other Rates/Formats
RSSI range(1)
dB
dB
64
99
±3
1
dB
dBm
dB
RSSI offset(1)
Absolute uncalibrated accuracy
Step size (LSB value)
dB
(1) Assuming CC2543 EM reference design. Other RF designs give an offset from the reported value.
FREQUENCY SYNTHESIZER CHARACTERISTICS
Measured on Texas Instruments CC2543EM reference design with TA = 25°C, VDD = 3 V, unless otherwise noted.
PARAMETER
TEST CONDITIONS
At ±1 MHz from carrier
MIN
TYP
–112
–119
–122
MAX UNIT
Phase noise, unmodulated carrier At ±3 MHz from carrier
At ±5 MHz from carrier
dBc/Hz
ANALOG TEMPERATURE SENSOR
Measured on Texas Instruments CC2543EM reference design with TA = 25°C, VDD = 3 V unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
1480
4.5
1
MAX
UNIT
12-bit
/ 1ºC
/ 0.1V
ºC
Output
Temperature coefficient
Voltage coeficcient
Measured using integrated ADC, internal band-gap voltage
reference, and maximum resolution
Initial accuracy without calibration
Accuracy using 1-point calibration
Current consumption when enabled
±10
±5
ºC
0.5
mA
COMPARATOR CHARACTERISTICS
TA = 25°C, VDD = 3 V. All measurement results are obtained using the CC2543 reference designs, post-calibration.
PARAMETER
Common-mode maximum voltage
Common-mode minimum voltage
Input offset voltage
TEST CONDITIONS
MIN
TYP MAX UNIT
VDD
–0.3
1
V
mV
µV/°C
mV/V
nA
Offset vs temperature
Offset vs operating voltage
Supply current
16
4
230
0.15
Hysteresis
mV
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ADC CHARACTERISTICS
TA = 25°C and VDD = 3 V
PARAMETER
TEST CONDITIONS
VDD is voltage from supply
VDD is voltage from supply
MIN
0
TYP
MAX
VDD
VDD
VDD
UNIT
V
Input voltage
External reference voltage
0
V
External reference voltage differential VDD is voltage from supply
0
V
Input resistance, signal
Full-scale signal(1)
Simulated using 4-MHz clock speed
Peak-to-peak, defines 0 dBFS
197
2.97
5.7
kΩ
V
Single-ended input, 7-bit setting
Single-ended input, 9-bit setting
7.5
Single-ended input, 10-bit setting
Single-ended input, 12-bit setting
Differential input, 7-bit setting
9.3
10.3
6.5
ENOB(1)
Effective number of bits
bits
Differential input, 9-bit setting
8.3
Differential input, 10-bit setting
10
Differential input, 12-bit setting
11.5
9.7
10-bit setting, clocked by RCOSC
12-bit setting, clocked by RCOSC
7-bit setting, both single and differential
Single ended input, 12-bit setting, –6 dBFS(1)
Differential input, 12-bit setting, –6 dBFS(1)
Single-ended input, 12-bit setting(1)
Differential input, 12-bit setting(1)
Single-ended input, 12-bit setting, –6 dBFS(1)
Differential input, 12-bit setting, –6 dBFS(1)
10.9
0–20
–75.2
–86.6
70.2
79.3
78.8
88.9
Useful power bandwidth
Total harmonic distortion
kHz
dB
THD
Signal to nonharmonic ratio
dB
dB
Differential input, 12-bit setting, 1-kHz sine
(0 dBFS), limited by ADC resolution
CMRR
Common-mode rejection ratio
Crosstalk
>84
>84
Single ended input, 12-bit setting, 1-kHz sine
(0 dBFS), limited by ADC resolution
dB
Offset
Midscale
–3
0.68%
0.05
0.9
mV
Gain error
12-bit setting, mean(1)
12-bit setting, maximum(1)
12-bit setting, mean(1)
DNL
INL
Differential nonlinearity
Integral nonlinearity
LSB
LSB
4.6
12-bit setting, maximum(1)
12-bit setting, mean, clocked by RCOSC
12-bit setting, max, clocked by RCOSC
Single ended input, 7-bit setting(1)
Single ended input, 9-bit setting(1)
Single ended input, 10-bit setting(1)
Single ended input, 12-bit setting(1)
Differential input, 7-bit setting(1)
Differential input, 9-bit setting(1)
Differential input, 10-bit setting(1)
Differential input, 12-bit setting(1)
7-bit setting
13.3
10
29
35.4
46.8
57.5
66.6
40.7
51.6
61.8
70.8
20
SINAD
(–THD+N)
Signal-to-noise-and-distortion
dB
9-bit setting
36
Conversion time
μs
10-bit setting
68
12-bit setting
132
(1) Measured with 300-Hz sine-wave input and VDD as reference.
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SWRS107E –APRIL 2012–REVISED OCTOBER 2013
ADC CHARACTERISTICS (continued)
TA = 25°C and VDD = 3 V
PARAMETER
TEST CONDITIONS
MIN
TYP
1.2
4
MAX
UNIT
mA
Power consumption
Internal reference VDD coefficient
mV/V
Internal reference temperature
coefficient
0.4
mV/10°C
V
Internal reference voltage
1.15
DC CHARACTERISTICS
Measured on Texas Instruments CC2543EM reference design with TA = 25°C, VDD = 3 V, unless otherwise noted.(1)
PARAMETER
Logic-0 input voltage
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
0.5
Logic-1 input voltage
2.5
–50
–50
V
Logic-0 input current
50
50
nA
nA
kΩ
V
Logic-1 input current
I/O pin pullup and pulldown resistors
Logic-0 output voltage 4-mA pins
Logic-1 output voltage 4-mA pins
Logic-0 output voltage 20-mA pins
Logic-1 output voltage 20-mA pins
20
Output load 4 mA
Output load 4 mA
Output load 20 mA
Output load 20 mA
0.5
0.5
2.4
2.4
V
V
V
(1) Note that only two of the three 20mA pins can drive in the same direction at the same time, and toggle at the same time.
CONTROL INPUT AC CHARACTERISTICS
TA = –40°C to 85°C, VDD = 2 V to 3.6 V.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
The undivided system clock is 32 MHz when crystal oscillator is used.
The undivided system clock is 16 MHz when calibrated 16-MHz RC
oscillator is used.
System clock, fSYSCLK
tSYSCLK = 1/ fSYSCLK
16
32 MHz
See item 1, Figure 1. This is the shortest pulse that is recognized as a
complete reset pin request. Note that shorter pulses may be recognized
but do not lead to complete reset of all modules within the chip.
RESET_N low duration
Interrupt pulse duration
1
µs
ns
See item 2, Figure 1.This is the shortest pulse that is recognized as an
interrupt request.
20
RESET_N
1
2
Px.n
T0299-01
Figure 1. Control Input AC Characteristics
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SPI AC CHARACTERISTICS
TA = –40°C to 85°C, VDD = 2 V to 3.6 V
PARAMETER
TEST CONDITIONS
Master, RX and TX
MIN
250
250
TYP
MAX UNIT
t1
SCK period
ns
Slave, RX and TX
Master
SCK duty cycle
50%
Master
63
63
63
63
t2
t3
SSN low to SCK, Figure 2 and Figure 3
ns
ns
Slave
Master
SCK to SSN high
Slave
t4
t5
t6
t7
MOSI early out
MOSI late out
MISO setup
Master, load = 10 pF
Master, load = 10 pF
Master
7
ns
ns
ns
ns
ns
ns
ns
ns
ns
10
90
10
MISO hold
Master
SCK duty cycle
MOSI setup
Slave
50%
t10
t11
t8
Slave
35
10
MOSI hold
Slave
MISO early out
MISO late out
Slave, load = 10 pF
Slave, load = 10 pF
Master, TX only
Master, RX and TX
Slave, RX only
Slave, RX and TX
0
95
8
t9
4
Operating frequency
MHz
8
4
SCK
t2
t3
SSN
t4
t5
MOSI
D0
X
D1
t6
t7
MISO
X
D0
X
T0478-01
Figure 2. SPI Master AC Characteristics
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SCK
t2
t3
SSN
MISO
MOSI
t8
t9
D0
X
D1
t10
t11
X
D0
X
T0479-01
Figure 3. SPI Slave AC Characteristics
DEBUG INTERFACE AC CHARACTERISTICS
TA = –40°C to 85°C, VDD = 2 V to 3.6 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
12
UNIT
MHz
ns
fclk_dbg
Debug clock frequency (see Figure 4)
Allowed high pulse on clock (see Figure 4)
Allowed low pulse on clock (see Figure 4)
t1
t2
35
35
ns
EXT_RESET_N low to first falling edge on debug
clock (see Figure 5)
t3
t4
t5
167
83
ns
ns
ns
Falling edge on clock to EXT_RESET_N high (see
Figure 5)
EXT_RESET_N high to first debug command (see
Figure 5)
83
t6
t7
t8
Debug data setup (see Figure 6)
Debug data hold (see Figure 6)
Clock-to-data delay (see Figure 6)
2
4
ns
ns
ns
Load = 10 pF
30
Time
DEBUG_CLK
P2_2
t1
t2
1/fclk_dbg
T0436-01
Figure 4. Debug Clock – Basic Timing
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Time
DEBUG_CLK
P2_2
RESET_N
t3
t4
t5
T0437-01
Figure 5. Debug Enable Timing
Time
DEBUG_CLK
P2_2
DEBUG_DATA
(to CC2543)
P2_1
DEBUG_DATA
(from CC2543)
P2_1
t6
t7
t8
T0438-03
Figure 6. Data Setup and Hold Timing
TIMER INPUTS AC CHARACTERISTICS
TA = –40°C to 85°C, VDD = 2 V to 3.6 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Synchronizers determine the shortest input pulse that can be
recognized. The synchronizers operate at the current system clock rate
(16 MHz or 32 MHz).
Input capture pulse duration
1.5
tSYSCLK
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DEVICE INFORMATION
PIN DESCRIPTIONS
CC2543
RHB Package
(Top View)
32 31 30 29 28 27 26 25
P1_3
P2_1/DD
P2_0
1
2
3
4
5
6
7
8
24
VDD
23
22
21
20
19
18
17
VDD
VSS
P0_7
RF_N
RF_P
VSS
P0_6
P0_5
P0_4
VDD
P0_3
XOSC_Q2
9
10 11 12 13 14 15 16
NOTE: The exposed ground pad must be connected to a solid ground plane; this is the main ground connection for the chip.
Table 1. Pin Description Table
NAME
P1_3
PIN
1
PIN TYPE
Digital I/O
DESCRIPTION
Port 1.3
P2_1/DD
2
Digital I/O /
Debug
Port 2.1 / Debug Data
P2_0
P0_7
3
4
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Power (analog)
Digital input
Port 2.0
Port 0.7
Port 0.6
Port 0.5
Port 0.4
Port 0.3
Port 0.2
Port 0.1
Port 0.0
P0_6
5
P0_5
6
P0_4
7
P0_3
8
P0_2
9
P0_1
10
11
12
13
14
P0_0
VDD
2-V-3.6V analog power-supply connection
Reset, active-low
RESET_N
P2_2/DC
Digital I/O /
Debug
Port 2.2 / Debug Clock
VDD
XOSC_Q1
XOSC_Q2
VDD
15
16
17
18
19
20
Power (analog)
Analog O
2-V-3.6V analog power-supply connection
32-MHz crystal oscillator pin 1
32-MHz crystal oscillator pin 2
2-V-3.6V analog power-supply connection
Connect to ground
Analog O
Power (analog)
Unused pin
RF I/O
VSS
RF_P
Positive RF input signal to LNA during RX
Positive RF output signal from PA during TX
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Table 1. Pin Description Table (continued)
NAME
PIN
PIN TYPE
RF I/O
DESCRIPTION
RF_N
21
Negative RF input signal to LNA during RX
Negative RF output signal from PA during TX
Connect to ground
VSS
VDD
22
23
24
25
26
27
28
29
30
31
32
Unused pin
Power (analog)
Power (analog)
Analog I/O
2-V–3.6-V analog power-supply connection
2-V–3.6-V analog power-supply connection
External precision bias resistor for reference current
Port 1.2, 20 mA
VDD
RBIAS
P1_2
P1_1
P1_0
VDD
Digital I/O
Digital I/O
Port 1.1, 20 mA
Digital I/O
Port 1.0, 20 mA
Power (analog)
Power (digital)
Unused pin
Digital I/O
2-V–3.6-V analog power-supply connection
1.8-V digital power-supply decoupling. Do not use for supplying external circuits.
Connect to ground
DCPL1
VSS
P1_4
VSS
Port 1.4
Ground Ground
pad
Must be connected to solid ground as this is the main ground connection for the chip. See
Pinout Diagram.
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BLOCK DIAGRAM
A block diagram of the CC2543 is shown in Figure 7. The modules can be roughly divided into one of three
categories: CPU-related modules; modules related to power, test, and clock distribution; and radio-related
modules. In the following subsections, a short description of each module is given. See CC2543/44/45 User's
Guide (SWRU283) for more details.
WATCHDOG
TIMER
POWER ON RESET
BROWN OUT
RESET_N
RESET
VDD (2 V–3.6 V)
DCOUPL
XOSC_Q2
XOSC_Q1
ON-CHIP VOLTAGE
REGULATOR
32-MHz
CLOCK MUX
and
CALIBRATION
CRYSTAL OSC
SLEEP TIMER
HIGH-
32-kHz
SPEED
DEBUG
INTERFACE
RC-OSC
RC-OSC
POWER MANAGEMENT CONTROLLER
P2_2
P2_1
P2_0
PDATA
XRAM
IRAM
SFR
RAM
SRAM
8051 CPU
CORE
MEMORY
ARBITRATOR
P1_4
P1_3
P1_2
P1_1
P1_0
FLASH
FLASH
UNIFIED
DMA
IRQ CTRL
FLASH CTRL
SRAM
P0_7
P0_6
P0_5
P0_4
P0_3
P0_2
P0_1
P0_0
ANALOG COMPARATOR
FIFOCTRL
PSEUDO
RANDOM
NUMBER
ROM
GENERATOR
RADIO REGISTERS
AES
ΔΣ
ADC
AUDIO/DC
ENCRYPTION
AND
DECRYPTION
Link Layer Engine
DEMODULATOR
MODULATOR
SDA
SCL
USART 0
I2C
RECEIVE
TRANSMIT
TIMER 1 (16-Bit)
TIMER 2
(RADIO TIMER)
DIGITAL
TIMER 3 (8-Bit)
TIMER 4 (8-Bit)
RF_P
RF_N
ANALOG
MIXED
B0301-12
Figure 7. CC2543 Block Diagram
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BLOCK DESCRIPTIONS
CPU and Memory
The 8051 CPU core is a single-cycle 8051-compatible core. It has three different memory access busses (SFR,
DATA, and CODE/XDATA), a debug interface, and an 15-input extended interrupt unit.
The memory arbiter is at the heart of the system, as it connects the CPU and DMA controller with the physical
memories and all peripherals through the SFR bus. The memory arbiter has four memory-access points, access
of which can map to one of three physical memories: an SRAM, flash memory, and XREG/SFR registers. It is
responsible for performing arbitration and sequencing between simultaneous memory accesses to the same
physical memory.
The SFR bus is drawn conceptually in Figure 7 as a common bus that connects all hardware peripherals to the
memory arbiter. The SFR bus in the block diagram also provides access to the radio registers in the radio
register bank, even though these are indeed mapped into XDATA memory space.
The 1-KB SRAM maps to the DATA memory space and to parts of the XDATA memory spaces.
The 18-KB/32-KB flash block provides in-circuit programmable non-volatile program memory for the device,
and maps into the CODE and XDATA memory spaces.
Peripherals
Writing to the flash block is performed through a flash controller that allows page-wise erasure and 4-bytewise
programming. See User Guide for details on the flash controller.
A versatile two-channel DMA controller is available in the system, accesses memory using the XDATA memory
space, and thus has access to all physical memories. Each channel (trigger, priority, transfer mode, addressing
mode, source and destination pointers, and transfer count) is configured with DMA descriptors that can be
located anywhere in memory. Many of the hardware peripherals (AES core, flash controller, USART, timers, etc.)
can be used with the DMA controller for efficient operation by performing data transfers between a single SFR or
XREG address and flash/SRAM.
The interrupt controller services a total of 17 interrupt sources, divided into six interrupt groups, each of which
is associated with one of four interrupt priorities. Any interrupt service request is serviced also when the device is
in idle mode by going back to active mode. Some interrupts can also wake up the device from sleep mode (when
in sleep mode, the device is in low-power mode PM1, PM2 or PM3).
The debug interface implements a proprietary two-wire serial interface that is used for in-circuit debugging.
Through this debug interface, it is possible to perform an erasure of the entire flash memory, control which
oscillators are enabled, stop and start execution of the user program, execute supplied instructions on the 8051
core, set code breakpoints, and single-step through instructions in the code. Using these techniques, it is
possible to perform in-circuit debugging and external flash programming elegantly.
The I/O controller is responsible for all general-purpose I/O pins. The CPU can configure whether peripheral
modules control certain pins or whether they are under software control, and if so, whether each pin is configured
as an input or output and if a pullup or pulldown resistor in the pad is connected. Each peripheral that connects
to the I/O pins can choose between several different I/O pin locations to ensure flexibility in various applications.
The sleep timer is an ultralow-power timer that uses an internal 32.753-kHz RC oscillator. The sleep timer runs
continuously in all operating modes. Typical applications of this timer are as a real-time counter or as a wake-up
timer to get out of power modes 1 or 2.
A built-in watchdog timer allows the CC2543 to reset itself if the firmware hangs. When enabled by software,
the watchdog timer must be cleared periodically; otherwise, it resets the device when it times out.
Timer 1 is a 16-bit timer with timer/counter/PWM functionality. It has a programmable prescaler, a 16-bit period
value, and five individually programmable counter/capture channels, each with a 16-bit compare value. Each of
the counter/capture channels can be used as a PWM output or to capture the timing of edges on input signals. It
can also be configured in IR generation mode, where it counts timer 3 periods and the output is ANDed with the
output of timer 3 to generate modulated consumer IR signals with minimal CPU interaction.
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Timer 2 is a 40-bit timer used by the Radio. It has a 16-bit counter with a configurable timer period and a 24-bit
overflow counter that can be used to keep track of the number of periods that have transpired. A 40-bit capture
register is also used to record the exact time at which a start-of-frame delimiter is received/transmitted or the
exact time at which a packet ends. There are two 16-bit timer-compare registers and two 24-bit overflow-
compare registers that can be used to give exact timing for start of RX or TX to the radio or general interrupts.
Timer 3 and timer 4 are 8-bit timers with timer/counter/PWM functionality. They have a programmable prescaler,
an 8-bit period value, and one programmable counter channel with an 8-bit compare value. Each of the counter
channels can be used as PWM output.
USART 0 is configurable as either an SPI master/slave or a UART. It provides double buffering on both RX and
TX and hardware flow control and is thus well suited to high-throughput full-duplex applications. The USART has
its own high-precision baud-rate generator, thus leaving the ordinary timers free for other uses. When configured
as SPI slaves, the USART samples the input signal using SCK directly instead of using some oversampling
scheme, and are thus well-suited for high data rates.
The I2C module provides a digital peripheral connection with two pins and supports both master and slave
operation.
The ADC supports 7 bits (30 kHz bandwidth) to 12 bits (4 kHz bandwidth) of resolution. DC and audio
conversions with up to eight input channels (Port 0) are possible. The inputs can be selected as single-ended or
differential. The reference voltage can be internal, AVDD, or a single-ended or differential external signal. The
ADC also has a temperature-sensor input channel. The ADC can automate the process of periodic sampling or
conversion over a sequence of channels.
The AES encryption/decryption core allows the user to encrypt and decrypt data using the AES algorithm with
128-bit keys. The AES core also supports ECB, CBC, CFB, OFB, CTR, and CBC-MAC, as well as hardware
support for CCM.
The ultralow-power analog comparator enables applications to wake up from PM2 or PM3 based on an analog
signal. Both inputs are brought out to pins; the reference voltage must be provided externally. The comparator
output is mapped into the digital I/O port and can be treated by the MCU as a regular digital input.
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TYPICAL CHARACTERISTICS
RX CURRENT
TX CURRENT
vs
TEMPERATURE
vs
TEMPERATURE
24
32
3-V Supply
TXPOWER Setting = 0xE5
3-V Supply
Standard Gain Setting
31
30
29
28
27
23
22
21
20
19
−70 dBm Input
2 Mbps, GFSK, 320 kHz deviation
−40
−20
0
20
40
60
80
−40
−20
0
20
Temperature (°C)
40
60
80
Temperature (°C)
G002
G001
Figure 8.
Figure 9.
RX SENSITIVITY
vs
TX POWER
vs
TEMPERATURE
TEMPERATURE
10
8
−80
−82
−84
−86
−88
−90
3-V Supply
3-V Supply
Standard Gain Setting
TXPOWER Setting = 0xE5
2 Mbps, GFSK, 320 kHz deviation
6
4
2
0
−40
−20
0
20
40
60
80
−40
−20
0
20
Temperature (°C)
40
60
80
Temperature (°C)
G004
G003
Figure 10.
Figure 11.
RX CURRENT
vs
SUPPLY VOLTAGE
TX CURRENT
vs
SUPPLY VOLTAGE
24
23
22
21
20
19
32
31
30
29
28
27
TA = 25°C
Standard Gain Setting
TA = 25°C
TXPOWER Setting = 0xE5
−70 dBm Input
2 Mbps, GFSK, 320 kHz deviation
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
2
2.2
2.4
2.6 3
Supply Voltage (V)
2.8
3.2
3.4
3.6
Supply Voltage (V)
G006
G005
Figure 12.
Figure 13.
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TYPICAL CHARACTERISTICS (continued)
RX SENSITIVITY
vs
TX POWER
vs
SUPPLY VOLTAGE
SUPPLY VOLTAGE
10
8
−80
−82
−84
−86
−88
−90
TA = 25°C
TXPOWER Setting = 0xE5
TA = 25°C
Standard Gain Setting
2 Mbps, GFSK, 320 kHz deviation
6
4
2
0
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
2
2.2
2.4
2.6
2.8
3
Supply Voltage (V)
3.2
3.4
3.6
Supply Voltage (V)
G008
G007
Figure 14.
Figure 15.
RX SENSITIVITY
vs
TX POWER
vs
FREQUENCY
FREQUENCY
10
8
−80
−82
−84
−86
−88
−90
3-V Supply
TA = 25°C
3-V Supply
TA = 25°C
Standard Gain Setting
TXPOWER Setting = 0xE5
2 Mbps, GFSK, 320 kHz deviation
6
4
2
0
2400
2420
2440
Frequency (MHz)
2460
2480
2400
2420
2440
Frequency (MHz)
2460
2480
G011
G009
Figure 16.
Figure 17.
RX INTERFERER REJECTION (SELECTIVITY)
vs
INTERFERER FREQUENCY
0
−10
−20
−30
−40
−50
−60
−70
−80
−90
3-V Supply
TA = 25°C
Standard Gain Setting
Wanted Signal at
2440 MHz with
−67 dBm Level
2400
2420
2440
2460
2480
Frequency (MHz)
G010
Figure 18.
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TYPICAL CHARACTERISTICS (continued)
Table 2. Recommended Output Power Settings(1)
TXPOWER Register Setting
Typical Output Power (dBm)
0xE5
0xD5
0xC5
0xB5
0xA5
0x95
0x85
0x75
0x65
0x55
0x45
0x35
0x25
0x15
0x05
5
4
3
2
0
–2
–3
–4
–6
–8
–11
–13
–15
–17
–20
(1) Measured on Texas Instruments CC2543 EM reference design with TA = 25°C, VDD = 3 V and fc = 2440 MHz.
See SWRU283 for recommended register settings.
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APPLICATION INFORMATION
Few external components are required for the operation of the CC2543. A typical application circuit is shown in
Figure 19. For suggestions of component values other than those listed in Table 3, see reference design
CC2543EM. The performance stated in this data sheet is only valid for the CC2543EM reference design. To
obtain similar performance, the reference design should be copied as closely as possible.
C301
2-V–3.6-V
Power Supply
R251
Antenna
(50 W)
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
P1_3
P2_1/DD
P2_0
VDD
VDD
VSS
RF_N
RF_P
P0_7
CC2543
P0_6
P0_5
DIE ATTACH PAD
VSS
VDD
P0_4
P0_3
XOSC_Q2
C171
C161
Power Supply Decoupling Capacitors are Not Shown
Digital I/O Not Connected
S0383-08
Figure 19. CC2543 Application Circuit
Table 3. Overview of External Components (Excluding Balun, Crystal and Supply Decoupling Capacitors)
COMPONENT
C301
DESCRIPTION
VALUE
1 µF
Decoupling capacitor for the internal 1.8V digital voltage regulator
Precision resistor ±1%, used for internal biasing
R251
56 kΩ
Input/Output Matching
When using an unbalanced antenna such as a monopole, a balun should be used to optimize performance. The
balun can be implemented using low-cost discrete inductors and capacitors. See reference design, CC2543EM,
for recommended balun.
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Crystal
An external 32-MHz crystal with two loading capacitors is used for the 32-MHz crystal oscillator. The load
capacitance seen by the 32-MHz crystal is given by:
1
CL =
+ Cparasitic
1
1
+
C161 C171
(1)
A series resistor may be used to comply with ESR requirement.
On-Chip 1.8-V Voltage Regulator Decoupling
The 1.8-V on-chip voltage regulator supplies the 1.8-V digital logic. This regulator requires a decoupling capacitor
(C301) for stable operation.
Power-Supply Decoupling and Filtering
Proper power-supply decoupling must be used for optimum performance. The placement and size of the
decoupling capacitors and the power supply filtering are very important to achieve the best performance in an
application. TI provides a compact reference design that should be followed very closely.
SPACER
REVISION HISTORY
Changes from Original (April 2012) to Revision A
Page
•
Changed data sheet status from Product Preview to Production Data ................................................................................ 1
Changes from Revision A (April 2012) to Revision B
Page
•
•
Added Comparator Characteristics specifications ................................................................................................................ 7
Added ADC Characteristics specifications ........................................................................................................................... 8
Changes from Revision B (May 2012) to Revision C
Page
•
Changed the Temperature coefficient Unit value From: mV/°C To: / 0.1°C ......................................................................... 7
Changes from Revision C (August 2012) to Revision D
Page
•
Changed the Pin Package From: RHM to: RHB ................................................................................................................. 13
Changes from Revision D (November 2012) to Revision E
Page
•
Changed the ADC CHARACTERISTICS Test Conditions From: VDD is voltage on AVDD5 pin To: VDD is voltage
from supply ........................................................................................................................................................................... 8
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3-Oct-2013
PACKAGING INFORMATION
Orderable Device
CC2543RHBR
CC2543RHBT
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
ACTIVE
VQFN
VQFN
RHB
32
32
3000
Green (RoHS CU NIPDAUAG Level-3-260C-168 HR
& no Sb/Br)
CC2543
CC2543
ACTIVE
RHB
250
Green (RoHS CU NIPDAUAG Level-3-260C-168 HR
& no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Oct-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
CC2543RHBR
CC2543RHBT
VQFN
VQFN
RHB
RHB
32
32
3000
250
330.0
180.0
12.4
12.4
5.3
5.3
5.3
5.3
1.5
1.5
8.0
8.0
12.0
12.0
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Oct-2013
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
CC2543RHBR
CC2543RHBT
VQFN
VQFN
RHB
RHB
32
32
3000
250
338.1
210.0
338.1
185.0
20.6
35.0
Pack Materials-Page 2
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相关型号:
CC2550RSTG3
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TI
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