CC2544_技术文档

CC2544

www.ti.com

SWRS103D –JUNE 2011–REVISED MAY 2012

System-on-Chip for 2.4-GHz USB Applications

1

FEATURES

•

Microcontroller

–

High-Performance and Low-Power 8051

Microcontroller Core With Code Prefetch

•

RF section

–

Single-Chip 2.4-GHz RF Transceiver and

–

32-KB Flash Program Memory

2 KB SRAM

MCU

–

Data Rates and Modulation Formats:

Hardware Debug Support

–

2-Mbps GFSK, 320-kHz Deviation

2-Mbps GFSK, 500-kHz Deviation

1-Mbps GFSK, 160-kHz Deviation

1-Mbps GFSK, 250-kHz Deviation

500-kbps MSK

Extensive Baseband Automation, Including

Auto-Acknowledgement and Address

Decoding

•

Peripherals

–

Full Speed USB 2.0

250-kbps GFSK, 160-kHz Deviation

250-kbps MSK

–

6 Endpoints (Endpoint 0 and 5 IN/OUT

Endpoints)

–

Excellent Link Budget, Enabling Long

Range Without External Front-Ends

–

Internal Pullup for D+

5-V to 3.3-V Regulator

–

Programmable Output Power up to 4 dBm

–

Powerful Two-Channel DMA

Excellent Receiver Sensitivity (–88 dBm at

2 Mbps)

General-Purpose Timers (One 16-Bit, Two

8-Bit)

–

Suitable for Systems Targeting Compliance

With Worldwide Radio Frequency

Regulations: ETSI EN 300 328 and EN 300

440 Category 2 (Europe), FCC CFR47 Part

15 (US), and ARIB STD-T66 (Japan)

–

Radio Timer, 40-Bit

IR Generation Circuitry

Several Oscillators:

–

32-MHz XOSC

16-MHz RCOSC

32-kHz RCOSC

–

Accurate RSSI Function

•

Layout

–

Few External Components

–

32-kHz Sleep Timer With Capture

AES Security Coprocessor

UART/SPI Serial Interface

Reference Designs Available

32-pin 5-mm × 5-mm QFN (8 General I/O

Pins) Package

8 General-Purpose I/O pins (6 × 4-mA and 2

× 20-mA Drive Strength)

Low Power

–

Active Mode RX: 22.5 mA

–

Watchdog Timer

Active Mode TX (0 dBm): 27 mA

Power Mode 1 (4-µs Wake-Up): 1 mA

Wide Supply-Voltage Range

True Random-Number Generator

APPLICATIONS

–

3.3V LDO Output

•

Proprietary 2.4-GHz Systems

Human Interface Devices (USB Dongle)

Consumer Electronics

Supply Range: 2 V–3.6 V

USB 5-V Regulator: 4 V–5.45 V

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

CC2544

SWRS103D –JUNE 2011–REVISED MAY 2012

www.ti.com

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

DESCRIPTION

The CC2544 is an optimized system-on-chip (SoC) solution for USB applications with datarates upto 2Mbps built

with low bill-of-material cost. The CC2544 combines the excellent performance of a leading RF transceiver with a

single-cycle 8051 compliant CPU, 32-KB in-system programmable flash memory, up to 2-KB RAM, and many

other powerful features.

The CC2544 is compatible with the CC2541/CC2543/CC2545. It comes in a 5-mm × 5-mm QFN32 package, with

SPI/UART/USB interface. The CC2544 comes complete with reference designs from Texas Instruments.

The devices target wireless consumer and HID applications. The CC2544 is ideal for USB dongle applications.

For block diagram, see Figure 7

ABSOLUTE MAXIMUM RATINGS⁽¹⁾

over operating free-air temperature range (unless otherwise noted)

PARAMETER

Supply voltage VBUS

Supply voltage VDD

Voltage on any digital pin

Input RF level

TEST CONDITIONS

MIN

–0.3

MAX

5.5

UNIT

V

All supply pins must have the same voltage

≤3.9

10

V

dBm

°C

Storage temperature range

–40

125

All pins, according to human-body model, JEDEC STD 22,

method A114 (HBM)

2

kV

V

ESD⁽²⁾

According to charged-device model, JEDEC STD 22, method

C101 (CDM)

750

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating

Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) CAUTION: ESD sensitive device. Precautions should be used when handing the device in order to prevent permanent damage.

RECOMMENDED OPERATING CONDITIONS

PARAMETER

TEST CONDITIONS

MIN

–40

4

MAX

85

UNIT

°C

V

Operating ambient temperature range, T_A

Operating supply voltage VBUS

Operating supply voltage VDD

Optional to use this regulator

5.45

3.6

All supply pins must have same voltage

2

V

2

Submit Documentation Feedback

Product Folder Link(s): CC2544

CC2544

www.ti.com

SWRS103D –JUNE 2011–REVISED MAY 2012

ELECTRICAL CHARACTERISTICS

Measured on Texas Instruments CC2544EM reference design with T_A= 25°C and VDD = 3.3 V, VBUS tied to 5 V, unless

otherwise noted.

PARAMETER

2 Mbps, GFSK, 320-kHz Deviation, 0.1% BER

RX mode, no peripherals active, low MCU activity

TEST CONDITIONS

MIN

TYP

MAX

UNIT

22.5

27

mA

TX mode, 0-dBm output power, no peripherals active, low MCU

activity

TX mode, 4-dBm output power, no peripherals active, low MCU

activity

30

mA

Active mode, 16-MHz RCOSC, Low MCU activity

4

7

mA

Active mode, 32-MHz clock frequency, low MCU activity

I _core– Core current

consumption

Power mode 0, CPU clock halted, all peripherals on, no clock

division, 32-MHz crystal selected

6

mA

Power mode 0, CPU clock halted, all peripherals on, clock

division at max. (Limits max. speed in peripherals except

radio), 32-MHz crystal selected

3.5

mA

Power mode 1. Digital regulator on; 16-MHz RCOSC and 32-

MHz crystal oscillator off; 32.753-kHz RCOSC, POR, BOD,

and sleep timer active; RAM and register retention

1

mA

Timer 1 (16-bit). Timer running, 32-MHz XOSC used

Radio timer(40 bit). Timer running, 32-MHz XOSC used

Timer 3 (8-bit). Timer running, 32-MHz XOSC used

Timer 4 (8-bit). Timer running, 32-MHz XOSC used

Sleep timer. Including 32.753-kHz RCOSC

90

60

70

0.6

µA

I _peri– Peripheral

current consumption

(Adds to core

current I_corefor each

peripheral unit

activated)

GENERAL CHARACTERISTICS

Measured on Texas Instruments CC2544EM reference design with T_A= 25°C and VDD = 3.3 V, VBUS tied to 5 V, unless

otherwise noted.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

WAKE-UP AND TIMING

Digital regulator on, 16-MHz RCOSC and 32-MHz crystal

oscillator off. Start-up of 16-MHz RCOSC.

Power mode 1 → Active

Active → TX or RX

4

µs

Crystal ESR = 16 Ω. Initially running on 16-MHz RCOSC, with

32-MHz XOSC OFF.

410

With 32-MHz XOSC initially on.

160

130

µs

RX/TX turnaround

RADIO PART

RF frequency range

Programmable in 1-MHz steps

2380

2495

MHz

2 Mbps, GFSK 320-kHz deviation

2-Mbps, GFSK 500 kHz deviation

1-Mbps, GFSK 160 kHz deviation

1-Mbps, GFSK 250 kHz deviation

Data rates and modulation

formats

500 kbps, MSK

250 kbps, GFSK 160 kHz deviation

250 kbps, MSK

Submit Documentation Feedback

3

Product Folder Link(s): CC2544

CC2544

SWRS103D –JUNE 2011–REVISED MAY 2012

www.ti.com

RF RECEIVE SECTION

Measured on Texas Instruments CC2544EM reference design with T_A= 25°C, VDD = 3.3 V, VBUS tied to 5 V, and f_C= 2440

MHz, unless otherwise noted.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

2 Mbps, GFSK, 320-kHz Deviation, 0.1% BER

Receiver sensitivity

Saturation⁽¹⁾

–84

0

dBm

dB

Co-channel rejection

Wanted signal at -67 dBm

–15

–5

30

40

42

±2-MHz offset, wanted signal –67 dBm

±4-MHz offset, wanted signal –67 dBm

±6-MHz offset, wanted signal –67 dBm

>12-MHz offset, wanted signal –67 dBm

In-band blocking rejection

dB

1-MHz resolution. Wanted signal –67 dBm, f < 2 GHz

Two exception frequencies with poorer performance

–35

–36

–12

1-MHz resolution. Wanted signal –67 dBm, 2 GHz > f < 3

GHz

Two exception frequencies with poorer performance

Out-of-band blocking

rejection

dBm

1-MHz resolution. Wanted signal –67 dBm, f > 3GHz

Two exception frequencies with poorer performance

Wanted signal –64 dBm, 1^stinterferer is CW, 2^ndinterferer

is GFSK-modulated signal. Offsets of interferers are:

6 and 12 MHz

8 and 16 MHz

10 and 20 MHz

Intermodulation

–43

Frequency error

tolerance⁽²⁾

Including both initial tolerance and drift. Limit set to

minimum sensitivity of –70dBm, 250K byte payload

–300

–120

300

120

kHz

Symbol rate error

tolerance⁽³⁾

Limit set to minimum sensitivity of –70 dBm, 250K byte

payload

ppm

2 Mbps, GFSK, 500-kHz Deviation, 0.1% BER

Receiver sensitivity

Saturation⁽¹⁾

–88

3

dBm

dB

Co-channel rejection

Wanted signal at -67 dBm

-9

±2-MHz offset, wanted signal –67 dBm

±4-MHz offset, wanted signal –67 dBm

±6-MHz offset, wanted signal –67 dBm

>12-MHz offset, wanted signal –67 dBm

-3

33

49

40

In-band blocking rejection

dB

Frequency error

tolerance⁽²⁾

Including both initial tolerance and drift. Sensitivity better

than –70 dBm. 250-byte payload

–300

–120

300

120

kHz

Symbol-rate error

tolerance⁽³⁾

Sensitivity better than –70 dBm. 250-byte payload

ppm

1 Mbps, GFSK, 250-kHz Deviation, 0.1% BER

Receiver sensitivity

Saturation⁽¹⁾

-91

5

dBm

dB

Co-channel rejection

Wanted signal at –67 dBm

-6

±2-MHz offset, wanted signal –67 dBm

±4-MHz offset, wanted signal –67 dBm

±6-MHz offset, wanted signal –67 dBm

>12-MHz offset, wanted signal –67 dBm

28

31

40

49

In-band blocking rejection

dB

Frequency error

tolerance⁽²⁾

Including both initial tolerance and drift. Sensitivity better

than –70 dBm. 250-byte payload

–250

–80

250

80

kHz

Symbol-rate error

tolerance⁽³⁾

Sensitivity better than –70 dBm. 250-byte payload

ppm

(1) AGC enabled

(2) Difference between center frequency of the received RF signal and local oscillator frequency

(3) Difference between incoming symbol rate and the internally generated symbol rate

4

Submit Documentation Feedback

Product Folder Link(s): CC2544

CC2544

www.ti.com

SWRS103D –JUNE 2011–REVISED MAY 2012

RF RECEIVE SECTION (continued)

Measured on Texas Instruments CC2544EM reference design with T_A= 25°C, VDD = 3.3 V, VBUS tied to 5 V, and f_C= 2440

MHz, unless otherwise noted.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

1 Mbps, GFSK, 160-kHz Deviation, 0.1% BER

Receiver sensitivity

Saturation⁽¹⁾

-87

5

dBm

dB

Co-channel rejection

Wanted signal at -67 dBm

-9

±2-MHz offset, wanted signal –67 dBm

±4-MHz offset, wanted signal –67 dBm

±6-MHz offset, wanted signal –67 dBm

>12-MHz offset, wanted signal –67 dBm

26

30

40

46

In-band blocking rejection

dB

Frequency error

tolerance⁽²⁾

Including both initial tolerance and drift. Sensitivity better

than –70 dBm. 250-byte payload

–250

–80

250

80

kHz

Symbol-rate error

tolerance⁽³⁾

Sensitivity better than –70 dBm. 250-byte payload

ppm

500 kbps, MSK, 0.1% BER

Receiver sensitivity

Saturation⁽⁴⁾

-96

5

dBm

dB

Co-channel rejection

Wanted signal at -67 dBm

-5

±2-MHz offset, wanted signal –67 dBm

±4-MHz offset, wanted signal –67 dBm

±6-MHz offset, wanted signal –67 dBm

>12-MHz offset, wanted signal –67 dBm

31

45

54

In-band blocking rejection

dB

Frequency error

tolerance⁽⁵⁾

Including both initial tolerance and drift. Sensitivity better

than –70 dBm. 250-byte payload

–150

–60

150

60

kHz

Symbol-rate error

tolerance⁽⁶⁾

Sensitivity better than –70 dBm. 250-byte payload

ppm

(4) AGC enabled

(5) Difference between center frequency of the received RF signal and local oscillator frequency

(6) Difference between incoming symbol rate and the internally generated symbol rate

Submit Documentation Feedback

5

Product Folder Link(s): CC2544

CC2544

SWRS103D –JUNE 2011–REVISED MAY 2012

www.ti.com

RF RECEIVE SECTION (continued)

Measured on Texas Instruments CC2544EM reference design with T_A= 25°C, VDD = 3.3 V, VBUS tied to 5 V, and f_C= 2440

MHz, unless otherwise noted.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

250 kbps, GFSK, 160-kHz Deviation, 0.1% BER

Receiver sensitivity

Saturation⁽⁷⁾

-95

5

dBm

dB

Co-channel rejection

Wanted signal at –67 dBm

-9

±2-MHz offset, wanted signal –67 dBm

±4-MHz offset, wanted signal –67 dBm

±6-MHz offset, wanted signal –67 dBm

>12-MHz offset, wanted signal –67 dBm

31

55

53

In-band blocking rejection

dB

Frequency error

tolerance⁽⁸⁾

Including both initial tolerance and drift. Sensitivity better

than –70 dBm. 250-byte payload

–150

–60

150

60

kHz

Symbol-rate error

tolerance⁽⁹⁾

Sensitivity better than –70 dBm. 250-byte payload

ppm

250 kbps, MSK, 0.1% BER

Receiver sensitivity

Saturation⁽⁷⁾

–95

5

dBm

dB

Co-channel rejection

Wanted signal at –67 dBm

–5

31

45

54

±2-MHz offset, wanted signal –67 dBm

±4-MHz offset, wanted signal –67 dBm

±6-MHz offset, wanted signal –67 dBm

>12-MHz offset, wanted signal –67 dBm

In-band blocking rejection

dB

Frequency error

tolerance⁽⁸⁾

Including both initial tolerance and drift. Sensitivity better

than –70 dBm. 250-byte payload

–150

–60

150

60

kHz

Symbol-rate error

tolerance⁽⁹⁾

Sensitivity better than –70 dBm. 250-byte payload

ppm

ALL RATES/FORMATS

Spurious emission in RX.

Conducted measurement

f < 1 GHz

f > 1 GHz

–67

–57

dBm

Spurious emission in RX.

Conducted measurement

(7) AGC enabled

(8) Difference between center frequency of the received RF signal and local oscillator frequency

(9) Difference between incoming symbol rate and the internally generated symbol rate

RF TRANSMIT SECTION

Measured on Texas Instruments CC2544EM reference design with T_A= 25°C, VDD = 3.3 V, VBUS tied to 5 V, and f_C= 2440

MHz, unless otherwise noted.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Output power, maximum

setting

Delivered to a single-ended 50-Ω load through a balun

using maximum recommended output power setting.

4

dBm

Output power, minimum

setting

Delivered to a single-ended 50-Ω load through a balun

using minimum recommended output power setting.

–20

24

dBm

dB

Programmable output power

range

Delivered to a single-ended 50-Ω load through a balun.

Spurious emission in TX.

Conducted measurement.

f < 1 GHz

f > 1 GHz

–46

dBm

Ω

Spurious emission in TX.

Conducted measurement.

–44

Differential impedance as seen from the RF port (RF_P

and RF_N) toward the antenna

Optimum load impedance

70 + j30

6

Submit Documentation Feedback

Product Folder Link(s): CC2544

CC2544

www.ti.com

SWRS103D –JUNE 2011–REVISED MAY 2012

32-MHz CRYSTAL OSCILLATOR

Measured on Texas Instruments CC2544EM reference design with T_A= 25°C, VDD = 3.3 V, VBUS tied to 5 V, unless

otherwise noted.

PARAMETER

Crystal frequency

TEST CONDITIONS

MIN

TYP

MAX

UNIT

32

MHz

Crystal frequency accuracy

requirement

2-Mbps data rate

–60

60

ppm

Equivalent series resistance

Crystal shunt capacitance

Crystal load capacitance

Start-up time

6

1

60

7

Ω

pF

ms

10

16

0.25

The crystal oscillator must be in power down for a guard

time before it is used again. This requirement is valid for

all modes of operation. The need for power-down guard

time can vary with crystal type and load.

Power-down guard time

3

ms

32-kHz RC OSCILLATOR

Measured on Texas Instruments CC2544EM reference design with T_A= 25°C, VDD = 3.3 V, VBUS tied to 5 V, unless

otherwise noted.

PARAMETER

Calibrated frequency⁽¹⁾

TEST CONDITIONS

MIN

TYP

32.753

±0.2%

0.4

MAX

UNIT

kHz

Frequency accuracy after calibration

Temperature coefficient⁽²⁾

Supply-voltage coefficient⁽³⁾

Calibration time⁽⁴⁾

%/ºC

%/V

ms

3

2

(1) The calibrated 32-kHz RC oscillator frequency is the 32-MHz XTAL frequency divided by 977.

(2) Frequency drift when temperature changes after calibration

(3) Frequency drift when supply voltage changes after calibration

(4) The 32-kHz RC oscillator is calibrated when a switch from the 16-MHz RC oscillator to the 32-MHz crystal oscillator is performed, while

SLEEPCMD.OSC32K_CALDIS is set to 0.

16-MHz RC OSCILLATOR

Measured on Texas Instruments CC2544EM reference design with T_A= 25°C, VDD = 3.3 V, VBUS tied to 5 V, unless

otherwise noted.

PARAMETER

Calibrated frequency

TEST CONDITIONS

MIN

TYP

16

MAX

UNIT

MHz

Uncalibrated frequency accuracy

Frequency accuracy after calibration⁽¹⁾

Start-up time

±18%

±0.6%

10

µs

Initial calibration time

50

(1) The calibrated 16-MHz RC oscillator frequency is the 32-MHz XTAL frequency divided by 2.

Submit Documentation Feedback

7

Product Folder Link(s): CC2544

CC2544

SWRS103D –JUNE 2011–REVISED MAY 2012

www.ti.com

RSSI CHARACTERISTICS

Measured on Texas Instruments CC2544 EM reference design with T_A= 25°C and VDD = 3 V

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

2 Mbps, GFSK, 320-kHz Deviation, 0.1% BER and 2 Mbps, GFSK, 500-kHz Deviation, 0.1% BER

RSSI range⁽¹⁾

RSSI offset⁽¹⁾

Absolute uncalibrated accuracy⁽¹⁾

Step size (LSB value)

All Other Rates/Formats

RSSI range⁽¹⁾

60

97

±6

1

dB

dBm

dB

60

101

±3

dB

dBm

dB

RSSI offset⁽¹⁾

Absolute uncalibrated accuracy⁽¹⁾

Step size (LSB value)

1

dB

(1) Assuming CC2544 EM reference design. Other RF designs give an offset from the reported value.

FREQUENCY SYNTHESIZER CHARACTERISTICS

Measured on Texas Instruments CC2544EM reference design with T_A= 25°C, VDD = 3.3 V, VBUS tied to 5 V, unless

otherwise noted.

PARAMETER

TEST CONDITIONS

At ±1 MHz from carrier

MIN

TYP

–112

–119

–124

MAX

UNIT

Phase noise, unmodulated carrier At ±2 MHz from carrier

At ±5 MHz from carrier

dBc/Hz

USB BUS 5-V to 3.3-V REGULATOR

Measured on Texas Instruments CC2544EM reference design with T_A= 25°C, VDD = 3.3 V, VBUS tied to 5 V, unless

otherwise noted.

PARAMETER

Input voltage, typical minimum

Input voltage, typical maximum

Current limit

TEST CONDITIONS

MIN

TYP

4

MAX

UNIT

V

5.45

100

0.8

3.3

V

mA

ms

V

Start-up time

Output voltage

8

Submit Documentation Feedback

Product Folder Link(s): CC2544

CC2544

www.ti.com

SWRS103D –JUNE 2011–REVISED MAY 2012

DC CHARACTERISTICS

Measured on Texas Instruments CC2544EM reference design with T_A= 25°C, VDD = 3.3 V, VBUS tied to 5 V, unless

otherwise noted.

PARAMETER

Logic-0 input voltage

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V

0.5

Logic-1 input voltage

2.5

–50

V

Logic-0 input current

50

nA

kΩ

V

Logic-1 input current

I/O pin pullup and pulldown resistors

Logic-0 output voltage 4-mA pins

Logic-1 output voltage 4-mA pins

Logic-0 output voltage 20-mA pins

Logic-1 output voltage, 20-A pins

20

Output load 4 mA

0.5

2.4

V

Output load 20 mA

Outpu load 20 mA

V

CONTROL INPUT AC CHARACTERISTICS

T_A= –40°C to 85°C, VDD = 2 V to 3.6 V.

PARAMETER

TEST CONDITIONS

MIN TYP

MAX UNIT

The undivided system clock is 32 MHz when crystal oscillator is used.

The undivided system clock is 16 MHz when calibrated 16-MHz RC

oscillator is used.

System clock, f_SYSCLK

t_SYSCLK= 1/ f_SYSCLK

16

32

MHz

See item 1, Figure 1. This is the shortest pulse that is recognized as

a complete reset pin request. Note that shorter pulses may be

recognized but do not lead to complete reset of all modules within the

chip.

RESET_N low duration

Interrupt pulse duration

1

µs

ns

See item 2, Figure 1.This is the shortest pulse that is recognized as

an interrupt request.

20

RESET_N

1

2

Px.n

T0299-01

Figure 1. Control Input AC Characteristics

SPI AC CHARACTERISTICS

T_A= –40°C to 85°C, VDD = 2 V to 3.6 V

PARAMETER

TEST CONDITIONS

MIN

250

TYP MAX UNIT

Master, RX and TX

Slave, RX and TX

Master

t₁

SCK period

ns

SCK duty cycle

50%

Master

63

SSN low to SCK,

Figure 2 and Figure 3

t₂

t₃

ns

Slave

Master

SCK to SSN high

ns

Slave

t₄

t₅

t₆

t₇

MOSI early out

MOSI late out

MISO setup

MISO hold

Master, load = 10 pF

Master

7

ns

10

90

10

Master

Submit Documentation Feedback

9

Product Folder Link(s): CC2544

CC2544

SWRS103D –JUNE 2011–REVISED MAY 2012

www.ti.com

SPI AC CHARACTERISTICS (continued)

T_A= –40°C to 85°C, VDD = 2 V to 3.6 V

PARAMETER

TEST CONDITIONS

MIN

TYP MAX UNIT

SCK duty cycle

MOSI setup

Slave

50%

ns

t₁₀

t₁₁

t₈

Slave

35

10

MOSI hold

Slave

MISO early out

MISO late out

Slave, load = 10 pF

Master, TX only

Master, RX and TX

Slave, RX only

Slave, RX and TX

0

95

8

t₉

4

Operating frequency

MHz

8

4

SCK

t₂

t₃

SSN

t₄

t₅

MOSI

D0

X

D1

t₆

t₇

MISO

X

D0

X

T0478-01

Figure 2. SPI Master AC Characteristics

SCK

t₂

t₃

SSN

t₈

t₉

MISO

D0

X

D1

t₁₀

t₁₁

MOSI

X

D0

X

T0479-01

Figure 3. SPI Slave AC Characteristics

10

Submit Documentation Feedback

Product Folder Link(s): CC2544

CC2544

www.ti.com

SWRS103D –JUNE 2011–REVISED MAY 2012

DEBUG INTERFACE AC CHARACTERISTICS

T_A= –40°C to 85°C, VDD = 2 V to 3.6 V

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

MHz

ns

f_{clk_dbg}

Debug clock frequency (see Figure 4)

Allowed high pulse on clock (see Figure 4)

Allowed low pulse on clock (see Figure 4)

12

t₁

t₂

35

ns

EXT_RESET_N low to first falling edge on debug

clock (see Figure 5)

t₃

t₄

t₅

167

83

ns

Falling edge on clock to EXT_RESET_N high (see

Figure 5)

EXT_RESET_N high to first debug command (see

Figure 5)

83

t₆

t₇

t₈

Debug data setup (see Figure 6)

Debug data hold (see Figure 6)

Clock-to-data delay (see Figure 6)

2

4

ns

Load = 10 pF

30

Time

DEBUG_ CLK

P1_2

t₁

t₂

1/f_{clk_dbg}

T0436-44

Figure 4. Debug Clock – Basic Timing

Ti me

DEBUG_ CLK

P1_2

RESET_N

t₃

t₄

t₅

T0437-44

Figure 5. Debug Enable Timing

Submit Documentation Feedback

11

Product Folder Link(s): CC2544

CC2544

SWRS103D –JUNE 2011–REVISED MAY 2012

www.ti.com

Time

DEBUG_CLK

P1_2

DEBUG_DATA

(to CC2544)

P1_3

DEBUG_DATA

(from CC2544)

P1_3

t₆

t₇

t₈

T0438-03

Figure 6. Data Setup and Hold Timing

TIMER INPUTS AC CHARACTERISTICS

T_A= –40°C to 85°C, VDD = 2 V to 3.6 V

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Synchronizers determine the shortest input pulse that can be

recognized. The synchronizers operate at the current system

clock rate (16 MHz or 32 MHz).

Input capture pulse duration

1.5

t_SYSCLK

12

Submit Documentation Feedback

Product Folder Link(s): CC2544

CC2544

www.ti.com

SWRS103D –JUNE 2011–REVISED MAY 2012

DEVICE INFORMATION

PIN DESCRIPTIONS

CC2544

RHB Package

(Top View)

32 31 30 29 28 27 26 25

24

USB_P

USB_N

1

2

3

4

5

6

7

8

VDD

RF_N

RF_P

23

22

VDD

DCPL2

VBUS

P1_0

21

VSS

Thermal Pad

20

19

18

17

VDD

P1_1

XOSC2

XOSC1

VDD

9

10 11 12 13 14 15 16

P0048-19

NOTE: The exposed ground pad must be connected to a solid ground plane; this is the main ground connection for the chip.

Table 1. Pin Description Table

NAME

DCPL1

31

4

DESCRIPTION

1.8-V reg. decouple

3.3-V reg. decouple

GPIO

DCPL2

P0_0

9

P0_1

10

13

14

6

GPIO

P0_2

GPIO

P0_3

GPIO

P1_0

GPIO/20 mA

GPIO/debug clock

GPIO/debug data

P1_1

7

P1_2

28

29

25

15

P1_3

RBIAS

RESET_N

External precision bias resistor for reference current

Reset, active-low

Negative RF input signal to LNA during RX

Negative RF output signal from PA during TX

RF_N

RF_P

21

20

Positive RF input signal to LNA during RX

Positive RF output signal from PA during TX

USB_P

USB_N

VBUS

VDD

1

2

USB module

5-V power

AVDD

5

3

VDD

8, 12

IOVDD

VDD

16, 19, 22, 23, 24 AVDD

Submit Documentation Feedback

13

Product Folder Link(s): CC2544

CC2544

SWRS103D –JUNE 2011–REVISED MAY 2012

www.ti.com

Table 1. Pin Description Table (continued)

NAME

DESCRIPTION

VDD

VSS

26

AVDD_GUARD

30

11, 27

32

IOVDD

Optional IOVSS

USB ground

Ground pad

17

Must be connected to solid ground as this is the main ground connection for the chip.

32-MHz crystal oscillator pin 1or external-clock input

32-MHz crystal oscillator pin 2

XOSC1

XOSC2

18

14

Submit Documentation Feedback

Product Folder Link(s): CC2544

CC2544

www.ti.com

SWRS103D –JUNE 2011–REVISED MAY 2012

BLOCK DIAGRAM

A block diagram of the CC2544 is shown in Figure 7. The modules can be roughly divided into one of three

categories: CPU-related modules; modules related to power, test, and clock distribution; and radio-related

modules. In the following subsections, a short description of each module is given. For more details, see the

CC2543/44/45 User’s Guide (SWRU283).

VDD (2 V–3.6 V)

WATCHDOG

TIMER

ON-CHIP VOLTAGE

REGULATOR

RESET_N

RESET

DCOUPL

XOSC_Q2

XOSC_Q1

32-MHz

POWER ON RESET

BROWN OUT

5 V to 3.3 V

VBUS (4 V –5.45 V)

VOLTAGE REGULATOR

CRYSTAL OSC

CLOCK MUX

and

CALIBRATION

SLEEP TIMER

HIGH-

32-kHz

SPEED

DEBUG

INTERFACE

POWER MANAGEMENT CONTROLLER

RC-OSC

PDATA

XRAM

IRAM

SFR

RAM

SRAM

8051 CPU

CORE

MEMORY

ARBITRATOR

P1_3

P1_2

P1_1

P1_0

FLASH

UNIFIED

DMA

IRQ CTRL

FLASH CTRL

1 KB SRAM

FIFOCTRL

PSEUDO-RANDOM

NUMBER

GENERATOR

P0_3

P0_2

P0_1

P0_0

RADIO REGISTERS

Link Layer Engine

AES

ENCRYPTION

AND

DECRYPTION

DEMODULATOR

MODULATOR

USB_N

USB_P

USB

RECEIVE

TRANSMIT

USART 0

TIMER 1 (16-Bit)

TIMER 2

(RADIO TIMER)

RF_P

RF_N

TIMER 3 (8-Bit)

TIMER 4 (8-Bit)

DIGITAL

ANALOG

MIXED

B0301-09

Figure 7. CC2544 Block Diagram

Submit Documentation Feedback

15

Product Folder Link(s): CC2544

CC2544

SWRS103D –JUNE 2011–REVISED MAY 2012

www.ti.com

BLOCK DESCRIPTIONS

CPU and Memory

The 8051 CPU core is a single-cycle 8051-compatible core. It has three different memory access busses (SFR,

DATA, and CODE/XDATA), a debug interface, and an 15-input extended interrupt unit.

The memory arbiter is at the heart of the system, as it connects the CPU and DMA controller with the physical

memories and all peripherals through the SFR bus. The memory arbiter has four memory-access points, access

of which can map to one of three physical memories: an SRAM, flash memory, and XREG/SFR registers. It is

responsible for performing arbitration and sequencing between simultaneous memory accesses to the same

physical memory.

The SFR bus is drawn conceptually in Figure 7 as a common bus that connects all hardware peripherals to the

memory arbiter. The SFR bus in the block diagram also provides access to the radio registers in the radio

register bank, even though these are indeed mapped into XDATA memory space.

The 2-KB SRAM maps to the DATA memory space and to parts of the XDATA memory spaces.

The 32-KB flash block provides in-circuit programmable non-volatile program memory for the device, and maps

into the CODE and XDATA memory spaces.

Peripherals

Writing to the flash block is performed through a flash controller that allows page-wise erasure and 4-bytewise

programming. See User Guide for details on the flash controller.

A versatile two-channel DMA controller is available in the system, accesses memory using the XDATA memory

space, and thus has access to all physical memories. Each channel (trigger, priority, transfer mode, addressing

mode, source and destination pointers, and transfer count) is configured with DMA descriptors that can be

located anywhere in memory. Many of the hardware peripherals (AES core, flash controller, USART, timers, etc.)

can be used with the DMA controller for efficient operation by performing data transfers between a single SFR or

XREG address and flash/SRAM.

The interrupt controller services a total of 15 interrupt sources, divided into six interrupt groups, each of which

is associated with one of four interrupt priorities. Any interrupt service request is serviced also when the device is

in idle mode by going back to active mode. Some interrupts can also wake up the device from sleep mode (when

in sleep mode, the device is in low-power mode PM1).

The debug interface implements a proprietary two-wire serial interface that is used for in-circuit debugging.

Through this debug interface, it is possible to perform an erasure of the entire flash memory, control which

oscillators are enabled, stop and start execution of the user program, execute supplied instructions on the 8051

core, set code breakpoints, and single-step through instructions in the code. Using these techniques, it is

possible to perform in-circuit debugging and external flash programming elegantly.

The I/O controller is responsible for all general-purpose I/O pins. The CPU can configure whether peripheral

modules control certain pins or whether they are under software control, and if so, whether each pin is configured

as an input or output and if a pullup or pulldown resistor in the pad is connected. Each peripheral that connects

to the I/O pins can choose between several different I/O pin locations to ensure flexibility in various applications.

The sleep timer is an ultralow-power timer that uses an internal 32.753-kHz RC oscillator. The sleep timer runs

continuously in all operating modes. Typical applications of this timer are as a real-time counter or as a wake-up

timer to get out of power mode 1.

A built-in watchdog timer allows the CC2544 to reset itself if the firmware hangs. When enabled by software,

the watchdog timer must be cleared periodically; otherwise, it resets the device when it times out.

Timer 1 is a 16-bit timer with timer/counter/PWM functionality. It has a programmable prescaler, a 16-bit period

value, and five individually programmable counter/capture channels, each with a 16-bit compare value. Each of

the counter/capture channels can be used as a PWM output or to capture the timing of edges on input signals. It

can also be configured in IR generation mode, where it counts timer 3 periods and the output is ANDed with the

output of timer 3 to generate modulated consumer IR signals with minimal CPU interaction.

16

Submit Documentation Feedback

Product Folder Link(s): CC2544

CC2544

www.ti.com

SWRS103D –JUNE 2011–REVISED MAY 2012

Timer 2 is a 40-bit timer used by the Radio. It has a 16-bit counter with a configurable timer period and a 24-bit

overflow counter that can be used to keep track of the number of periods that have transpired. A 40-bit capture

register is also used to record the exact time at which a start-of-frame delimiter is received/transmitted or the

exact time at which a packet ends. There are two 16-bit timer-compare registers and two 24-bit overflow-

compare registers that can be used to give exact timing for start of RX or TX to the radio or general interrupts.

Timer 3 and timer 4 are 8-bit timers with timer/counter/PWM functionality. They have a programmable prescaler,

an 8-bit period value, and one programmable counter channel with an 8-bit compare value. Each of the counter

channels can be used as PWM output.

USART 0 is configurable as either an SPI master/slave or a UART. It provides double buffering on both RX and

TX and hardware flow control and is thus well suited to high-throughput full-duplex applications. The USART has

its own high-precision baud-rate generator, thus leaving the ordinary timers free for other uses. When configured

as SPI slaves, the USART samples the input signal using SCK directly instead of using some oversampling

scheme, and are thus well-suited for high data rates.

The AES encryption/decryption core allows the user to encrypt and decrypt data using the AES algorithm with

128-bit keys. The AES core also supports ECB, CBC, CFB, OFB, CTR, and CBC-MAC, as well as hardware

support for CCM.

Submit Documentation Feedback

17

Product Folder Link(s): CC2544

CC2544

SWRS103D –JUNE 2011–REVISED MAY 2012

www.ti.com

TYPICAL CHARACTERISTICS

RX CURRENT

vs

TX CURRENT

vs

TEMPERATURE

23.5

31.5

3.3-V Supply

−70 dBm Input

3.3-V Supply

TXPOWER = 4 dBm

23.0

31.0

30.5

30.0

29.5

29.0

28.5

22.5

22.0

21.5

21.0

20.5

−40

−20

0

20

40

60

80

−40

−20

0

20

40

60

80

Temperature (°C)

Figure 8.

Figure 9.

RX SENSITIVITY

vs

TX POWER

vs

TEMPERATURE

−80

6

5

4

3

2

1

0

3.3-V Supply

TXPOWER = 4 dBm

−81

−82

−83

−84

−85

−86

−40

−20

0

20

40

60

80

−40

−20

0

20

40

60

80

Temperature (°C)

Figure 10.

Figure 11.

18

Submit Documentation Feedback

Product Folder Link(s): CC2544

CC2544

www.ti.com

SWRS103D –JUNE 2011–REVISED MAY 2012

TYPICAL CHARACTERISTICS (continued)

RX CURRENT

vs

TX CURRENT

vs

SUPPLY VOLTAGE

23.0

22.8

22.6

22.4

22.2

22.0

21.8

21.6

21.4

21.2

21.0

30.5

30.0

29.5

29.0

28.5

T = 25°C

−70 dBm Input

T = 25°C

TXPOWER = 4 dBm

2.0

2.2

2.4

2.6

2.8

3.0

3.2

3.4

3.6

2.0

2.2

2.4

2.6

2.8

3.0

3.2

3.4

3.6

Supply Voltage (V)

Figure 12.

Figure 13.

RX SENSITIVITY

vs

TX POWER

vs

SUPPLY VOLTAGE

−82

−83

−84

−85

−86

6

5

4

3

2

T = 25°C

TXPOWER = 4 dBm

2.0

2.2

2.4

2.6

2.8

3.0

3.2

3.4

3.6

2.0

2.2

2.4

2.6

2.8

3.0

3.2

3.4

3.6

Supply Voltage (V)

Figure 14.

Figure 15.

Submit Documentation Feedback

19

Product Folder Link(s): CC2544

CC2544

SWRS103D –JUNE 2011–REVISED MAY 2012

www.ti.com

TYPICAL CHARACTERISTICS (continued)

RX SENSITIVITY

TX POWER

vs

FREQUENCY

−82

−83

−84

−85

−86

6

5

4

3

3.3-V Supply

T = 25°C

3.3-V Supply

T = 25°C

TXPOWER = 4 dBm

2

2400

2420

2440

2460

2480

2420

2440

2460

2480

Frequency (MHz)

Figure 16.

Figure 17.

RX INTERFERER REJECTION (SELECTIVITY)

vs

INTERFERER FREQUENCY

85

3.3-V Supply

75

T = 25°C

Wanted signal at 2426 MHz

55

35

15

−5

−25

−45

−65

Wanted signal 3 dB above sensitivity limit

Wanted signal 10 dB above sensitivity limit

Wanted signal 30 dB above sensitivity limit

Wanted signal 50 dB above sensitivity limit

−15

−10

−5

0

5

10

15

Frequency Offset (MHz)

Figure 18.

20

Submit Documentation Feedback

Product Folder Link(s): CC2544

CC2544

www.ti.com

SWRS103D –JUNE 2011–REVISED MAY 2012

APPLICATION INFORMATION

Few external components are required for the operation of the CC2544. A typical application circuit is shown in

Figure 19. For suggestions of component values other than those listed in Table 2, see reference design

CC2544EM. The performance stated in this data sheet is only valid for the CC2544EM reference design. To

obtain similar performance, the reference design should be copied as closely as possible.

C311

R251

Antenna

(50 W)

C11

C21

R11

R21

1

2

3

4

5

6

7

8

24

23

22

21

20

19

18

17

D+

D–

USB_P

USB_N

VDD

RF_N

RF_P

DCPL2

VBUS

P1_0

CC2544

4-V to 5.45-V

Power Supply

DIE ATTACH PAD

VDD

XOSC2

XOSC1

P1_1

VDD

C41

C171

C181

Power Supply Decoupling Capacitors are Not Shown

Digital I/O Not Connected

S0383-06

Figure 19. CC2544 Application Circuit

Table 2. Overview of External Components (Excluding Balun, Crystal and Supply Decoupling Capacitors)

Component

C11

Description

Value

47 pF

USB D+ decoupling

USB D– decoupling

C21

Decoupling capacitor for the internal 5V-3.3V digital voltage

regulator

C41

1 µF

Decoupling capacitor for the internal 1.8V digital voltage

regulator

C311

R11

R21

USB D+ series resistor

33 Ω

USB D– series resistor

R251

Precision resistor ±1%, used for internal biasing

56 kΩ

Input/Output Matching

When using an unbalanced antenna such as a monopole, a balun should be used to optimize performance. The

balun can be implemented using low-cost discrete inductors and capacitors. See reference design, CC2544EM,

for recommended balun.

Submit Documentation Feedback

21

Product Folder Link(s): CC2544

CC2544

SWRS103D –JUNE 2011–REVISED MAY 2012

www.ti.com

Crystal

An external 32-MHz crystal with two loading capacitors is used for the 32-MHz crystal oscillator. The load

capacitance seen by the 32-MHz crystal is given by:

1

C_L=

+ C_parasitic

1

+

C₁₇₁C₁₈₁

(1)

A series resistor may be used to comply with ESR requirement.

On-Chip 1.8-V Voltage Regulator Decoupling

The 1.8-V on-chip voltage regulator supplies the 1.8-V digital logic. This regulator requires a decoupling capacitor

(C311) for stable operation.

On-Chip 5-V to 3.3-V USB Voltage Regulator Decoupling

The 5-V to 3.3-V on-chip voltage regulator supplies the 1.8-V on-chip voltage regulator. This regulator requires a

decoupling capacitor (C41) for stable operation.

Power-Supply Decoupling and Filtering

Proper power-supply decoupling must be used for optimum performance. The placement and size of the

decoupling capacitors and the power supply filtering are very important to achieve the best performance in an

application. TI provides a compact reference design that should be followed very closely.

22

Submit Documentation Feedback

Product Folder Link(s): CC2544

CC2544

www.ti.com

SWRS103D –JUNE 2011–REVISED MAY 2012

REVISION HISTORY

Changes from Original (June 2011) to Revision A

Page

•

Changes to the Product Preview data sheet ........................................................................................................................ 1

Changes from Revision A (March 2012) to Revision B

Page

•

Changed From: (–84 dBm at 2 Mbps) To: (–88 dBm at 2 Mbps) ......................................................................................... 1

Changes from Revision B (April 2012) to Revision C

Page

•

Changed the device From: Preview To: Production ............................................................................................................. 1

Changes from Revision C (April 2012) to Revision D

Page

•

Added the Description .......................................................................................................................................................... 2

Submit Documentation Feedback

23

Product Folder Link(s): CC2544

PACKAGE MATERIALS INFORMATION

www.ti.com

2-May-2012

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

CC2544RHBR

CC2544RHBT

QFN

RHB

32

3000

250

330.0

12.4

5.3

1.5

8.0

12.0

Q2

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

2-May-2012

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

CC2544RHBR

CC2544RHBT

QFN

RHB

32

3000

250

338.1

20.6

Pack Materials-Page 2

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements,

and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should

obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are

sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.

TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard

warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where

mandated by government requirements, testing of all parameters of each product is not necessarily performed.

TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and

applications using TI components. To minimize the risks associated with customer products and applications, customers should provide

adequate design and operating safeguards.

TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right,

or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information

published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a

warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual

property of the third party, or a license from TI under the patents or other intellectual property of TI.

Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied

by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive

business practice. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional

restrictions.

Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all

express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not

responsible or liable for any such statements.

TI products are not authorized for use in safety-critical applications (such as life support) where a failure of the TI product would reasonably

be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement specifically governing

such use. Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications, and

acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products

and any use of TI products in such safety-critical applications, notwithstanding any applications-related information or support that may be

provided by TI. Further, Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in

such safety-critical applications.

TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products are

specifically designated by TI as military-grade or "enhanced plastic." Only products designated by TI as military-grade meet military

specifications. Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is solely at

the Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use.

TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products are

designated by TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any non-designated

products in automotive applications, TI will not be responsible for any failure to meet such requirements.

Following are URLs where you can obtain information on other Texas Instruments products and application solutions:

Products

Audio

Applications

www.ti.com/audio

amplifier.ti.com

dataconverter.ti.com

www.dlp.com

Automotive and Transportation www.ti.com/automotive

Communications and Telecom www.ti.com/communications

Amplifiers

Data Converters

DLP® Products

DSP

Computers and Peripherals

Consumer Electronics

Energy and Lighting

Industrial

www.ti.com/computers

www.ti.com/consumer-apps

www.ti.com/energy

dsp.ti.com

Clocks and Timers

Interface

www.ti.com/clocks

interface.ti.com

logic.ti.com

www.ti.com/industrial

www.ti.com/medical

www.ti.com/security

Medical

Logic

Security

Power Mgmt

Microcontrollers

RFID

power.ti.com

Space, Avionics and Defense www.ti.com/space-avionics-defense

microcontroller.ti.com

www.ti-rfid.com

Video and Imaging

www.ti.com/video

OMAP Mobile Processors www.ti.com/omap

Wireless Connectivity www.ti.com/wirelessconnectivity

TI E2E Community Home Page

e2e.ti.com

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	CC2544
厂家：	TEXAS INSTRUMENTS
描述：	System-on-Chip for 2.4-GHz USB Applications 系统级芯片为2.4GHz的USB应用
文件：	总30页 (文件大小：769K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

CC2544 [TI]

相关型号：

CC2544RHBR

CC2544RHBT

CC2545

CC2545RGZR

CC2545RGZT

CC2550

CC2550-RTR1

CC2550-RTY1

CC2550EMK

CC2550RSTG3

CC2550RSTR

CC2550RTK